FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12621-1E
8-bit Microcontrollers
CMOS
F2MC-8FX MB95130MB Series
MB95136MB/F133MBS/F133NBS/F133JBS/F134MBS/F134NBS/F134JBS/
MB95F136MBS/F136NBS/F136JBS/F133MBW/F133NBW/F133JBW/F134MBW/
MB95F134NBW/F134JBW/F136MBW/F136NBW/F136JBW/FV100D-103
■ DESCRIPTION
The MB95130MB series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product)
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2007 FUJITSU LIMITED All rights reserved
MB95130MB Series
(Continued)
• Timer
• 8/16-bit compound timer × 1 channel
• 8/16-bit PPG × 1 channel
• 16-bit PPG × 1 channel
• Timebase timer × 1 channel
• Watch prescaler (for dual clock product) × 1 channel
• LIN-UART × 1 channel
• LIN function, Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
• UART/SIO × 1 channel
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
• External interrupt × 8 channels
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter × 8 channels
• 8-bit or 10-bit resolution can be selected.
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode (for dual clock product)
• Timebase timer mode
• I/O port
• The number of maximum ports
• Single clock product : 20 ports
• Dual clock product : 18 ports
• Configuration
• General-purpose I/O ports (COMS) : Single clock product : 20 ports
Dual clock product : 18 ports
• Programmable input voltage levels of port
Automotive input level / CMOS input level / hysteresis input level
• Flash memory security function
Protects the content of Flash memory (Flash memory device only)
2
MB95130MB Series
■ MEMORY LINEUP
MB95F133MBS/F133NBS/F133JBS
MB95F133MBW/F133NBW/F133JBW
MB95F134MBS/F134NBS/F134JBS
MB95F134MBW/F134NBW/F134JBW
MB95F136MBS/F136NBS/F136JBS
MB95F136MBW/F136NBW/F136JBW
Flash memory
RAM
8 Kbytes
256 bytes
16 Kbytes
512 bytes
32 Kbytes
1 Kbyte
3
MB95130MB Series
■ PRODUCT LINEUP
Part number
MB95136MB
Parameter
Type
MB95
F133MBS/
F134MBS/
F136MBS
Option*2
Low voltage
detection
reset
Clock
supervisor
MB95
F133MBW/
F134MBW/
F136MBW
MASK ROM
product
MB95
F133NBW/
F134NBW/
F136NBW
MB95
F133JBS/
F134JBS/
F136JBS
MB95
F133JBW/
F134JBW/
F136JBW
Flash memory product
ROM capacity*1
RAM capacity*1
Reset output
Clock
system
MB95
F133NBS/
F134NBS/
F136NBS
32 Kbytes (Max)
1 Kbyte (Max)
Yes
Selectable
single/dual
clock*3
Yes/No
Yes/No
No
Single clock
No
Dual clock
Yes
No
No
Single clock
Dual clock
Yes
Yes
Peripheral functions
Number of basic instructions
: 136
Instruction bit length
: 8 bits
Instruction length
: 1 to 3 bytes
CPU functions
Data bit length
: 1, 8, and 16 bits
Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)
Interrupt processing time
: 0.6 µs (at machine clock frequency 16.25 MHz)
• Single clock product : 20 ports
General• Dual clock product : 18 ports
purpose
Programmable input voltage levels of port :
I/O port
Automotive input level / CMOS input level / hysteresis input level
Timebase
timer
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
(1 channel)
Reset generated cycle
Watchdog
At main oscillation clock 10 MHz
: Min 105 ms
timer
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
Wild register Capable of replacing 3 bytes of ROM data
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator
UART/SIO
NRZ type transfer format, error detected function
(1 channel)
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
Dedicated reload timer allowing a wide range of communication speeds to be set.
LIN-UART Full duplex double buffer.
(1 channel) Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN functions available as the LIN master or LIN slave.
8/10-bit
A/D
8-bit or 10-bit resolution can be selected.
converter
(8 channels)
(Continued)
4
MB95130MB Series
(Continued)
Part number
MB95136MB
Parameter
MB95
F133MBS/
F134MBS/
F136MBS
MB95
F133NBS/
F134NBS/
F136NBS
MB95
F133MBW/
F134MBW/
F136MBW
MB95
F133NBW/
F134NBW/
F136NBW
MB95
F133JBS/
F134JBS/
F136JBS
MB95
F133JBW/
F134JBW/
F136JBW
Peripheral functions
8/16-bit
Each channel of the timer can be used as “8-bit timer x 2 channels” or “16-bit timer x 1 channel”.
compound
Built-in timer function, PWC function, PWM function, capture function and square wave-form output
timer
Count clock: 7 internal clocks and external clock can be selected.
(1 channel)
PWM mode or one-shot mode can be selected.
16-bit PPG
Counter operating clock: Eight selectable clock sources
(1 channel)
Support for external trigger start
8/16-bit PPG Each channel of the PPG can be used as “8-bit PPG x 2 channels” or “16-bit PPG x 1 channel”.
(1 channel) Counter operating clock: Eight selectable clock sources
Watch
counter
Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
(for dual
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting clock
clock
source 1 second and setting counter value to 60)
product)
(1 channel)
Watch
prescaler
(for dual
Four selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
clock
product)
(1 channel)
External
Interrupt by edge detection (rising, falling, or both edges can be selected.)
interrupt
Can be used to recover from standby modes.
(8 channels)
Supports automatic programming, Embedded AlgorithmTM *4
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Flash memory Data retention time : 20 years
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
(MB95F136MBS/F136NBS/F136JBS/F136MBW/F136NBW/F136JBW)
Standby mode Sleep, stop, watch (for dual clock product), and timebase timer
*1 : For ROM capacity and RAM capacity, refer to “■ MEMORY LINEUP”.
*2 : For details of option, refer to “■ MASK OPTION”.
*3 : Specify clock mode when ordering MASK ROM.
*4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
Note : Part number of evaluation product in MB95130MB series is MB95FV100D-103.
When using it, the MCU board (MB2146-303A) is required.
5
MB95130MB Series
■ OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum
value is shown below.
Oscillation stabilization wait time
14
(2 -2) /FCH
Remarks
Approx. 4.10 ms (at main oscillation clock 4 MHz)
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95136MB
Package
FPT-28P-M17
FPT-30P-M02
BGA-224P-M08
: Available
: Unavailable
6
MB95F133MBS
MB95F133NBS
MB95F134MBS
MB95F134NBS
MB95F136MBS
MB95F136NBS
MB95F133JBS
MB95F134JBS
MB95F136JBS
MB95F133MBW
MB95F133NBW
MB95F134MBW
MB95F134NBW
MB95F136MBW
MB95F136NBW
MB95F133JBW
MB95F134JBW
MB95F136JBW
MB95FV100D-103
MB95130MB Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on using evaluation products
The Evaluation product has not only the functions of the MB95130MB series but also those of other products to
support software development for multiple series and models of the F2MC-8FX. The I/O addresses for peripheral
resources not used by the MB95130MB series are therefore access-barred. Read/write access to those accessbarred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected
malfunctions of hardware or software.
Particularly, do not use word access to an odd-numbered-byte address in the prohibited areas (If such access is
used, the address may be read or written unexpectedly) .
Also, as the read values of prohibited addresses on the evaluation product are different to the values on the flash
memory and mask ROM products, do not use these values in the software processing.
The Evaluation product does not support the functions of some bits in single-byte registers. Read/write access
to these bits does not cause hardware malfunctions. No particular precautions are required to the flash memory
and mask ROM products, as they have the identical read/write operation to the evaluation products.
• Difference of memory spaces
If the amount of memory on the Evaluation product is different from that of the Flash memory or MASK ROM
product, carefully check the difference in the amount of memory from the model to be actually used when
developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current consumption
• The current consumption of Flash memory product is greater than for MASK ROM product.
• For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS”
and “■ PACKAGE DIMENSION”.
• Operating voltage
The operating voltage is different among the Evaluation, Flash memory, and MASK ROM products.
For details of the operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Difference MOD Pins
A pull-down resistor is provided for the MOD pin of the MASK ROM product.
7
MB95130MB Series
■ PIN ASSIGNMENT
(TOP VIEW)
P16
1
28
P15
PF0
2
27
P14/PPG0
PF1
3
26
P13/TRG0/ADTG
MOD
4
25
P12/UCK0/EC0
X0
5
24
P11/UO0
X1
6
23
P10/UI0
VSS
7
22
P07/INT07/AN07
VCC
8
21
P06/INT06/AN06/TO01
C
PG2/X1A*
9
20
P05/INT05/AN05/TO00
10
19
P04/INT04/AN04/SIN
PG1/X0A*
11
18
P03/INT03/AN03/SOT
RST
12
17
P02/INT02/AN02/SCK
AVCC
13
16
P01/INT01/AN01/PPG01
AVSS
14
15
P00/INT00/AN00/PPG00
SOP-28
(FPT-28P-M17)
* : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
8
MB95130MB Series
(TOP VIEW)
P16
1
30
P15
PF0
2
29
P14/PPG0
PF1
3
28
P13/TRG0/ADTG
MOD
4
27
P12/UCK0/EC0
X0
5
26
NC
X1
6
25
P11/UO0
VSS
7
24
P10/UI0
VCC
8
23
P07/INT07/AN07
C
PG2/X1A*
9
22
P06/INT06/AN06/TO01
10
21
P05/INT05/AN05/TO00
PG1/X0A*
11
20
P04/INT04/AN04/SIN
RST
12
19
NC
AVCC
13
18
P03/INT03/AN03/SOT
AVSS
14
17
P02/INT02/AN02/SCK
P00/INT00/AN00/PPG00
15
16
P01/INT01/AN01/PPG01
SSOP-30
(FPT-30P-M02)
* : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
9
MB95130MB Series
■ PIN DESCRIPTION
Pin no.
Pin name
I/O
circuit
type*3
H
General-purpose I/O port
K
General-purpose I/O port for large current
B
Operating mode designation pin
Function
SSOP*1
SOP*2
1
1
P16
2
2
PF0
3
3
PF1
4
4
MOD
5
5
X0
6
6
X1
7
7
VSS
⎯
Power supply pin (GND)
8
8
VCC
⎯
Power supply pin
9
9
C
⎯
Capacity connection pin
10
10
PG2/X1A
A
H/A
Main clock oscillation input pin
Main clock oscillation input/output pin
Single clock product is general-purpose port (PG2) .
Dual clock product is sub clock input/output oscillation pin (32 kHz) .
Single clock product is general-purpose port (PG1) .
Dual clock product is sub clock input oscillation pin (32 kHz) .
11
11
PG1/X0A
12
12
RST
B’
Reset pin
13
13
AVCC
⎯
A/D converter power supply pin
14
14
AVSS
⎯
A/D converter power supply pin (GND)
15
15
P00/INT00/
AN00/
PPG00
General-purpose I/O port
Shared with external interrupt input (INT00), A/D converter analog
input (AN00) and 8/16-bit PPG ch.0 output (PPG00).
16
16
P01/INT01/
AN01/
PPG01
General-purpose I/O port
Shared with external interrupt input (INT01), A/D converter analog
input (AN01) and 8/16-bit PPG ch.0 output (PPG01).
17
17
P02/INT02/
AN02/SCK
General-purpose I/O port
Shared with external interrupt input (INT02), A/D converter analog
input (AN02) and LIN-UART clock I/O (SCK).
18
18
P03/INT03/
AN03/SOT
General-purpose I/O port
Shared with external interrupt input (INT03), A/D converter analog
input (AN03) and LIN-UART data output (SOT).
20
19
P04/INT04/
AN04/SIN
21
20
P05/INT05/
AN05/TO00
22
21
P06/INT06/
AN06/TO01
23
22
P07/INT07/
AN07
D
E
D
General-purpose I/O port
Shared with external interrupt input (INT04), A/D converter analog
input (AN04) and LIN-UART data input (SIN).
General-purpose I/O port
Shared with external interrupt input (INT05 & INT06), A/D converter
analog input (AN05 & AN06) and 8/16-bit compound timer ch.0
output (TO00 & TO01).
General-purpose I/O port
Shared with external interrupt input (INT07) and A/D converter
analog input (AN07).
(Continued)
10
MB95130MB Series
(Continued)
Pin no.
Pin name
I/O
circuit
type*3
G
SSOP*1
SOP*2
24
23
P10/UIO
25
24
P11/UO0
27
25
P12/UCK0/
EC0
28
26
P13/TRG0/
ADTG
29
27
P14/PPG0
30
28
P15
19,26
⎯
NC
Function
General-purpose I/O port
Shared with UART/SIO ch.0 data input (UI0)
General-purpose I/O port
Shared with UART/SIO ch.0 data output (UO0)
General-purpose I/O port
Shared with UART/SIO ch.0 clock I/O (UCK0) and 8/16-bit compound
timer ch.0 clock input (EC0)
H
General-purpose I/O port
Shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D converter
trigger input (ADTG)
General-purpose I/O port
Shared with 16-bit PPG ch.0 output (PPG0)
General-purpose I/O port
⎯
Internally connected pins.
Be sure to leave it open.
*1 : FPT-30P-M02
*2 : FPT-28P-M17
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
11
MB95130MB Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
Clock
input
X1 (X1A)
A
N-ch
X0 (X0A)
• Oscillation circuit
• High-speed side
Feedback resistance: approx. 1 MΩ
• Low-speed side
Feedback resistance: approx. 10 MΩ
Standby control
Mode input
B
R
Reset input
B’
N-ch
Reset output
R
P-ch
P-ch
Only for input
• Hysteresis input only for MASK ROM
product
• Pull-down resistor available only to MASK
ROM product
• Hysteresis input only for MASK ROM
product
• Reset output
•
•
Pull-up control
•
•
Digital output •
CMOS output
Hysteresis input
Analog input
Pull-up control available
Automotive input
Digital output
N-ch
D
Analog input
Automotive input
A/D control
Standby control
External
interrupt control
Hysteresis input
(Continued)
12
MB95130MB Series
(Continued)
Type
Circuit
Remarks
R
P-ch
P-ch
N-ch
•
•
Pull-up control
•
•
Digital output
•
Digital output •
CMOS output
CMOS input
Hysteresis input
Analog input
Pull-up control available
Automotive input
Analog input
E
CMOS input
Hysteresis input
Automotive input
A/D control
Standby control
External
interrupt control
Pull-up control
R
P-ch
P-ch
Digital output
•
•
•
•
•
CMOS output
CMOS input
Hysteresis input
Pull-up control available
Automotive input
•
•
•
•
CMOS output
Hysteresis input
Pull-up control available
Automotive input
Digital output
G
N-ch
CMOS input
Hysteresis input
Automotive input
Standby
control
Pull-up control
R
P-ch
P-ch
H
Digital output
Digital output
N-ch
Hysteresis input
Standby
control
Automotive input
P-ch
N-ch
K
Digital output
Digital output
• CMOS output
• Hysteresis input
• Automotive input
Hysteresis input
Standby
control
Automotive input
13
MB95130MB Series
■ HANDLING DEVICES
• Preventing latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when the devices are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if voltage higher than the rating voltage is applied between
VCC pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
Also, take care to prevent the analog power supply voltage (AVCC) and analog input voltage from exceeding the
digital power supply voltage (VCC) when the analog system power supply is turned on or off.
• Stable supply voltage
Supply voltage should be stabilized.
A sudden change in power supply voltage may cause a malfunction even within the guaranteed operating range
of the VCC power supply voltage.
For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range
(50 / 60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient
variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
• Precautions for use of external clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from the sub clock mode or stop mode.
PIN CONNECTION
• Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent
damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ.
Any unused input/output pins may be set to the output mode and left open, or set to the input mode and treated
the same as unused input pins. If there is any unused output pin, make it open.
• Treatment of power supply pins on A/D converter
Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor
as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, all the pins must be connected to external power
supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe
signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect
the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins
near this device.
• Mode pin (MOD)
Connect the mode pin directly to VCC or VSS pins.
To prevent the device unintentionally entering the test mode due to noise, lay out the printed circuit board so as
to minimize the distance from the mode pins to VCC or VSS pins and to provide a low-impedance connection.
14
MB95130MB Series
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin
must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram
below.
• C Pin Connection Diagram
C
CS
• Analog power supply
Always set the same potential to AVCC and VCC. When VCC > AVCC, the current may flow through the AN00 to
AN07 pins.
• NC pins
Any pins marked “NC”(not connected) must be left open.
15
MB95130MB Series
■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER
• Supported parallel programmers and adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
FPT-28P-M17
TEF110-95F136HSPF
FPT-30P-M02
TEF110-95F136MB
Parallel programmers
AF9708 (Since Rev 02.43E )
AF9709/B (Since Rev 02.43E )
Note : For information about applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector configuration
The following table shows sector-specific addresses for data access by CPU and by the parallel programmer.
• MB95F136MBS/F136NBS/F136MBW/F136NBW/F136JBS/F136JBW (32 Kbytes)
Flash memory
CPU address
Programmer address*
8000H
18000H
FFFFH
1FFFFH
32 Kbytes
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in
Flash memory.
• Programming method
1) Set the type code of the parallel programmer to “17237”.
2) Load program data to programmer addresses 18000H to 1FFFFH.
3) Write data with the parallel programmer.
• MB95F134MBS/F134NBS/F134JBS/F134MBW/F134NBW/F134JBW (16 Kbytes)
Flash memory
CPU address
Programmer address*
C000H
1C000H
FFFFH
1FFFFH
16 Kbytes
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in
Flash memory.
• Programming method
1) Set the type code of the parallel programmer to “17237”.
2) Load program data to programmer addresses 1C000H to 1FFFFH.
3) Write data with the parallel programmer.
16
MB95130MB Series
• MB95F133MBS/F133NBS/F133JBS/F133MBW/F133NBW/F133JBW (8 Kbytes)
Flash memory
CPU address
Programmer address*
E000H
1E000H
8 Kbytes
FFFFH
1FFFFH
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in
Flash memory.
• Programming method
1) Set the type code of the parallel programmer to “17237”.
2) Load program data to programmer addresses 1E000H to 1FFFFH.
3) Write data with the parallel programmer.
17
MB95130MB Series
■ BLOCK DIAGRAM
F2MC-8FX CPU
RST
X0/X1
PG2/(X1A)*
PG1/(X0A)*
Reset control
ROM 32 Kbytes
RAM 1 Kbyte
Clock control
Interrupt control
Watch counter
Wild register
P00/INT00 to P07/INT07
P10/U10
P11/UO0
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
P15/P16
P00/AN00 to P07/AN07
AVCC
AVSS
External interrupt
8 channels
UART/SIO
1 channel
16-bit PPG
1 channel
8/10-bit
A/D converter
8 channels
Port
Internal bus
Watch prescaler
8/16-bit PPG
2 channels
LIN-UART
1 channel
8/16-bit
compound timer
1 channel
(P00/PPG00)
(P01/PPG01)
(P02/SCK)
(P03/SOT)
(P04/SIN)
(P05/TO00)
(P06/TO01)
(P12/EC0)
PF0/PF1
Port
Other pins
MOD, VCC, VSS, C
*: Single clock product is a general-purpose port, and dual clock product is a sub clock oscillation pin.
18
MB95130MB Series
■ CPU CORE
1. Memory Space
Memory space of the MB95130MB series is 64 Kbytes and consists of I/O area, data area, and program area.
The memory space includes special-purpose areas such as the general-purpose registers and vector table.
Memory map of the MB95130MB series is shown below.
• Memory Map
MB95136MB
0000H
MB95F133MBS/F133NBS/F133JBS
MB95F134MBS/F134NBS/F134JBS
MB95F136MBS/F136NBS/F136JBS
MB95F133MBW/F133NBW/F133JBW
MB95F134MBW/F134NBW/F134JBW
MB95F136MBW/F136NBW/F136JBW
0000H
I/O
0080H
0100H
RAM 1 Kbyte
Register
0200H
Access
prohibited
0F80H
I/O
0080H
RAM
0100H Register
0200H
Address #1
0480H
0000H
I/O
0080H
1000H
0200H
Access
prohibited
0F80H
Extended I/O
Extended I/O
1000H
1000H
Access
prohibited
Access
prohibited
8000H
Flash memory
60 Kbytes
Address #2
MASK ROM
32 Kbytes
FFFFH
MB95F133MBS/F133NBS/F133JBS
MB95F133MBW/F133NBW/F133JBW
MB95F134MBS/F134NBS/F134JBS
MB95F134MBW/F134NBW/F134JBW
MB95F136MBS/F136NBS/F136JBS
MB95F136MBW/F136NBW/F136JBW
RAM 3.75 Kbytes
0100H Register
0F80H
Extended I/O
MB95FV100D-103
Flash memory
FFFFH
FFFFH
Flash memory
RAM
Address #1
Address #2
8 Kbytes
256 bytes
0180H
E000H
16 Kbytes
512 bytes
0280H
C000H
32 Kbytes
1 Kbyte
0480H
8000H
19
MB95130MB Series
2. Register
The MB95130MB series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as include:
Program counter (PC)
Accumulator (A)
Temporary accumulator (T)
Index register (IX)
Extra pointer (EP)
Stack pointer (SP)
Program status (PS)
: A 16-bit register to indicate locations where instructions are stored.
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower 1-byte is used.
: A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower 1-byte is used.
: A 16-bit register for index modification
: A 16-bit pointer to point to a memory address.
: A 16-bit register to indicate a stack area.
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register
Initial Value
16 bits
PC
: Program counter
FFFDH
AH
AL
: Accumulator
0000H
TH
TL
: Temporary accumulator
0000H
IX
: Index register
0000H
EP
: Extra pointer
0000H
SP
: Stack pointer
0000H
PS
: Program status
0030H
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR). (Refer to the diagram below.)
• Structure of the program status
bit15 bit14 bit13 bit12 bit11 bit10
PS
R4
R3
R2
RP
20
R1
R0
DP2
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DP1
DP0
H
I
IL1
IL0
N
Z
V
C
DP
CCR
MB95130MB Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP upper
“0”
“0”
“0”
“0”
“0”
“0”
OP code lower
“0”
“1”
R4
R3
R2
R1
R0
b2
b1
b0
Generated address A15 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
The DP specifies the area for mapping instructions (16 different types of instructions such as MOV A and dir)
using direct addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
XXXB (no effect to mapping)
0000H to 007FH
0000H to 007FH (without mapping)
000B (initial value)
0080H to 00FFH (without mapping)
001B
0100H to 017FH
010B
0180H to 01FFH
011B
0080H to 00FFH
100B
0200H to 027FH
0280H to 02FFH
101B
0300H to 037FH
110B
0380H to 03FFH
111B
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data content and the bits that
control CPU operations at interrupt.
H flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I flag
: Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is cleared to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
IL1
IL0
Interrupt level
Priority
0
0
0
High
0
1
1
1
0
2
1
1
3
Low (no interruption)
N flag
: Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
Z flag
V flag
: Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
bit is set to “0”.
C flag
: Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
: Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
21
MB95130MB Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8
registers. Up to a total of 32 banks can be used on the MB95130MB series. The bank currently in use is specified
by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)
to general-purpose register 7 (R7).
• Register Bank Configuration
8-bit
1F8H
This address = 0100H + 8 × (RP)
Address 100H
R0
R0
R0
R1
R2
R3
R4
R5
107H
R6
R1
R2
R3
R4
R5
R6
R1
R2
R3
R4
R5
R6
1FFH
R7
R7
R7
Bank 0
Memory area
22
Bank 31
32 banks
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
MB95130MB Series
■ I/O MAP
Address
Register
abbreviation
Register name
R/W
Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
⎯
(Disabled)
⎯
⎯
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W
1010X011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R/W
XXXXXXXXB
000AH
TBTC
Timebase timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
to
0027H
⎯
(Disabled)
⎯
⎯
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
PUL1
Port 1 pull-up register
R/W
00000000B
002EH
to
0034H
⎯
(Disabled)
⎯
⎯
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit compound timer 01 control status register 1 ch.0
R/W
00000000B
0037H
T00CR1
8/16-bit compound timer 00 control status register 1 ch.0
R/W
00000000B
0038H,
0039H
⎯
(Disabled)
⎯
⎯
003AH
PC01
8/16-bit PPG1 control register ch.0
R/W
00000000B
003BH
PC00
8/16-bit PPG0 control register ch.0
R/W
00000000B
003CH
to
0041H
⎯
(Disabled)
⎯
⎯
0042H
PCNTH0
16-bit PPG control status register (Upper byte) ch.0
R/W
00000000B
0043H
PCNTL0
16-bit PPG control status register (Lower byte) ch.0
R/W
00000000B
(Continued)
23
MB95130MB Series
Address
Register
abbreviation
Register name
R/W
Initial value
0044H
to
0047H
⎯
(Disabled)
⎯
⎯
0048H
EIC00
External interrupt circuit control register ch.0,ch.1
R/W
00000000B
0049H
EIC10
External interrupt circuit control register ch.2,ch.3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch.4,ch.5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch.6,ch.7
R/W
00000000B
004CH
to
004FH
⎯
(Disabled)
⎯
⎯
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART reception/transmission data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
SMC10
UART/SIO serial mode control register 1 ch.0
R/W
00000000B
0057H
SMC20
UART/SIO serial mode control register 2 ch.0
R/W
00100000B
0058H
SSR0
UART/SIO serial status register ch.0
R/W
00000001B
0059H
TDR0
UART/SIO serial output data register ch.0
R/W
00000000B
005AH
RDR0
UART/SIO serial input data register ch.0
R
00000000B
005BH
to
006BH
⎯
(Disabled)
⎯
⎯
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (Upper byte)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (Lower byte)
R/W
00000000B
0070H
WCSR
Watch counter status register
R/W
00000000B
0071H
⎯
(Disabled)
⎯
⎯
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector writing control register 0
R/W
00000000B
0074H
SWRE1
Flash memory sector writing control register 1
R/W
00000000B
0075H
⎯
(Disabled)
⎯
⎯
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
(Continued)
24
MB95130MB Series
Address
Register
abbreviation
Register name
R/W
Initial value
0078H
⎯
(Register bank pointer (RP)
Mirror of direct bank pointer (DP)
⎯
⎯
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
⎯
(Disabled)
⎯
⎯
0F80H
WRARH0
Wild register address setting register (Upper byte) ch.0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (Lower byte) ch.0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch.0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (Upper byte) ch.1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (Lower byte) ch.1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch.1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (Upper byte) ch.2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (Lower byte) ch.2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch.2
R/W
00000000B
0F89H
to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
T01CR0
8/16-bit compound timer 01 control status register 0 ch.0
R/W
00000000B
0F93H
T00CR0
8/16-bit compound timer 00 control status register 0 ch.0
R/W
00000000B
0F94H
T01DR
8/16-bit compound timer 01 data register ch.0
R/W
00000000B
0F95H
T00DR
8/16-bit compound timer 00 data register ch.0
R/W
00000000B
0F96H
TMCR0
8/16-bit compound timer 00/01 timer mode control register
ch.0
R/W
00000000B
0F97H
to
0F9BH
⎯
(Disabled)
⎯
⎯
0F9CH
PPS01
8/16-bit PPG1 cycle setting buffer register ch.0
R/W
11111111B
0F9DH
PPS00
8/16-bit PPG0 cycle setting buffer register ch.0
R/W
11111111B
0F9EH
PDS01
8/16-bit PPG1 duty setting buffer register ch.0
R/W
11111111B
0F9FH
PDS00
8/16-bit PPG0 duty setting buffer register ch.0
R/W
11111111B
0FA0H
to
0FA3H
⎯
(Disabled)
⎯
⎯
(Continued)
25
MB95130MB Series
(Continued)
26
Address
Register
abbreviation
Register name
R/W
Initial value
0FA4H
PPGS
8/16-bit PPG start register
R/W
00000000B
0FA5H
REVC
8/16-bit PPG output inversion register
R/W
00000000B
0FA6H
to
0FA9H
⎯
(Disabled)
⎯
⎯
0FAAH
PDCRH0
16-bit PPG down counter register (Upper byte) ch.0
R
00000000B
0FABH
PDCRL0
16-bit PPG down counter register (Lower byte) ch.0
R
00000000B
0FACH
PCSRH0
16-bit PPG cycle setting buffer register (Upper byte) ch.0
R/W
11111111B
0FADH
PCSRL0
16-bit PPG cycle setting buffer register (Lower byte) ch.0
R/W
11111111B
0FAEH
PDUTH0
16-bit PPG duty setting buffer register (Upper byte) ch.0
R/W
11111111B
0FAFH
PDUTL0
16-bit PPG duty setting buffer register (Lower byte) ch.0
R/W
11111111B
0FB0H
to
0FBBH
⎯
(Disabled)
⎯
⎯
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
PSSR0
UART/SIO dedicated baud rate generator
prescaler selection register ch.0
R/W
00000000B
0FBFH
BRSR0
UART/SIO dedicated baud rate generator
baud rate setting register ch.0
R/W
00000000B
0FC0H
to
0FC2H
⎯
(Disabled)
⎯
⎯
0FC3H
AIDRL
A/D input disable register (Lower byte)
R/W
00000000B
0FC4H
to
0FE2H
⎯
(Disabled)
⎯
⎯
0FE3H
WCDR
Watch counter data register
R/W
00111111B
0FE4H
to
0FE6H
⎯
(Disabled)
⎯
⎯
0FE7H
ILSR2
Input level select register 2 (option)
R/W
00000000B
0FE8H,
0FE9H
⎯
(Disabled)
⎯
⎯
0FEAH
CSVCR
Clock supervisor control register
R/W
00011100B
0FEBH
to
0FEDH
⎯
(Disabled)
⎯
⎯
0FEEH
ILSR
Input level select register
R/W
00000000B
0FEFH
WICR
Interrupt pin control register
R/W
01000000B
0FF0H
to
0FFFH
⎯
(Disabled)
⎯
⎯
MB95130MB Series
• R/W access symbols
R/W : Readable / Writable
R
: Read only
W
: Write only
• Initial value symbols
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
27
MB95130MB Series
■ INTERRUPT SOURCE TABLE
Interrupt source
Interrupt
request
number
Vector table address
Same level
Bit name of
priority order
interrupt level
(at simultaneous
setting register
occurrence)
Upper
Lower
IRQ0
FFFAH
FFFBH
L00 [1 : 0]
IRQ1
FFF8H
FFF9H
L01 [1 : 0]
IRQ2
FFF6H
FFF7H
L02 [1 : 0]
IRQ3
FFF4H
FFF5H
L03 [1 : 0]
UART/SIO ch.0
IRQ4
FFF2H
FFF3H
L04 [1 : 0]
8/16-bit compound timer ch.0 (Lower)
IRQ5
FFF0H
FFF1H
L05 [1 : 0]
8/16-bit compound timer ch.0 (Higher)
IRQ6
FFEEH
FFEFH
L06 [1 : 0]
LIN-UART (reception)
IRQ7
FFECH
FFEDH
L07 [1 : 0]
LIN-UART (transmission)
IRQ8
FFEAH
FFEBH
L08 [1 : 0]
(Unused)
IRQ9
FFE8H
FFE9H
L09 [1 : 0]
(Unused)
IRQ10
FFE6H
FFE7H
L10 [1 : 0]
(Unused)
IRQ11
FFE4H
FFE5H
L11 [1 : 0]
8/16-bit PPG ch.0 (Upper)
IRQ12
FFE2H
FFE3H
L12 [1 : 0]
8/16-bit PPG ch.0 (Lower)
IRQ13
FFE0H
FFE1H
L13 [1 : 0]
IRQ14
FFDEH
FFDFH
L14 [1 : 0]
IRQ15
FFDCH
FFDDH
L15 [1 : 0]
(Unused)
IRQ16
FFDAH
FFDBH
L16 [1 : 0]
(Unused)
IRQ17
FFD8H
FFD9H
L17 [1 : 0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1 : 0]
Timebase timer
IRQ19
FFD4H
FFD5H
L19 [1 : 0]
Watch prescaler/Watch counter
IRQ20
FFD2H
FFD3H
L20 [1 : 0]
(Unused)
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
(Unused)
IRQ22
FFCEH
FFCFH
L22 [1 : 0]
IRQ23
FFCCH
FFCDH
L23 [1 : 0]
External interrupt ch.0
High
External interrupt ch.4
External interrupt ch.1
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
(Unused)
16-bit PPG ch.0
Flash memory
28
Low
MB95130MB Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1
Input voltage*1
Output voltage*
1
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
Rating
VCC
AVCC
VSS − 0.3
VSS + 6.0
V
*2
VI
VSS − 0.3
VSS + 6.0
V
*3
VO
VSS − 0.3
VSS + 6.0
V
*3
ICLAMP
− 2.0
+ 2.0
mA
Applicable to pins*4
Σ|ICLAMP|
⎯
20
mA
Applicable to pins*4
IOL1
IOL2
“L” level average
current
⎯
“H” level maximum
output current
15
⎯
mA
mA
12
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
IOH1
IOH2
⎯
“H” level average
current
− 15
− 15
mA
−4
IOHAV1
⎯
mA
−8
IOHAV2
“H” level total maximum
output current
15
4
IOLAV2
“L” level total average
output current
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 50
mA
Power consumption
Pd
⎯
320
mW
Operating temperature
TA
− 40
+ 85
°C
Tstg
− 55
+ 150
°C
“H” level total average
output current
Storage temperature
Remarks
Max
IOLAV1
“L” level total maximum
output current
Unit
Min
Other than PF0, PF1
PF0, PF1
Other than PF0, PF1
Average output current =
operating current × operating ratio
(1 pin)
PF0, PF1
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total of pins)
Other than PF0, PF1
PF0, PF1
Other than PF0, PF1
Average output current =
operating current × operating ratio
(1 pin)
PF0, PF1
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total number of pins)
29
MB95130MB Series
*1: The parameter is based on AVSS = VSS = 0.0 V.
*2: Apply equal potential to AVCC and VCC.
*3: VI and VO should not exceed Vcc + 0.3 V. VI must not exceed the rating voltage. However, if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes
the VI rating.
*4: Applicable pins: P10 to P15, PF0, PF1 (Inapplicable pins: PG1, PG2)
• Use within recommended operating conditions.
• Use at DC voltage (current).
• +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affects
other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept
+B signal input.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
+ B input (0 V to 16 V)
Vcc
Limiting
resistance
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
30
MB95130MB Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Min
Max
Unit
Power supply voltage
VCC,
AVCC
2.42*2
5.5*1
2.3
5.5
Smoothing capacitor
CS
0.1
1.0
µF
Operating temperature
TA
− 40
+ 85
°C
V
Remarks
At normal operation
Holds condition in stop mode
*3
*1: The value varies depending on the operating frequency.
*2: The value is 2.88 V when the low-voltage detection reset is used.
*3: Use ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin
must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram
below.
• C pin connection diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
31
MB95130MB Series
3. DC Characteristics
(VCC = = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter Symbol
“H” level
input
voltage
“L” level
output
voltage
Value
Min
Typ
Max
Unit
Remarks
VIHI
⎯
0.7 VCC
⎯
VCC + 0.3
V
Hysteresis input
VIHSI
P00 to P07,
P10 to P16, PF0,
PF1,
PG1, PG2
⎯
0.8 VCC
⎯
VCC + 0.3
V
Hysteresis input
VIHA
P00 to P07,
P10 to P16, PF0,
PF1,
PG1, PG2
⎯
0.8 Vcc
⎯
VCC + 0.3
V
Pin input at selecting
of Automotive
input level
⎯
0.7 VCC
⎯
VCC + 0.3
V
CMOS input
(Flash memory
product)
⎯
0.8 VCC
⎯
VCC + 0.3
V
Hysteresis input
(MASK ROM
product)
VIL
P04 (selectable
in SIN),
P10 (selectable
in UI0)
⎯
VSS − 0.3
⎯
0.3 VCC
V
Hysteresis input
VILS
P00 to P07,
P10 to P16, PF0,
PF1,
PG1, PG2
⎯
VSS − 0.3
⎯
0.2 VCC
V
Hysteresis input
VILA
P00 to P07,
P10 to P16, PF0,
PF1,
PG1, PG2
⎯
VSS − 0.3
⎯
0.5 VCC
V
Pin input at selecting
of Automotive
input level
⎯
VSS − 0.3
⎯
0.3 VCC
V
CMOS input
(Flash memory
product)
⎯
VSS − 0.3
⎯
0.2 VCC
V
Hysteresis input
(MASK ROM
product)
VOH1
Output pins other
IOH = − 4.0 mA VCC − 0.5
than PF0, PF1
⎯
⎯
V
VOH2
PF0, PF1
IOH = − 8.0 mA VCC − 0.5
⎯
⎯
V
VOL1
Output pins other
than PF0 to PF7, IOL = 4.0 mA
RST*1
⎯
⎯
0.4
V
VOL2
PF0, PF1
IOL = 12 mA
⎯
⎯
0.4
V
VILM
“H” level
output
voltage
Condition
P04 (selectable
in SIN),
P10 (selectable
in UI0)
VIHM
“L” level
input
voltage
Pin name
RST, MOD
RST, MOD
(Continued)
32
MB95130MB Series
(VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter Symbol
Input
leakage
current
(Hi-Z output leakage
current)
ILI
Pin name
Condition
P00 to P07, P10
to P16, PF0,
0.0 V < VI < VCC
PF1, PG1, PG2
−5
Unit
Remarks
+5
When the
pull-up
µA
prohibition
setting
100
kΩ
VI = VCC
50
100
200
kΩ
MASK ROM
product only
f = 1 MHz
⎯
5
15
pF
RMOD
MOD
Other than
AVCC, AVss, C,
Vcc and Vss
⎯
VCC = 5.5 V
FCH = 20 MHz
FMP = 10 MHz
Main clock mode
(divided by 2)
ICC
⎯
Max
50
Pull-down
resistor
Power
supply
current*2
Typ
25
RPULL
P00 to P07, P10
to P16, PG1,
VI = 0.0 V
PG2
CIN
Min
When the
pull-up
permission
setting
Pull-up
resistor
Input
capacity
Value
VCC
(External clock
operation)
12.5
⎯
30
35
Flash memory
product
mA (at Flash
memory writing
and erasing)
⎯
7.2
9.5
mA
20.0
Flash memory
product
(at other than
mA
Flash memory
writing and
erasing)
⎯
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
9.5
Flash memory
product
(at other than
mA
Flash memory
writing and
erasing)
15.2
MASK ROM
product
⎯
35.7
42.5
Flash memory
product
mA (at Flash
memory writing
and erasing)
⎯
11.6
15.2
mA
MASK ROM
product
(Continued)
33
MB95130MB Series
Parameter Symbol
Pin name
(VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Condition
Unit
Remarks
Min
Typ
Max
VCC = 5.5 V
FCH = 20 MHz
FMP = 10 MHz
Main Sleep mode
(divided by 2)
⎯
4.5
7.5
mA
FCH = 32 MHz
FMP = 16 MHz
Main Sleep mode
(divided by 2)
⎯
7.2
12.0
mA
ICCL
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Sub clock mode
(divided by 2) ,
TA = + 25 °C
⎯
45
100
µA
Dual clock
product only
ICCLS
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2) ,
TA = + 25 °C
⎯
10
81
µA
Dual clock
product only
VCC = 5.5 V
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
⎯
4.6
27
µA
Dual clock
product only
⎯
9.3
12.5
mA
Flash memory
product
⎯
7
9.5
mA
MASK ROM
product
⎯
14.9
20.0
mA
Flash memory
product
⎯
11.2
15.2
mA
MASK ROM
product
⎯
160
400
µA
Dual clock
product only
ICCS
VCC
(External clock
operation)
Power
supply
current*2
ICCT
ICCMPLL
VCC = 5.5 V
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
ICCSPLL
VCC = 5.5 V
FCL = 32 kHz
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
(Continued)
34
MB95130MB Series
(Continued)
Parameter Symbol
ICTS
Pin name
VCC
(External clock
operation)
ICCH
Power
supply
current*2
IA
AVcc
IAH
(VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Condition
Unit
Remarks
Min
Typ
Max
VCC = 5.5 V
FCH = 10 MHz
Timebase timer
mode
TA = + 25 °C
⎯
0.15
1.1
mA
VCC = 5.5 V
Sub stop mode
TA = + 25 °C
⎯
3.5
20.0
µA
VCC = 5.5 V
FCH = 16 MHz
When A/D conversion is in operation
⎯
2.4
4.7
mA
VCC = 5.5 V
FCH = 16 MHz
When A/D conversion is stopped
TA = + 25 °C
⎯
1
5
µA
Main stop mode
for single clock
product
*1: Product without clock supervisor only
*2: • The power supply current is specified by the external clock. When the low-voltage detection and clock
supervisor options are selected, the consumption current values of both the low-voltage detection circuit (ILVD)
and the built-in CR oscillator (ICSV) must also be added to the power supply current value.
• Refer to “4. AC Characteristics: (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC Characteristics: (2) Source Clock/Machine Clock” for FMP and FMPL.
35
MB95130MB Series
4. AC Characteristics
(1) Clock Timing
(VCC = 2.42 V to 5.0 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
SymCondiPin name
bol
tion
FCH
X0, X1
Clock frequency
FCL
X0, X1
Clock cycle time
Input clock pulse width
Input clock rise/fall time
36
Unit
Remarks
16.25
MHz
When using main
oscillation circuit
⎯
32.50
MHz When using external clock
3.00
⎯
10.00
MHz Main PLL multiplied by 1
3.00
⎯
8.13
MHz Main PLL multiplied by 2
3.00
⎯
6.50
MHz Main PLL multiplied by 2.5
3.00
⎯
4.06
MHz Main PLL multiplied by 4
⎯
32.768
⎯
kHz
When using sub
oscillation circuit
⎯
32.768
⎯
kHz
When using sub PLL
VCC = 2.3 V to 3.6 V
61.5
⎯
1000
ns
When using main
oscillation circuit
30.8
⎯
1000
ns
When using external clock
Min
Typ
Max
1.00
⎯
1.00
X0A, X1A
⎯
tHCYL
Value
tLCYL
X0A, X1A
⎯
30.5
⎯
µs
When using sub
oscillation circuit
tWH1
tWL1
X0
61.5
⎯
⎯
ns
tWH2
tWL2
X0A
⎯
15.2
⎯
µs
When using external clock
duty ratio is about 30% to
70%.
tCR
tCF
X0, X0A
⎯
⎯
5
ns
When using external clock
MB95130MB Series
• Input wave form for using external clock (main clock)
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of Main Clock Input Port External Connection
When using crystal or
ceramic oscillator
When using external clock
Microcontroller
X0
Microcontroller
X1
X0
X1
Open
FCH
FCH
C1
C2
• Input wave form for using external clock (sub clock)
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of Sub clock Input Port External Connection
When using crystal or
ceramic oscillator
Microcontroller
X0A
X1A
FCL
When using external clock
Microcontroller
X0A
X1A
Open
FCL
C1
C2
37
MB95130MB Series
(2) Source Clock/Machine Clock
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Source clock
cycle time*1
(Clock before
setting division)
Source clock
frequency
Machine clock
cycle time*2
(Minimum
instruction
execution time)
Machine clock
frequency
Symbol
tSCLK
Pin
name
Value
Unit
Remarks
2000
ns
When using main clock
Min : FCH = 8.125 MHz, PLL multiplied by 2
Max : FCH = 1 MHz, divided by 2
⎯
61.0
µs
When using sub clock
Min : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
Min
Typ
Max
61.5
⎯
7.6
⎯
FSP
⎯
0.50
⎯
16.25
MHz When using main clock
FSPL
⎯
16.384
⎯
131.072
kHz When using sub clock
61.5
⎯
32000
ns
When using main clock
Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
7.6
⎯
976.5
µs
When using sub clock
Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
0.031
⎯
16.250
MHz When using main clock
1.024
⎯
131.072
kHz When using sub clock
tMCLK
FMP
FMPL
⎯
⎯
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
• Outline of clock generation block
FCH
(main oscillation)
Divided by 2
Main PLL
×1
×2
× 2.5
×4
SCLK
(source clock)
FCL
(sub oscillation)
Divided by 2
Sub PLL
×2
×3
×4
38
Clock mode select bit
(SYCC: SCS1, SCS0)
Division
circuit
×1
× 1/4
× 1/8
× 1/16
MCLK
(machine clock)
MB95130MB Series
• Operating voltage - Operating frequency (When TA = − 40 °C to + 85 °C)
• MB95F133MBS/F133NBS/F133JBS/F134MBS/F134NBS/F134JBS/F136MBS/F136NBS/F136JBS/
MB95F133MBW/F133NBW/F133JBW/F134MBW/F134NBW/F134JBW/F136MBW/F136NBW/
MB95F136JBW
Main clock mode and main PLL mode
operation guarantee range
Sub PLL, sub clock mode and
watch mode operation guarantee range
5.5
2.42
16.384 kHz
32 kHz
131.072 kHz
Operating voltage (V)
Operating voltage (V)
5.5
3.5
2.42
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSPL)
• Operating voltage - Operating frequency (When TA = + 5 °C to + 35 °C)
• MB95FV100D-103
Main clock mode and main PLL mode
operation guarantee range
Sub PLL, sub clock mode and
watch mode operation guarantee range
5.5
2.7
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Operating voltage (V)
Operating voltage (V)
5.5
3.5
2.7
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSPL)
Source clock frequency (FSP)
39
MB95130MB Series
• Main PLL operation frequency
[MHz]
16.25
16
15
×4
Source clock frequency (FSP)
12
× 2.5
10
×1
×2
7.5
6
5
3
0
3
4
4.062
5
6.4
6.5
Machine clock frequency (FMP)
40
8
8.125
10 [MHz]
MB95130MB Series
(3) External Reset
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
RST “L” level
pulse width
tRSTL
Value
Pin
name
RST
Unit
Remarks
Min
Max
2 tMCLK*1
⎯
ns
At normal operation
Oscillation time of oscillator*2
+ 100
⎯
µs
At stop mode, sub clock mode,
sub sleep mode & watch mode
100
⎯
µs
At timebase timer mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the
oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between
hundreds of µs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
RST
tRSTL
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
100 µs
Oscillation time
Oscillation stabilization wait time
of oscillator
Execute instruction
Internal reset
41
MB95130MB Series
(4) Power-on Reset
(AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Power supply rising time
tR
Power supply cutoff time
tOFF
Pin
name
VCC
Condition
Value
Unit
Min
Max
⎯
⎯
50
ms
⎯
1
⎯
ms
Remarks
Waiting time until
power-on
Note : Complete the power-on process within the selected oscillation stabilization wait time.
tR
tOFF
2.5 V
VCC
0.2 V
0.2 V
0.2 V
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 30 mV/ms as shown below.
VCC
Limiting the slope of rising within
30 mV/ms is recommended.
2.3 V
Hold Condition in stop mode
VSS
42
MB95130MB Series
(5) Peripheral Input Timing
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Peripheral input “H” pulse
tILIH
Peripheral input “L” pulse
tIHIL
INT00 to INT07,
EC0, TRG0/ADTG
Value
Unit
Min
Max
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIH
tIHIL
0.8 VCC 0.8 VCC
INT00 to INT07,
EC0,TRG0/ADTG
0.2 VCC
0.2 VCC
43
MB95130MB Series
(6) UART/SIO Serial I/O Timing
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑→ valid UI hold time
tSHIX
Serial clock “H” pulse width
Value
Condition
Max
4 tMCLK*
⎯
ns
− 190
+190
ns
2 tMCLK*
⎯
ns
UCK0, UI0
2 tMCLK*
⎯
ns
tSHSL
UCK0
4 tMCLK*
⎯
ns
Serial clock “L” pulse width
tSLSH
UCK0
4 tMCLK*
⎯
ns
UCK ↓ → UO time
tSLOV
UCK0, UO0
⎯
190
ns
Valid UI → UCK ↑
tIVSH
UCK0, UI0
2 tMCLK*
⎯
ns
UCK ↑→ valid UI hold time
tSHIX
UCK0, UI0
2 tMCLK*
⎯
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
External clock
operation output pin :
CL = 80 pF + 1 TTL.
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
UCK0
2.4 V
0.8 V
0.8 V
tSLOV
UO0
2.4 V
0.8 V
tIVSH
UI0
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC 0.8 VCC
UCK0
0.2 VCC 0.2 VCC
tSLOV
UO0
2.4 V
0.8 V
tIVSH
UI0
44
Unit
Min
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
MB95130MB Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Serial clock cycle time
SCK ↓→ SOT delay time
SymPin name
bol
tSCYC
tSLOVI
Valid SIN → SCK↑
tIVSHI
SCK ↑→ valid SIN hold time
tSHIXI
Serial clock “L” pulse width
tSLSH
Serial clock “H” pulse width
tSHSL
Value
Condition
Max
5 tMCLK*3
⎯
ns
− 95
+95
ns
⎯
ns
0
⎯
ns
3 tMCLK*3 − tR
⎯
ns
* + 95
⎯
ns
SCK
Internal clock
SCK, SOT
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
SCK, SIN
SCK
SCK
SCK ↓ → SOT delay time
tSLOVE SCK, SOT
Valid SIN → SCK↑
tIVSHE
SCK↑→ valid SIN hold time
tSHIXE
External clock
SCK, SIN operation output pin :
CL = 80 pF + 1 TTL.
SCK, SIN
Unit
Min
t
* + 190
MCLK 3
MCLK 3
t
⎯
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
45
MB95130MB Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
tSLSH
SCK
0.8 VCC
0.8 VCC
0.2 VCC
tF
SOT
0.2 VCC
tR
tSLOVE
2.4 V
0.8 V
tIVSHE
SIN
tSHIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
46
0.8 VCC
MB95130MB Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 5.0 V± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK↑→ SOT delay time
tSHOVI
SCK, SOT
Parameter
Value
Condition
Internal clock
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
SCK, SIN
Unit
Min
Max
5 tMCLK*3
⎯
ns
− 95
+95
ns
⎯
ns
0
⎯
ns
* + 190
Valid SIN → SCK↓
tIVSLI
SCK ↓→ valid SIN hold time
tSLIXI
Serial clock “H” pulse width
tSHSL
SCK
3 tMCLK*3 − tR
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3 + 95
⎯
ns
SCK, SOT
⎯
SCK↑ → SOT delay time
tSHOVE
Valid SIN → SCK↓
tIVSLE
SCK ↓→ valid SIN hold time
tSLIXE
External clock
SCK, SIN operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
t
MCLK 3
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
47
MB95130MB Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
SCK
0.8 VCC
tSLSH
0.8 VCC
0.2 VCC
tR
SOT
tF
tSHOVE
2.4 V
0.8 V
tIVSLE
SIN
tSLIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
48
0.2 VCC
MB95130MB Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 5.0 V± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK↑→ SOT delay time
tSHOVI
SCK, SOT
Parameter
Valid SIN → SCK↓
tIVSLI
SCK, SIN
SCK ↓→ valid SIN hold time
tSLIXI
SCK, SIN
SOT → SCK ↓ delay time
tSOVLI
SCK, SOT
Value
Condition
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
Max
5 tMCLK*3
⎯
ns
− 95
+95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
* + 190
MCLK 3
t
Unit
Min
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSLI
SIN
0.8 V
tSHOVI
tSOVLI
0.8 VCC
0.2 VCC
tSLIXI
0.8 VCC
0.2 VCC
49
MB95130MB Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 5.0 V± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK ↓→ SOT delay time
tSLOVI
Parameter
Value
Condition
Unit
Min
Max
SCK
5 tMCLK*3
⎯
ns
SCK, SOT
− 95
+95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
Valid SIN → SCK↑
tIVSHI
SCK↑→ valid SIN hold time
tSHIXI
Internal clock
SCK, SIN operating output pin :
CL = 80 pF + 1 TTL.
SCK, SIN
SOT → SCK↑ delay time
tSOVHI
SCK, SOT
t
* + 190
MCLK 3
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSOVHI
SOT
2.4 V
0.8 V
tIVSHI
SIN
50
tSLOVI
2.4 V
0.8 V
0.8 VCC
0.2 VCC
tSHIXI
0.8 VCC
0.2 VCC
MB95130MB Series
(8) Low voltage Detection
(AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Symbol
Min
Typ
Max
Release voltage
VDL+
2.52
2.70
2.88
V
At power-supply rise
Detection voltage
VDL−
2.42
2.60
2.78
V
At power-supply fall
Hysteresis width
VHYS
70
100
⎯
mV
Power-supply start voltage
Voff
⎯
⎯
2.3
V
Power-supply end voltage
Von
4.9
⎯
⎯
V
0.3
⎯
⎯
µs
Slope of power supply that reset release signal generates
⎯
3000
⎯
µs
Slope of power supply that reset release signal generates within rating
(VDL+)
300
⎯
⎯
µs
Slope of power supply that reset
detection signal generates
⎯
300
⎯
µs
Slope of power supply that reset
detection signal generates within rating (VDL-)
Parameter
Power-supply voltage
change time
(at power supply rise)
Unit
tr
Power-supply voltage
change time
(at power supply fall)
tf
Reset release delay time
td1
⎯
⎯
400
µs
Reset detection delay time
td2
⎯
⎯
30
µs
Consumption current
ILVD
⎯
38
50
µA
Remarks
Consumption current of low voltage
detection circuit only
51
MB95130MB Series
VCC
Von
Voff
Time
VCC
tr
tf
VDL+
VHYS
VDL-
Internal reset
signal
Time
td2
52
td1
MB95130MB Series
(9) Clock Supervisor Clock
(VCC = AVCC = 5 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Symbol
Min
Typ
Max
Oscillation frequency
fOUT
50
100
200
kHz
Oscillation start time
twk
⎯
⎯
10
µs
Current consumption
ICSV
⎯
20
36
µA
Parameter
Unit
Remarks
Current consumption of built-in
CR oscillator at 100 kHz
oscillation
53
MB95130MB Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVCC = VCC = 4.0 V to 5.5 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Unit
Min
Typ
Max
Resolution
⎯
⎯
10
bit
Total error
− 3.0
⎯
+ 3.0
LSB
− 2.5
⎯
+ 2.5
LSB
− 1.9
⎯
+ 1.9
LSB
Linearity error
⎯
Differential linear
error
Remarks
Zero transition
voltage
VOT
AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
V
Full-scale transition
voltage
VFST
AVCC − 4.5 LSB AVCC − 1.5 LSB AVCC + 0.5 LSB
V
0.9
⎯
16500
µs
4.5 V ≤ AVCC ≤ 5.5 V
1.8
⎯
16500
µs
4.0 V ≤ AVCC < 4.5 V
0.6
⎯
∞
µs
4.5 V ≤ AVcc ≤ 5.5 V,
At external impedance
< at 5.4 kΩ
1.2
⎯
∞
µs
4.0 V ≤ AVcc ≤ 4.5 V,
At external impedance
< at 2.4 kΩ
Compare time
Sampling time
54
Value
⎯
⎯
Analog input current
IAIN
− 0.3
⎯
+ 0.3
µA
Analog input voltage
VAIN
AVSS
⎯
AVCC
V
MB95130MB Series
(2) Notes on Using A/D Converter
• External impedance of analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
R
Analog input
Comparator
C
During sampling : ON
R
2.0 kΩ (Max)
8.2 kΩ (Max)
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
C
16 pF (Max)
16 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = at 0 kΩ to 20 kΩ)
100
90
80
70
60
50
40
30
20
10
0
AVCC ≥ 4.5 V
AVCC ≥ 4.0 V
0
2
4
6
8
10
12
Minimum sampling time [µs]
14
External impedance [kΩ]
External impedance [kΩ]
(External impedance = at 0 kΩ to 100 kΩ)
20
18
16
14
12
10
8
6
4
2
0
AVCC ≥ 4.5 V
AVCC ≥ 4.0 V
0
1
2
3
4
Minimum sampling time [µs]
• Errors
As |AVCC − AVSS| becomes smaller, values of relative errors grow larger.
55
MB95130MB Series
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
3FEH
1.5 LSB
3FDH
004H
003H
002H
VOT
Digital output
Digital output
3FEH
3FDH
Actual conversion
characteristic
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
1 LSB
VNT
Actual conversion
characteristic
Ideal characteristics
001H
001H
0.5 LSB
AVSS
AVCC
Analog input
1 LSB =
AVCC − AVSS
1024
(V)
AVSS
AVCC
Analog input
Total error of VNT − {1 LSB × (N − 1) + 0.5 LSB}
=
[LSB]
digital output N
1 LSB
N : A/D converter digital output value
VNT : Voltage at which digital output transits from (N-1) H to NH.
(Continued)
56
MB95130MB Series
(Continued)
Full-scale transition error
Zero transition error
Ideal
characteristics
004H
3FFH
Digital output
Digital output
Actual conversion
characteristics
003H
Ideal
characteristics
002H
Actual conversion
characteristics
Actual conversion
characteristics
3FEH
VFST
(Actual value)
3FDH
Actual conversion
characteristics
001H
3FCH
VOT (Actual value)
AVSS
AVCC
AVSS
AVCC
Analog input
Analog input
Differential linear error
Linearity error
Actual conversion
characteristics
3FFH
(N+1)H
3FDH
{1 LSB × N + VOT}
VFST
(Actual value)
VNT
004H
Actual conversion
characteristics
003H
Digital output
3FEH
Digital output
Ideal characteristics
Actual conversion
characteristics
V (N+1)T
NH
(N-1)H
VNT
Actual conversion
characteristics
Ideal characteristics
002H
(N-2)H
001H
VOT (Actual value)
AVSS
Analog input
AVCC
Linear error of = VNT − {1 LSB × N + VOT}
1 LSB
digital output N
AVSS
Analog input
Differential linear error =
of digital output N
V (N + 1) T − VNT
1 LSB
AVCC
−1
N : A/D converter digital output value
VNT : Voltage at which digital output transits from (N - 1)H to NH.
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVCC − 1.5 LSB [V]
57
MB95130MB Series
6. Flash Memory Program/Erase Characteristics
Parameter
Value
Unit
Remarks
15.0*2
s
Excludes 00H programming prior erasure.
32
3600
µs
Excludes system-level overhead.
10000
⎯
⎯
cycle
Power supply voltage at erase/
program
4.5
⎯
5.5
V
Flash memory data retention
time
20*3
⎯
⎯
year
Min
Typ
Max
Chip erase time
⎯
1.0*1
Byte programming time
⎯
Erase/program cycle
Average TA = +85 °C
*1 : TA = + 25 °C, VCC = 5.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 4.5 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
58
MB95130MB Series
■ MASK OPTION
Part number
MB95136MB
MB95F133MBS
MB95F133NBS
MB95F133JBS
MB95F134MBS
MB95F134NBS
MB95F134JBS
MB95F136MBS
MB95F136NBS
MB95F136JBS
Specifying procedure
Specify when
ordering
MASK
Setting
disabled
selectable
Single-system
clock mode
No.
Clock mode select
1 • Single-system clock mode
• Dual-system clock mode
Low voltage detection reset*
• With low voltage detection Specify when
2
reset
ordering
• Without low voltage
MASK
detection reset
Clock supervisor*
3 • With clock supervisor
• Without clock supervisor
Specify when
ordering
MASK
Reset output*
4 • With reset output
• Without reset output
Specify when
ordering
MASK
Oscillation stabilization
5
wait time
Fixed to
oscillation
stabilization
wait time of
(214 − 2) /FCH
MB95F133MBW
MB95F133NBW
MB95F133JBW
MB95F134MBW
MB95F134NBW
MB95F134JBW
MB95F136MBW
MB95F136NBW
MB95F136JBW
MB95FV100D-103
Setting
disabled
Setting
disabled
Dual-system clock
Changing by the
mode
switch on MCU board
Specified by
part number
Specified by
part number
Change by the switch
on MCU board
Specified by part
number
Specified by part
number
Change by the switch
on MCU board
Specified by part
number
MCU board switch set
as following ;
Specified by part • With supervisor :
number
Without reset output
• Without supervisor :
With reset output
Fixed to oscillation
stabilization wait
time of
(214 − 2) /FCH
Fixed to oscillation
Fixed to oscillation
stabilization wait
stabilization wait time
time of
of (214 − 2) /FCH
(214 − 2) /FCH
*: Refer to table below about clock mode select, low voltage detection reset, clock supervisor select and reset
output.
59
MB95130MB Series
Low-voltage
detection reset
Clock supervisor
Reset output
No
No
Yes
Yes
No
Yes
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Yes
Yes
No
MB95F133MBS
No
No
Yes
MB95F133NBS
Yes
No
Yes
MB95F133JBS
Yes
Yes
No
MB95F134MBS
No
No
Yes
Yes
No
Yes
MB95F134JBS
Yes
Yes
No
MB95F136MBS
No
No
Yes
MB95F136NBS
Yes
No
Yes
MB95F136JBS
Yes
Yes
No
MB95F133MBW
No
No
Yes
MB95F133NBW
Yes
No
Yes
MB95F133JBW
Yes
Yes
No
MB95F134MBW
No
No
Yes
Yes
No
Yes
MB95F134JBW
Yes
Yes
No
MB95F136MBW
No
No
Yes
MB95F136NBW
Yes
No
Yes
MB95F136JBW
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Yes
Yes
No
Part number
Clock mode select
Single - system
MB95136MB
Dual - system
MB95F134NBS
MB95F134NBW
Single - system
Dual - system
Single - system
MB95FV100D-103
Dual - system
60
MB95130MB Series
■ ORDERING INFORMATION
Part number
Package
MB95136MBPF
MB95F133MBSPF
MB95F133NBSPF
MB95F133JBSPF
MB95F134MBSPF
MB95F134NBSPF
MB95F134JBSPF
MB95F136MBSPF
MB95F136NBSPF
MB95F136JBSPF
MB95F133MBWPF
MB95F133NBWPF
MB95F133JBWPF
MB95F134MBWPF
MB95F134NBWPF
MB95F134JBWPF
MB95F136MBWPF
MB95F136NBWPF
MB95F136JBWPF
28-pin plastic SOP
(FPT-28P-M17)
MB95136MBPFV
MB95F133MBSPFV
MB95F133NBSPFV
MB95F133JBSPFV
MB95F134MBSPFV
MB95F134NBSPFV
MB95F134JBSPFV
MB95F136MBSPFV
MB95F136NBSPFV
MB95F136JBSPFV
MB95F133MBWPFV
MB95F133NBWPFV
MB95F133JBWPFV
MB95F134MBWPFV
MB95F134NBWPFV
MB95F134JBWPFV
MB95F136MBWPFV
MB95F136NBWPFV
MB95F136JBWPFV
MB2146-303A
(MB95FV100D-103PBT)
30-pin plastic SSOP
(FPT-30P-M02)
MCU board
224-pin plastic PFBGA
(BGA-224P-M08)
(
)
61
MB95130MB Series
■ PACKAGE DIMENSION
28-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
8.6 × 17.75 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
2.80 mm MAX
Weight
0.82 g
Code
(Reference)
P-SOP28-8.6×17.75-1.27
(FPT-28P-M17)
28-pin plastic SOP
(FPT-28P-M17)
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
+0.25
+.010
+0.03
*1 17.75 –0.20 .699 –.008
0.17 –0.04
+.001
.007 –.002
28
15
11.80±0.30
(.465±.012)
*2 8.60±0.20
INDEX
(.339±.008)
Details of "A" part
2.65±0.15
(Mounting height)
(.104±.006)
0.25(.010)
1
1.27(.050)
14
0.47±0.08
(.019±.003)
0.13(.005)
"A"
0~8˚
M
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.20±0.15
(.008±.006)
(Stand off)
0.10(.004)
C
2002 FUJITSU LIMITED F28048S-c-3-4
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
62
MB95130MB Series
(Continued)
30-pin plastic SSOP
Lead pitch
0.65 mm
Package width ×
package length
5.60 × 9.70 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.45 mm MAX
Code
(Reference)
P-SSOP30-5.6×9.7-0.65
(FPT-30P-M02)
30-pin plastic SSOP
(FPT-30P-M02)
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
*1 9.70±0.10(.382±.004)
30
0.17±0.03
(.007±.001)
16
INDEX
*2 5.60±0.10
(.220±.004)
7.60±0.20
(.299±.008)
Details of "A" part
+0.20
1.25 –0.10
+.008
.049 –.004
1
(Mounting height)
15
+0.08
0.65(.026)
"A"
0.25(.010)
0.24 –0.07
.009
+.003
–.003
0~8˚
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
0.10(.004)
C
2003 FUJITSU LIMITED F30003S-c-3-4
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
63
MB95130MB Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
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party or does Fujitsu warrant non-infringement of any third-party’s
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Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
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reaction control in nuclear facility, aircraft flight control, air traffic
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satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
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Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
The company names and brand names herein are the trademarks or
registered trademarks of their respective owners.
Edited
Business Promotion Dept.
F0707