MC10E445, MC100E445 5VECL 4-Bit Serial/Parallel Converter Description The MC10/100E445 is an integrated 4-bit serial to parallel data converter. The device is designed to operate for NRZ data rates of up to http://onsemi.com 2.0 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both 4-bit conversion and a two chip 8-bit conversion function. The conversion sequence was chosen to convert the first serial bit to Q0, the second to Q1 etc. PLCC−28 FN SUFFIX Two selectable serial inputs provide a loopback capability for testing CASE 776 purposes when the device is used in conjunction with the E446 parallel to serial converter. The start bit for conversion can be moved using the SYNC input. A single pulse applied asynchronously for at least two input clock cycles MARKING DIAGRAM* shifts the start bit for conversion from Qn to Qn−1. For each additional 1 28 shift required an additional pulse must be applied to the SYNC input. Asserting the SYNC input will force the internal clock dividers to “swallow” a clock pulse, effectively shifting a bit from the Qn to the Qn−1 output (see Timing Diagram B). MCxxxE445FNG The MODE input is used to select the conversion mode of the device. AWLYYWW With the MODE input LOW, or open, the device will function as a 4-bit converter. When the mode input is driven HIGH the data on the output will change on every eighth clock cycle thus allowing for an 8-bit conversion xxx = 10 or 100 scheme using two E445’s. When cascaded in an 8-bit conversion scheme A = Assembly Location the devices will not operate at the 2.0 Gb/s data rate of a single device. WL = Wafer Lot Refer to the applications section of this data sheet for more information on YY = Year cascading the E445. WW = Work Week Upon power-up the internal flip-flops will attain a random state. To G = Pb−Free Package synchronize multiple E445’s in a system the master reset must be asserted. The VBB pin, an internally generated voltage supply, is available to this *For additional marking information, refer to device only. For single-ended input conditions, the unused differential Application Note AND8002/D. input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a ORDERING INFORMATION 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When See detailed ordering and shipping information in the package not used, VBB should be left open. dimensions section on page 11 of this data sheet. The 100 Series contains temperature compensation. Features • ESD Protection: Human Body Model; > 2 kV, • On-Chip Clock ÷4 and ÷8 Machine Model; > 100 V • 2.0 Gb/s Data Rate Capability • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Differential Clock and Serial Inputs • Moisture Sensitivity Level: Pb = 1; Pb−Free = 3 • VBB Output for Single-Ended Input Applications For Additional Information, see Application Note • Asynchronous Data Synchronization AND8003/D • Mode Select to Expand to 8-Bits • Flammability Rating: UL 94 V−0 @ 0.125 in, • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V Oxygen Index: 28 to 34 with VEE = 0 V • Transistor Count = 528 devices • NECL Mode Operating Range: VCC = 0 V • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = −4.2 V to −5.7 V with VEE = 0 V • Internal Input 50 kW Pulldown Resistors • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 12 1 Publication Order Number: MC10E445/D SINB 26 SINB 27 SEL 28 25 24 RESET SINA SINA SYNC MC10E445, MC100E445 23 22 Table 1. PIN DESCRIPTION MODE NC VCCO 21 20 MC10E445 PIN 19 18 SOUT 17 SOUT 16 VCC 15 Q0 VEE 1 CLK 2 14 Q1 CLK 3 13 VCCO VBB 4 12 Q2 5 6 7 8 9 10 SINA, SINA SINB, SINB SEL Q0−Q3 CLK, CLK CL/4, CL/4 CL/8, CL/8 MODE SYNCH VBB VCC, VCCO VEE NC 11 CL/8 CL/8 VCCO CL/4 CL/4 VCCO Q3 * All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Pinout: PLCC−28 (Top View) http://onsemi.com 2 FUNCTION ECL Differential Serial Data Input A ECL Differential Serial Data Input B ECL Serial Input Selector Pin ECL Parallel Data Outputs ECL Differential Clock Inputs ECL Differential ÷4 Clock Output ECL Differential ÷8 Clock Output ECL Conversion Mode 4-Bit/8-Bit ECL Conversion Synchronizing Input Reference Voltage Output Positive Supply Negative Supply No Connect MC10E445, MC100E445 SINB SINB SINA D Q D Q Q3 D Q D Q Q2 D Q D Q Q1 D Q D Q Q0 SINA SEL SOUT SOUT 1 0 MODE CLK In Out Latch EN CLK D SYNC Q CL/4 Out ÷4 R CL/4 CL/8 Out ÷2 R D CL/8 Q VBB RESET Figure 2. Logic Diagram Table 2. FUNCTION TABLES Mode Conversion SEL Serial Input L H 4-Bit 8-Bit H L A B http://onsemi.com 3 MC10E445, MC100E445 Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 VCC PECL Mode Power Supply VEE = 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V Iout Output Current Continuous Surge IBB VBB Sink/Source TA Operating Temperature Range Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm qJC Thermal Resistance (Junction−to−Case) Standard Board Tsol Wave Solder Pb Pb−Free Condition 2 VI ≤ VCC VI ≥ VEE Rating Unit 8 V 6 −6 V V 50 100 mA mA ± 0.5 mA 0 to +85 °C −65 to +150 °C PLCC−28 PLCC−28 63.5 43.5 °C/W °C/W PLCC−28 22 to 26 °C/W 265 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 4 MC10E445, MC100E445 Table 4. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1) 0°C Symbol Characteristic Min 25°C Typ Max Min 154 185 4070 4160 4020 4170 3975 85°C Typ Max Min 154 185 4105 4190 4090 4170 3975 Typ Max Unit 154 185 mA 4185 4280 mV 4170 mV 3227 3405 mV IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 3980 VOHsout Output HIGH Voltage sout/sout 3975 VOL Output LOW Voltage (Note 2) 3050 3210 3370 3050 3210 3370 3050 VIH Input HIGH Voltage (Single−Ended) 3830 3995 4160 3870 4030 4190 3940 4110 4280 mV VIL Input LOW Voltage (Single−Ended) 3050 3285 3520 3050 3285 3520 3050 3302 3555 mV VBB Output Voltage Reference 3.62 3.74 3.65 3.75 3.69 3.81 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) 2.2 4.6 2.2 4.6 2.2 4.6 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 0.3 150 0.5 0.25 0.3 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. Table 5. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 4) 0°C Symbol Characteristic Min 25°C Typ Max Min 154 185 −930 −840 −980 −830 −1025 −1630 −1950 85°C Typ Max Min 154 185 −895 −810 −910 −830 −1025 −1630 −1950 Typ Max Unit 154 185 mA −815 −720 mV −830 mV −1595 mV IEE Power Supply Current VOH Output HIGH Voltage (Note 5) −1020 VOHsout Output HIGH Voltage sout/sout −1025 VOL Output LOW Voltage (Note 5) −1950 −1790 VIH Input HIGH Voltage (Single−Ended) −1170 −1005 −840 −1130 −970 −810 −1060 −970 −720 mV VIL Input LOW Voltage (Single−Ended) −1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445 mV VBB Output Voltage Reference −1.38 −1.27 −1.35 −1.25 −1.31 −1.19 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) −2.8 −0.4 −2.8 −0.4 −2.8 −0.4 V IIH Input HIGH Current 150 mA IIL Input LOW Current −1790 150 0.5 0.3 −1773 150 0.5 0.065 0.3 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V. 5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. http://onsemi.com 5 MC10E445, MC100E445 Table 6. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 7) 0°C Symbol Characteristic Min 25°C Typ Max Min 154 185 4050 4120 3975 4170 3975 85°C Typ Max Min 154 185 4050 4120 3975 4170 3975 Typ Max Unit 177 212 mA 4050 4120 mV 4170 mV IEE Power Supply Current VOH Output HIGH Voltage (Note 8) 3975 VOHsout Output HIGH Voltage sout/sout 3975 VOL Output LOW Voltage (Note 8) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mV VIH Input HIGH Voltage (Single−Ended) 3835 3975 4120 3835 3975 4120 3835 3975 4120 mV VIL Input LOW Voltage (Single−Ended) 3190 3355 3525 3190 3355 3525 3190 3355 3525 mV VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.74 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration Configuration) (Note 9) 2.2 4.6 2.2 4.6 2.2 4.6 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 0.3 150 0.5 0.25 0.5 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V. 8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 9. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. Table 7. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 10) 0°C5 Symbol Characteristic Min 25°C Typ Max Min 154 185 −950 −880 −1025 −830 −1025 −1620 −1810 −1745 85°C Typ Max Min Typ Max Unit 154 185 177 212 mA −950 −880 −1025 −950 −880 mV −830 −1025 −830 mV −1620 −1810 −1740 −1620 mV IEE Power Supply Current VOH Output HIGH Voltage (Note 11) −1025 VOHsout Output HIGH Voltage sout/sout −1025 VOL Output LOW Voltage (Note 11) −1810 −1705 VIH Input HIGH Voltage (Single−Ended) −1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV VIL Input LOW Voltage (Single−Ended) −1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) Configuration (Note 12) −2.8 −0.4 −2.8 −0.4 −2.8 −0.4 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 0.3 150 0.5 0.25 0.5 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V. 11. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 12. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. http://onsemi.com 6 MC10E445, MC100E445 Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 13) 0°C Symbol Characteristic Min fMAX Maximum Conversion Frequency tPLH tPHL Propagation Delay to Output CLK to Q, Reset to Q CLK to SOUT (Diff) CLK to CL/4(Diff) CLK to CL/8(Diff) ts Setup Time th Hold Time tRR Reset Recovery Time tPW Minimum Pulse Width tJITTER Random Clock Jitter (RMS) VPP Input Voltage Swing (Differential Configuration) tr tf Rise/Fall Times 20%−80% Typ 25°C Max 2.0 1800 975 1325 1325 SINA, SINB SEL −100 0 SINA, SINB, SEL 2100 1150 1550 1550 1800 975 1325 1325 −250 −200 −100 0 450 300 500 300 400 2100 1150 1550 1550 225 425 Min Typ 1800 975 1325 1325 −250 −200 −100 0 −250 −200 450 300 450 300 500 300 500 300 150 350 650 100 200 2100 1150 1550 1550 225 425 150 350 650 100 200 ps ps ps ps <1 1000 Unit ps 400 <1 1000 Max Gb/s NRZ 1500 800 1100 1100 400 150 100 200 85°C Max 2.0 1500 800 1100 1100 <1 SOUT Other Typ 2.0 1500 800 1100 1100 CLK, MR Min ps 1000 225 425 350 650 mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. 10 Series: VEE can vary −0.46 V / +0.06 V. 100 Series: VEE can vary −0.46 V / +0.8 V. 14. Devices are designed to meet the AC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. tRR Reset CLK / CLK Figure 3. http://onsemi.com 7 MC10E445, MC100E445 CLK SIN Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 RESET Q0 Dn-4 Dn Q1 Dn-3 Dn+1 Q2 Dn-2 Dn+2 Q3 Dn-1 Dn+3 SOUT Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 CL/4 CL/8 Timing Diagram A. 1:4 Serial to Parallel Conversion CLK SIN Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+4 RESET SYNC Q0 Dn-4 Dn+1 Q1 Dn-3 Dn+2 Q2 Dn-2 Dn+3 Q3 Dn-1 Dn+4 SOUT Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 CL/4 CL/8 Timing Diagram B. 1:4 Serial to Parallel Conversion With SYNC Pulse Figure 4. Timing Diagrams http://onsemi.com 8 Dn+4 MC10E445, MC100E445 APPLICATIONS INFORMATION The MC10E/100E445 is an integrated 1:4 serial to parallel converter. The chip is designed to work with the E446 device to provide both transmission and receiving of a high speed serial data path. The E445, can convert up to a 2.0 Gb/s NRZ data stream into 4-bit parallel data. The device also provides a divide by four clock output to be used to synchronize the parallel data with the rest of the system. The E445 features multiplexed dual serial inputs to provide test loop capability when used in conjunction with the E446. Figure 5 illustrates the loop test architecture. The architecture allows for the electrical testing of the link without requiring actual transmission over the serial data path medium. The SINA serial input of the E445 has an extra buffer delay and thus should be used as the loop back serial input. PARALLEL DATA SOUT SOUT CLOCK CLOCK E445a SERIAL INPUT DATA SIN SIN E445b SOUT SOUT SIN SIN Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 PARALLEL OUTPUT DATA 100ps CLOCK TO SERIAL MEDIUM Tpd CLK to SOUT 800 ps 1150 ps PARALLEL DATA SINA SINA SINB SINB Figure 6. Cascaded 1:8 Converter Architecture FROM SERIAL MEDIUM With a minimum delay of 800 ps on this output the clock for the lower order E445 cannot be delayed more than 800 ps relative to the clock of the first E445 without potentially missing a bit of information. Because the setup time on the serial input pin is negative coincident excursions on the data and clock inputs of the E445 will result in correct operation. Figure 5. Loopback Test Architecture The E445 features a differential serial output and a divide by 8 clock output to facilitate the cascading of two devices to build a 1:8 demultiplexer. Figure 6 illustrates the architecture for a 1:8 demultiplexer using two E445’s; the timing diagram for this configuration can be found on the following page. Notice the serial outputs (SOUT) of the lower order converter feed the serial inputs of the the higher order device. This feed through of the serial inputs bounds the upper end of the frequency of operation. The clock to serial output propagation delay plus the setup time of the serial input pins must fit into a single clock period for the cascade architecture to function properly. Using the worst case values for these two parameters from the data sheet, TPD CLK to SOUT = 1150 ps and tS for SIN = −100 ps, yields a minimum period of 1050 ps or a clock frequency of 950 MHz. The clock frequency is significantly lower than that of a single converter, to increase this frequency some games can be played with the clock input of the higher order E445. By delaying the clock feeding the second E445 relative to the clock of the first E445 the frequency of operation can be increased. The delay between the two clocks can be increased until the minimum delay of clock to serial out would potentially cause a serial bit to be swallowed (Figure 7). CLOCK A CLOCK B Tpd CLK to SOUT 800 ps 1150 ps Figure 7. Cascade Frequency Limitation Perhaps the easiest way to delay the second clock relative to the first is to take advantage of the differential clock inputs of the E445. By connecting the clock for the second E445 to the complementary clock input pin the device will clock a half a clock period after the first E445 (Figure 8). Utilizing this simple technique will raise the potential conversion frequency up to 1.4 GHz. The divide by eight clock of the second E445 should be used to synchronize the parallel data to the rest of the system as the parallel data of the two E445’s will no longer be synchronized. This skew problem between the outputs can be worked around as the parallel information will be static for eight more clock pulses. http://onsemi.com 9 MC10E445, MC100E445 CLOCK CLOCK E445a SERIAL INPUT DATA SIN SIN 700ps (1.4GHz) E445b CLOCK A SIN SIN SOUT SOUT Q3 Q2 Q1 Q0 100ps CLOCK B Tpd CLK to SOUT Q3 Q2 Q1 Q0 800ps Q7 Q6 Q5 Q4 1150ps Q3 Q2 Q1 Q0 PARALLEL OUTPUT DATA Figure 8. Extended Frequency 1:8 Demultiplexer CLK SINa Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Q0 Dn-4 Q1 Dn-3 Q2 Dn-2 Q3 Dn-1 Q4 (Q0 a) Dn Q5 (Q1 a) Dn+1 Q6 (Q2 a) Dn+2 Q7 (Q3 a) Dn+3 SOUTa Dn-4 Dn-3 Dn-2 SOUTb Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn-4 Dn-3 Dn-2 Dn-1 CL/4a CL/4b CL/8a CL/8b Figure 9. Timing Diagram A. 1:8 Serial to Parallel Conversion http://onsemi.com 10 Dn Dn+1 MC10E445, MC100E445 Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 10. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping † MC10E445FN PLCC−28 37 Units / Rail MC10E445FNG PLCC−28 (Pb−Free) 37 Units / Rail MC10E445FNR2 PLCC−28 500 / Tape & Reel MC10E445FNR2G PLCC−28 (Pb−Free) 500 / Tape & Reel MC100E445FN PLCC−28 37 Units / Rail MC100E445FNG PLCC−28 (Pb−Free) 37 Units / Rail MC100E445FNR2 PLCC−28 500 / Tape & Reel MC100E445FNR2G PLCC−28 (Pb−Free) 500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 11 MC10E445, MC100E445 PACKAGE DIMENSIONS PLCC−28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776−02 ISSUE E B Y BRK −N− 0.007 (0.180) U T L−M M 0.007 (0.180) M N S T L−M S S N S D Z −M− −L− W 28 D X V 1 G1 A 0.007 (0.180) R 0.007 (0.180) C M M T L−M T L−M S S N S N S H 0.007 (0.180) N S S G J 0.004 (0.100) −T− SEATING T L−M S N T L−M S N S K PLANE F VIEW S G1 M K1 E S T L−M S VIEW D−D Z 0.010 (0.250) 0.010 (0.250) VIEW S S NOTES: 1. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM −T−, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 −−− 0.025 −−− 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 −−− 0.020 2_ 10_ 0.410 0.430 0.040 −−− http://onsemi.com 12 MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 −−− 0.64 −−− 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 −−− 0.50 2_ 10_ 10.42 10.92 1.02 −−− 0.007 (0.180) M T L−M S N S MC10E445, MC100E445 ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 13 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC10E445/D