Document Number: MC33742 Rev. 11, 6/2008 Freescale Semiconductor Advance Information System Basis Chip with Enhanced High Speed CAN Transceiver 33742 33742S The 33742 and the 33742S are SPI-controlled System Basis Chips (SBCs) combining many frequently used functions along with a CAN 2.0compliant transceiver, used in many automotive electronic control units (ECUs). The 33742 SBC has a fully protected fixed 5.0V low dropout internal regulator with current limiting, over-temperature pre-warning, and reset. A second 5.0V regulator can be implemented using external pass PNP bipolar junction pass transistor driven by the SBC’s external V2 sense input and V2 output drive pins. The SBC has four main operating modes: Normal, Standby, Stop, and Sleep mode. Additionally there is an internally switched high side power supply output, four wake-up inputs pins, a programmable window watchdog, interrupt, reset, and a SPI module for communication and control. The high speed CAN A and B transceiver is available for intermodule communication. SYSTEM BASIS CHIP DW SUFFIX EG SUFFIX (PB-FREE) 98ASB42345B 28-PIN SOICW Features • 1.0Mbps CAN transceiver bus interface with bus diagnostic capability • SPI control at frequencies up to 4.0Mhz • 5.0V low dropout voltage regulator with current limiting, overtemperature prewarning, and output monitoring and reset • a Second 5.0V regulator capability using an external series pass transistor • Normal, Standby, Stop, and Sleep modes of operation with Low sleep and Stop mode current • A high side (HS) switch output driver for controlling external circuitry. • Pb-free packaging designated by suffix code EG and EP EP SUFFIX (PB-FREE) 98ASA10825D 48-PIN QFN ORDERING INFORMATION Device Temperature Range (TA) MC33742DW/R2 MCZ33742EG/R2 MC33742SDW/R2 - 40°C to 125°C MC33742EP/R2 48 QFN VPWR MCU CS SCLK MOSI MISO SPI VDD VSUP RST V2CTRL V2 CS SCLK MOSI L0 L1 L2 MISO L3 WDOG INT TXD GND RXD HS CANH CANL GND V2 VPWR Safe Circuitry ECU Local Circuitry Twisted Pair CAN Bus Figure 1. 33742 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007-2008. All rights reserved. 28 SOICW MCZ33742SEG/R2 33742 5.0V Package DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Differences During a Reset Condition Part No. Reset Duration Device Differences See Page 33742 15ms (typical) The duration the RST pin is asserted low when the Reset mode is entered after the SBC is powered up, a VDD under-voltage condition is detected, and the watchdog register is not properly triggered. page 20 33742S 3.5ms (typical) The duration the RST pin is asserted low when the Reset mode is entered after the SBC is powered up, a VDD under-voltage condition is detected, and the watchdog register is not properly triggered. page 20 33742 2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM V2CTRL V2 VSUP Monitor Dual Voltage Regulator VSUP V1 Monitor HS Control 5.0V/200mA V1 Mode Control Oscillator HS Interrupt Watchdog Reset L1 Programmable Wake-up Input L2 INT WDOG RST MOSI SPI SCLK MISO L3 CS L4 High-speed 1.0Mbps CAN Physical Interface CANH CANL TXD RXD GND Figure 2. 33742 Simplified Internal Block Diagram 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS PIN CONNECTIONS RXD TXD VDD 1 28 2 27 3 26 RST INT 4 25 5 24 GND GND GND GND V2 V2CTRL VSUP HS L0 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 WDOG CS MOSI MISO SCLK GND GND GND GND CANL CANH L3 L2 L1 Figure 3. 33742 28-Pin Connections Table 2. 33742 28-Pin Definitions A functional description of each pin can be found in the Functional Pin description section beginning on page 23. Pin Pin Name Formal Name Definition 1 RXD Receive Data CAN bus receive data output pin. 2 TXD Transmit Data CAN bus transmit data input pin. 3 VDD Voltage Digital Drain 4 RST Reset Output (Active LOW) This is the device reset output pin whose main function is to reset the MCU. This pin has an internal pullup current source to VDD. 5 INT Interrupt Output (Active LOW) This output is asserted LOW when an enabled interrupt condition occurs. The output is a push-pull structure. 6–9 20 – 23 GND Ground These device ground pins are internally connected to the package lead frame to provide a 33742-to-PCB thermal path. 10 V2 Voltage Source 2 Sense input for the V2 regulator using an external series pass transistor. V2 is also the internal supply for the CAN transceiver. 11 V2CTRL Voltage Source 2 Control Output drive source for the V2 regulator connected to the external series pass transistor. 12 VSUP Voltage Supply 13 HS High Side Output Output of the internal high side switch. The output current is internally limited to 150mA. 14 –17 L0- L3 Level 0 - 3 Inputs Inputs from external switches or from logic circuitry. 18 CANH CAN High Output CAN high output pin. 19 CANL CAN Low Output CAN low output pin. 24 SCLK Serial Data Clock Clock input pin for the Serial Peripheral Interface (SPI). 25 MISO Master In Slave Out SPI data sent to the MCU by the 33742. When CS is HIGH, the pin is in the highimpedance state. 26 MOSI Master Out Slave In SPI data received by the 33742. 27 CS Chip Select (Active LOW) 28 WDOG Watchdog Output (Active LOW) 5.0V regulator output pin. Supply pin for the MCU. Supply input pin for the 33742. The CS input pin is used with the SPI bus to select the 33742. When the CS is asserted LOW, the 33742 is the selected device of the SPI bus. The WDOG output pin is asserted LOW if the software watchdog is not correctly triggered. 33742 4 Analog Integrated Circuit Device Data Freescale Semiconductor 48 47 46 45 44 43 42 41 40 39 38 37 NC NC NC NC GND GND GND GND NC NC NC NC PIN CONNECTIONS Transparent Top View NC SCLK MISO MOSI CS WDOG RXD NC CANL CANH L3 L2 L1 L0 HS VSUP V2 CTRL V2 NC NC NC NC NC GND GND GND GND NC NC NC NC 13 14 15 16 17 18 19 20 21 22 23 24 TXD VDD RST INT NC 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 Figure 4. 33742 48-Pin Connections Table 3. 33742 48-Pin Definitions A functional description of each pin can be found in the Functional Pin description section beginning on page 23. Pin Pin Name Formal Name Definition 1, 12-16, 21-25, 36-40, 45-48 NC No Connect 2 SCLK Serial Data Clock 3 MISO Master In Slave Out SPI data sent to the MCU by the 33742. When CS is HIGH, the pin is in the highimpedance state. 4 MOSI Master Out Slave In SPI data received by the 33742. 5 CS Chip Select (Active LOW) 6 WDOG Watchdog Output (Active LOW) 7 RXD Receive Data CAN bus receive data output pin. 8 TXD Transmit Data CAN bus transmit data input pin. 9 VDD Voltage Digital Drain 10 RST Reset Output (Active LOW) This is the device reset output pin whose main function is to reset the MCU. This pin has an internal pullup current source to VDD. 11 INT Interrupt Output (Active LOW) This output is asserted LOW when an enabled interrupt condition occurs. The output is a push-pull structure. 17-20 41-44 GND Ground These device ground pins are internally connected to the package lead frame to provide a 33742-to-PCB thermal path. No connection. Clock input pin for the Serial Peripheral Interface (SPI). The CS input pin is used with the SPI bus to select the 33742. When the CS is asserted LOW, the 33742 is the selected device of the SPI bus. The WDOG output pin is asserted LOW if the software watchdog is not correctly triggered. 5.0V regulator output pin. Supply pin for the MCU. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 5 PIN CONNECTIONS Table 3. 33742 48-Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin description section beginning on page 23. Pin Pin Name Formal Name Definition 26 V2 Voltage Source 2 Sense input for the V2 regulator using an external series pass transistor. V2 is also the internal supply for the CAN transceiver. 27 V2CTRL Voltage Source 2 Control 28 VSUP Voltage Supply 29 HS High Side Output Output of the internal high side switch. The output current is internally limited to 150mA. 30-33 L0- L3 Level 0 - 3 Inputs Inputs from external switches or from logic circuitry. 34 CANH CAN High Output CAN high output pin. 35 CANL CAN Low Output CAN low output pin. Output drive source for the V2 regulator connected to the external series pass transistor. Supply input pin for the 33742. 33742 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 4. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating Symbol Value Unit ELECTRICAL RATINGS Power Supply Voltage at VSUP VSUP V Continuous (Steady-state) - 0.3 to 27 Transient Voltage (Load Dump) - 0.3 to 40 Logic Signals (RXD, TXD, MOSI, MISO, CS, SCLK, RST, WDOG, and INT) VLOG - 0.3 to VDD + 0.3 V Output Voltage at VDD VDD 0.0 to 5.3 V Output Current at VDD IDD Internally Limited A Voltage VHS - 0.3 to VSUP + 0.3 V Output Current IHS Internally Limited A HS ESD Capability, Human Body Model(1) VESD1 V MC33742 in 28-pin SOIC HS, L0, L1, L2, L3, CANH, CANL pins ± 4000 All Other pins ± 2000 MC33742 in 48-pin QFN All pins ± 2000 ESD Capability, Machine Model(1) VESD2 ± 200 V VDCIN - 0.3 to 40 V Input Voltage/Current at L0, L1, L2, L3 DC Input Voltage DC Input Current IDCIN ± 2.0 mA VTRINEC ± 100 V Continuous Voltage VCANH/L - 27 to 40 V Continuous Current ICANH/L 200 mA VLDH/L 40 V VTRH/L ± 40 V Transient Input Voltage attached to external circuitry(2) CANL and CANH CANH and CANL Transient Voltage (Load Dump)(3) CANH and CANL Transient Voltage (3) Notes 1. Testing done in accordance with the Human Body Model (CZAP = 100pF, RZAP = 1500Ω), Machine Model (CZAP = 200pF, RZAP = 0Ω). 2. 3. Testing done in accordance with ISO 7637-1. See Figure 5. Load dump testing done in accordance with ISO 7637-1, Transient test done in accordance with ISO 7637-1. See Figure 6. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 4. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating Symbol Value Unit Ambient TA - 40 to 125 Junction TJ - 40 to 150 Storage Temperature TSTG - 55 to 165 °C Thermal Resistance RθJG 20 °C/W RTJC-RθJC TBD °C/W PD 1.0 W TPPRT Note 7 °C THERMAL RATINGS Operating Temperature °C Thermal Resistance Junction Case (QFN) Power Dissipation (4) Peak Package Reflow Temperature During Reflow(6),(7) Notes 4. Maximum power dissipation is at 85°C ambient temperature in free aIr and with no heatsink, according to JEDEC JESD51-2 and JESD51-3 specifications. 5. The package is not designed for immersion soldering. The maximum soldering time is 10 seconds at 240°C on any pin. Exceeding the maximum temperature and time limits may cause permanent damage to the device. 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33742 33742 1.0nF 1.0nF Lx 10 kΩ GND Transient Pulse Generator (Note) GND Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b. Figure 5. Transient Test Setup for L0 : L3 Inputs CANH Transient Pulse Generator (Note) CANL GND 1.0nF GND Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b. Figure 6. Transient Test Setup for CANH / CANL 33742 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ VSUP ≤ 18V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max 5.5 — 18 18 — 27 Unit INPUT PIN (VSUP) Supply Voltage VSUP Nominal DC Voltage Extended DC Voltage: Full Functionality(8) (9) V 4.5 — 5.5 Load Dump — — 40 Jump Start — — 27 Extended DC Voltage: Reduced Functionality Supply Current in Standby Mode(10) (IOUT at VDD = 40mA, CAN Recessive or Sleep Mode) ISUP(STDBY) TA ≥ 25°C mA — Supply Current in Normal Mode(10) (IOUT at VDD = 40mA, CAN Recessive or Sleep mode) mA — Running(13) VSUP = 18V, Oscillator Running(12) Supply Current in Sleep Mode(10) (V1 and V2 OFF, VSUP < 13.5V, Oscillator Not Running(13), CAN in Sleep Mode with Wake-up Enabled) TA = 25°C TA = 125°C Supply Current in Stop (IOUT at VDD < 2.0mA, VDD ON, CAN in Sleep Mode with Wake-up Disabled(11)) VSUP < 13.5V, Oscillator Running(12) VSUP < 13.5V, Oscillator Not Running(13) VSUP = 18V, Oscillator Running(12) 45 μA — 85 — 53 105 80 — 110 140 μA ISUP(SLP-WE) TA = - 40°C Mode(10) 42 ISUP(SLP-WD) VSUP < 13.5V, Oscillator Running(12) VSUP < 13.5V, Oscillator Not 45 ISUP(NORM) TA ≥ 25°C Supply Current in Sleep Mode(10) (VDD and V2 OFF, CAN in Sleep Mode with CAN Wake-up Disabled(11)) 42 — 80 — — 65 — — 55 — μA ISUP(STOP-WD) — — 160 — 80 160 — 100 210 Notes 8. All functions and modes available and operating: Watchdog, HS turn ON / turn OFF, CAN transceiver operating, L0 : L3 inputs operating, normal SPI operation. The 33742 may experience an over-temperature fault. 9. At VDD > 4.0V, RST HIGH if reset 2 selected via SPI. The logic HIGH level will be degraded but the 33742 is functional. 10. Current measured at the VSUP pin. 11. If CAN Module is Sleep-enabled for wake-up, an additional current (ICAN-SLEEP) must be added to specified value. 12. 13. Oscillator running means one of the following function is active: Forced Wake-up or Cyclic Sense or Software Watchdog in Stop mode. Oscillator not running means none of the following functions are active: Forced Wake-up and Cyclic Sense and Software Watchdog in Stop mode. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ VSUP ≤ 18V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit INPUT PIN (VSUP) (CONTINUED) Supply Current in Stop Mode(14) ( IOUT at VDD < 2.0mA, VDD ON, VSUP < 13.5V, Oscillator Not Running, CAN in Sleep Mode with Wake-up Enabled)(15) TA = - 40°C — 100 — — 92 — — 80 — VBF 1.5 3.0 4.0 V VBF(HYS) — 1.0 — V 5.3 5.8 6.3 TA = 25°C TA = 125°C BATFAIL Flag Internal Threshold BATFAIL Flag Hysteresis (16) Battery Fall Early Warning Threshold VBF(EW) In Normal and Standby Modes Battery Fall Early Warning Hysteresis In Normal and Standby μA ISUP(STOP-WE) V VBF(EW-HYST) Modes(16) V 0.1 0.2 0.3 OUTPUT PIN (VDD)(17) VDD Output Voltage (2.0mA < IV1 < 200mA) VDDOUT V 5.5V < VSUP < 27V 4.9 5.0 5.1 4.5V < VSUP < 5.5V 4.0 — — Dropout Voltage VDDDRP1 IDD = 200mA Dropout Voltage, Limited Output Current and Low VSUP — VDDTEMP Bit Set 0.1 0.25 IDD mA 200 285 350 160 — 200 125 — 160 TSD Normal or Standby Mode Over-temperature Pre-warning (Junction) 0.5 V — Internally Limited Thermal Shutdown (Junction) 0.2 VDDDRP2 IDD = 50 mA, 4.5 V < VSUP Output Current V °C TPW °C Notes 14. Current measured at the VSUP pin. 15. Oscillator not running means none of the following functions are active: Forced Wake-up and Cyclic Sense and Software Watchdog in Stop mode. 16. Guaranteed by design; it is not production tested. 17. IDD is the total regulator output current. V1 specification with external capacitor. Stability requirement: Capacitance > 47μF, ESR < 1.3Ω (tantalum capacitor). In Reset, Normal Request, Normal and Standby modes. Measures with capacitance = 47μF tantalum. 33742 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ VSUP ≤ 18V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit TSD - TPW 20 — 40 °C Threshold 1, Default Value after Reset, RSTTH Bit Set to Logic [0] 4.5 4.6 4.7 Threshold 2, RSTTH Bit Set to Logic [1] 4.0 4.2 4.3 1.0 — VRSTTH 9.0V < VSUP < 18V — 5.0 25 5.5V < VSUP < 27V — 10 25 OUTPUT PIN (VDD) (CONTINUED)(18) Temperature Threshold Difference Reset Threshold VRSTTH VDD for Reset Active VDDR Line Regulation (IDD = 10mA, Capacitance = 47μF Tantalum at VDD) VDDR Load Regulation (Capacitance = 47μF Tantalum at V1) V mV VLD 1.0mA < IDD < 200mA mV — 25 75 — 30 50 IDD ≤ 2.0mA 4.75 5.0 5.25 IDD ≤ 10mA 4.75 5.0 5.25 10 17 25 Threshold 1, Default Value after Reset, RSTTH Bit Set to Logic [0] 4.5 4.6 4.7 Threshold 2, RSTTH Bit Set to Logic [1] 4.1 4.2 4.3 — 5.0 25 — 15 75 Thermal Stability VTHERM-S VSUP = 13.5V, IDD = 100mA(19) V mV OUTPUT PIN IN STOP MODE (VDD)(18) VDD Output Voltage IDD Output Current to Wake-up Reset Threshold(18) Line Regulation (Capacitance = 47μF Tantalum at VDD) VDDSTOP IDDS-WU VRST-STOP 1.0mA < IDD < 10mA mA V VLR-STOP 5.5V < VSUP < 27V, IDD = 2.0mA Load Regulation (Capacitance = 47μF Tantalum at V1) V mV VLD-STOP mV Notes 18. IDD is the total regulator output current. VDD specification with external capacitor. Stability requirement: capacitance > 47μF, ESR < 1.3Ω (tantalum capacitor). In Reset, Normal Request, Normal and Standby modes, measures with capacitance = 47μF tantalum.Selectable by RSTTH bit in SPI Register Reset Control Register (RCR). 19. Guaranteed by characterization and design; it is not production tested. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ VSUP ≤ 18V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max 0.99 1.0 1.01 200 — — 0.0 — 10 3.75 4.0 4.25 0.0 — 1.0 Unit TRACKING VOLTAGE REGULATOR (V2)(20) V2 Output Voltage (Capacitance = 10μF Tantalum at V2) V2 2.0mA ≤ IV2 ≤ 200mA, 5.5V < VSUP < 27V IV2 Output Current (for Information Only) IV2 Depending on External Ballast Transistor V2 Control Drive Current Capability(21) mA IV2CTRL Worst Case at TJ = 125°C V2LOW Flag Threshold VDD V2LTH mA V LOGIC OUTPUT PIN (MISO)(22) Low-level Output Voltage VOL IOUT = 1.5mA High-level Output Voltage VOH IOUT = -250μA Tri-stated MISO Leakage Current 0V < VMISO < VDD V V VDD - 0.9 — VDD μA IHZ - 2.0 — 2.0 Notes 20. V2 specification with external capacitor. Stability requirement: capacitance > 42μF and ESR < 1.3Ω (tantalum capacitor), external resistor between base and emitter required. Measurement conditions: ballast transistor MJD32C, capacitance > 10μF tantalum, 2.2kΩ resistor between base and emitter of ballast transistor. 21. The guaranteed V2CTRL current capability is 10mA. No active current limiting is used so the actual available current may be higher. 22. Push-pull structure with tri-state condition (CS HIGH). 33742 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ VSUP ≤ 18V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit High-level Input Voltage VIH 0.7 VDD — VDD + 0.3 V Low-level Input Voltage VIL - 0.3 — 0.3 VDD V High-level Input Current on CS I IH LOGIC INPUT PINS (MOSI, SCLK, CS) VIN = 4.0V Low-level Input Current on CS -100 — - 20 μA I IL VIN = 1.0V MOSI and SCLK Input Current μA -100 — - 20 μA I IN 0V < VIN < VDD -10 — 10 - 300 - 250 -150 IO = 1.5mA, 5.5V < VSUP < 27V 0.0 — 0.9 IO = 0mA, 1.0V <VSUP < 5.5V 0.0 — 0.9 2.3 — 5.0 0.0 — 0.9 VDD - 0.9 — VDD 0.0 — 0.9 VDD - 0.9 — VDD OUTPUT PIN (RST)(23) High-level Output Current Low-level Output Voltage RST Pulldown Current μA IOH 0V < VOUT < 0.7 VDD VOL V IPDW V > 0.9V mA OUTPUT PIN (WDOG)(24) Low-level Output Voltage VOL IO = 1.5mA, 1.0V < VSUP < 27V High-level Output Voltage V VOH IO = -250μA V OUTPUT PIN (INT)(24) Low-level Output Voltage VOL IO = 1.5 mA High-level Output Voltage V VOH IO = -250μA V Notes 23. Output pin only. Supply from VDD. Structure switch to ground with pullup current source. 24. Push-pull structure. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ VSUP ≤ 18V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit TA = 25°C, IOUT - 150mA, VSUP > 9.0V — 2.0 2.5 TA = 125°C, IOUT - 150mA, VSUP > 9.0V — — 4.5 TA = 125°C, IOUT - 120mA, 5.5V < VSUP < 9.0V — 3.5 5.5 160 — 500 TSD 155 — 190 °C ILEAK — — 10 μA OUTPUT PIN (HS) Driver Output ON Resistance Output Current Limitation ILIM VSUP - VHS > 1.0V HS Thermal Shutdown HS Leakage Current Output Clamp Voltage Ω RDS(ON) mA VCL IOUT = -10mA, No Inductive Load Drive Capability V -1.5 — - 0.3 5.5V < VSUP < 6.0V 2.0 2.5 3.0 6.0V < VSUP < 18V 2.5 3.0 3.6 18V < VSUP < 27V 2.7 3.2 3.7 5.5V < VSUP < 6.0V 2.7 3.3 3.8 6.0V < VSUP < 18V 3.0 4.0 4.6 18V < VSUP < 27V 3.5 4.2 4.7 0.6 — 1.3 -10 — 10 INPUT PINS (L0, L1, L2, AND L3) Low-voltage Detection Threshold High-voltage Detection Threshold Hysteresis VTHL VTHH V VHYS 5.5V < VSUP < 27V Input Current V V μA I IN - 0.2V < VIN < 40V CAN TRANSCEIVER CURRENT Supply Current of CAN Module CAN in Normal mode, Bus Recessive State IRES — 1.3 3.0 mA CAN in Normal mode, Bus Dominant State without Bus Load IDOM — 1.5 3.5 mA ICAN-SLEEP — 12 24 μA IDIS — — 1.0 μA CAN in Sleep State, Wake-up Enabled, V2 Regulator OFF CAN in Sleep State, Wake-up Disabled, V2 Regulator OFF(25) Notes 25. Guaranteed by design; it is not production tested. 33742 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ VSUP ≤ 18V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit VCM - 27 — 40 V Recessive State at RXD — — 500 Dominant State at RXD 900 — — 100 — — 28-pin SOIC 5.0 — 100 48-pin QFN 5.0 — 50 10 — 100 PINS (CANH AND CANL) Bus Pin Common Mode Voltage Differential Input Voltage (Common Mode Between - 3.0V and 7.0V) Differential Input Hysteresis (RXD) Input Resistance Differential Input Resistance CANH Output Voltage VCANH - VCANL VHYS mV RIN RIND kΩ VCANH kΩ V TXD Dominant State 2.75 — 4.5 TXD Recessive State — — 3.0 CANL Output Voltage mV VCANL V TXD Dominant State 0.5 — 2.25 TXD Recessive State 2.0 — — TXD Dominant State 1.5 — 3.0 V TXD Recessive State — — 100 mV Differential Output Voltage VoH - VoL Output Current Capability (Dominant State) mA CANH ICANH — — - 35 CANL ICANL 35 — — TSD 160 180 — CANL ICANL /OC 60 — 200 CANH ICANH /OC - 200 — - 60 Over-temperature Shutdown CANL Over-current Detection(26) CANH and CANL Input Current, Device Supplied (CAN Sleep mode with CAN Wake-up Enabled or Disabled) mA μA ICAN1 VCANH, VCANL from 0V to 5.0V — 3.0 10 VCANH, VCANL = - 2.0V - 60 - 50 — VCANH, VCANL = 7.0V — 60 75 VCANH, VCANL = 2.5V — 40 100 VCANH, VCANL = - 2.0V - 60 - 50 — VCANH, VCANL = 7.0V — 190 240 CANH and CANL Input Current, Device Unsupplied °C μA ICAN2 Notes 26. Reported in CAN register. For a description of the contents of the CAN register, refer to CAN Register (CAN) on page 49 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 15 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ VSUP ≤ 18V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit CANL to GND Threshold VLG — 1.75 — V CANH to GND Threshold VHG — 1.75 — V CANL to VSUP Threshold VLVB — VSUP - 2.0 — V CANH to VSUP Threshold VHVB — VSUP - 2.0 — V CANL to VDD Threshold VL5 — VDD - 0.43 — V CANH to VDD Threshold VH5 — VDD - 0.43 — V — 100 — DIAGNOSTIC INFORMATION (CANH AND CANL) RXD Weak Pull-down Current Source(27) μA IRXDW RXD Permanent Dominant Failure Condition PINS (TXD AND RXD) TXD Input High-voltage VIH 0.7 VDD — VDD + 0.4 V TXD Input Low-voltage VIL - 0.4 — 0.3 VDD V TXD High-level Input Current IIH -10 — 10 -150 - 100 - 50 VDD - 1.0 — — — — 0.5 VTXD = V2 TXD Low-level Input Current VOH IRXD = 250μA RXD Output Low-voltage IRXD = 1.0mA μA IIL VTXD = 0V RXD Output High Voltage(28) μA V VOL V Notes 27. Guaranteed by design; it is not production tested. 28. RXD is a push-pull structure between the V2 pin and GND. 33742 16 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ VSUP ≤ 18V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit SPI Operation Frequency f REQ 0.25 — 4.0 MHz SCLK Clock Period t PCLK 250 — N/A ns SCLK Clock High Time t WSCLKH 125 — N/A ns SCLK Clock Low Time t WSCLKL 125 — N/A ns Falling Edge of CS to Rising Edge of SCLK t LEAD 100 — N/A ns Falling Edge of SCLK to Rising Edge of CS t LAG 100 — N/A ns MOSI to Falling Edge of SCLK t SISU 40 — N/A ns Falling Edge of SCLK to MOSI t SIH 40 — N/A ns Time(30) t RSO DIGITAL INTERFACE TIMING (SCLK, CS, MOSI, MISO)(29) MISO Rise CL = 220pF (30) MISO Fall Time ns — 25 50 — 25 50 — — 50 — — 50 t FSO CL = 220pF ns Time from Falling or Rising Edges of CS MISO Low-impedance MISO High-impedance Time from Rising Edge of SCLK to MISO Data Valid ns t SOEN t SODIS t VALID 0.2 VDD ≤ MISO ≥ 0.8 VDD, CL = 200pF ns — — 50 18 — 34 7.0 10 13 — 100 — STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command) and Stop mode Activation(31) Interrupt Low-level Duration t CS-STOP t INT Stop Mode Internal Oscillator Frequency(32) Notes 29. 30. 31. 32. μs f OSC μs kHz See Figure 7, SPI Timing Diagram, page 22. Not production tested. Guaranteed by design. Not production tested. Guaranteed by design. Detected by V2 OFF. f OSC is indirectly measured (1.0ms reset) and trimmed. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 17 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ VSUP ≤ 18V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) (CONTINUED) Watchdog Period Normal and Standby Modes t WDOG ms 28-pin SOIC Period 1 8.58 9.75 10.92 Period 2 39.6 45 50.4 Period 3 88 100 112 308 350 392 8.3 9.75 10.92 38.5 45 50.4 86 100 112 300 350 392 28-pin SOIC 308 350 392 48-pin QFN 300 350 392 Period 1 6.82 9.75 12.7 Period 2 31.5 45 58.5 Period 3 70 100 130 Period 4 245 350 455 Normal and Standby Modes -12 — 12 Stop Mode - 30 — 30 Timing 1 3.22 4.6 5.98 Timing 2 6.47 9.25 12 Timing 3 12.9 18.5 24 Timing 4 25.9 37 48.1 Timing 5 51.8 74 96.2 Timing 6 66.8 95.5 124 Timing 7 134 191 248 Timing 8 271 388 504 Period 4 48-pin QFN Period 1 Period 2 Period 3 Period 4 Normal Request Mode Timeout Watchdog Period Stop Mode Watchdog Period Accuracy Cyclic Sense / FWU Timing Sleep and Stop Modes Cyclic Sense ON Time t NRTOUT t WD-STOP Sleep and Stop modes ms t ACC % t CSFWU ms t ON Sleep and Stop modes. Cyclic Sense / FWU Timing Accuracy ms μs 200 350 500 - 30 — 30 t ACC % 33742 18 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ VSUP ≤ 18V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ — — Max Unit STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) (CONTINUED) Delay Between SPI Command and HS Turn ON(33) t S-HSON Delay Between SPI Command and HS Turn OFF(33) t S-HSOFF — 22 t S-V2ON Command(33) Normal Request mode — 22 t S-V2OFF μs 9.0 Normal mode Delay Between Normal Request and Normal mode After Watchdog Trigger μs 9.0 Standby mode Delay Between SPI and V2 Turn OFF(33) μs — Normal or Standby mode, VSUP > 9.0V Delay Between SPI and V2 Turn ON(33) μs 22 Normal or Standby mode, VSUP > 9.0V — 22 t S-NR2N μs 15 35 70 Notes 33. Delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn ON” or “Turn OFF” of HS or V2. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 19 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ VSUP ≤ 18V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max — — 10 — — 10 Unit STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) (CONTINUED) Delay Between SPI and CAN Normal mode(34) t S-CAN_N Normal mode(35) Delay Between SPI and CAN Sleep Mode(34) Normal mode t S-CAN_S (35) Delay Between CS Wake-up (CS LOW to HIGH) and Device in Normal Request mode (VDD ON and RST HIGH) μs μs t W-CS Stop mode μs 15 Delay Between CS Wake-up (CS LOW to HIGH) and First Accepted SPI Command μs 90 — N/A 20 — N/A 25 — — t S-1STSPI Device in Stop mode After Wake-up Delay Between Two SPI Messages Addressing the Same Register 90 t W-SPI Device in Stop mode After Wake-up Delay Between INT Pulse and First SPI Command Accepted 40 t 2SPI μs μs OUTPUT PIN (VDD) Reset Delay Time μs tD Measured at 50% of Reset Signal 4.0 — 30 tIDD-DGLT 40 55 75 33742 t RSTDUR 12 15 18 33742S t RSTDURS 3.0 3.5 4.0 t WUF 8.0 20 38 IDD Over-current to Wake-up Deglitcher Time(35) μs OUTPUT PIN (RST) Reset Duration After VDD HIGH ms INPUT PINS (L0, L1, L2, AND L3) Wake-up Filter Time μs Notes 34. Delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn ON” or “Turn OFF” of HS or V2. 35. Guaranteed by design; it is not production tested. 33742 20 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ VSUP ≤ 18V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit t DOUT 200 360 520 μs Slew Rate 3 60 100 210 Slew Rate 2 70 110 225 Slew Rate 1 80 130 255 Slew Rate 0 110 200 310 Slew Rate 3 20 65 110 Slew Rate 2 25 80 150 Slew Rate 1 35 100 200 Slew Rate 0 50 160 300 10 50 140 CAN MODULE – SIGNAL EDGE RISE AND FALL TIMES (CANH, CANL) Dominant State Timeout Propagation Loop Delay TXD to RXD (Recessive to Dominant)(36) Propagation Delay TXD to CAN (Recessive to Dominant)(37) t LRD ns t TRD Propagation Delay CAN to RXD (Recessive to Dominant)(38) t RRD Propagation Loop Delay TXD to RXD (Dominant to Recessive)(36) t LDR ns ns Slew Rate 3 100 150 200 Slew Rate 2 120 165 220 Slew Rate 1 140 200 250 Slew Rate 0 250 340 410 Slew Rate 3 60 125 150 Slew Rate 2 65 150 190 Slew Rate 1 75 180 250 200 310 460 t RDR 20 30 60 t SL3 t SL2 t SL1 t SL0 4.0 19 40 3.0 13.5 20 2.0 8.0 15 1.0 5.0 10 tBUS 60k — 1.0M Propagation Delay TXD to CAN (Dominant to Recessive)(37) t TDR Slew Rate 0 Propagation Delay CAN to RXD (Dominant to Recessive) (38) ns Non-Differential Slew Rate (CANL or CANH) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 Bus Communication Rate ns ns V/μs bps Νοτεσ 36. See Figure 8, page 22. 37. See Figure 9, page 22. 38. See Figure 10, page 22. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 21 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS t PCLK CS t WSCLKH t LEAD t LAG SCLK t WSCLKL t SIH t SISU MOSI Undefined DI 8 Don’t Care DI 0 Don’t Care t VALID t SODIS t SOEN MISO DO 0 DO 8 Note Incoming data at MOSI pin is sampled by the 33742 at SCLK falling edge. Outgoing data at MISO pin is set by the 33742 at SCLK rising edge (after t VALID delay time). Figure 7. SPI Timing Diagram tLRD TXD tTRD TXD 0.8 V 2.0 V 2.0 V tTDR 0.8 V tLDR 0.9 V VDIFF 0.5 V 2.0 V RXD VDIFF = VCANH - VCANL 0.8 V Figure 9. Propagation Delay TXD to CAN Figure 8. Propagation Loop Delay TXD to RXD tRDR 0.9 V VDIFF tRRD 0.5 V 2.0 V RXD 0.8 V Figure 10. Propagation Delay CAN to RXD 33742 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33742 and the 33742S are system basis chips (SBCs) dedicated to automotive applications. Their functions include the following: • One fully protected 5.0V voltage regulator with 200mA total output current capability available at the VDD pin. • VDD regulator under-voltage reset function, programmable window or time-out software watchdog function. • Internal driver (V2) for an external series pass transistor to implement a second 5.0V voltage regulator. • Two running modes: Normal and Standby modes set by the system microcontroller. • Sleep and Stop modes low power operating modes to reduce an application’s current consumption while providing a wake-up capability from the CAN interface, L3 : L0 wake-up inputs, or from a timer wake-up. • Programmable wake-up input and cyclic sense wakeups. • CAN high-speed physical bus interface with TXD and RXD fault diagnostic capability and enhanced protection features. • An SPI interface for use in communicating with a MCU and Interrupt outputs to report SBC status, perform diagnostics, and report wake-up events. FUNCTIONAL PIN DESCRIPTION RECEIVE AND TRANSMIT DATA (RXD AND TXD) The RXD and TXD pins (receive data and transmit data pins, respectively) are connected to a microcontroller’s CAN protocol handler. TXD is an input and controls the CANH and CANL line state (dominant when TXD is LOW, recessive when TXD is HIGH). RXD is an output and reports the bus state (RXD LOW when CAN bus is dominant, HIGH when CAN bus is recessive). The RXD terminal is a push-pull structure between the V2 pin and GND. Voltage Digital Drain (VDD) The VDD pin is the output pin of the 5.0V internal regulator. It can deliver up to 200mA. This output is protected against over-current and over-temperature. It includes an overtemperature pre-warning flag, which is set when the internal regulator temperature exceeds 130°C typical. When the temperature exceeds the over-temperature shutdown (170°C typical), the regulator is turned off. VDD includes an under-voltage reset circuitry, which sets the RST pin LOW when VDD is below the under-voltage reset threshold. RESET OUTPUT (RST) The Reset pin RST, is an output that is set LOW when the device is in reset mode. The RST pin is set HIGH when the device is not in reset mode. RST includes an internal pullup current source. When RST is LOW, the sink current capability is limited, allowing RST to be shorted to 5.0V for software debug or software download purposes. INTERRUPT OUTPUT (INT) The Interrupt pin INT, is an output that is set LOW when an interrupt occurs. INT is enabled using the Interrupt Register (INTR). When an interrupt occurs, INT stays LOW until the interrupt source is cleared. INT output also reports a wake-up event by a 10μs typical pulse when the device is in Stop mode. VOLTAGE SOURCE 2 (V2) The V2 pin is the input sense for the V2 regulator. It is connected to the external series pass transistor. V2 is also the 5.0V supply of the internal CAN interface. It is possible to connect V2 to an external 5.0V regulator or to the VDD output when no external series pass transistor is used. In this case, the V2CTRL pin must be left open. Refer to Figure 31, SBC Typical Application Schematic, page 57. VOLTAGE SOURCE 2 CONTROL (V2CTRL) The V2CTRL pin is the output drive pin for the V2 regulator connected to the external series pass transistor. VOLTAGE SUPPLY (VSUP) The VSUP pin is the battery supply input of the device. HIGH-SIDE OUTPUT (HS) The HS pin is the internal high side driver output. It is internally protected against over-current and overtemperature. LEVEL 0-3 INPUTS (L0: L3) The L0 : L3 pins can be connected to contact switches or the output of other ICs for external inputs. The input states can be read by SPI. These inputs can be used as wake-up events for the SBC when operating in the Sleep or Stop mode. CAN HIGH AND CAN LOW OUTPUTS (CANH AND CANL) The CAN High and CAN Low pins are the interfaces to the CAN bus lines. They are controlled by TXD input level, and 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION the state of CANH and CANL is reported through RXD output. A 60Ω termination resistor is connected between CANH and CANL pins. MASTER OUT SLAVE IN (MOSI) MOSI is the Master Out Slave In pin of the serial peripheral interface. Control data from a microcontroller is received through this pin. SERIAL DATA CLOCK (SCLK) SCLK is the Serial Data Clock input pin of the serial peripheral interface. CHIP SELECT (CS) CS is the Chip Select pin of the serial peripheral interface. When this pin is LOW, the SPI port of the device is selected. MASTER IN SLAVE OUT (MISO) MISO is the Master In Slave Out pin of the serial peripheral interface. Data is sent from the SBC to the microcontroller through the MISO pin. WATCHDOG OUTPUT (WDOG) The Watchdog output pin is asserted LOW to flag that the software watchdog has not been properly triggered. 33742 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION MC33742 - Functional Block Diagram Integrated Supply Outputs VSUP Control & Monitor 5.0V Linear Regulator (LDO) Analog Circuitry 5.0V Regulator Base PNP Drive Mode Control Oscillator Programmable Wake-up High-side Switch MCU Interface SPI Interface CAN Interface / Control Reset & INT Watchdog Timer Integrated Supply Analog Circuitry CAN Physical Layer Interface MCU Interface Outputs OUTPUTS INTEGRATED SUPPLY 5.0V LINEAR REGULATOR (LDO) VSUP CONTROL & MONITOR This low dropout linear regulator (V1) outputs a regulated 5.0V at 200mA. The associated monitoring circuit provides detection of under-voltage, over-current, and short-circuit conditions, as well as over-temperature and a reset function. This circuitry protects the IC from transient conditions such as vehicle jump-start (27V) and load dump (40V). If the VSUP voltage falls below 3.0V (or a 6.0V warning interrupt), an under-voltage detection is reported. 5.0V REGULATOR BASE PNP DRIVE ANALOG CIRCUITRY The V2 linear regulator control circuitry provides drive for an external series pass transistor (PNP type). The 5.0V output tracks the V1 regulator OSCILLATOR This circuit is used to generate the internal timings for reset, watchdog, cyclic wake-up, filtering time, etc. HIGH SIDE SWITCH The high switch provides a 2.0 Ohm (typ.) RDSON MOSFET driver connected to the VSUP pin. The output is protected against short-circuit conditions and provides overtemperature shutdown. MODE CONTROL CAN PHYSICAL LAYER INTERFACE PROGRAMMABLE WAKE-UP This circuitry provides communication between the TXD & RXD pins, from/to the MCU, and the CANL & CANH pins of the CAN physical interface. The various modes of the CAN interface are controlled through the SPI control registers. The 4 inputs are used in conjunction with various SPI control register bits to determine the wake-up conditions and the reaction of the IC. They can be connected to contact switches or other ICs. The 4 operating modes of the IC are controlled through the SPI control registers. There are also several special modes possible. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION MCU INTERFACE WATCHDOG TIMER The IC and the MCU communicate using the SPI control and status reporting registers. The clock speed (SCLK) can be as high as 4.0MHz. The timer can be used as a watchdog window or watchdog timeout function. The SPI control register provide the choice as well as the timeout value. When the watchdog timer is not properly serviced by the MCU, an error signal (WDOGN low) and a reset signal (RSTN low) are output. RESET & INT CAN INTERFACE/CONTROL These 2 outputs notify the MCU when the IC is in reset mode, or when an enabled interrupt condition has occurred. The operation of the CAN interface is controlled by the MCU through the use of SPI control register bits. SPI INTERFACE 33742 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION SUPPLY VOLTAGE AT VSUP The 33742 receives its operating voltage via the VSUP pin. An external diode is needed in series with the VSUP pin and the supply voltage to protect the SBC against negative transients or from a reverse battery situation that can occur in a vehicle application. The 33742 will operate from a supply voltage input as low as 4.5VDC to as high as 27VDC. The later voltage is often encountered during a vehicle jump-start. The VSUP pin can tolerate automotive transient conditions such as load dump to 40V. The SBC is able to detect when VSUP falls below 3.0V typical. This under-voltage state is detected and retained in the parts Mode Control Register (MCR) as the BATFAIL bit. This detection capability is available across all operating modes. Note For a detailed description of all the registers mentioned in this section, refer to the section titled SPI Interface And Register Description beginning on page 47. The SBC incorporates a VSUP level early warning function, which provides a maskable interrupt if the VSUP voltage level falls below 6.0V typical. Hysteresis is used to reduce false detections. The early warning function works only in Normal and Standby operation modes. An under-voltage at the VSUP pin is reported in the Input / Output Register (IOR). VDD REGULATOR The VDD regulator provides a 5.0V low dropout voltage capable of supplying up to 200mA with monitoring circuitry for under-voltage detection and a reset function. The VDD regulator is protected against over-current and short-circuit conditions. It has over-temperature detection and will set warning flags (bit VDDTEMP in the MCR and INTR registers) and has over-temperature shutdown with hysteresis. V2 REGULATOR The V2 regulator feature provides for a second 5.0VDC voltage source The internal V2 circuitry will drive an external series pass transistor, substantially increasing the available supply current. Two pins, the V2 and the V2CTRL, are used to sense and drive the series pass transistor. The output voltage is 5.0V and tracks the VDD regulator. The MJD32C transistor is recommended for use as the external pass device. Other PNP transistors can be used but depending on the device’s gain, an external resistor-capacitor network might be needed. V2 is also the supply voltage for the onboard CAN module. An under-voltage condition for the V2 voltage is reported in the IOR Register (bit V2LOW set to logic [1] if V2 falls below 4.0V typical). HS VSUP SWITCH OUTPUT The HS output is a 2.0Ω typical switch tied to the VSUP pin. It can power or bias external switches and their associated pullup or put-downs or other circuitry. An example is biasing a set of switches connected to the L0 : L3 wake-up input pins. The HS VSUP output current is limited to 200mA and is protected against short circuits conditions and will report an over-temperature shutdown condition (bit HSOT in the IOR register and bit HSOT - V2LOW in the INTR register). The HS output “on” state is set by the HSON bit in the IOR register. A cyclic mode of operation can be implemented using an internal timer in the Sleep and Stop operating modes. It can also be turned on in Normal or Standby modes to drive loads or supply peripheral components. No internal protection circuitry is provided, however. Dedicated chip protection circuitry is required for inductive load applications. The HS output pin should not go below - 0.3V. BATTERY FAIL EARLY WARNING Refer to the previous discussion under the heading, Supply Voltage at VSUP. INTERNAL CLOCK The 33742 has an internal clock used to generate all timings (reset, watchdog, cyclic wake-up, filtering time, etc.). There are two on-board oscillators: a higher accuracy (±12 percent) oscillator used in Normal Request, Normal, and Standby modes, and a lower accuracy (±30 percent) oscillator used during Sleep and Stop modes. OPERATIONAL MODES INTRODUCTION STANDBY MODE The 33742 has four modes of operation, all controllable via the SPI. The modes are Standby, Normal, Stop, and Sleep. An additional temporary mode called Normal Request mode is automatically accessed by the device after reset or wakeup from Stop mode. A Reset mode is also implemented. Special modes and configurations are possible for debug and program microcontroller flash memory. Table 7, page 29, offers a summary of the functional modes. In Standby mode only the VDD regulator is ON. The V2 regulator is turned OFF by disabling the V2CTRL pin. Other functions available are the L0 : L3 inputs read through via the SPI and HS output activation. The CAN interface is not able to send messages. If a CAN message is received, the CANWU bit is set. The watchdog timer is running. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES NORMAL MODE RESET MODE In Normal mode, both the VDD and V2 regulators are in the ON state. All functions are available in this operating mode (watchdog, wake-up input reading through SPI, HS activation, and CAN communication). The watchdog timer is running and must be periodically cleared through SPI. In the Reset mode, the RST pin is LOW and a timer runs for t RSTDUR time. After t RSTDUR has elapsed, the 33742 enters the Normal Request operating mode. The Reset mode is entered if a reset condition occurs (VDD LOW, watchdog time-out, or watchdog trigger in a closed window). STOP MODE NORMAL REQUEST MODE The V2 regulator is turned OFF by disabling the V2CTRL pin. The VDD regulator is activated in a special low power mode supplying only a few mA of current. This maintains “keep alive” power for the application’s MCU while the MCU is in a power-saving state (i.e., a MCU’s version of Stop or Wait). In the Stop mode, the supply current available from VSUP pin is very low. Both parts (the SBC or the MCU) can be awakened from either the 33742 side (for example, cyclic sense, forced wake-up, CAN message, wake-up inputs, and over-current on VDD) or from the MCU side (key wake-up, etc.). Stop mode is always selected via SPI. In Stop mode, the watchdog software may be either running or not running depending upon selection by SPI (Reset Control Register [RCR], bit WDSTOP). To clear a running watchdog timer, the SBC must be awakened using the CS pin (SPI wake-up). In Stop mode, wake-up is identical to that in Sleep mode, with the addition of CS and VDD over-current wake-up. Refer to Table 7, page 29. The Normal Request mode is a temporary operating mode automatically entered by the SBC after the Reset mode or after the 33742 wakes up from the Stop mode. After a wake-up from the Sleep mode or after a device power-up, the SBC enters the Reset mode prior to entering the Normal Request mode. After a wake-up from the Stop mode, the 33742 enters the Normal Request mode directly. In Normal Request mode, the VDD regulator is ON, the V2 regulator is OFF, and the RST pin is HIGH. As soon as the SBC enters the Normal Request mode, an internal 350ms timer is started (parameter tNRTOUT). During this time, the application’s MCU must address the 33742 via SPI and configure the TIM1 sub register to select the watchdog period. This is required of the SBC to stop the 350ms watchdog timer and enter the Normal or Standby mode and to set the watchdog timer configuration. SLEEP MODE In Sleep mode, the VDD and V2 regulators are OFF. Current consumption from the VSUP pin is cut. In Sleep mode, the SBC can be awakened by sensing individual level individual level changes in the L0 : L3 inputs, by cyclic checking of the L0 : L3 inputs, by the forced wake-up timer, or from the CAN physical interface upon receiving a CAN message. When a wake-up occurs, the SBC goes first into the Reset mode before entering Normal Request mode. NORMAL REQUEST ENTERED AND NO WATCHDOG CONFIGURATION OCCURS If the Normal Request mode is entered after the SBC powers up or after a wake-up from Stop mode and no watchdog configuration occurs before the 350ms time period has expired, the device enters the Reset mode. If no watchdog configuration is performed, the 33742 will cycle from the Normal Request mode to Reset mode to Normal Request mode. If the Normal Request mode is entered after a wake-up from Sleep mode, and no watchdog configuration occurs while the 33742S is in Normal Request mode, the SBC returns to the Sleep mode. 33742 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 7. Table of Operations Mode Voltage Regulator HS Switch Wake-up Capabilities (if Enabled) RST Pin INT Pin Watchdog Software CAN Cell – – – Running TXD / RXD Running Low power Normal Request VDD: ON, V2: OFF, HS: OFF – Low for t RSTDUR time, then HIGH Normal VDD: ON, V2: ON, HS: Controllable – Normally HIGH. If enabled, signal Active LOW if WDOG failure (VDD Pre-warning or VDD under-voltage Temp, CAN, HS) occurs Standby VDD: ON, V2: OFF, HS: Controllable – Same as Normal mode Same as Normal mode Stop VDD: ON (Limited Current Capability), V2: OFF, HS:OFF or Cyclic Sense CAN, SPI, L0 : L3, Cyclic Sense, Forced Wake-up, IDD Over-current(40) Normally HIGH. Active LOW if WDOG(41) or VDD under-voltage occurs Signal 33742S wake-up and IDD > IDDS-WU (not maskable) Sleep VDD: OFF, V2: OFF, HS: OFF or Cyclic CAN, SPI, L0 : L3, Cyclic Sense Forced Wake-up LOW Not Active Normal Debug(39) Same as Normal – Standby Debug(39) Same as Standby – Stop Debug(39) Same as Stop Flash Programming Forced externally Running if Low power. enabled. Wake-up capability Not running if if enabled disabled Not running Low power. Wake-up capability if enabled Normally HIGH. Same as Normal Active LOW if VDD under-voltage occurs Not running Same as Normal Normally HIGH. Same as Standby Active LOW if VDD under-voltage occurs Not running Same as Standby Same as Stop Normally HIGH. Active LOW if VDD under-voltage occurs Same as Stop Not running Same as Stop – Not operating Not operating Not operating Not operating Notes 39. Mode entered via special sequence described under the heading Debug Mode: Hardware and Software Debug with the 33742, beginning on page 34. 40. IDD over-current always enabled. 41. WDOG if enabled. APPLICATION WAKE-UP FROM THE 33742 STOP MODE CURRENT MONITOR When the application is in Stop mode, it can be awakened from the SBC side. When a wake-up condition is detected by the SBC (for example, CAN, wake-up input), the 33742 enters the Normal Request mode and generates an interrupt pulse at the INT pin. If the VDD output current exceeds an internal set threshold (IDDS-WU), the SBC automatically enters the Normal Request mode and generates an interrupt at the INT pin. The interrupt is a non-maskable and the INTR register will have no flag set. APPLICATION WAKE-UP FROM THE MCU When the device is in the Stop mode, a wake-up event may come from the system MCU. In this case the MCU selects the device the using a LOW-to-HIGH transition on the 33742 CS pin. Then the 33742S goes into Normal Request mode and generates an interrupt pulse at the INT pin. INTERRUPT GENERATION WHEN WAKE-UP FROM STOP MODE When the SBC wakes from Stop mode, it first enters the Normal Request mode before generating a 10 μs typical pulse on the INT pin. These are non-maskable interrupts with the wake-up event read through the SPI registers, the CANWU bit in the CAN Register (CANR), or the LCTRx bit in the Wake-up Register (WUR). In case of wake-up from Stop 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES mode over-current situation or from forced wake-up, no bits are set. After the INT pulse, the 33742 accepts SPI command after a time delay (t S-1STSPI). WATCHDOG SOFTWARE IN STOP MODE If the SBC watchdog is enabled, the application must provide a “system ok” response before the end of the 33742 watchdog time. Typically an MCU initiates the wake-up of the 33742 through the SPI wake-up (CS activation). The SBC will awaken and jump into the Normal Request mode. The MCU has to configure the 33742 to go to either Normal or Standby mode. The MCU can then decide to return to the Stop mode. If no MCU wake-up occurs within the watchdog time period, the SBC activates the RST pin and jumps into the Normal Request mode. The MCU can then be re-initialized. STOP MODE ENTER COMMAND Stop mode is entered at the end of the SPI message at the rising edge of the CS. (Refer to the t CS-STOP data in the Dynamic Electrical Characteristics table on page 17.) Once Stop mode is entered, the SBC can wake up from a VDD regulator over-current detection state. In order to allow time for the MCU to complete the last CPU instruction and enter its low power mode, a deglitcher time of 40μs typical is implemented. Figure 11, page 30, depicts the operation of entering the Stop mode. SPI Stop/Sleep Command SPI CS t CS-STOP 33742 in Normal or Standby mode t IDD-DGLT 33742 in Stop mode. No IDD over IDD-DGLT 33742 in Stop mode. IDD over IDD-DGLT Figure 11. Entering the Stop Mode WATCHDOG SOFTWARE (RST AND WDOG) (SELECTABLE WATCHDOG WINDOW OR WATCHDOG TIME-OUT) A watchdog is used in the SBC Normal and Standby modes for monitoring the MCU operation. The watchdog timer may be implemented as either a watchdog window or watchdog timeout, selectable by SPI (TIM1 sub register, bit WDW). Default operation is a watchdog window. The watchdog period can be set from 10ms to 350ms (TIM1 sub register, bits WDT0 and WDT1). When a watchdog window is selected, the closed window is the first part of the selected period, and the open window is the second part of the period. (Refer to Timing Register (TIM1 / 2) beginning on page 52.) The watchdog can only be cleared within the open window time period. Any attempt to clear watchdog in the closed window will generate a reset. The watchdog is cleared addressing the TIM1 sub register using the SPI RST PIN DESCRIPTION A 33742 output is available to perform a reset of the MCU. Reset can happen from: • VDD Falling Out of Range — If VDD falls below the reset threshold (V RSTTH), the RST pin is pulled LOW until VDD returns to the normal voltage. • Power-ON Reset — At 33742 power-on or wake-up from Sleep mode, the RST pin is maintained LOW until VDD is within its operation range. • Watchdog Timeout — If watchdog is not cleared, the 33742 will pull the RST pin LOW for the duration of the reset time (t RSTDUR). RST AND WDOG OPERATION Table 8 describes watchdog and reset output modes of operation. RST is activated in the event VDD fall or watchdog is not triggered. WDOG output is active LOW as soon as RST goes LOW and stays LOW as long as the watchdog is not properly reset via SPI. The WDOG output pin is designed as a push-pull structure that can drive off chip components signaling, for instance, errant MCU operation. Figure 12 illustrates the device behavior in the event the TIM1 register in not properly accessed. In this case, a software reset occurs and the WDOG pin is set LOW until the TIM1 register is properly accessed. 33742 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 8. Watchdog and Reset Output Operation Events WDOG Output RST Output Device Power-Up LOW to HIGH LOW to HIGH VDD Normal, WDOG Properly Triggered HIGH HIGH VDD < VRSTTH HIGH LOW WDOG Time-out Reached LOW (42) LOW Notes 42. WDOG stays LOW until the TIM1 register is properly addressed through SPI. Device power up Device is in Normal mode, W/D refresh failure VSUP VDD VDD RST RST WDOG WDOG SPI Watchdog Period SPI Mode RESET N-Request Normal SPI CS Power up Watchdog refresh failure Device is in stop mode Device is in sleep mode VSUP VSUP VDD VDD RST INT WDOG WDOG SPI SPI Mode Sleep RESET N-Request Normal Mode Stop N-Request Normal Wake-up event Wake up event Legend: TIM1 register write Figure 12. RST and WDOG Output Operation WAKE-UP CAPABILITIES Several wake-up capabilities are available to the SBC when it is in Sleep or Stop mode. When a wake-up has occurred, the wake-up event is stored in the Wake-up Register (WUR) or the CAN register and read by the MCU to determine the wake-up source. The wake-up options are selectable through SPI while the 33742 is in Normal or Standby mode and prior to entering low power modes (Sleep or Stop mode). When a wake-up occurs in Sleep mode, the SBC reactivates the VDD supply. It generates an interrupt if a wake-up occurs from Stop mode. WAKE-UP FROM WAKE-UP INPUTS (L0 : L3) WITHOUT CYCLIC SENSE The wake-up lines are used to determine the state of external switches and if changes occurred to wake up the MCU (in Sleep or Stop modes). The wake-up pins L0 : L3 are able to handle up to 40VDC. The internalize” threshold is 3.0V typical, and these inputs can be used as an input port 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES expander. The wake-up input states are read through SPI (WUR register). In order to select and activate direct wake-up from the L0 : L3 inputs, the WUR register must be configured with the appropriate level sensitivity. Additionally, the Low Power Control (LPC) Register must be configured with 0xx0 data (bits LX2HS and HSAUTO are set to 0). The sensitivity of the L0 : L3 inputs is selected by the WUR register. Level sensitivity is configured by L0 : L3 input pairs: L0 and L1 level sensitivity are configured together, while L2 and L3 are configured together. CYCLIC SENSE WAKE-UP (CYCLIC SENSE TIMER AND WAKE-UP INPUTS L0 : L3) The 33742 can wake up upon state change of one of the four wake-up input lines (L0 : L3). The external pullup or pulldown resistor of the switches associated with the wake-up input lines can be biased from the HS VSUP switch. The HS switch is activated in Sleep or Stop modes from an internal timer. Cyclic Sense and Forced Wake-up are exclusive states. If Cyclic Sense is enabled, Forced Wake-up cannot be enabled. In order to select and activate the cyclic sense wake-up from the L0 : L3 inputs, the WUR register must be configured with the appropriate level sensitivity and the LPC register must be configured with 1xx1 data (bit LX2HS set at 1 and bit HSAUTO set at 1). The wake-up mode selection (direct or cyclic sense) is valid for all four wake-up inputs. FORCED WAKE-UP The SBC can wake up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic Sense and Forced Wake-up are exclusive. If Forced Wake-up is enabled (FWU bit set to 1 in the LPC register), Cyclic Sense cannot be enabled. CAN INTERFACE WAKE-UP The SBC incorporates a high-speed 1.0 Mbps CAN physical interface. It is compatible with ISO 11898-2 standard. The operation of the CAN physical interface is controlled through the SPI. The CAN operating modes are independent of the 33742 operational modes. The SBC can wake up from a CAN message if the CAN wake-up feature is enabled. Refer to the section titled LOGIC COMMANDS AND REGISTERS beginning on page 47 for details of the wake-up detection. SPI WAKE-UP The 33742 can be awakened by changes on the CS pin in Sleep or Stop modes. Wake-up is detected as a LOW-toHIGH level transition on the CS pin. In the Stop mode, this corresponds to a condition where an MCU and the SBC are both in the Stop mode and when the application wake-up event comes through the MCU. 33742 POWER-UP AND WAKE-UP FROM SLEEP MODE After device or system power-up, or after the SBC awakens from Sleep mode, the 33742S enters into the Reset mode prior to moving into Normal Request mode. Figure 13, shows the device state diagram. Figure 14, shows device operation after power-up. 33742 32 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Watchdog: Timeout OR VDD Low Watchdog: Timeout & Nostop &!BATFAIL V DD Power Down Lo w 2 (4 4) 1 Stop SPI: Stop & CS LOW to HIGH Transition Watchdog: Timeout OR VDD Low Nostop and SPI: Sleep & CS LOW to HIGH Transition R Normal 1 Nostop and SPI: Sleep & CS LOW to HIGH ut O SPI: Normal :T im eo 4 Standby 3 SP do g VDD Low OR Watchdog: Timeout 350 ms & Nostop Wake-Up ch Normal Request 1 g: do ch r at e W rigg T 33742S Power- 1 I: H Sto ig p h & Tr C an S s i Lo tio w n to Reset W at SPI: Standby and Watchdog Trigger 2 SPI: Standby Reset Counter (3.4 ms) Expired Wake-Up (VDD High Temperature OR [VDD Low > 100 ms & VSUP > BFew]) & Nostop &!BATFAIL 1 2 3 4 Sleep Denotes priority State Machine Description Nostop = Nostop bit = 1 ! Nostop = Nostop bit = 0 BATFAIL = Batfail bit = 1 ! BATFAIL = Batfail bit = 0 VDD Over-temperature = VDD thermal shutdown occurs VDD LOW = VDD below reset threshold VDD LOW > 100 ms = VDD below reset threshold for more than 100 ms Watchdog: Trigger = TIM1 subregister write operation VSUP > BFew = VSUP > Battery Fail Early Warning (6.1 V typical) Watchdog: Timeout = TIM1 register not written before watchdog timeout period expired, or watchdog written in incorrect time window if watchdog window selected (except Stop mode). In Normal Request mode, timeout is 355 ms p2.2 (350 ms p3) ms. SPI: Sleep = SPI write command to MCR register, data sleep SPI: Stop = SPI write command to MCR register, data stop SPI: Normal = SPI write command to MCR register, data normal SPI: Standby = SPI write command to MCR register, data standby Notes 43. These two SPI commands must be sent consecutively in this sequence. 44. If watchdog activated. Figure 13. SBC State Diagram (Not Valid in Debug Modes) Power-Up Operation after power-up if no trigger appears Operation after reset of BATFAIL if no trigger appears Reset Normal Request Yes No Trigger No No Batfail No Stop Yes Sleep Yes Normal Figure 14. Operation After SBC Power-Up 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES DEBUG MODE: HARDWARE AND SOFTWARE DEBUG WITH THE 33742 normal 33742 operation, it is recommended that the disable be done using the following sequence: When a SBC, and the MCU it serves, is used on the same printed circuit board, both the MCU software and the 33742 operation must be debugged concurrently. The following features permit system debugging by allowing the disabling of the SBC internal software watchdog timer. • Step 1– Power down the SBC. • Step 2 – Power up the SBC. This sets the BATFAIL bit, allowing the 33742 to enter Normal Request mode. • Step 3 – Write to the TIM1 sub register to allow the SBC to enter Normal mode. • Step 4 – Write to the MCR register with data 0000. This enables the debug mode. Complete SPI byte is 0001 0000. • Step 5 – Write to the MCR register normal debug. SPI byte is 0001 x101. Important While in debug mode, the SBC can be used without having to clear the watchdog on a regular basis to facilitate software and hardware debug. • Step 6 – To leave the debug mode, write 0000 to the MCR register. DEVICE POWER-UP, RESET PIN CONNECTED TO VDD The VDD voltage is available when the 33742 power-up but the 33742 will not have received any SPI communication to configure itself. Until set up by the system MCU, the 33742 will generate a reset every 350ms until the part is configured. To avoid continuous MCU hardware resets, the 33742’s RST pin can be connected directly to the VDD pin by a hardware jumper. DEBUG MODES WITH SOFTWARE WATCHDOG DISABLED THOUGH SPI (NORMAL DEBUG, STANDBY DEBUG, AND STOP DEBUG) The software configurable watchdog can be disabled through the SPI. To set the watchdog disable while limiting the risk of inadvertently disabling the watchdog timer during At Step 2, the SBC is in Normal Request. Steps 3, 4, and 5 should be completed consecutively and within the 350ms time period of the Normal Request mode. If not, the 33742 will go into Reset mode and enter Normal Request again. Figure 15, page 34, illustrates debug mode selection. VSUP VDD BATFAIL TIM1(Step 3) MCR (Step 5) MCR (Step 6) SPI MCR (Step 4) Debug Mode SPI: Read BATFAIL 33742 in Debug mode. No Watchdog 33742 not in Debug mode. Watchdog ON Figure 15. Entering Debug Mode When the SBC is operating in the debug mode and has been set into Stop Debug or Sleep mode, a wake-up causes the 33742 to enter the Normal Request mode for 350ms. To avoid having the SBC generate an unwanted reset (enter Reset mode), the next debug mode (Normal Debug or Standby Debug) should be configured within the 350ms time window of the Normal Request mode. To avoid entering debug mode after a power-up, first read the BATFAIL bit (MCR read) and write 0000 into the MCR register. Figures 16 and 17, page 35, show the detailed operation of the SBC once the debug mode has been selected. 33742 34 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Watchdog: Timeout 350ms Reset Counter (3.4ms) Expired Power Down Reset Watchdog: Trigger Normal Request SPI: MCR (0000) and Normal Debug Normal Normal Debug SPI: MCR (0000) and Standby Debug Standby Debug Figure 16. Transitions to Enter Debug Modes Watchdog: Timeout 350ms og : Tr ig g er R D Normal by ma l De b E St an d or I: I: N ug SP SPI: Standby Debug Standby Debug eb ug Standby R Sleep &!BATFAIL & NOSTOP & SPI: Sleep hd R SP SPI: Stop Debug & CS Low to High Transition SPI: Stop Stop Debug Wa tc R Wake-up Reset E SPI: Standby Debug Normal Debug SPI: Normal Debug R SPI: Normal Debug W ak eup R R Reset Counter (3.4ms) Expired Normal Request SPI: Standby & Watchdog: Trigger Wake-up Stop (1) R (1) If Stop mode is entered, it is entered without watchdog, no matter the WDSTOP bit. (E) Debug mode entry point (Step 5 of the Debug mode entering sequence). (R) Represents transitions to Reset mode due to V1 low. Figure 17. Simplified 33742S State Diagram in Debug Modes 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES MCU FLASH PROGRAMMING CONFIGURATION To allow for new software to be loaded into a SBC’s MCU NVM or to standalone EEPROM or Flash, the 33742 is capable of having (1) VSUP applied to it to from an external power 5.0V supply and (2) having the RST and the WDOG outputs pins eternally forced to 0.0V or 5.0V without damaging the device. This allows the SBC to be externally powered and offboard signals to be applied to the reset pins. No functions of the 33742 are operating. Figure 18 illustrates a typical configuration for the connection of programming and debugging tools. The VSUP should be left open or forced to a value equal to or above V. The VDD regulator uses an internal pass transistor between VSUP and the VDD output pin. Biasing the VDD output pin with a voltage greater than VDD potential will force current through the body diode of the internal pass transistor to the VSUP pin. The RST pin is periodically pulled LOW for the t RSTDUR time (device in Reset mode), before being pulled to VDD for 350ms typical (device in Normal Request mode). During the time reset is LOW, the RST pin sinks 5.0mA maximum (IPDW). VDD VSUP (Open or > 5.0V RST 33742 WDOG 5.0 V MCU with Flash Memory Programming Bus Programming Tool Note External supply and sources applied to VDD, RST, and WDOG test points on application circuit board. Figure 18. Simplified Schematic for Microcontroller Flash Programming 33742 36 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES CAN PHYSICAL INTERFACE The SBC features a high-speed CAN physical interface for bus communication from 60kbps up to 1.0Mbps. Figure 19 is a simplified block diagram of the CAN interface of the 33742. 33742 V2 V2 V2 SPI Control TXD Driver QH CANH V2 CANH Line Differential Receiver RXD 2.5 V Bus Termination (60Ω) CANL Line V2 CANL Driver QL SPI Control VSUP Internal Wake-up Signal Wake-up Pattern Recognition Wake-up Receiver SPI Control Figure 19. Simplified Block Diagram of CAN Interface CAN INTERFACE SUPPLY CAN DRIVER OPERATION IN TXRX MODE The supply voltage for the CAN transceiver is the V2 pin. The CAN interface also has a supply path from the external supply line through the VSUP pin. This path is used in CAN Sleep mode to allow wake-up detection. During CAN communication (transmission and reception), the CAN interface current is sourced from the V2 pin. During CAN low power mode, the current is sourced from the VSUP pin. When the CAN interface is in TXRX mode, the driver has two states: recessive or dominant. The driver state is controlled by the TXD pin. The bus state is reported through the RXD pin. When TXD is HIGH, the driver is set in recessive state, and CANH and CANL lines are biased to the voltage set at V2 divided by 2, or approximately 2.5V. When TXD is LOW, the bus is set into dominant state: CANL and CANH drivers are active. CANL is pulled to ground, and CANH is pulled HIGH toward 5.0V (voltage at V2). The RXD pin reports the bus state: CANH minus CANL voltage is compared versus an internal threshold (a few hundred millivolts). If CANH minus CANL is below the threshold, the bus is recessive and RXD is set HIGH. If CANH minus CANL is above the threshold, the bus is dominant and RXD is set LOW. This is illustrated in Figure 19. MAIN OPERATION MODES DESCRIPTION The CAN interface of the SBC has two main operating modes: TXRX and Sleep mode. The modes are controlled by the CAN SPI Register. In the TXRX mode, which is used for communication, four different slew rates are available for the user. In the Sleep mode, the user has the option of enabling or disabling the remote CAN wake-up capability. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 37 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES TXD CANH CANL Typ 2.5V Typ 2.5V VCANH -VCANL > 900mV VCANH -VCANL < 500mV RXD CAN Recessive State CAN Dominant State CAN Recessive State Figure 20. CAN Interface Levels TXD AND RXD PINS The TXD pin has an internal pullup to V2. The state of TXD depends on the V2 status. RXD is a push-pull structure, supplied by V2. When V2 is set at 5.0V and CAN is TXRX mode, RXD reports bus status. For details, refer to Table 7, page 29, Table 9, below, and Table 10, page 39. The TXD pin is a push-pull structure between the V2 pin and GND. The circuitry has a parasitic diode between RXD and V2. It is illustrated in Figure 25. This parasitic diode is reversed biased in normal operation (TXD voltage is lower or equal to V2). In case the TXD voltage is greater than V2, a current will flow into the diode. If the V2 pin is low (e.g. in sleep mode, or in stop with a ballast transistor), the current leakage at V2 is low enough (10μA max) to ensure than the RXD pin can be pulled up by an external resistor (i.e. the MCU RXD pin internal pullup). The states of the RXD pin in the following Table 9 and 10 is dependant upon external circuitry connected to the V2 and RXD pins. CAN TXRX MODE AND SLEW RATE SELECTION The slew rate selection is done via CAN register (refer to Tables 21 through 23 on page 50). Four slew rates are available and control the recessive-to-dominant and dominant-to-recessive transitions. The delay time from TXD pin to CAN bus, from CAN bus to RXD, and from the TXD to RXD loop time is affected by the slew rate selection. 33742 38 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 9. CAN Interface / 33742S Modes and Pin Status—Operation with Ballast on V2(45) Mode CAN Mode (Controlled by SPI) V2 Voltage TXD Pin RXD Pin(46) CANH/CANL (Disconnected from Other Node) CAN Communication Unpowered – 0.0V LOW LOW Floating to GND NO Reset (with Ballast) – 0.0V LOW LOW Floating to GND NO Normal Request (with Ballast) – 0.0V LOW LOW Floating to GND NO Normal Sleep 5.0V 0.0V 5.0V Floating to GND NO Normal Normal Slew Rate 0, 1, 2, 3 5.0V Internal Pullup to V2 Standby with External Ballast Normal or Sleep 0.0V LOW LOW Floating to GND NO Sleep Sleep 0.0V LOW LOW Floating to GND NO. Wake-up if enabled Stop Sleep 0.0V LOW LOW Floating to GND NO. Wake-up if enabled Report Bus State Bus Recessive HIGH if Bus CANH = CANL = 2.5V Recessive, LOW if dominant YES Notes 45. See also Figure 31, page 57. 46. The state of the RXD pin is dependant upon: 1) the V2 voltage, 2) the external circuitry connected to RXD, (i.e. the MCU RXD pin), and 3) any external pull-up between RXD and the 5V supply. Table 10. CAN Interface / 33742 Modes and Pin Status — Operation without Ballast on V2 (47) Mode CAN Mode (Controlled by SPI) V2 Voltage TXD Pin RXD Pin(48) CANH/CANL (Disconnected from Other Node) CAN Communication Unpowered – 0.0V LOW LOW Floating to GND NO Reset (without Ballast) – 5.0V LOW LOW Floating to GND NO Normal Request without Ballast. V2 Connected to VDD – 5.0V LOW 5.0V Floating to GND NO Standby without External Ballast,. V2 connected to VDD Normal or Sleep 5.0V 0.0V 5.0V Floating to GND NO Normal without External Ballast. V2 Connected to VDD Normal Slew Rate 0, 1, 2,3 5.0V 5.0V 5.0V Bus Recessive CANH = CANL = 2.5V YES Normal without External Ballast,. V2 Connected to VDD Sleep 5.0V 0.0V 5.0V Floating to GND NO Sleep Sleep 0.0V LOW LOW Floating to GND NO. Wake-up if enabled Stop Sleep 5.0V LOW LOW Floating to GND NO. Wake-up if enabled Notes 47. See also Figure 36, page 60. 48. The state of the RXD pin is dependant upon: 1) the V2 voltage, 2) the external circuitry connected to RXD, (i.e. the MCU RXD pin), and 3) any external pull-up between RXD and the 5V supply. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 39 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES CAN SLEEP MODE The 33742 offers two CAN Sleep modes: • Sleep mode with CAN wake-up enable: detection of incoming CAN message and SBC wake-up. • Sleep mode with CAN wake-up disable: no detection of incoming CAN message. The CAN Sleep modes are set via the CAN SPI register. In CAN Sleep mode (with wake-up enable or disable), the CAN interface is internally supplied from the VSUP pin. The voltage at V2 pin can be either 5.0V or turned off. When the CAN is in Sleep mode, the current sourced from V2 is extremely low. In most cases the V2 voltage is off; however, the CAN can be placed into Sleep mode even with 5.0V applied on V2. In CAN Sleep mode, the CANH and CANL drivers are disabled, and the receiver is also disabled. CANH and CANL are high-impedance mode to ground. CAN SIGNALS IN TXRX AND SLEEP MODES When the CAN interface is set back into TXRX mode by an SPI command, CAN H and CANL are set in recessive level. This is illustrated in Figure 21. TXD CANH Dominant CANH CANL/CANH Recessive 2.5V CANL CANL Dominant Ground RXD CAN in TXRX Mode CAN in Sleep Mode (Wake-up Enable or Disable) CAN in TXRX Mode (Controlled by SPI Command) Figure 21. CAN Signals in TXRX and Sleep Modes CAN IN SLEEP MODE WITH WAKE-UP ENABLE When the CAN interface is in Sleep mode with wake-up enable, the CAN bus traffic is detected. The CAN bus wakeup is a pattern wake-up. PATTERN WAKE-UP • The distance between 2 pulses must be lower than 500μs. • The three pulses must occur within a time frame of 1.0ms. The pattern wake-up of the 33742 CAN interface allow wake-up by any CAN message content. Figure 22 below illustrates the CAN signals during a CAN bus Sleep state and wake-up sequence. In order to wake up the CAN interface, the following criteria must be fulfilled: • The CAN interface wake-up receiver must receive a series of three consecutive valid dominant pulses, each of which must be longer than 500ns and shorter than 500μs. 33742 40 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES TXD CANH Dominant CANH CANL/CANH Recessive 2.5V CANH Dominant CANH Dominant CANH Dominant Pulse # 1 Pulse # 2 Pulse # 3 CANL Dominant CANL Dominant CANL Dominant CANL CANL Dominant Ground CAN Bus Sleep State RXD CAN in TXRX Mode Incoming CAN Message CAN in Sleep Mode (Wake-up Enable) WU Receiver Min 500ns Max 500μs Internal Wake-up Signal Figure 22. CAN Bus Signal During Can Sleep State and Wake-up Sequence 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 41 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Figure 23 illustrates how the wake-up signal is generated. First the CAN signal is detected by a low consumption receiver (WU receiver). Then the signal passes through a pulse width filter, which discards the undesired pulses. The pulse must have a width bigger than 0.5μs and smaller than 500μs to be accepted. When a pulse is discarded, the pulse counter is reset and no wake-up signal is generated. When a Pulse OK CANH Pulse Width Filter CANL WU Receiver Narrow Pulse pulse is accepted, the pulse counter is incremented and, after three pulses, the internal wake-up signal is asserted. Each one of the pulses must be spaced by no more than 500μs. If not, the counter will be reset and no wake-up signal will be generated. This is accomplished by the wake-up timeout generator. The wake-up cycle is completed (and the wake-up flag reset) when the CAN interface is brought to CAN Normal mode. Counter Latch RST RST + Internal Wake-up Signal Time-out Standby Time-out Generator Figure 23. Wake-Up Functional Block Diagram CAN WAKE-UP REPORT The CAN wake-up reporting depend upon the low power mode the SBC is in. If the SBC is placed into Sleep mode (VDD and V2 off), the CAN wake-up or any wake-up results in the VDD regulator turning on, leading to turning on the MCU supply and releasing reset. If the 33742 is in Stop mode (V2 off and VDD active), the CAN wake-up or any wake-up is signalled by a pulse on the INT output. In addition the CANWU bit is set in the CAN register. If the SBC is in Normal or Standby mode and the CAN interface is in Sleep mode with wake-up enabled, the CAN wake-up is reported by the CANWU bit in the CAN register. In the event the SBC is in Normal mode and CAN Sleep mode with wake-up enabled, it is recommended that the user check for the CANWU bit prior to placing the 33742 in Sleep or Stop mode in case bus traffic has occurred while the CAN interface was in Sleep mode. After a CAN wake-up, a flag is set in the CAN register. Bit CANWU reports the CAN wake-up event while the 33742 was in Sleep or Stop mode. This bit is set until the CAN is in placed by SPI command into TXRX mode and the CAN register can be read. CAN BUS DIAGNOSTIC The SBC can diagnose CANH or CANL lines short to GND, shorts to VSUP or VDD. As illustrated in Figure 24, several single-ended comparators are implemented on the CANH and CANL bus lines. These comparators monitor the bus voltage level in the recessive and dominant states. This information is then managed by a logic circuit to determine if a failure has occurred and to report it. Table 11 indicates the state of the comparators in the event of bus failure and the state of the drivers; that is, whether they are recessive or dominant. 33742 42 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES V R5 H5 VSUP (12V–14V) V RVB Hb TXD Diagnostic Hg VDD V RVB (VSUP - 2.0V) V RG CANH V RG CANL Logic Lg Lb VDD (5.0V) V R5 (VDD - 0.43V) CANH Dominant Level (3.6V) Recessive Level (2.5V) V RG (1.75V) V RVB L5 CANL Dominant Level (1.4V) V R5 GND (0.0V) Figure 24. CAN Bus Simplified Structure Table 11. Short to GND, Short to VSUP , and Short to 5.0V (VDD) Detection Truth Table Driver Recessive State Driver Dominant State Failure Description Lg (Threshold 1.75V) Hg (Threshold 1.75V) Lg (Threshold 1.75V) Hg (Threshold 1.75V) No failure 1 1 0 1 CANL to GND 0 0 0 1 CANH to GND 0 0 0 0 Lb (Threshold VSUP - 2.0V) Hb (Threshold VSUP - 2.0V) Lb (Threshold VSUP - 2.0V) Hb (Threshold VSUP -2.0V) No failure 0 0 0 0 CANL to VSUP 1 1 1 1 CANH to VSUP 1 1 0 1 L5 (Threshold VDD- 0.43V) H5 (Threshold VDD- 0.43V) L5 (Threshold VDD- 0.43V) H5 (Threshold VDD- 0.43V) No failure 0 0 0 0 CANL to VDD 1 1 1 1 CANH to VDD 1 1 0 1 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 43 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES DETECTION PRINCIPLE In the recessive state, if one of the two bus lines is shorted to GND, VDD, or VSUP, then voltage at the other line follows the shorted line due to bus termination resistance and the high-impedance of the driver. For example, if CANL is shorted to GND, CANL voltage is zero, and CANH voltage, as measured by the Hg comparator, is also close to zero. In the recessive state the failure detection to GND or VSUP is possible. However, it is impossible to distinguish which bus line, CANL or CANH, is shorted to GND or VSUP. In the dominant state, the complete diagnostic is possible once the driver is turned on. CAN BUS FAILURE REPORTING CANL bus line failures (for example, CANL short to GND) is reported in the SPI register TIM1/2. CANH bus line (for example, CANH short to VSUP) is reported in the LPC register. In addition CAN-F and CAN-UF bits in the CAN register indicate that a CAN bus failure has been detected. NON-IDENTIFIED AND FULLY IDENTIFIED BUS FAILURES As indicated in Table 11, page 43, when the bus is in a recessive state it is possible to detect an error condition; however, is it not possible to fully identify the specific error. This is called “non-identified” or “under-acquisition” bus failure. If there is no communication (i.e., bus idle), it is still possible to warn the MCU that the SBC has started to detect a bus failure. TXD Diag 2.0 V V2 RXD Driver GND The failure detector requires at least one cycle of recessive and dominant state to properly recognize the bus failure. The error will be fully detected after five cycles of recessive-dominant states. As long as the failure detection circuitry has not detected the same error for five recessivedominant cycles, the bit “non-identified failure” (CAN-UF) will be set. RXD PERMANENT RECESSIVE FAILURE The purpose of this detection mechanism is to diagnose an external hardware failure at the RXD output pin and to ensure that a permanent failure at the RXD pin does not disturb network communication.In the event RXD is shorted to a permanent high level signal (i.e., 5.0V), the CAN protocol module within the MCU cannot receive any incoming message. Additionally, the CAN protocol module cannot distinguish the bus idle state and could start communication at any time. To prevent this, an RXD failure detection, as illustrated in Figure 25 and explained below, is necessary. Diff Output Sampling Sampling Sampling Sampling V2 RXD Sense RXD NUMBER OF SAMPLES FOR PROPER FAILURE DETECTION CANL CANH TXD Driver Logic In the CAN register, bits D2 and D1 (CAN-F and CAN-UF, respectively) are used to signal bus failure. Bit D2 reports a bus failure and bit D1 indicates if the failure is identified or not (bit D1 is set to logic [1} if the error is not identified). When the detection mechanism is fully operating any bus error will be detected and reported in the TIM1/2 and LPC registers and bit D1 will be reset to logic [0]. RXD Output CANH 60 Ω Diff CANL RXD Short to V1 RXD Flag Latched RXD Flag Prop Delay Note The RXD Flag is neither the RXPR bit in the LPC register, nor the CANF bit in the INTR register. Figure 25. RXD Path and RXD Permanent Recessive Detection Principle 33742 44 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES RXD FAILURE DETECTION TXD PERMANENT DOMINANT FAILURE The SBC senses the RXD output voltage at each LOW-toHIGH transition of the differential receiver. Excluding internal propagation delay, RXD output should be LOW when the differential receiver is LOW. In the event RXD is shorted to 5.0V (e.g., to VDD), RXD will be tied to a high level and the RXD short to 5.0V can be detected at the next LOW-to-HIGH transition of the differential receiver. Compete detection requires three samples. When the error is detected, an error flag is latched and the CAN driver is disabled. The error is reported through the SPI register LPC, bit RXPR. RECOVERY CONDITION The SBC will try to recover from a bus fault condition by sampling for a correct low level at TXD, as illustrated in Figure 26. As soon as an RXD permanent recessive is detected, the RXD driver is deactivated and a weak pulldown current source is activated in order to allow recovery conditions. The driver stays disabled until the failure is cleared (RXD no longer permanent recessive) and the bus driver is activated by an SPI register command (write 1 to the CANCLR bit in the CAN register). PRINCIPLE In the event TXD is set to a permanent low level, the CAN bus is set into dominant level, and no communication is possible. The SBC has a TXD permanent timeout detector. After timeout, the bus driver is disabled and the bus is released in a recessive state. The TXD permanent dominant failure is reported in the TIM1 register. RECOVERY The TXD permanent dominant is used and activated also in case of TXD short to RXD. The recovery condition for TXD permanent dominant (recovery means the reactivation of the CAN drivers) is done by an SPI command and is controlled by the MCU. The driver stays disabled until the failure is cleared (TXD no longer permanent dominant) and the bus driver is activated by an SPI register command (write logic [1] to CANCLR bit in the CAN register). TXD TO RXD SHORT CIRCUIT FAILURE PRINCIPLE In the event the TXD is shorted to RXD when an incoming CAN message is received, the RXD will be at a LOW. Consequently, the TXD pin is LOW and drives CANH and CANL into the dominant state. The bus is stuck in dominant mode and no further communication is possible. CANL CANH Diff Output Sampling RXD Output Sampling RXD Short to VDD RXD Flag Latched RXD no longer shorted to VDD RXD Flag Note RXD Flag is neither the RXPR bit in the LPC register nor the CANF bit in INTR register. DETECTION AND RECOVERY The TXD permanent dominant timeout will be activated and release the CANL and CANH drivers. However, at the next incoming dominant bit, the bus will be stuck again in dominant. In order to avoid this situation, the recovery from a failure (recovery means the reactivation of the CAN drivers) is done by an SPI command and controlled by the MCU. INTERNAL ERROR OUTPUT FLAGS Figure 26. RXD Recovery Conditions There are internal error flags to signal whenever thermal protection is activated or over-current detection occurs on the CANL or CANH pins (THERM-CUR bit). The errors are reported in the CAN register. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 45 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES DEVICE FAULT OPERATION Table 12 describes the relationship between device fault or warning and the operation of the VDD, V2, CAN, and HS interface. Table 12. Fault / Warning Fault / Warning VDD V2 CAN HS Battery Fail Turn OFF Turn OFF Turn OFF due to V2. No communication OFF VDD Temperature Pre-warning Warning flag only. Leave as is No change No change No change VDD Over-temperature Turn OFF Turn OFF Turn OFF due to V2. No communication OFF VDD Over-current VDD regulator enters linear mode. VDD under-voltage reset may occurs. VDD over-temperature Prewarning or shutdown may occur Turn OFF if VDD undervoltage reset occurs If V2 is OFF, turn OFF and no communication Turn OFF if VDD undervoltage reset occurs VDD Short-circuit VDD under-voltage reset occurs. VDD overtemperature Pre-warning or shutdown may occur Turn OFF Turn OFF due to V2. No communication OFF Watchdog Reset ON Turn OFF Turn OFF due to V2. No communication OFF V2LOW (e.g., V2 < 4.0V) No change V2 out of range Turn OFF due to V2 low No change HS Over-temperature No change No change No change OFF HS Over-current No change No change No change HS over-temperature may occur VSUP LOW No change No change No change No change CAN Over-temperature No change No change Disable. As soon as temperature falls, CAN is re-enabled automatically No change CAN Over-current No change No change (49) No change No change CANH Short to VDD No change No change Communication OK No change CANH Short to VSUP No change No change Communication OK No change CANL Short to GND No change No change Communication OK No change CANL Short to VSUP No change No change No change No change No communication(51) CANH Short to GND CANL Short to VDD No change(50) No No change communication(51) No change (51) No change No communication Notes 49. Refer to descriptions of CANH and CANL short to GND, VDD, and VSUP elsewhere in table. 50. Peak current 150mA during TXD dominant only. Due to loss of communication, CAN controller reaches bus OFF state. Average current out of V2 is below 10mA. 51. Over-current might be detected. THERM-CUR bit set in CAN register. 33742 46 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS SPI INTERFACE AND REGISTER DESCRIPTION DATA FORMAT DESCRIPTION Figure 27 illustrates an 8-bit byte corresponding to the 8 bits in a SPI register. The first three bits are used to identify the internal SBC register address. Bit 4 is a read/write bit. The last four bits are data sent from the MCU to the SBC or read back from the 33742 to the MCU. The state of the MISO has no significance during the write operation. However, during a read operation the final four bits of MISO have meaning; namely, they contain the content of the accessed register. MISO Bit 7 Bit 6 A2 A1 Bit 5 A0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W D2 D0 D3 D1 MOSI Table 13. Possible Reset Conditions Condition Name 33742 Reset POR Power-ON Reset 33742 Mode Transition NR2R Normal Request to Reset mode NR2N Normal Request to Normal mode NR2STB Normal Request to Standby mode 33742 Mode Definition N2R Normal to Reset mode STB2R Standby to Reset mode STO2R Stop to Reset mode STO2NR Stop to Normal Request RESET 33742S in Reset mode REGISTER DESCRIPTIONS Address The following tables in this section describe the SPI register list and register bit meaning. Register reset values are also described, along with the reset condition. A reset condition is the condition causing the bit to be set at the reset value. Data Note Read operation: R/W bit = logic [0] : Write operation: R/W = logic [1] Figure 27. Data Format Description. Table 14. List of Registers Register Address Comment and Use Formal Name and Link Write Read MCR $000 Mode Control Register (MCR) on page 48 Selection for Normal, Standby, Sleep, Stop, and Debug modes RCR $001 Reset Control Register (RCR) on page 49 Configuration for reset voltage level, CAN Sleep and Stop modes CAN $010 CAN Register (CAN) on page 49 CAN slew rate, Sleep and Wake-up enable/disable modes, drive enable after failure CAN wake-up and CAN failure status bits IOR $011 Input / Output Register (IOR) on page 50 HS (high side switch) control in Normal and Standby mode HS over-temperature bit, VSUP, and V2 LOW status WUR $100 on page 51 Control of wake-up input polarity Wake-up input and real time Lx input state TIM $101 Timing Register (TIM1 / 2) on • page 52 • BATFAIL, general failure, VDD prewarning, and Watchdog flag TIM1: Watchdog timing control, Watch- CANL and TXD failure reporting dog Window (WDW) or Watchdog Timeout (WTO) mode TIM2: Cyclic Sense and Forced Wakeup timing selection LPC $110 Low Power Control Register (LPC) on page 54 Control HS periodic activation in Sleep and Stop modes, Forced Wake-up mode activation, CAN-INT mode selection CANH and RXD failure reporting INTR $111 Interrupt Register (INTR) on page 56 Enable or Disable of Interrupts Interrupt source 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 47 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS MODE CONTROL REGISTER (MCR) Tables 15 through 17 describes the various Mode Control Registers. Table 15. Mode Control Register MCR R/W D3 $000b W – R Reset Value (53) Reset Condition (Write) BATFAIL (52) D2 D1 D0 MCTR2 MCTR1 MCTR0 VDDTEMP GFAIL WDRST – – 0 0 0 – – POR, RESET POR, RESET POR, RESET Notes 52. BATFAIL bit cannot be set by SPI. BATFAIL is set when VSUP falls below 3.0V. 53. See Table 13 page 47, for definitions of reset conditions Table 16. Mode Control Register Control Bits MCTR MCTR MCTR 2 1 0 33742S Mode Description To enter/exit Debug Mode, refer to detailed description in Debug Mode: Hardware and Software Debug with the 33742, page 34. 0 0 0 Enter/Exit Debug Mode 0 0 1 Normal – 0 1 0 Standby – 0 1 1 Stop, Watchdog OFF(54) – 0 1 1 Stop, Watchdog ON(54) – 1 0 0 Sleep(55) – 1 0 1 Normal 1 1 0 Standby 1 1 1 Stop No Watchdog running. Debug mode. Notes 54. Watchdog ON or OFF depends on RCR bit D3. 55. Before entering Sleep mode, BATFAIL bit in MCR must be previously cleared (MCR read operation), and NOSTOP bit in RCR must be previously set to logic [1]. Table 17. Mode Control Register Status Bits Name BATFAIL VDDTEMP GFAIL WDRST Logic Description 0 VSUP was not below VBF. 1 VSUP has been below VBF. 0 No over-temperature pre-warning. 1 Temperature pre-warning on VDD regulator (bit latched). 0 No failure. 1 CAN Failure or HS over-temperature or V2 low. 0 No watchdog reset occurred. 1 Watchdog reset occurred. 33742 48 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS RESET CONTROL REGISTER (RCR) Tables 18 and 19 contain various Reset Control Register information. Table 18. Reset Control Register RCR R/W $001b W R D3 D2 D1 D0 WDSTOP NOSTOP CAN SLEEP RSTTH Reset Value – 1 0 0 0 Reset Condition – POR, RESET, STO2NR POR, NR2N, NR2STB POR, NR2N, NR2STB POR (Write)(56) Notes 56. See Table 13 page 47, for definitions of reset conditions. Table 19. Reset Control Register Control Bits Name Logic WDSTOP NOSTOP CAN SLEEP RSTTH Description 0 No Watchdog in Stop mode. 1 Watchdog runs in Stop mode. 0 Device cannot enter Sleep mode. 1 Sleep mode allowed. Device can enter Sleep mode. 0 CAN Sleep mode disable (despite D0 bit in CAN register). 1 CAN Sleep mode enabled (in addition to D0 in CAN register). 0 Reset Threshold 1 selected (typ 4.6V). 1 Reset Threshold 2 selected (typ 4.2V). CAN REGISTER (CAN) Tables 20 through 23 contain the information on the CAN register. Table 20 describes control of the high-speed CAN module, mode, slew rate, and wake-up. Table 20. CAN Register CAN R/W D3 D2 D1 D0 W CANCLR SC1 SC0 MODE R CANWU CAN-F CAN-UF THERM-CUR Reset Value – 0 0 0 1 Reset Condition (Write)(57) – POR POR POR NR2N, STB2N $010b Notes 57. See Table 13, page 47, for definitions of reset conditions. Table 21. CANCLR Control Bits Logic Description 0 No effect. 1 Re-enables CAN driver after TXD permanent dominant or RXD permanent recessive failure occurred. Failure recovery conditions must occur to re-enable. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 49 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS HIGH-SPEED CAN TRANSCEIVER MODES The MODE bit (D0) controls the state of the CAN interface, TXRX or Sleep mode (Table 22). SC0 bit (D1) defines the slew rate when the CAN module is in TXRX, and it controls the wake-up option (wake-up enable or disable) when the CAN module is in Sleep mode. Table 22. CAN High-Speed Transceiver Modes SC1 SC0 MODE CAN Mode (Pass 1.1) 0 0 0 CAN TXRX, Slew Rate 0 0 1 0 CAN TXRX, Slew Rate 1 1 0 0 CAN TXRX, Slew Rate 2 1 1 0 CAN TXRX, Slew Rate 3 x 1 1 CAN Sleep and CAN Wake-up Disable x 0 1 CAN Sleep and CAN Wake-up Enable x = Don’t care. Table 23. CAN Register Status Bits Name Logic CANWU CAN-F CAN-UF THERM-CUR Description 0 No CAN wake-up occurred. 1 CAN wake-up occurred. 0 No CAN failure. 1 CAN failure(58). 0 Identified CAN failure(58). 1 Non-identified CAN failure. 0 No over-temperature or over-current on CANH or CANL drivers. 1 Over-temperature or over-current on CANH or CANL drivers. Notes 58. Error bits are latched in the CAN register. INPUT / OUTPUT REGISTER (IOR) Tables 24 through 26 contain the Input / Output Register information. Table 25 provides information about information HS control in Normal and Standby modes, while Table 26 provides status bit information. Table 24. Input / Output Register IOR R/W D3 D2 D1 D0 W – HSON – – R V2LOW HSOT VSUPLOW DEBUG Reset Value – – 0 – – Reset Condition (Write)(59) – – POR – – $011b Notes 59. See Table 13, page 47, for definitions of reset conditions. 33742 50 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 25. HSON Control Bits Logic HS State 0 HS OFF, in Normal and Standby modes. 1 HS ON, in Normal and Standby modes.(60) Notes 60. When HS is turned OFF due to an over-temperature condition, it can be turned ON again by setting the appropriate control bit to 1. Error bits are latched in the IOR register. Table 26. Input / Output Register Status Bits Name Logic V2LOW HSOT VSUPLOW DEBUG Description 0 V2LTH > 4.0V. 1 V2LTH < 4.0V. 0 No HS over-temperature. 1 HS over-temperature. 0 VBF(EW) > 5.8V. 1 VBF(EW) < 5.8V. 0 SBC not in Debug mode. 1 SBC accepts command to go to Debug modes (no Watchdog). WAKE-UP REGISTER (WUR) Tables 27 through 29 contain the Wake-up Register information. Local wake-up inputs L0 : L3 can be used in both Normal and Standby modes as port expander, as well as for waking up the SBC from Sleep or Stop modes (Table 27). Table 27. Wake-Up Register WUR $100b Reset Value (61) Reset Condition (Write) R/W D3 D2 D1 D0 W LCTR3 LCTR2 LCTR1 LCTR0 R L3WU L2WU L1WU L0WU – 0 0 0 0 – POR, NR2R, N2R, STB2R, STO2R Notes 61. See Table 13, page 47, for definitions of reset conditions. Wake-up inputs can be configured by pair. L0 and L1 can be configured together, and L1 and L2, and L2 and L3 can be configured together (Table 28). 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 51 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 28. Wake-up Register Control Bits LCTR3 LCTR2 LCTR1 LCTR0 L0 L1 : L1 L2 Config L2 L3 : L3 L4 Config x x 0 0 Inputs Disabled – x x 0 1 High Level Sensitive x x 1 0 Low Level Sensitive x x 1 1 Both Level Sensitive 0 0 x x – 0 1 x x High Level Sensitive 1 0 x x Low Level Sensitive 1 1 x x Both Level Sensitive Inputs Disabled x = Don’t care. Table 29. Wake-up Register Status Bits (62) Name Logic Description L3WU 0 or 1 L2WU 0 or 1 If bit = 1, wake-up occurred from Sleep or Stop modes; if bit = 0, no wake-up has occurred. L1WU 0 or 1 L0WU 0 or 1 When device is in Normal or Standby mode, bit reports the State on Lx pin (LOW or HIGH) (0 = Lx LOW, 1 = Lx HIGH) Notes 62. WUR status bits have two functions. After SBC wake-up, they indicate the wake-up source; for example, L2WU set at logic [1] if wakeup source is L2 input. After SBC wake-up and once the WUR register has been read, status bits indicate the real-time state of the Lx inputs (1 = Lx is above threshold, 0 = Lx input is below threshold). If after a wake-up from Lx input a watchdog timeout occurs before the first reading of the WUR register, the LxWU bits are reset. This can occur only if the SBC was in Stop mode. TIMING REGISTER (TIM1 / 2) Tables 30 through 34 contain the Timing Register information. The TIM register is composed of two sub registers: • TIM1 — Controls the watchdog timing selection as well as either the watchdog window or the watchdog timeout option (Figure 28 and Figure 29, respectively). TIM1 is selected when bit D3 is 0 (Table 30). Watchdog timing characteristics are described in Table 31. • TIM2 — Selects an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching the HS on or off. TIM2 is selected when bit D3 is 1 (Table 32). Figure 30, page 54, describes HS operation when cyclic sense is selected Cyclic sense timing characteristics are described in Table 34, page 54. Both subregisters also report the CANL and TXD diagnostics. Table 30. TIM1 Timing and CANL Failure Diagnostic Register TIM1 R/W D3 D2 D1 D0 $101b W 0 WDW WDT1 WDT0 R CANL2VDD CANL2BAT CANL2GND TXPD Reset Value – – 0 0 0 Reset Condition (Write)(63) – – POR, RESET POR, RESET POR, RESET Notes 63. See Table 13, page 47, for definitions of reset conditions. 33742 52 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 31. TIM1 Control Bits WDW WDT1 WDT0 Timing (ms typ) Parameter 0 0 0 9.75 Watchdog Period 1 0 0 1 45 Watchdog Period 2 0 1 0 100 Watchdog Period 3 0 1 1 350 Watchdog Period 4 1 0 0 9.75 Watchdog Period 1 1 0 1 45 Watchdog Period 2 1 1 0 100 Watchdog Period 3 1 1 1 350 Watchdog Period 4 Window Closed No Watchdog Clear Allowed No Window Watchdog Watchdog Window enabled (Window length is half the Watchdog Timing). Window Open for Watchdog Clear Window Open for Watchdog Clear Watchdog Timing x 50% Description Watchdog Period (Watchdog Timing Selected by TIM1 Bit WDW = 0) Watchdog Timing x 50% Watchdog Period (Watchdog Timing Selected by TIM1 Bit WDW =1) Figure 29. Timeout Watchdog Figure 28. Window Watchdog Table 32. Timing Register Status Bits Name Logic CANL2VDD CANL2BAT CANL2GND TXPD Failure Description 0 No CANL short to VDD. 1 CANL short to VDD. 0 No CANL short to VSUP . 1 CANL short to VSUP . 0 No CANL short to GND. 1 CANL short to GND. 0 No TXD dominant. 1 TXD dominant. Table 33. TIM2 Timing and CANL Failure Diagnostic Register TIM2 $101b R/W D3 D2 D1 D0 W 1 CSP2 CSP1 CSP0 R CANL2VDD CANL2BAT CANL2GND TXPD Reset Value – – 0 0 0 Reset Condition (Write)(64) – – POR, RESET POR, RESET POR, RESET Notes 64. See Table 13, page 47, for definitions of reset conditions. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 53 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Cyclic Sense Timing, ON Time HS ON Cyclic Sense Timing, OFF Time HS 10μs HS OFF Lx Sampling Point Sample time Figure 30. HS Operation When Cyclic Sense Is Selected Table 34. TIM2 Control Bits Parameter CSP2 CSP1 CSP0 Cyclic Sense Timing (ms) 0 0 0 4.6 Cyclic Sense/FWU Timing 1 0 0 1 9.25 Cyclic Sense/FWU Timing 2 0 1 0 18.5 Cyclic Sense/FWU Timing 3 0 1 1 37 Cyclic Sense/FWU Timing 4 1 0 0 74 Cyclic Sense/FWU Timing 5 1 0 1 95.5 Cyclic Sense/FWU Timing 6 1 1 0 191 Cyclic Sense/FWU Timing 7 1 1 1 388 Cyclic Sense/FWU Timing 8 LOW POWER CONTROL REGISTER (LPC) Tables 35 through 39 contain the Low Power Control Register information. The LPC register controls: • The state of HS in Stop and Sleep modes (HS permanently OFF or HS cyclic). • Enable or disable of the forced wake-up function (SBC automatic wake-up after time spent in Sleep or Stop modes; time is defined by the TIM2 sub register). • Enable or disable the sense of the wake-up inputs (Lx) at the sampling point of the Cyclic Sense period (LX2HS bit). (Refer to Reset Control Register (RCR) on page 49 for details of the LPC register setup required for proper cyclic sense or direct wakeup operation. The LPC register also reports the CANH and RXD diagnostic. Table 35. Low Power Control Register LPC R/W D3 D2 D1 D0 W LX2HS FWU CAN-INT HSAUTO R CANH2VDD CANH2BAT CANH2GND RXPR Reset Value – 0 0 0 0 Reset Condition (Write)(65) – POR, NR2R, N2R, STB2R, STO2R POR, NR2R, N2R, STB2R, STO2R POR, NR2R, N2R, STB2R, STO2R POR, NR2R, N2R, STB2R, STO2R $110b Notes 65. See Table 13, page 47, for definitions of reset conditions. 33742 54 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 36. LX2HS Control Bits Logic Wake-up Inputs Supplied by HS 0 No. 1 Yes. Lx inputs sensed at sampling point. Table 37. HSAUTO Control Bits Logic Auto-timing HS in Sleep and Stop modes 0 OFF. 1 ON, HS Cyclic, period defined in TIM2 subregister. Table 38. CAN-INT Control Bits Logic(66) Description 0 Interrupt as soon as CAN bus failure detected. 1 Interrupt when CAN bus failure detected and fully identified. Notes 66. If CAN-INT is at logic [0], any undetermined CAN failure will be latched in the CAN register (bit D1: CAN-UF) and can be accessed by SPI (refer to CAN Register (CAN) on page 49). After reading the CAN register or setting CAN-INT to logic [1], it will be cleared automatically. The existence of CAN-UF always has priority over clearing, meaning that a further undetermined CAN failure does not allow clearing the CAN-UF bit. Table 39. LPC Status Bits Name CANH2VDD CANH2BAT CANH2GND RXPR Logic Failure Description 0 No CANH short to VDD. 1 CANH short to VDD. 0 No CANH short to VSUP. 1 CANH short to VSUP. 0 No CANH short to GND. 1 CANH short to GND. 0 No RXD permanent recessive. 1 RXD permanent recessive. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 55 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS INTERRUPT REGISTER (INTR) Tables 40 through 42 contain the Interrupt Register information. The INTR register allows masking or enabling the interrupt source. A read operation identifies the interrupt source. Table 42 provides status bit information. The status bits of the INTR register content are copies of the IOR, CAN, TIM, and LPC registers status content. To clear the Interrupt Register bits, the IOR, CAN, TIM, and/or LPC registers must be cleared (read register) and the recovery condition must occur. Errors bits are latched in the CAN register and the IOR register. Table 40. Interrupt Register INTR R/W D3 D2 (67) D1 D0 V1TEMP CANF W VSUPLOW R VSUPLOW HSOT V1TEMP CANF Reset Value – 0 0 0 0 Reset Condition (Write)(68) – POR, RST POR, RST POR, RST POR, RST $111b HSOT-V2LOW Notes 67. If only HSOT - V2LOW interrupt is selected (only bit D2 set in INTR register), reading INTR register bit D2 leads to two possibilities: 1. Bit D2 = 1: Interrupt source is HSOT. 2. Bit D2 = 0: Interrupt source is V2LOW. HSOT and V2LOW bits status are available in the IOR register. 68. See Table 13, page 47, for definitions of reset conditions. Table 41. Interrupt Register Control Bits Name CANF VDDTEMP HSOT - V2LOW VSUPLOW Description Mask bit for CAN failures. Mask bit for VDD medium temperature (pre-warning). Mask bit for HS over-temperature AND V2LTH < 4.0V. Mask bit for VBF(EW) < 5.8V. When the mask bit is set, the INT pin goes LOW if the appropriate condition occurs. Upon a wake-up condition from Stop mode due to over-current detection (IDDS-WU1 or IDDS-WU2), an INT pulse is generated; however, INTR register content remains at 0000 (not bit set into the INTR register). Table 42. Interrupt Register Status Bits Name VSUPLOW HSOT VDDTEMP CANF Logic Description 0 No VBF(EW) < 5.8V. 1 VBF(EW) < 5.8V. 0 No HS over-temperature. 1 HS over-temperature. 0 No VDD medium temperature (pre-warning). 1 VDD medium temperature (pre-warning). 0 No CAN failure. 1 CAN failure. 33742 56 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS TYPICAL APPLICATIONS SBC POWER SUPPLY The 33742 is supplied from the battery line. A serial diode is necessary to protect the device against negative transient pulses and from reverse battery. This is illustrated in Figure 31. VPWR Q1 D1 VSUP Rp R1 SW1 to L1 C1 C2 33742 R5 VSUP Monitor Dual Voltage Regulator VDD Monitor 5.0V/200mA V2CTRL HS Control C6 HS L0 Rp R2 SW2 L1 to L1 L2 Programmable Wake-up Input L3 C7 Mode Control Oscillator V2 V2 VDD C3 C4 Interrupt Watchdog Reset INT WDOG RST SPI Interface MOSI SCLK MISO C10 C5 MCU CS CANH CANL 1.0 Mbps CAN Physical Interface SW3 TXD RXD GND R3 Rd Internal Module Supply to L2 C8 SW4 Safe Circuitry Clamp (1) R4 Rd to L3 C9 Connector Legend D1: Example: 1N4002 type Q1: MJD32C R1, R2, R3, R4: 10kΩ Rp, Rd: Example: 1.0kΩ depending on switch type. R5: 2.2kΩ C1: 10μF C2: 100nF C3: 47μF C4: 100nF C5: 47μF tantalum or 100μF chemical C6, C7, C8, C9, C10: 100nF (1) Clamp circuit to ensure max ratings for HS (HS from - 0.3V to VSUP + 0.3) are respected. Figure 31. SBC Typical Application Schematic 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 57 TYPICAL APPLICATIONS The recommended value are as follows: VOLTAGE REGULATOR The SBC contains two 5.0V regulators: a V1 regulator, fully integrated and protected, and a V2 regulator, which operates with an external ballast transistor. VDD REGULATOR The VDD regulator provides 5.0V output, 2.0% accuracy with current capability of 200mA max. It requires external decoupling and stabilizing capacitors. The minimum recommended values are as follows: • • • • C4: 100nF C3: 10μF < C3 <22μF, ESR < 1.0Ω or C3: 22μF < C3 <47μF, ESR < 5.0Ω or C3: ≥ 47μF, ESR < 10Ω • 22μF, ESR < 5.0Ω • 47μF, ESR < 10Ω The V2 pin has two functions: it is a sense input for the V2 regulator and is a 5.0V power supply input to the CAN interface. With respect to ballast transistor selection, either PNP or PMOS transistors may be used. A resistor between base and emitter (or source and drain) is necessary to ensure proper operation and optimized performances. Recommended bipolar transistor is MJD32C. V2 REGULATOR: OPERATION WITHOUT BALLAST TRANSISTOR V2 REGULATOR: OPERATING WITH EXTERNAL BALLAST TRANSISTOR The V2 regulator is a tracking regulator of the VDD output. Its accuracy relative to VDD is ±1.0%. It requires external decoupling and stabilizing capacitors. The external ballast transistor is optional. If the application does not requires more than the maximum output current capability of the VDD regulator, then the ballast transistor can be omitted. The thermal aspects must be analyzed as well. The electrical connection is illustrated in Figure 32. No Connect 33742 VPWR V2CTRL VSUP C1 V2 Components List VDD C2 C3 C1: 22μF C4 VDD RST RESET MCU C2: 100nF C3: >10μF C4: 100nF Figure 32. V2 Regulator Electrical Connection FAILURE ON VDD, WDOG, RESET, AND INT PINS The paragraphs below describe the behavior of the device and of the INT, RST, and WDOG pins at power-up and under failure of the VDD regulator. POWER-UP AND SBC ENTERING NORMAL OPERATION After power-up the 33742 enters Normal Request mode (CAN interface is in TXRX mode): VDD is on and V2 is off. After 350ms if no watchdog is written (no TIM1 register write), a reset occurs and the 33742 returns to Normal Request mode. During this sequence WDOG is active (low level). Once watchdog is written, the 33742 goes to Normal mode: VDD is still on and V2 turns on, WDOG is no longer active, and the RST pin is HIGH. If watchdog is not refreshed, the 33742 generates a reset and returns to Normal Request mode. Figure 33, page 59, illustrates the operation. 33742 58 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS Missing Watchdog Refresh Watchdog Refresh VDD SPI (CS) Watchdog Refresh WD RST INT 350ms SBC in Reset mode SBC in Normal Request & Reset modes SBC in Normal mode SBC in Normal Request & Reset mode Reset each 350ms Figure 33. Power up sequence, No W/D write at first POWER UP AND VDD GOING LOW WITH STOP MODE AS DEFAULT LOW POWER MODE IS SELECTED The first part of Figure 34 is identical to Figure 33. If VDD is pulled below VDD under-voltage reset (typ 4.6V), say by an overcurrent or short-circuit (for instance, short to 4.0V), and if a low power mode previously selected was Stop mode, the 33742 enters Reset mode (RST pin is active). The WDOG pin stays HIGH, but the high level (Voh) follows V1 level. The INT pin goes LOW. When the VDD overload condition is removed, the 33742 restarts in Normal Request mode. Under-voltage at VDD (VDD < VRSTTH) Watchdog Refresh VDD 350ms SPI (CS) WD RST INT SBC in Reset mode SBC in Normal Request & Reset modes SBC in Normal mode SBC in Normal Reset mode Reset each 350ms Figure 34. Under-voltage on VDD 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 59 TYPICAL APPLICATIONS POWER-UP AND VDD GOING LOW WITH SLEEP MODE AS DEFAULT LOW POWER MODE IS SELECTED The first part of Figure 35 is identical to Figure 34. If VDD is pulled below the VDD under-voltage reset (typ 4.6V), say by an over-current or short-circuit (for instance, short to 4.0V), and if the low power mode previously selected was Sleep mode and if the BATFAIL flag has been cleared, the 33742 enters in Reset mode for a time period of 100ms. The WDOG pin stays HIGH, but the high level (VOH) follows VDD level. The RST and INT pins are low. After 100ms the 33742 goes into Sleep mode, and the VDD and V2 are off. Figure 35 shows an example wherein VDD is shorted to 4.0V, and after 100ms the 33742 enters Sleep mode. . Under-voltage at VDD Watchdog Refresh VDD SPI (CS) 100ms WD RST Reset mode INT SBC in Reset mode SBC in Normal Request & Reset modes SBC in Normal mode Reset each 350ms SBC in Sleep mode SBC in Reset mode for 100ms, then enter Sleep mode Figure 35. Under-voltage at VDD. Sleep mode selected. CANH R6 CH CH R5 R7 CANL (33742) CANL CAN Connector CANH (33742) CANH (33742) CANH CL Legend R5: 60Ω CL, CH: 220pF Figure 36. CAN Bus Standard Termination CANL (33742) CANL CAN Connector CL CS Legend R6, R7: 30Ω CL, CH: 220pF CS: > 470pF Figure 37. CAN Bus Split Termination 33742 60 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE AND THERMAL CONSIDERATIONS PACKAGING PACKAGE AND THERMAL CONSIDERATIONS The 33742 SBC is a standard surface mount 28-pin SOIC wide body. In order to improve the thermal performances of the SOIC package, eight of the 28 pins are internally connected to the package lead frame for heat transfer to the printed circuit board. PACKAGING DIMENSIONS Important For the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98A drawing number below. DW SUFFIX EG SUFFIX (PB-FREE) 28-LEAD SOICW 98ASB42345B ISSUE G 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 61 PACKAGING PACKAGING DIMENSIONS DW SUFFIX EG SUFFIX (PB-FREE) 28-LEAD SOICW 98ASB42345B ISSUE G 33742 62 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGING DIMENSIONS EP SUFFIX (PB-FREE) 48-LEAD QFN 98ASA10825D ISSUE 0 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 63 PACKAGING PACKAGING DIMENSIONS EP SUFFIX (PB-FREE) 48-LEAD QFN 98ASA10825D ISSUE 0 33742 64 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGING DIMENSIONS EP SUFFIX (PB-FREE) 48-LEAD QFN 98ASA10825D ISSUE 0 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 65 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0) ADDITIONAL DOCUMENTATION 33742DW 33742EG THERMAL ADDENDUM (REV 2.0) Introduction This thermal addendum is provided as a supplement to the MC33742 technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the data sheet. 28-PIN SOICW Packaging and Thermal Considerations The MC33742 is offered in a 28 pin SOICW exposed pad, single die package. There is a single heat source (P), a single junction temperature (TJ), and thermal resistance (RθJA). TJ = RθJA . P The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. DW SUFFIX EG SUFFIX (PB-FREE) 98ASB42345B 28-PIN SOICW Note For package dimensions, refer to the 33742 data sheet. Standards 1.0 Table 43. Thermal Performance Comparison Thermal Resistance [°C/W] RθJA(1), (2) 41 RθJB(2), (3) 10 RθJA(1), (4) 68 RθJC(5) 220 Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the center lead. 4. Single layer thermal test board per JEDEC JESD51-3. 5. Thermal resistance between the die junction and the package top surface; cold plate attached to the package top surface and remaining surfaces insulated. 0.2 1.0 0.2 * All measurements are in millimeters 28 Pin SOICW 1.27 mm Pitch 16.0 mm x 7.5 mm Body Figure 38. Surface Mount for SOIC Wide Body non-Exposed Pad 33742 66 Analog Integrated Circuit Device Data Freescale Semiconductor ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0) RXD TXD VDD RST INT GND GND GND GND V2 V2CTRL VSUP HS L0 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 WDOG CS MOSI MISO SCLK GND GND GND GND CANL CANH L3 L2 L1 A 33742 Pin Connections 28-Pin SOICW 1.27 mm Pitch 18.0 mm x 7.5 mm Body Figure 39. Thermal Test Board Device on Thermal Test Board Material: Single layer printed circuit board FR4, 1.6mm thickness Cu traces, 0.07mm thickness Outline: 80mm x 100mm board area, including edge connector for thermal testing Area A: Cu heat-spreading areas on board surface Ambient Conditions: Natural convection, still air Table 44. Thermal Resistance Performance A [mm²] RθJA [°C/W] 68 0 52 300 47 600 RθJA is the thermal resistance between die junction and ambient air. 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 67 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0) Thermal Resistance [ºC/W] 80 70 60 50 40 30 x 20 RθJA 10 0 0 300 Heat spreading area A [mm²] 600 Figure 40. Device on Thermal Test Board RθJA Thermal Resistance [ºC/W] 100 10 x RθJA 1 0.1 1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time[s] Figure 41. Transient Thermal Resistance RθJA, 1 W Step response, Device on Thermal Test Board Area A = 600 (mm2) 33742 68 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES • • • • Converted to Freescale format Implemented Revision History page Added Thermal Addendum (Rev. 1.0) Changed Data Sheet from “Advanced” to “Final” 3 2/2006 4 6/2006 5 8/2006 • Added MCZ33742EG/R2 and MCZ33742SEG/R2 to the Ordering Information block 6 8/2006 7 10/2006 8 2/2007 • Replaced label for Logic Inputs to Logic Signals (RXD, TXD, MOSI, MISO, CS, SCLK, RST, WDOG, and INT) on page 7 • Removed all references to the 54 pin package. • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 7. Added note with instructions from www.freescale.com. • Revised () and (), • Restated notes in Maximum Ratings on page 7 9 3/2007 • Text corrections to the included thermal addendum 10 5/2007 11 6/2008 • • • • • • Added EP 48 pin QFN package Added 98ARH99048A Package drawing Added PCZ33742EP/R2 to the ordering information Made changes defining RXD as a push-pull structure on page 16, 23, 38, and 39 Updated figures Figure 12 and Figure 25 Added provisions of differentiation for 28-pin SOIC and 48-pin QFN for ESD Capability, Human Body Model(1) on page 7, Watchdog Period Normal and Standby Modes on page 18, and Normal Request Mode Timeout on page 18 • Update the Freescale format and style to the current standards • Added the Functional Internal Block Description section • Changed PCZ33742EP/R2 to MC33742EP/R2 in the ordering information 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 69 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 [email protected] For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. 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