Freescale Semiconductor Advance Information Document Number: MC33897 Rev. 16.0, 6/2007 Single Wire CAN Transceiver 33897/A/B/C/D/T The 33897 Series provides a physical layer for digital communications purposes using a Carrier Sense Multiple Access/ Collision Resolution (CSMA/CR) data link operating over a single wire medium. This is more commonly referred to as Single Wire Controller Area Network (CAN). The 33897 Series operates directly from a vehicle's 12 V battery system or a broad range of DC-power sources. It can operate at either low or high (33.33 kbps or 83.33 kbps) data rates. A highvoltage wake-up feature allows the device to control the regulator used in support of the MCU and other logic. The device includes a control terminal that can be used to put the module regulator into Sleep mode. The presence of a defined wake-up voltage level on the bus will reactivate the control line to turn the regulator and the system back on. The device complies with the GMW3089v2.4 General Motors Corporation specification. SINGLE WIRE CAN TRANSCEIVER D SUFFIX EF (PB-FREE) SUFFIX 98ASB42565B 14-TERMINAL SOICN EF (PB-FREE) SUFFIX 98ASB42564B 8-TERMINAL SOICN Features • • • • • • • • Waveshaping for Low Electromagnetic Interference (EMI) Detects and Automatically Handles Loss of Ground Worst-Case Sleep Mode Current of Only 60 µA (75 µA on the 33897T) Current Limit Prevents Damage Due to Bus Shorts Built-In Thermal Shutdown on Bus Output Protected Against Vehicular Electrical Transients Undervoltage Lockout Prevents False Data with Low Battery Pb-Free Packaging Designated by Suffix Code EF ORDERING INFORMATION Contains Lead MC33897D/R2 Pb-Free MC33897EF/R2 RoHS Temperature Range (TA) Package MCZ33897EF/R2 MCZ33897TEF/R2 MC33897AD/R2 MC33897AEF/R2 *MCZ33897CEF/R2 MC33897BEF/R2 - 40°C to 125°C MCZ33897BEF/R2 *MCZ33897DEF/R2 *Recommended device for all new designs * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. 14 SOICN MCZ33897AEF/R2 8 SOICN Power Source VCC Voltage Regulator Battery EN VBATT VCC CNTL TXD RXD MCU BUS MODE0 SWC BUS LOAD MODE1 GND 4 33897/A/C/T Figure 1. 33897/A/C Simplified Application Diagram VCC Battery VBATT VCC TXD RXD MCU BUS MODE0 SWC BUS LOAD MODE1 GND 33897B/D Figure 2. 33897B/D Simplified Application Diagram 33897/A/B/C/D/T 2 Analog Integrated Circuit Device Data Freescale Semiconductor DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Variations Part No. Load Voltage Sleep Mode 33897 1.0 V Max 33897T 33897A 33897B 0.1 V Max *33897C *33897D Other Significant Differences See Page • 14-Pin Package 8 • 14-Pin Package 6, 7, 8 • Quiescent Current in Sleep Mode, 5.0V ∠ VΒΑΤΤ ∠ 13V, Typical - 55 µA, Max - 75µA • ESD Voltage: Machine Model ±100V • 14-Pin Package • Removes diode drop during Sleep Mode • May not detect Loss of Ground under certain module characteristics. • 8-Pin Package • Removes diode drop during Sleep Mode • Does not include the CNTL terminal • May not detect Loss of Ground under certain module characteristics. • 14-Pin Package • Removes diode drop during Sleep Mode • Effectively detects Loss of Ground • ESD Voltage: Human Body Model ±1500V, Machine Model ±100V • 8-Pin Package • Removes diode drop during Sleep Mode • Effectively detects Loss of Ground • Does not include the CNTL terminal • ESD Voltage: Human Body Model ±1500V, Machine Model ±100V 8 2, 4, 6, 7, 8 ,13, 16 8 2, 4, 6, 7, 8 ,13, 16 *Recommended device for all new designs 33897/A/B/C/D/T Analog Integrated Circuit Device Data Freescale Semiconductor 3 INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM TXD BUSDRVR DRVR TX Bus MODE0 MODE1 HV WU E n HVWU Enable Wa ve Sha ping E nEnable Waveshaping Mode Mode Co ntrol Control TX Dat Data a TXD BUS Disab le Disable Bus BUSRCVR RCVR HVWU HV WU De Detect t RX Dat a Disab le RXD Data Disable TXD RXD Timers Undervoltage Detect VBATT BAT Load Switch LOAD Timer OSC GND CNTL CNTL* *CNTL terminal is present on 33897/A/C/T only. Figure 3. 33897/A/B/C/D/T Simplified Internal Block Diagram 33897/A/B/C/D/T 4 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS 33897/A/C/T GND 1 14 GND TXD 2 13 NC MODE0 3 12 MODE1 4 33897B/D TXD 11 88 GND BUS MODE0 22 77 BUS 11 LOAD MODE1 33 66 LOAD RXD 5 10 VBATT RXD 44 55 VBATT NC 6 9 CNTL GND 7 8 GND Figure 4. 33897/A/B/C/D/T Pin Connections Table 2. Pin Definitions A functional description of each terminal can be found in the Functional Pin Description section, beginning on page 13. 33897/A/C/T Terminal 33897B/D Terminal Pin Name Formal Name Definition 1, 7, 8, 14 8 GND Ground Electrical Common Ground and Heat removal. A good thermal path will also reduce the die temperature. 2 1 TXD Transmit Data Data input here will appear on the BUS terminal. A logic [0] will assert the bus, a logic [1] will make the bus go to the recessive state. 3, 4 2, 3 MODE0, MODE1 Mode Control These Pins control Sleep Mode, Transmit Level, and Speed. They have weak pulldowns. 5 4 RXD Receive Data Open drain output of the data on BUS. A recessive bus = a logic [1], a dominant bus = logic [0]. An external pullup is required. 6, 13 – NC No Connect No internal connection to these Pins. Pin 13 can be connected to GND to allow the use of the 14-terminal or 8-terminal device. (1) 9 – CNTL Control Provides a battery-level logic signal. 10 5 VBATT Battery Power input. An external diode is needed for reverse battery protection. 11 6 LOAD Load The external bus load resistor connects here to prevent bus pullup in the event of loss of module ground. 12 7 BUS Bus This terminal connects to the bus through external components. Notes 1. Module boards can be planned for the 14-terminal package and still use the 8-terminal package. 33897/A/B/C/D/T Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit VBATT - 0.3 to 40 V VIN - 0.3 to 7.0 V RXD Pin Voltage VRXD - 0.3 to 7.0 V CNTL Pin Voltage (33897/A/C/T only) VCNTL - 0.3 to 40 V Electrical Ratings Supply Voltage Input Logic Voltage ESD Voltage (2) VESD V Human Body Model All Pins Except BUS ± 2000 33897/A/B/T ±1500 33897C/D BUS Terminal (All Pkgs) Machine Model ± 4000 33897/A/B ± 200 33897C/D/T ± 100 Thermal Ratings Ambient Operating Temperature(3) TA - 40 to 125 °C Junction Operating Temperature TJ - 40 to 150 °C Storage Temperature TSTG - 55 to 150 °C Junction-to-Ambient Thermal Resistance RθJA 150 °C/W TPPRT Note 5. °C Peak Package Reflow Temperature During Reflow (4), (5) Notes 2. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 3. 4. 5. When using the 8-terminal device, consider the power dissipation at a high operating voltage and maximum network loading at ambient temperatures exceeding 85°C. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33897/A/B/C/D/T 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions of -40°C ≤ TA ≤ 125°C, unless otherwise stated. Voltages are relative to GND unless otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal. Characteristic Symbol Min Typ Max Unit 33897/A/B/C/D – – 45 55 60 75 µA 33897T – 4.0 mA – 9.0 mA GENERAL Quiescent Current Sleep IQSLP 5.0 V ≤ VBATT ≤ 13 V (6) Awake with Transmitter Disabled IQATDIS 5.0 V ≤ VBATT ≤ 26.5 V – Awake with Transmitter Enabled IQATEN 5.0 V ≤ VBATT ≤ 26.5 V – Undervoltage Shutdown VBATTUV 4.0 – 5.0 V Undervoltage Hysteresis VUVHYS 0.1 – 0.5 V 190 °C 20 °C Thermal Shutdown (7) TSD 5.0 V ≤ VBATT ≤ 26.5 V Thermal Shutdown Hysteresis (7) 150 – 10 – – – TSDHYS 5.0 V ≤ VBATT ≤ 26.5 V LOGIC I /O, MODE0, MODE1, TXD, RXD Logic Input Low Level (MODE0, MODE1, and TXD) VIL 5.0 V ≤ VBATT ≤ 26.5 V Logic Input High Level (MODE0, MODE1, and TXD) VIH 5.0 V ≤ VBATT ≤ 26.5 V Mode Pin Pulldown Current (MODE0 and MODE1) V 2.0 – – 10 – 50 µA IPD Pin Voltage = 0.8 V, 5.0 V ≤ VBATT ≤ 26.5 V Receiver Output Low (RXD) V 0.8 VOL IIN = 2.0 mA, 5.0 V ≤ VBATT ≤ 26.5 V V – – 0.45 CNTL (33897/A/C/T ONLY) CNTL Output Low VOLCNTL IIN = 5.0 µA, 5.0 V ≤ VBATT ≤ 26.5 V CNTL Output High IOUT = 180 µA, 5.0 V ≤ VBATT ≤ 26.5 V V – – 0.8 VBATT - 0.8 – VBATT VOHCNTL V Notes 6. After tCNTLFDLY 7. Thermal shutdown causes the BUS output driver to be disabled. Guaranteed by characterization. 33897/A/B/C/D/T Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions of -40°C ≤ TA ≤ 125°C, unless otherwise stated. Voltages are relative to GND unless otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal. Characteristic Symbol Min Typ Max Unit LOAD LOAD Voltage Rise (8) VLDRISE V Normal Speed and Voltage Mode, Transmit HighVoltage Mode, Transmit High-Speed Mode IIN = 1.0 mA, 5.0 V ≤ VBATT ≤ 26.5 V – – 0.1 – – 1.0 – – 0.1 – – 1.0 Sleep Mode IIN = 7.0 mA IIN = 7.0 mA (9) 33897/T 33897A/B/C/D Loss of Battery IIN = 7.0 mA LOAD Leakage During Loss of Module Ground (10) µA ILDLEAK 0.0 V ≤ VBATT ≤ 18 V 33897/A/B/T 0.0 – - 90 0.0 V ≤ VBATT ≤ 18 V 33897C/D -10 – 10 BUS µA Passive Out BUS Leakage Passive In 0.0 V ≤ VBATT ≤ 26.5 V, -1.5 V ≤ VBUS < 0 V ILEAK -5.0 – 5.0 -5.0 – 5.0 -10 – 10 0.0 – -90 ILKAI Active In 0.0 V ≤ VBATT ≤ 26.5 V, 0 V < VBUS ≤ 12.5 V BUS Leakage During Loss of Module Ground (11) 0.0 V ≤ VBATT ≤ 18 V 33897/A/B/T 0.0 V ≤ VBATT ≤ 18 V 33897C/D IBLKLOG High-Voltage Wake-up Mode Output High Voltage V 12 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω 33897/T VHVWUOHF 9.7 – 33897A/B/C/D VHVWUOHO 9.9 – 5.0 V ≤ VBATT < 12 V, 200 Ω ≤ RL ≤ 3332 Ω High-Speed Mode Output High Voltage Lesser of VBAT - 1.5 or 9.7 12.5 12.5 VBATT VOHHS 8.0 V ≤ VBATT ≤ 16 V, 75 Ω ≤ RL ≤ 135 Ω V 4.2 – 5.1 Normal Mode Output High Voltage V 6.0 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω VNOHF 4.4 – 5.1 5.0 V ≤ VBATT < 6.0 V, 200 Ω ≤ RL ≤ 3332 Ω VNOHO Lesser of VBATT - 1.6 or 4.4 – Lesser of VBATT or 5.1 - 0.2 – 0.2 -350 – - 150 BUS Low Voltage VOL 5.0 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω Short Circuit BUS Output Current Dominant State, 5.0 V ≤ VBATT ≤ 26.5 V V IBSC mA Notes 8. GMW3089V2.4 specifies the maximum load voltage rise to be 0.1 V whenever module battery is intact, including when in Sleep mode. The maximum load voltage rise of 1.0 V in Sleep mode is a GM-approved exception to GMW3089V2.4. 9. 33897A/B/C/D remove diode drop during Sleep mode. 10. LOAD terminal is at system ground voltage. 11. BUS terminal is at system ground voltage 33897/A/B/C/D/T 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions of -40°C ≤ TA ≤ 125°C, unless otherwise stated. Voltages are relative to GND unless otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal. Characteristic Symbol Min Typ Max Unit BUS (CONTINUED) Input Threshold V Awake 5.0 V ≤ VBATT ≤ 26.5 V VBIA 2.0 – 2.2 VBISF 6.6 – 7.9 VBISO Lesser of 6.6 V or VBATT - 4.3 – Lesser of 7.9 V or VBATT - 3.25 Sleep 12 V ≤ VBATT ≤ 26.5 V Sleep 5.0 V ≤ VBATT < 12 V 33897/A/B/C/D/T Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions of -40°C ≤ TA ≤ 125°C, unless otherwise stated. Voltages are relative to GND unless otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal. Characteristic Symbol Min Typ Max 2.0 – 6.3 1.8 – 8.5 0.1 – 1.7 Unit BUS Normal Speed Rising Output Delay µs t DLYNORMRO 200 Ω ≤ RL ≤ 3332 Ω, 1.0 µs ≤ Load Time Constants ≤ 4.0 µs Measured from TXD = VIL to VBUS as follows: Max Time to VBUSMOD = 3.7 V, 6.0 V ≤ VBATT ≤ 26.5 V (12) Min Time to VBUSMOD = 1.0 V, 6.0 V ≤ VBATT ≤ 26.5 V (12) Max Time to VBUSMOD = 2.7 V, VBATT = 5.0 V (12) Min Time to VBUSMOD = 1.0 V, VBATT = 5.0 V (12) Normal Speed Falling Output Delay µs t DLYNORMFO 200 Ω ≤ RL ≤ 3332 Ω, 1.0 µs ≤ Load Time Constants ≤ 4.0 µs Measured from TXD = VIH to VBUS as follows: Max Time to VBUSMOD = 1.0 V, 6.0 V ≤ VBATT ≤ 26.5 V (12) Min Time to VBUSMOD = 3.7 V, 6.0 V ≤ VBATT ≤ 26.5 V (12) Max Time to VBUSMOD = 1.0 V, VBATT = 5.0 V (12) Min Time to VBUSMOD = 2.7 V, VBATT = 5.0 V (12) High-Speed Rising Output Delay µs t DLYHSRO 75 Ω ≤ RL ≤ 135 Ω, 0.0 µs ≤ Load Time Constants ≤ 1.5 µs, 8.0 V ≤ VBATT ≤ 16 V Measured from TXD = VIL to VBUS as follows: Max Time to VBUS = 3.7 V (13) Min Time to VBUS = 1.0 V (13) High-Speed Falling Output Delay 75 Ω ≤ RL ≤ 135 Ω, 0.0 µs ≤ Load Time Constants ≤ 1.5 µs, 8.0 V ≤ VBATT ≤ 16 V µs t DLYHSFO 0.04 – 3.0 Measured from TXD = VIH to VBUS as follows: Max Time to VBUS = 1.0 V (13) Min Time to VBUS = 3.7 V (13) Notes 12. VBUSMOD is the voltage at the BUSMOD node in Figure 7, page 15. 13. VBUS is the voltage at the BUS terminal in Figure 8, page 15. 33897/A/B/C/D/T 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions of -40°C ≤ TA ≤ 125°C, unless otherwise stated. Voltages are relative to GND unless otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal. Characteristic Symbol Min Typ Max Unit BUS (CONTINUED) High-Voltage Rising Output Delay µs t DLYHVRO 200 Ω ≤ RL ≤ 3332 Ω, 1.0 µs ≤ Load Time Constants ≤ 4.0 µs Measured from TXD=VIL to VBUS as follows: Max Time to VBUSMOD = 3.7 V, 6.0 V ≤ VBATT ≤ 26.5 V (14) 2.0 – 6.3 Min Time to VBUSMOD = 1.0 V, 6.0 V ≤ VBATT ≤ 26.5 V (14) 2.0 – 6.3 2.0 – 18 Max Time to VBUSMOD = 9.4 V, 12.0 V ≤ VBATT ≤ 26.5 V (14) High-Voltage Falling Output Delay µs t DLYHVFO 200 Ω ≤ RL ≤ 3332 Ω, 1.0 µs ≤ Load Time Constants ≤ 4.0 µs, 12.0 V ≤ VBATT ≤ 26.5 V Measured from TXD=VIH to VBUS as follows: Max Time to VBUSMOD = 1.0 V (14) 1.8 – 14 Min Time to VBUSMOD = 3.7 V (14) 1.8 – 14 0.2 – 1.0 10 – 70 300 – 1000 RECEIVER RXD Receive Delay Time (5.0 V ≤ VBATT ≤ 26.5 V) µs t RDLY Awake Receive Delay Time (BUS Rising to RXD Falling, 5.0 V ≤ VBATT ≤ 26.5 V) µs t RDLYSL Sleep CNTL CNTL Falling Delay Time (5.0 V ≤ VBATT ≤ 26.5 V) (33897/A/C/T only) t CNTLFDLY ms Notes 14. VBUSMOD is the voltage at the BUSMOD node in Figure 7, page 15. 33897/A/B/C/D/T Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS tDLYNORMFO tDLYNORMRO V IH V IL TXD V NOHF Bus V BIA V BUSMOD * V BIA V BUSMOD * V IH RXD V IL tRDLY tRDLY * VBUSMOD is the voltage at the BUSMOD node in Figure 7. Figure 5. TXD, Bus and RXD Waveforms in Normal Mode TDLYHSRO tDLYHSFO VIH TXD VIL VNOHF VBUS * Bus VBIA VBIA VBUS * VIH RXD VIL tRDLY tRDLY * VBUS is the voltage at the BUS terminal in Figure 8. Figure 6. TXD, Bus and RXD Waveforms in High Speed Mode 33897/A/B/C/D/T 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33897 Series is intended for use as a physical layer device in a Single Wire CAN communications bus. Communications takes place from a single terminal over a single wire using a common ground for a current return path. Two data rates are available, with the high rate used for factory or assembly line communications and the lower for actual system communications where the radiated EMI of the higher rate could be an issue. Two Pins control the mode of operation (sleep, low-speed, high-speed, and high-voltage wake-up). FUNCTIONAL PIN DESCRIPTION The 33897 Series is intended to be used with an MCU to control its operation and to process and generate the data for the bus. GROUND PINS (33897/A/C/T) The four ground PINS are not only for electrical conduction, their number and locations at each of the four corners serve also to remove heat from the IC. The biggest benefit of this is obtained by putting a lot of copper on the PCB in this area and, if ground is an internal layer, by adding numerous plated-through connections to it with the largest diameter holes the layout can use. RXD Data The data received on the bus is translated to logic levels on this terminal. This terminal is a logic high when the bus is in the recessive state (near zero volts) and is logic low when the bus is in either the normal or high-voltage dominant state. This is an open-drain type of output that requires an external resistor to pull it up. When the device is in sleep mode, the output will be off unless a high-voltage wake-up level is detected on the bus. If the wake-up level is detected, the output will be driven by the data on the bus. If the level of the data returns to normal level, the output will return to off after a short delay unless a non-sleep mode condition is set by the MCU. TXD DATA The data driven onto the SWCAN bus is inverted from the TXD terminal. A “1” driven on TXD will result in an undriven (recessive) state (bus at near zero volts). When the TXD terminal is low, the output goes to a driven state. The voltage and waveshaping in the driven state is determined by the levels on the MODE0 and MODE1 Pins (refer to Table 6). Table 6. Mode Control Logic Levels Logic Level Operation MODE0 MODE1 0 0 Sleep Mode 0 1 High Voltage Wake-Up Mode 1 0 High Speed Mode 1 1 Normal Mode MODE CONTROL The MODE Pins control the transmitter filtering and BUS voltage and the IC sleep mode operation. Table 6 shows the mode versus the logic levels on MODE0 and MODE1. The MODE0 and MODE1 Pins have a weak pulldown in the IC so that in case the Pins are not driven, the device will enter the sleep mode. This is usually the situation as the MCU comes out of reset, before the driving signals have been configured as outputs. LOAD Switch This switch is on in all operating modes unless a loss of ground is detected. If this happens, the switch is opened and the resistor normally attached to its terminal will no longer pass current to or from the bus. CNTL Output (33897/A/C/T ONLY) This logic level signal is used to control a VCC regulator. When the output is low, the VCC regulator is expected to shutdown. This is normally used to shut down the MCU and all the devices powered by VCC when the IC is in sleep mode. This is done to save power. When the part is taken out of the sleep mode by the higher-than-normal bus voltage, this terminal is asserted high and the VCC regulator brings its output up to the regulated level. This starts the MCU, which controls the mode of the IC. The MCU must change the mode signals to non-sleep mode levels in order to keep this terminal from going low. There is a delay to allow the MCU to fully wake up and take control after the high-voltage signaling is removed before the level on this output returns low. After a delay time, even if the bus is at high voltage, the IC will return to sleep mode if both MODE Pins are low. VBATT Input This power input is not reverse battery protected and should use an external diode to protect it from damage owing to reverse battery if this protection is desired. The voltage drop of the diode must be taken into consideration when the operating range of the system is being determined. This 33897/A/B/C/D/T Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM COMPONENTS diode is generally used to protect the entire module from reverse battery and should be selected accordingly. BUS I /O This input / output may require electrostatic discharge (ESD) and /or EMI external circuitry. A set of components is shown in the simplified application diagrams on page 16 of this datasheet. The value of the capacitor should be adjusted downward in direct proportion to the added capacitance of the ESD or EMI circuits. The series resistance of the inductor should be kept below 3.5 Ω to prevent its voltage drop from significantly degrading system noise margins. FUNCTIONAL BLOCK DIAGRAM COMPONENTS Timer OSC TXD BUS DRVR This circuit generates a 500 kHz signal to be used for internal logic. It is the reference for some of the required delays. This circuit drives the BUS. It can drive it with the higher voltage wake-up signals when enabled by the Mode Control circuit. It can also provide waveshaping for reduced EMI or not provide it for the higher data rate mode. The actual data is received on TXD at CMOS logic levels, then translated by this circuit to the necessary operating voltages. Timers This circuit contains the timing logic used to hold the CNTL active for the required time after the conditions for sleep mode have been met. It is also used to keep the TXD driver active for a period of time after it has generated a passive level on the bus. Mode Control This circuit contains the control logic for the various operating modes and conditions required for the IC. BUS RCVR This circuit translates the levels on the BUS terminal to a CMOS level indicating the presence of a logic [0] or a logic [1]. It also determines the presence of a high-voltage wake-up (HVWU) signal that is passed to Mode Control and Timers circuits. An analog filter is used to “de-glitch” the highvoltage wake-up signal and prevent false exits from the sleep mode. Undervoltage Detect This circuit monitors internal operating voltage to assure proper operation of the part. If a low-voltage condition is detected, it sends a signal to disable the BUS RCVR and TXD BUS DRVR circuits. This prevents incorrect data from being put on the bus or sent to the MCU. Load Switch The LOAD switch provides a path for an external resistor connected to the BUS to be connected to ground. When a loss of ground is detected, this switch is opened to prevent the current that would normally be flowing to the ground from the module from going back through the load resistor and raising the bus level. The circuit is opened when the voltage between GND and VBATT becomes too low as would be the case if module ground were lost. 33897/A/B/C/D/T 14 Analog Integrated Circuit Device Data Freescale Semiconductor BUS LOADING PARAMETERS FUNCTIONAL BLOCK DIAGRAM COMPONENTS BUS LOADING PARAMETERS VBATT 100 pF 1.0 kΩ 33897 47 µH BUSMOD BUS 6.49 kΩ CNOM = 100 pF + (n -1) 220 pF R= 6.49 kΩ (n -1) LOAD GND Note: The letter “n” represents the number of nodes in the system. Figure 7. Transmitter Delays in Normal and Transmit High-Voltage Wake-Up Modes 33897 BUS 6.49 kΩ 130 Ω CNOM = (n) 220 pF R= 6.49 kΩ (n -1) LOAD GND Note: The letter “n” represents the number of nodes in the system. Figure 8. Transmitter Delays in Transmit High-Speed Mode 33897/A/B/C/D/T Analog Integrated Circuit Device Data Freescale Semiconductor 15 TYPICAL APPLICATIONS TYPICAL APPLICATIONS level on the bus. This wake-up voltage will activate the control line, which enables the regulator and turns the module back on. This 33897/A/C/T feature allows the module to be more energy efficient since the current consumption is significantly lowered when it goes into sleep mode. The 33897/A/C/T can be used in applications where the module includes a regulator that has the capability of going into Sleep mode by having an Enable terminal. See Figure 9. When the module’s regulator is in sleep mode, the module is turned off. The module waits for a defined wake-up voltage VCC Voltage Regulator Power Battery Source 100 nF EN 100 pF VBATT 1.0 kΩ CNTL VCC 10 kΩ 4.7 µF 2.7 kΩ 47 µH BUS TXD SWC BUS 47 pF RXD MODE0 LOAD MCU 6.49 kΩ MODE1 4 GND 33897/A/C/T Figure 9. 33897/A/C/T Typical Application Schematic is no need for the module to have control over its regulator via The 33897B/D do not have a control terminal to enable the the transceiver. module’s regulator. See Figure 10. The 33897B/D can be used in applications where board space is limited and there Battery 100 nF 4.7 µF 100 pF VCC VBATT 1.0 kΩ VCC 10 kΩ 2.7 kΩ 47 µH TXD BUS SWC BUS 47 pF RXD MCU MODE0 LOAD 6.49 kΩ MODE1 GND 33897B/D Figure 10. 33897B/D Typical Application Schematic 33897/A/B/C/D/T 16 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important: For the most current Package revision, visit www.freescale.com and perform a Keyword Search on the “98A” drawing number below. D SUFFIX EF (Pb-FREE) SUFFIX 14-TERMINAL SOICN PLASTIC PACKAGE 98ASB42565B ISSUE H 33897/A/B/C/D/T Analog Integrated Circuit Device Data Freescale Semiconductor 17 PACKAGING PACKAGE DIMENSIONS (CONTINUED) PACKAGE DIMENSIONS (CONTINUED) EF (Pb-FREE) SUFFIX 8-TERMINAL SOICN PLASTIC PACKAGE 98ASB42564B ISSUE U 33897/A/B/C/D/T 18 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES • • • • • • • Converted to Freescale format Added A & B Versions Updated Device Variation Table, and Note “* Recommended device for all new designs” Added EF (Pb-Free) Devices, and higher soldering temperature Implemented Revision History page Updated Simplified Application Diagrams Updated Typical Application Schematic 9.0 5/2005 10.0 8/2005 11.0 12/2005 • Added 33897C and D versions and Timing Diagrams 12.0 1/2006 13.0 6/2006 14.0 8/2006 15.0 10/2006 • Updated Table 4, Static Electrical Characteristics - LOAD and BUS parameters • Updated Ordering Information. • Removed “Unless otherwise noted” from Static Electrical Characteristics & Dynamic Electrical Characteristics table introductions • Added Part Numbers MC33897TD and MC33897TEF to Ordering Information on Page 1. • Added 33897T to Table 1, Device Variations on Page 3, Referencing Electrical Changes per Errata MC33897TER, Revision 3 and specifying ESD variations • Removed Part Numbers MC33897TD/R2, MC33897TEF/R2, MC33897CLEF/R2, PC33897CLEF/R2, MC33897DLEF/R2, and PC33897DLEF/R2 • Added Part Numbers MCZ33897EF/R2, MCZ33897TEF/R2, MCZ33897AEF/R2, MCZ33897CEF/R2, MCZ33897BEF/R2, and MCZ33897DEF/R2 to the Ordering Information block on Page 1. • Updated Device Variations on page 3 for “T” suffix products • Split out Human Body Model on page 6 to differentiate between T and non-T versions • Added Undervoltage Hysteresis on page 7 • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 6. Added note with instructions to obtain this information from www.freescale.com. 16.0 6/2007 • Removed watermark, “Advance Information” from page 1. 33897/A/B/C/D/T Analog Integrated Circuit Device Data Freescale Semiconductor 19 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http:// www.freescale.com/epp. USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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