Freescale MC33990D/DR2 Enhanced class b serial transceiver Datasheet

Freescale Semiconductor
Technical Data
Document Number: MC33990
Rev 4.0, 10/2008
Enhanced Class B Serial
Transceiver
33990
The 33990 is a serial transceiver designed to provide bi-directional
half-duplex communication meeting the automotive SAE Standard J1850 Class B Data Communication Network Interface specification. It
is designed to interface directly to on-board vehicle microcontrollers
and serves to transmit and receive data on a single-wire bus at data
rates of 10.4 kbps using Variable Pulse Width Modulation (VPWM).
The 33990 operates directly from a vehicle's 12 V battery system and
functions in a true logic fashion as an I/O interface between the
microcontroller's 5.0 V CMOS logic level swings and the required 0 V
to 7.0 V waveshaped signal swings of the bus. The bus output driver
is short circuit current limited.
J-1850 SERIAL TRANSCEIVER
D SUFFIX
EF SUFFIX (PB-FREE)
98ASB42564B
8-PIN SOICN
Features
• Designed for SAE J-1850 Class B Data Rates
• Full Operational Bus Dynamics Over a Supply Voltage of 9.0 V
to 16 V
• Ambient Operating Temperature of -40°C to 125°C
• Interfaces Directly to Standard 5.0 V CMOS Microcontroller
• BUS Pin Protected Against Shorts to Battery and Ground
• Thermal Shutdown with Hysteresis
• Voltage Waveshaping of Bus Output Driver
• Internally Reverse Battery Protected
• 40 V Max VBAT Capability
• Pb-Free Packaging Designated by Suffix Code EF
ORDERING INFORMATION
Device
MC33990D/DR2
MCZ33990EF/R2
Temperature
Range (TA)
Package
-40°C to 125°C
8 SOICNN
33990
VBAT
+VBAT
Primary
Node
BUS
SLEEP
TX
LOAD
MCU
RX
GND
4X/LOOP
Figure 1. 33990 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006-2008. All rights reserved.
Secondary
Nodes
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
33990
Bus
Driver
VBAT
SLEEP
Thermal
Shutdown
4.5 V
Reference
Waveshaping
Filter
TX
RX
4X/LOOP
BUS
Voltage
Regulator
Digital Output
Driver
Loss of Ground
Protection
4X Enable
Loopback
LOAD
GND
Note This device contains approximately 400 active transistors and 250 gates.
Figure 2. 33990 Simplified Internal Block Diagram
33990
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
SLEEP
11
88
RX
GND
22
77
TX
LOAD
33
66
4X/LOOP
BUS
44
55
VBAT
Figure 3. 33990 Pin Connections
Table 1. 33990 Pin Definitions
Pin Number
Pin Name
Definition
Enables the transceiver when Logic 1 and disables the transceiver when Logic 0.
1
SLEEP
2
GND
Device ground pin.
3
LOAD
Accommodates an external pull-down resistor to ground to provide loss of ground protection.
4
BUS
5
VBAT
6
4X/ LOOP
7
TX
Serial data input (DI) from the microcontroller to be transmitted onto Bus.
8
RX
Bus received serial data output (DO) sent to the microcontroller.
Waveshaped SAE Standard J-1850 Class B transmitter output and receiver input.
Provides device operating input power.
Tristate input mode control; Logic 0 = normal waveshaping, Logic 1 = waveshaping disabled for 4X
transmitting, high impedance = loopback mode.
33990
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
VBAT
-16 to 40
V
VI/O(CPU)
-0.3 to 7.0
V
VBUS
-2.0 to 16
V
Human Body Model (3)
VESD1
±2000
Machine Model (4)
VESD2
±200
Storage Temperature
TSTG
-65 to 150
°C
TA
-40 to 125
°C
TJ
-40 to 150
°C
TPPRT
Note 6.
°C
RθJ-A
180
°C / W
VBAT DC Supply Voltage
Input I/O Pins
(1)
(2)
BUS and LOAD Outputs
ESD Voltage
V
Operating Ambient Temperature
Operating Junction Temperature
Peak Package Reflow Temperature During Reflow
Thermal Resistance (Junction-to-Ambient)
(5), (6)
Notes
1. An external series diode must be used to provide reverse battery protection of the device.
2. SLEEP, TX, RX, and 4X / LOOP are normally connected to a microcontroller.
3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
4.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
5.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
6.
33990
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions of 7.0 V ≤ VBAT ≤ 16 V, -40°C ≤ TA ≤ 125°C, SLEEP = 5.0 V unless otherwise noted.
Typical values reflect the parameter's approximate midpoint average value with VBAT = 13 V, TA = 25°C. All positive currents
are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER CONSUMPTION
Operational Battery Current (RMS with Tx = 7.812 kHz Square Wave)
mA
BUS Load = 1380 Ω to GND, 3.6 nF to GND
IBAT (OP1)
–
3.0
11.5
BUS Load = 257 Ω to GND, 20.2 nF to GND
IBAT (OP2)
–
22.4
32
After SLEEP Toggle Low to High; Prior to Tx Toggling
IBAT(BUS L1)
–
1.1
3.0
After Tx Toggle High to Low
IBAT(BUS L2)
–
6.4
8.5
–
38.2
65
4.25
3.9
–
Battery Bus Low Input Current
Sleep State Battery Current
mA
IBAT(SLEEP)
VSLEEP = 0 V
µA
BUS
BUS Input Receiver Threshold (7)
Threshold High (Bus Increasing until Rx ≥ 3.0 V)
Threshold Low (Bus Decreasing until Rx ≤ 3.0 V)
Threshold in Sleep State (SLEEP = 0 V)
Hysteresis (VBUS(IH) - VBUS(IL), SLEEP = 0 V)
V
VBUS(IH)
VBUS(IL)
–
3.7
3.5
BUSTH(SLEEP)
2.4
3.0
3.4
VBUS(HYST)
0.1
0.2
0.6
BUS-Out Voltage (Tx = 5.0 V, 257 Ω ≤ RBUS(L) to GND ≤ 1380 Ω)
V
8.2 V ≤ VBAT ≤ 16 V
VBUS (OUT1)
6.25
6.9
8.0
4.25 V ≤ VBAT ≤ 8.2 V
VBUS (OUT2)
VBAT - 1.6
–
VBAT
Tx = 0 V
VBUS (OUT3)
–
0.27
0.7
60
129
170
-0.055
0.5
BUS Short Circuit Output Current
IBUS (SHORT)
Tx = 5.0 V, -2.0 V ≤ VBUS ≤ 4.8 V
mA
BUS Leakage Current
mA
-2.0 V ≤ VBUS ≤ 0 V (≥ 2.0 ms after Tx Falls to 0 V)
IBUS (LEAK1)
-0.5
0 V ≤ VBUS ≤ VBAT
IBUS (LEAK2)
-0.5
0.5
1.0
0 V ≤ VBUS ≤ 8.0 V
IBUS (LEAK3)
–
0.25
0.5
150
170
190
10
12
15
-1.0
–
0.1
-1.0
–
0.1
BUS Thermal Shutdown (8) (Tx = 5.0 V, IBUS = -0.1 mA)
TBUS (LIM)
Increase Temperature until VBUS ≤ 2.5 V
BUS Thermal Shutdown Hysteresis (9)
TBUS (LI MHYS)
TBUS (LIM) - TBUS (REEN)
LOAD Input Current with Loss of Ground
°C
ILOAD (LOG)
VLOAD = -18 V (see Figure 4)
BUS Input Current with Loss of Ground
°C
mA
IBUS (LOG)
VBUS = -18 V (see Figure 4)
mA
Notes
7. Typical threshold value is the approximate actual occurring switch point value with VBAT = 13 V, TA = 25°C.
8.
9.
Device characterized but not production tested for thermal shutdown.
Device characterized but not production tested for thermal shutdown hysteresis.
33990
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions of 7.0 V ≤ VBAT ≤ 16 V, -40°C ≤ TA ≤ 125°C, SLEEP = 5.0 V unless otherwise noted.
Typical values reflect the parameter's approximate midpoint average value with VBAT = 13 V, TA = 25°C. All positive currents
are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
–
–
0.5
–
0.07
0.2
0.3
0.67
0.9
Unit
BUS (CONTINUED)
BUS Input Current with Loss of VBAT
IBUS (LOB)
VBUS = 9.0 V (see Figure 5)
LOAD Output
LON
IL = 6.0 mA
Unpowered LOAD Output
mA
V
LDIO
VBAT = 0 V, IL = 6.0 mA
V
TX
TX Input Voltage
V
VBUS ≤ 3.875 V
VTx(IL)
–
2.27
0.8
VBUS ≥ 3.875 V
VTx(IH)
3.5
2.27
–
VTx = 5.0 V
ITx(IH)
50
120
200
VTx = 0 V
ITx(IL)
-2.0
-0.1
2.0
V4X / LOOP = 0 V (Normal Mode)
I4X / LOOP(IL)
-200
-95
–
V4X / LOOP = 5.0 V (4X Mode)
I4X / LOOP(IH)
–
95
200
Normal Mode to Loopback Mode
V4X / LOOP(IL)
1.4
1.6
1.8
Loopback Mode to 4X Mode
V4X / LOOP(IH)
3.2
3.43
3.6
0.01
0.18
0.4
4.25
4.48
4.75
2.0
5.9
8.0
4.25
4.56
4.85
TX Input Current
µA
LOOP
4X / LOOP Input Current
µA
4X / LOOP Input Threshold (Tx = 4096 Hz square wave)
V
RX
RX Output Voltage Low
RX Output Voltage High
mA
IRx
VRx = High; Short Circuit Protection Limits
RX Sleep State Output Voltage
V
VRx(HIGH)
VBUS = 7.0 V, IRx = -200 µA
RX Output Current
V
VRx (LOW)
VBUS = 0 V, IRx = 1.6 mA
V
VRx
SLEEP = 0 V, 0 ≤ VBUS ≤ 7.0 V
SLEEP Input Current
µA
VSLEEP = 0 V
ISLEEP (IL)
–
-0.003
-2.0
VSLEEP = 5.0 V
ISLEEP (IH)
1.0
9.5
20
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions of 7.0 V ≤ VBAT ≤ 16 V, -40°C ≤ TA ≤ 125°C, SLEEP = 5.0 V unless otherwise noted.
Typical values reflect the parameter's approximate midpoint average value with VBAT = 13 V, TA = 25°C. All positive currents
are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
Unit
BUS
BUS Voltage Rise Time (10) (9.0 V ≤ VBAT ≤ 16 V, Tx = 7.812 kHz Square
Wave) (see Figure 6)
trise (BUS)
µs
BUS Load = 3,300 pF and 1.38 kΩ to GND
9.0
11.15
15
BUS Load = 16,500 pF and 300 Ω to GND
9.0
11.86
15
BUS Voltage Fall Time
Wave) (see Figure 6)
(10)
(9.0 V ≤ VBAT ≤ 16 V, Tx = 7.812 kHz Square
tfall (BUS)
µs
BUS Load = 3,300 pF and 1.38 kΩ to GND
9.0
10.50
15
BUS Load = 16,500 pF and 300 Ω to GND
9.0
11.17
15
Pulse Width Distortion Time (9.0 V ≤ VBAT ≤ 16 V, Tx = 7.812 kHz Square
Wave) (see Figure 7)
µs
tpwd (BUS)
35
62
93
–
17.7
25
4X Mode
–
2.6
4.0
Normal Mode
13
17.3
24
tSLEEPTxSU
80
40
–
Low-to-Output High
tRxDelay / L–H
–
0.11
2.0
High-to-Output Low
tRxDelay / H–L
–
0.38
2.0
BUS Load = 3,300 pF and 1.38 kΩ to GND
Propagation Delay
tpd (BUS)
TX Threshold to RX Threshold
µs
TX
TX to BUS Delay Time (Tx = 2.5 V to VBUS = 3.875 V) (Figure 8)
SLEEP to Tx Setup Time (Figure 8)
µs
tTxDelay
µs
RX
RX Output Delay Time (TX = 2.5 V to VBUS = 3.875 V) (see Figure 9)
µs
RX Output Transition Time (CRx = 50 pF to GND, 10% and 90% Points)
(see Figure 10)
Low-to-Output High
µs
tRxTrans / L–H
tRxTrans /H–L
High-to-Output Low
(11)
Rx Output Transition Time
90% Points) (see Figure 10)
–
0.34
1.0
–
0.08
1.0
(CRx = 50 pF to GND, SLEEP = 0 V, 10% and
Low-to-Output High
High-to-Output Low
µs
tRxTrans / L–H
tRxTrans /H–L
–
0.32
5.0
–
0.08
5.0
Notes
10. Typical is the parameter's approximate average value with VBAT = 13 V, TA = 25°C.
11.
RX Output Transition Time from a sleep state.
33990
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
TEST FIGURES
5.0 V
64 μs
Tx
33990
0V
IBUS (LOG)
-18 V
BUS
VBAT
tpwd(min)
tpwd
Floating
GND
LOAD
1.5 V
tpwd(max)
ILOAD (LOG)
Figure 4. Loss of Ground Test Circuit
Figure 7. Pulse Width Distortion
33990
IBUS (LOB)
VBAT
SLEEP
2.5 V
9.0 V
BUS
Floating
Tx
tSLEEPTxSU
2.5 V
GND
tTxDelay
BUS
Figure 5. Loss of VBAT Test Circuit
3.875 V
Figure 8. SLEEP to Tx Delay Times
3.5 V
Tx
BUS
64 μs
0.8 V
122 μs
3.875 V
tRxDelay / lowto-output high
tRxDelay /high-tooutput low
80%
BUS
Rx
20%
t rise
2.5 V
t fall
Figure 6. BUS Rise and Fall Times
Figure 9. BUS-to-Rx Delay Time
33990
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TEST FIGURES
tRxTrans / L–H
tRxTrans / H–L
90%
90%
Rx
10%
10%
Figure 10. Rx Rise and Fall Time
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Freescale Semiconductor
9
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33990 is a serial transceiver device designed to meet
the SAE Standard J-1850 Class B performance for bidirectional half-duplex communication. The device is
packaged in an economical surface-mount SOIC plastic
package. An internal block diagram of the device is shown in
Figure 2.
The 33990 derives its robustness to temperature and
voltage extremes from being built on a SMARTMOS process,
incorporating CMOS logic, bipolar/MOS analog circuitry, and
DMOS power FETs. Though the 33990 was principally
designed for automotive applications requiring SAE J-1850
Class B standards, it is suited for other serial communication
applications. It is parametrically specified over an ambient
temperature range of -40°C ≤ TA ≤ 125°C and 7.0 V ≤ VBAT ≤
16 V supply. The economical 8-pin SOICN surface mount
plastic package makes the device a cost-effective solution.
FUNCTIONAL PIN DESCRIPTION
Input Power (VBAT Pin)
This is the only required input power source necessary to
operate the 33990. The internal voltage reference of the
33990 will remain fully operational with a minimum of 9.0 V
on this pin. Bus transmissions can continue with battery
voltages down to 5.0 V. The bus output voltage will follow the
battery voltage down and, in doing so, track approximately
1.6 V below the battery voltage. The device will continue to
receive and transmit bus data to the microcontroller with
battery voltages as low as 4.25 V. The pin can withstand
voltages from -16 V to 40 V.
1.5 kΩ ± 5% pull-down resistor to ground. With more than 26
nodes, there is no primary node (see Figure 13). All nodes
will have a 470 ± 10% pF capacitor and a 10.6 kΩ ± 5% pulldown resistor. No matter how many secondary nodes are on
the Class B bus, the RC time constant of the Class B bus is
maintained at approximately 5.0 μs. The minimum and
maximum capacitance and resistance on the Class B bus is
given by the expressions shown in Table 6.
One Primary Node
Sleep Input (SLEEP Pin)
This input is used to enable and disable the Class B
transmitter. The Class B receiver is always enabled so long
as adequate VBAT pin voltage is applied. When the SLEEP pin
voltage is 5.0 V, the Class B transmitter is enabled. If this
input is logic low, the Class B transmitter will be disabled and
less than 65 µA of current will be drawn by the VBAT pin. The
pin also provides a 5.0 V reference, internal to the device,
used to establish the Rx output level and slew rate times.
10.6 kΩ
470 pF
1.5 kΩ
3300 pF
Figure 11. Minimum Bus Load
Primary Node
Class B Functional Description
The transmitter provides an analog waveshaped 0 V to
7.0 V waveform on the BUS output. It also receives
waveforms and transmits a digital level signal back to a logic
IC. The transmitter can drive up to 32 secondary Class B
transceivers (see Figures 11 and 12). These secondary
nodes may be at ground potentials that are ± 2.0 V relative to
the control assembly. Waveshaping will only be maintained
during 2 of the 4 corners when the 0 to ± 2.0 V ground
potential difference condition exists. The 33990 is a
secondary node on the Class B bus. Each secondary
transceiver has a 470 ± 10% pF capacitor on its output for
EMI suppression purposes, as well as a 10.6 kΩ ± 5% pulldown resistor to ground. The primary node has a 3300 ± 10%
pF capacitor on its output for EMI suppression, as well as a
10.6 kΩ
470 pF
1.5 kΩ
3300 pF
24 Secondary Nodes
442 Ω
11280 pF
Figure 12. Maximum Number of Nodes
33990
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
31 Secondary Nodes
10.6 kΩ
470 pF
342 Ω
14570 pF
Figure 13. Maximum Bus Load
Table 6. Class B Bus Capacitance and Resistance Expressions
Level
Capacitance
Resistance to Ground
Minimum
(3.3 x 0.9) + (0.47 x 0.9) = 3.39 nF
(1.5 x 0.95) || (10.6 x 0.95) / 25 = 314 Ω
Maximum
(3.3 x 1.1) + 25 (0.47 x 1.1) = 16.55 nF
(1.5 x 1.05) || (10.6 x 1.05) = 1.38 kΩ
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Analog Integrated Circuit Device Data
Freescale Semiconductor
11
TYPICAL APPLICATIONS
FUNCTIONAL PIN DESCRIPTION
TYPICAL APPLICATIONS
CLASS B MODULE INPUTS
Transmitter Data from the MCU (TX)
The Tx input is a push-pull (N-channel / P-channel FETs)
buffer with hysteresis for noise immunity purposes. This pin is a
5.0 V CMOS logic level input from the MCU following a true
logic protocol. A logic [0] input drives the BUS output to 0 V (via
the external pull-down resistor to ground on each node), while
a logic [1] input produces a high voltage at the BUS output. A
logic [0] input level is guaranteed when the Tx input pin is an
open-circuit by virtue of an internal 40 kΩ pull-down resistor. No
external resistor is required for its operation.
Waveshaping and 4X / Loop
This input is a tristateable input: 0 V = normal waveshaping,
5.0 V = waveshaping is disabled for 4X transmitting, and high
impedance = loopback mode of operation. This is a logic level
input used to select whether waveshaping for the Class B
output is enabled or disabled. A logic [0] enables waveshaping,
while a logic [1] disables waveshaping. In the 4X mode, the
BUS output rise time is less than 2.0 μs and the fall time is less
than 5.0 μs (owing to the external RC pull-down to ground). In
the loopback condition, the Tx signal is fed back to the Rx
output after waveshaping without being transmitted onto the
BUS. This mode of operation is useful for system diagnostic
purposes.
CLASS B MODULE OUTPUTS
Transceiver Output (BUS)
This is the output driver stage that sources current to the bus.
Its output follows the waveshaped waveform input. Its output
voltage is limited to 6.25 V to 8.0 V under normal battery level
conditions. The limited level is controlled by an internal
regulator/clamp circuit. Once the battery voltage drops below
9.0 V, the regulator / clamp circuit saturates, causing the bus
voltage to track the battery voltage. A 1.5 kΩ ± 5% external
resistor (as well as any 10.6 kΩ pull-down resistors of any
secondary nodes) sinks the current to discharge the capacitors
during high-to-low transitions. This sourcing output is short
circuit-protected (60 mA to 170 mA) against a short to -2.0 V
and sinks less than 1.0 mA when shorted to VBAT. If a short
occurs, the overtemperature shutdown circuit protects the
source driver of the device. In the event battery power is lost to
the assembly, the bus transmitter's output stage will be disabled
and the leakage current from the BUS output will not source or
sink more than 100 mA of current. The transceiver will operate
with a remote ground offset of ± 2.0 V, but the lower corners of
transmission will not be rounded during this condition.
Receiver Output to the Microcontroller (RX)
This is a 5.0 V CMOS compatible push-pull output used to
send received data to the microcontroller. It does not require an
external pull-up resistor to be used. The receiver is always
enabled and draws less than 65 µA of current from VBAT. The
receive threshold is dependent on the state of the SLEEP pin.
The initial state of this output is always a logic [0] after supply
voltage is applied, but before the SLEEP pin goes to a logic [1]
state. The receiver circuitry is able to operate with VBAT
voltages as low as 4.25 V and still remains capable of “waking
up” the 33990 when remote Class B activity is detected.
When the SLEEP pin is low and message activity occurs on
the bus, the receiver passes the bus message through to the
microcontroller. The 33990 does not automatically “wake up”
from a sleep state when bus activity occurs: the microcontroller
must tell it to do so.
In the Static Electrical Characteristics table, the maximum
voltage for Rx is specified as 4.75 V over an operating range of
-40°C to 125°C temperature and 7.0 V to 16 V VBAT. This
maximum Rx voltage is compatible with the minimum VDD
voltage of microcontrollers to prevent the 33990 from sourcing
current to the microcontroller's output.
Switched Ground Output (LOAD)
Normally this output is a saturated switch to ground, which
pulls down the external resistor between the BUS and LOAD
outputs. In the event ground is lost to the assembly, the LOAD
output will bias itself “off” and will not leak more than 100 μA of
current out of this pin.
Overtemperature Shutdown
If the BUS output becomes shorted to ground for any
duration, an overtemperature shutdown circuit “latches off” the
output source transistor whenever the die temperature exceeds
150°C to 190°C. The output transistor remains latched off until
the Tx input is toggled from a logic [0] to a logic [1]. The rising
edge provides the clearing function, provided the locally sensed
temperature is 10°C to 15°C below the latch-off temperature trip
temperature.
Waveshaping
Waveshaping is incorporated into the 33990 to minimize
radiated EMI emissions.
Receiver Protocol
The Class B communication scheme uses a variable pulse
width (VPW) protocol. The microcontroller provides the VPW
decoding function. Once the receiver detects a transition on Rx,
it starts an internal counter. The initial “start of frame” bit is a
logic [1] and lasts 200 μs. For subsequent bits, if there is a bus
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Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
FUNCTIONAL PIN DESCRIPTION
transition before 96 μs, one logic state is inferred. If there is a
bus transition after 96 μs, the other logic state is inferred. The
“end of data” bit is a logic [0] and lasts 200 μs. If there is no
activity on the bus for 280 μs to 320 μs following a broadcast
message, multiple unit nodes may arbitrate for control of the
next message. During an arbitration, after the “start of frame”
bit has been transmitted, the secondary node transmitting the
most consecutive logic [0] bits will be granted sole
transmission access to the bus for that message.
and biased “off” when loss-of-ground occurs. When a loss of
assembly ground occurs, the load transistor switch is selfbiased “off”, allowing no more than 100 μA of leakage current
to flow in the LOAD pin. During such a loss of assembly
ground condition, the BUS and LOAD pins exhibit a high
impedance to VBAT; all other pins will exhibit a low impedance
to VBAT. During this condition the BUS pin is prevented from
sourcing any current or loading the bus, which would cause a
corruption of any data being transmitted on the bus. While a
particular assembly is experiencing a loss of ground, all other
assembly nodes are permitted to function normally. It should
be noted that with other nodes existing on the bus, the bus
will always have some minimum / maximum impedance to
ground as shown in Table 6, page 11.
Loss of Assembly Ground Connection
The definition of a loss of assembly ground condition at the
device level is that all pins of the 33990, with the exception of
BUS and LOAD, see a very low impedance to VBAT.
The LOAD pin of the device has an internal transistor
switch connected to it that is normally saturated to ground.
This pulls the LOAD-side of the external resistor (tied from
BUS to LOAD) to ground under normal conditions. The LOAD
pin switch is essentially that of an “upside down” FET, which
is normally biased “on” so long as module ground is present
Loss of Assembly Battery Connection
The definition of a loss of assembly battery condition at the
device level is that the VBAT pin of the 33990 sees an infinite
impedance to VBAT, but there is some undefined impedance
between these pins and ground.
33990
VBAT
+VBAT
47μH
Primary
Node
BUS
470pF
10.6kΩ
SLEEP
TX
LOAD
MCU
Secondary
Nodes
RX
GND
4X/LOOP
Figure 14. Typical Application
33990
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
D SUFFIX
EF SUFFIX (PB-FREE)
8-PIN
PLASTIC PACKAGE
98ASB42564B
33990
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
2.0
10/2006
•
•
Implemented Revision History page
Converted to Freescale format
3.0
11/2006
•
Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
Maximum Ratings on page 4. Added note with instructions to obtain this information from
www.freescale.com.
4.0
10/2008
•
Changed status to final, “Technical Data” thereby removing the “Advance Information” watermark
on page 1. No Technical Changes.
33990
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
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MC33990
Rev 4.0
10/2008
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