MC68HC908QY4A MC68HC908QT4A MC68HC908QY2A MC68HC908QT2A MC68HC908QY1A MC68HC908QT1A Data Sheet M68HC08 Microcontrollers MC68HC908QY4A Rev. 3 03/2010 freescale.com MC68HC908QY4A MC68HC908QY2A MC68HC908QY1A MC68HC908QT4A MC68HC908QT2A MC68HC908QT1A Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2007–2010. All rights reserved. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 3 Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date Revision Level December, 2005 N/A August, 2006 April, 2007 March, 2010 1 2 3 Page Number(s) Description Initial release N/A Added 1.7 Unused Pin Termination. 20 Figure 4-1. Auto Wakeup Interrupt Request Generation Logic — Corrected clock source. 51 4.3 Functional Description — Clarified operation. 52 4.5.1 Wait Mode — Corrected operation details. 53 4.6.4 Configuration Register 2 — Corrected clock source. 55 4.6.5 Configuration Register 1 — Added SSREC bit description. 55 5.2 Functional Description — Corrected clock source. 58 12.1 Introduction — Replaced note. 103 13.7.2 Stop Mode — Corrected clock source. 121 16.12 Supply Current Characteristics — Updated maximum values for SIDD at both 5 V and 3 V. 165 A.2.3 Improved Auto Wakeup Module (AWU) — Corrected clock source. 194 Chapter 3 Analog-to-Digital Converter (ADC10) Module — Renamed ADCSC register to ADSCR to be consistent with development tools. 37 Figure 15-18. Monitor Mode Entry Timing — Changed CGMXCLK to BUSCLKX4 154 16.12 Supply Current Characteristics — Added note 6 below table 165 Chapter 17 Ordering Information and Mechanical Specifications — Updated chapter to include: Table 17-1. Consumer and Industrial Device Numbering System Table 17-2. Automotive Device Numbering System 17.3 Orderable Part Numbering System 17.3.1 Consumer and Industrial Orderable Part Numbering System 17.3.2 Automotive Orderable Part Number System 171 171 172 172 172 Clarify internal oscillator trim register information. 27, 30, 31, 34, 95, 101 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 4 Freescale Semiconductor List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 3 Analog-to-Digital Converter (ADC10) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chapter 4 Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Chapter 5 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Chapter 6 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Chapter 7 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Chapter 8 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Chapter 10 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Chapter 11 Oscillator (OSC) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Chapter 12 Input/Output Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Chapter 13 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Chapter 14 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Chapter 17 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 171 Appendix A 908QTA/QYxA Conversion Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 5 List of Chapters MC68HC908QYA/QTA Family Data Sheet, Rev. 3 6 Freescale Semiconductor Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Function Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Pin Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 17 18 19 20 20 Chapter 2 Memory 2.1 2.2 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.6.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Memory Emulation Using FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 21 28 29 29 30 31 31 32 34 35 Chapter 3 Analog-to-Digital Converter (ADC10) Module 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Clock Select and Divide Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Input Select and Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Conversion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.1 Initiating Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.2 Completing Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.3 Aborting Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.4 Total Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 37 39 40 40 40 40 40 41 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 7 Table of Contents 3.3.4 Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.1 Sampling Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.2 Pin Leakage Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.3 Noise-Induced Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.4 Code Width and Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.5 Linearity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.6 Code Jitter, Non-Monotonicity and Missing Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 ADC10 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 ADC10 Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 ADC10 Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 ADC10 Voltage Reference High Pin (VREFH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 ADC10 Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.5 ADC10 Channel Pins (ADn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 ADC10 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 ADC10 Result High Register (ADRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3 ADC10 Result Low Register (ADRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.4 ADC10 Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 42 42 43 43 43 44 44 44 44 44 45 45 45 45 45 46 46 46 47 48 48 Chapter 4 Auto Wakeup Module (AWU) 4.1 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 51 52 52 53 53 53 53 53 54 54 55 55 Chapter 5 Configuration Register (CONFIG) 5.1 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 8 Freescale Semiconductor Chapter 6 Computer Operating Properly (COP) 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.4 6.5 6.6 6.6.1 6.6.2 6.7 6.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSCLKX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 62 62 62 62 62 62 62 63 63 63 63 63 63 63 63 Chapter 7 Central Processor Unit (CPU) 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 65 65 66 66 67 67 68 69 69 69 69 69 70 75 Chapter 8 External Interrupt (IRQ) 8.1 8.2 8.3 8.3.1 8.3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 77 77 79 79 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 9 Table of Contents 8.4 8.5 8.5.1 8.5.2 8.6 8.7 8.7.1 8.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Input Pins (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 80 80 80 80 80 80 81 Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 Keyboard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1.1 MODEK = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1.2 MODEK = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.2 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6 KBI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.1 KBI Input Pins (KBIx:KBI0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.1 Keyboard Status and Control Register (KBSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.2 Keyboard Interrupt Enable Register (KBIER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.3 Keyboard Interrupt Polarity Register (KBIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 83 83 83 84 85 86 86 86 86 86 86 87 87 87 87 88 88 Chapter 10 Low-Voltage Inhibit (LVI) 10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.4 10.5 10.5.1 10.5.2 10.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 89 89 90 90 90 90 91 91 91 91 91 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 10 Freescale Semiconductor Chapter 11 Oscillator (OSC) Module 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3.1 Internal Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3.1.1 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3.1.2 XTAL Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1.3 RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1.4 Internal Oscillator Clock (INTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1.5 Bus Clock Times 4 (BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1.6 Bus Clock Times 2 (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.2 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.2.1 Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.2.2 Internal to External Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.3.2.3 External to Internal Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.3.3 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.3.4 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.3.5 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.6 OSC During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.7.1 Oscillator Input Pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.7.2 Oscillator Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.8.1 Oscillator Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.8.2 Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Chapter 12 Input/Output Ports (PORTS) 12.1 12.2 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.4 12.4.1 12.4.2 12.4.3 12.4.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Pin Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 103 103 104 104 105 106 106 106 107 108 108 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 11 Table of Contents Chapter 13 System Integration Module (SIM) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2 Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.1 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.2 Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 109 110 111 111 111 111 111 112 113 113 113 114 114 114 114 114 114 115 115 115 118 118 119 119 119 120 120 120 120 120 121 122 122 123 Chapter 14 Timer Interface Module (TIM) 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 125 125 125 126 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 12 Freescale Semiconductor 14.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7.1 TIM Channel I/O Pins (TCH1:TCH0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7.2 TIM Clock Pin (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 127 128 128 129 129 130 131 131 131 131 131 132 132 132 132 132 134 134 135 137 Chapter 15 Development Support 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.3 Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.4 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.6 Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 139 139 141 141 141 141 142 142 143 143 143 144 144 144 148 148 149 150 150 150 150 154 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 13 Table of Contents Chapter 16 Electrical Specifications 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 16.11 16.12 16.13 16.14 16.15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical 5-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical 3-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 155 156 156 157 158 159 160 161 162 163 165 167 169 170 Chapter 17 Ordering Information and Mechanical Specifications 17.1 17.2 17.3 17.3.1 17.3.2 17.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Orderable Part Numbering System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consumer and Industrial Orderable Part Numbering System . . . . . . . . . . . . . . . . . . . . . . Automotive Orderable Part Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 171 172 172 172 172 Appendix A 908QTA/QYxA Conversion Guidelines A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2 Benefits of the Enhanced QYxA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.1 New Analog-to-Digital Converter Module (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.1.1 Registers Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.2 Enhanced Oscillator Module (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.2.1 Registers Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.3 Improved Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.3.1 Registers Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.4 New Power-on Reset Module (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.5 Keyboard Interface Module (KBI) Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.5.1 Registers Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.6 On-Chip Routine Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.3 Conversion Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.4 Code Changes Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.5 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.6 Differences in Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 191 191 192 193 193 194 194 194 195 195 195 196 196 197 197 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 14 Freescale Semiconductor Chapter 1 General Description 1.1 Introduction The MC68HC908QY4A is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 0.4 Table 1-1. Summary of Device Variations Device FLASH Memory Size ADC Pin Count MC68HC908QT1A MC68HC908QT2A 1536 bytes — 8 pins 1536 bytes 6 channel, 10 bit 8 pins MC68HC908QT4A 4096 bytes 6 channel, 10 bit 8 pins MC68HC908QY1A 1536 bytes — 16 pins MC68HC908QY2A 1536 bytes 6 channel, 10 bit 16 pins MC68HC908QY4A 4096 bytes 6 channel, 10 bit 16 pins 1.2 Features Features include: • High-performance M68HC08 CPU core • Fully upward-compatible object code with M68HC05 Family • 5-V and 3-V operating voltages (VDD) • 8-MHz internal bus operation at 5 V, 4-MHz at 3 V • Trimmable internal oscillator – Software selectable 1 MHz, 2 MHz, or 3.2 MHz internal bus operation – 8-bit trim capability – ±25% untrimmed – Trimmable to approximately 0.4%(1) • Software selectable crystal oscillator range, 32–100 kHz, 1–8 MHz and 8–32 MHz • Software configurable input clock from either internal or external source • Auto wakeup from STOP capability using dedicated internal 32-kHz RC or bus clock source • On-chip in-application programmable FLASH memory – Internal program/erase voltage generation – Monitor ROM containing user callable program/erase routines – FLASH security(2) 1. See 16.11 Oscillator Characteristics for internal oscillator specifications 2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 15 General Description • • • • • • • • • • • • • On-chip random-access memory (RAM) 2-channel, 16-bit timer interface (TIM) module 6-channel, 10-bit analog-to-digital converter (ADC) with internal bandgap reference channel (ADC10) Up to 13 bidirectional input/output (I/O) lines and one input only: – Six shared with KBI – Six shared with ADC – Two shared with TIM – One input only shared with IRQ – High current sink/source capability on all port pins – Selectable pullups on all ports, selectable on an individual bit basis – Three-state ability on all port pins 6-bit keyboard interrupt with wakeup feature (KBI) – Programmable for rising/falling or high/low level detect Low-voltage inhibit (LVI) module features: – Software selectable trip point System protection features: – Computer operating properly (COP) watchdog – Low-voltage detection with reset – Illegal opcode detection with reset – Illegal address detection with reset External asynchronous interrupt pin with internal pullup (IRQ) shared with general-purpose input pin Master asynchronous reset pin with internal pullup (RST) shared with general-purpose input/output (I/O) pin Memory mapped I/O registers Power saving stop and wait modes MC68HC908QY4A, MC68HC908QY2A and MC68HC908QY1A are available in these packages: – 16-pin plastic dual in-line package (PDIP) – 16-pin small outline integrated circuit (SOIC) package – 16-pin thin shrink small outline packages (TSSOP) MC68HC908QT4A, MC68HC908QT2A and MC68HC908QT1A are available in these packages: – 8-pin PDIP – 8-pin SOIC – 8-pin dual flat no lead (DFN) package Features of the CPU08 include the following: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the HC05) • 16-bit index register and stack pointer • Memory-to-memory data transfers • Fast 8 × 8 multiply instruction • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support MC68HC908QYA/QTA Family Data Sheet, Rev. 3 16 Freescale Semiconductor MCU Block Diagram 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908QY4A. PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE VDD POWER SUPPLY VSS RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device PTA[0:5]: Higher current sink and source capability PTB[0:7]: Not available on 8-pin devices Figure 1-1. Block Diagram MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 17 General Description 1.4 Pin Assignments The MC68HC908QT4A, MC68H908QT2A, and MC68HC098QT1A are available in 8-pin packages. The MC68HC908QY4A, MC68HC908QY2A, and MC68HC908QY1A are available in 16-pin packages. Figure 1-2 shows the pin assignment for these packages. VDD 1 8 VSS PTA0/TCH0/KBI0 PTA5/OSC1/AD3/KBI5 2 7 PTA0/TCH0/AD0/KBI0 6 PTA1/TCH1/KBI1 PTA4/OSC2/AD2/KBI4 3 6 PTA1/TCH1/AD1/KBI1 5 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 4 5 PTA2/IRQ/KBI2/TCLK VDD 1 8 VSS PTA5/OSC1/KBI5 2 7 PTA4/OSC2/KBI4 3 PTA3/RST/KBI3 4 8-PIN ASSIGNMENT MC68HC908QT1A PDIP/SOIC 8-PIN ASSIGNMENT MC68HC908QT2A AND MC68HC908QT4A PDIP/SOIC VDD 1 16 VSS PTB0 PTB7 2 15 PTB0/AD4 14 PTB1 PTB6 3 14 PTB1/AD5 13 PTA0/TCH0/KBI0 PTA5/OSC1/AD3/KBI5 4 13 PTA0/TCH0/AD0/KBI0 PTA1/TCH1/KBI1 PTA4/OSC2/AD2/KBI4 5 12 PTA1/TCH1/AD1/KBI1 PTB2 PTB5 6 11 PTB2 PTB3 PTB4 7 10 PTB3 PTA3/RST/KBI3 8 9 VDD 1 16 VSS PTB7 2 15 PTB6 3 PTA5/OSC1/KBI5 4 PTA4/OSC2/KBI4 5 PTB5 6 12 11 PTB4 7 10 PTA3/RST/KBI3 8 9 PTA2/IRQ/KBI2/TCLK 16-PIN ASSIGNMENT MC68HC908QY2A AND MC68HC908QY4A PDIP/SOIC 16-PIN ASSIGNMENT MC68HC908QY1A PDIP/SOIC PTA0/TCH0/KBI0 PTB1 PTB0 VSS VDD PTB7 PTB6 PTA5/OSC1/KBI5 1 2 3 4 5 6 7 8 PTA1/TCH1/KBI1 PTB2 PTB3 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTB4 PTB5 PTA4/OSC2/KBI4 16 15 14 13 12 11 10 9 16-PIN ASSIGNMENT MC68HC908QY1A TSSOP PTA0/TCH0/KBI0 1 PTA2/IRQ/KBI2/TCLK PTA0/TCH0/AD0/KBI0 PTB1/AD5 PTB0/AD4 VSS VDD PTB7 PTB6 PTA5/OSC1/AD3/KBI5 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PTA1/TCH1/AD1/KBI1 PTB2 PTB3 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTB4 PTB5 PTA4/OSC2/AD2/KBI4 16-PIN ASSIGNMENT MC68HC908QY2A AND MC68HC908QY4A TSSOP 8 PTA1/TCH1/KBI1 PTA0/TCH0/AD0/KBI0 1 8 PTA1/TCH1/AD1/KBI1 VSS 2 7 PTA2/IRQ/KBI2/TCLK VSS 2 7 PTA2/IRQ/KBI2/TCLK VDD 3 6 PTA3/RST/KBI3 VDD 3 6 PTA3/RST/KBI3 PTA5/OSC1/KB15 4 5 PTA4/OSC2/KBI4 8-PIN ASSIGNMENT MC68HC908QT1A DFN PTA5//OSC1/AD3/KB15 4 5 PTA4/OSC2/AD2/KBI4 8-PIN ASSIGNMENT MC68HC908QT2A AND MC68HC908QT4A DFN Figure 1-2. MCU Pin Assignments MC68HC908QYA/QTA Family Data Sheet, Rev. 3 18 Freescale Semiconductor Pin Functions 1.5 Pin Functions Table 1-2 provides a description of the pin functions. Table 1-2. Pin Functions Pin Name Description Input/Output VDD Power supply Power VSS Power supply ground Power PTA0 PTA1 PTA2 PTA0 — General purpose I/O port Input/Output TCH0 — Timer Channel 0 I/O Input/Output AD0 — A/D channel 0 input Input KBI0 — Keyboard interrupt input 0 Input PTA1 — General purpose I/O port Input/Output TCH1 — Timer Channel 1 I/O Input/Output AD1 — A/D channel 1 input Input KBI1 — Keyboard interrupt input 1 Input PTA2 — General purpose input-only port Input IRQ — External interrupt with programmable pullup and Schmitt trigger input Input KBI2 — Keyboard interrupt input 2 Input TCLK — Timer clock input Input PTA3 — General purpose I/O port PTA3 PTA4 PTA5 PTB0(1) PTB1(1) PTB2PTB7(1) RST — Reset input, active low with internal pullup and Schmitt trigger Input/Output Input KBI3 — Keyboard interrupt input 3 Input PTA4 — General purpose I/O port Input/Output OSC2 —XTAL oscillator output (XTAL option only) RC or internal oscillator output (OSC2EN = 1 in PTAPUE register) Output Output AD2 — A/D channel 2 input Input KBI4 — Keyboard interrupt input 4 Input PTA5 — General purpose I/O port Input/Output OSC1 — XTAL, RC, or external oscillator input Input AD3 — A/D channel 3 input Input KBI5 — Keyboard interrupt input 5 Input PTB0 — General-purpose I/O port Input/Output AD4 — A/D channel 4 input PTB1 — General-purpose I/O port Input Input/Output AD5 — A/D channel 5 input Input 6 General-purpose I/O port Input/Output 1. The PTB pins are not available on the 8-pin packages. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 19 General Description 1.6 Pin Function Priority Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin. NOTE Upon reset all pins come up as input ports regardless of the priority table. Table 1-3. Function Priority in Shared Pins Pin Name Highest-to-Lowest Priority Sequence PTA0(1) AD0 → TCH0 → KBI0 → PTA0 PTA1(1) AD1 → TCH1 → KBI1 → PTA1 PTA2 IRQ → TCLK → KBI2 → PTA2 PTA3 RST → KBI3 → PTA3 PTA4(1) OSC2 → AD2 → KBI4 → PTA4 PTA5(1) OSC1 → AD3 → KBI5 → PTA5 PTB0(1) AD4 → PTB0 PTB1(1) AD5 → PTB1 1. When a pin is to be used as an ADC pin, the I/O port function should be left as an input and all other shared modules should be disabled. The ADC does not override additional modules using the pin. 1.7 Unused Pin Termination Input pins and I/O port pins that are not used in the application must be terminated. This prevents excess current caused by floating inputs, and enhances immunity during noise or transient events. Termination methods include: 1. Configuring unused pins as outputs and driving high or low; 2. Configuring unused pins as inputs and enabling internal pull-ups; 3. Configuring unused pins as inputs and using external pull-up or pull-down resistors. Never connect unused pins directly to VDD or VSS. Since some general-purpose I/O pins are not available on all packages, these pins must be terminated as well. Either method 1 or 2 above are appropriate. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 20 Freescale Semiconductor Chapter 2 Memory 2.1 Introduction The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1. 2.2 Unimplemented Memory Locations Executing code from an unimplemented location will cause an illegal address reset. In Figure 2-1, unimplemented locations are shaded. 2.3 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1, register locations are marked with the word Reserved or with the letter R. 2.4 Direct Page Registers Figure 2-2 shows the memory mapped registers of the MC68HC908QYA/QTA Family. Registers with addresses between $0000 and $00FF are considered direct page registers and all instructions including those with direct page addressing modes can access them. Registers between $0100 and $FFFF require non-direct page addressing modes. See Chapter 7 Central Processor Unit (CPU) for more information on addressing modes. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 21 Memory $0000 ↓ $003F IDIRECT PAGE REGISTERS 64 BYTES $0040 ↓ $007F UNIMPLEMENTED 64 BYTES $0080 ↓ $00FF RAM 128 BYTES $0100 ↓ $27FF UNIMPLEMENTED 9984 BYTES $2800 ↓ $2A1F AUXILIARY ROM 544 BYTES $2A20 ↓ $2F7D UNIMPLEMENTED 1374 BYTES $2F7E ↓ $2FFF AUXILIARY ROM 130 BYTES $3000 ↓ $EDFF UNIMPLEMENTED 48640 BYTES $EE00 ↓ $FDFF FLASH MEMORY 4096 BYTES RESERVED 2560 BYTES $EE00 ↓ $F7FF $FE00 ↓ $FE1F MISCELLANEOUS REGISTERS 32 BYTES FLASH MEMORY 1536 BYTES $F800 ↓ $FDFF $FE20 ↓ $FF7D MONITOR ROM 350 BYTES $FF7E ↓ $FFAF UNIMPLEMENTED 50BYTES $FFB0 ↓ $FFBD FLASH 14 BYTES $FFBE ↓ $FFC1 MISCELLANEOUS REGISTERS 4 BYTES $FFC2 ↓ $FFCF FLASH 14 BYTES $FFD0 ↓ $FFFF USER VECTORS 48 BYTES MC68HC908QY4A, MC68HC908QT4A Memory Map MC68HC908QT1A, MC68HC908QT2A, MC68HC908QY1A, and MC68HC908QY2A Memory Map Figure 2-1. Memory Map MC68HC908QYA/QTA Family Data Sheet, Rev. 3 22 Freescale Semiconductor Direct Page Registers Addr. Register Name Bit 7 Read: $0000 $0001 $0002 ↓ $0003 $0004 $0005 $0006 ↓ $000A $000B $000C $000D ↓ $0019 $001A $001B $001C Port A Data Register (PTA) Write: See page 104. Reset: Port B Data Register Read: (PTB) Write: See page 106. Reset: R 6 AWUL 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 Bit 0 PTA1 PTA0 PTB1 PTB0 DDRA1 DDRA0 Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 Unaffected by reset Reserved Data Direction Register A Read: (DDRA) Write: See page 104. Reset: Data Direction Register B Read: (DDRB) Write: See page 107. Reset: 0 R R DDRA5 DDRA4 DDRA3 0 0 0 0 0 0 0 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 0 0 0 0 0 0 0 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0 0 0 0 0 0 0 0 0 0 0 KEYF 0 IMASKK MODEK Reserved Port A Input Pullup Enable Read: OSC2EN Register (PTAPUE) Write: See page 105. Reset: 0 Port B Input Pullup Enable Read: PTBPUE7 Register (PTBPUE) Write: See page 108. Reset: 0 0 Reserved Keyboard Status and Read: Control Register (KBSCR) Write: See page 87. Reset: 0 Keyboard Interrupt Read: Enable Register (KBIER) Write: See page 88. Reset: 0 Read: 0 0 Keyboard Interrupt Polarity Register (KBIPR) Write: See page 88. Reset: ACKK 0 0 0 0 0 0 0 0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 0 0 0 KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0 0 0 0 0 0 0 R = Reserved = Unimplemented U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 23 Memory Addr. Register Name Read: $001D $001E IRQ Status and Control Register (INTSCR) Write: See page 81. Reset: Configuration Register 2 Read: (CONFIG2)(1) Write: See page 57. Reset: Bit 7 6 5 4 3 2 0 0 0 0 IRQF 0 ACK 1 Bit 0 IMASK MODE 0 0 0 0 0 0 0 0 IRQPUD IRQEN R R R R OSCENINSTOP RSTEN 0 0 0 0 0 0 0 0(2) 1. One-time writable register after each reset. 2. RSTEN reset to 0 by a power-on reset (POR) only. $001F Configuration Register 1 Read: (CONFIG1)(1) Write: See page 58. Reset: COPRS LVISTOP LVIRSTD LVIPWRD LVITRIP SSREC STOP COPD 0 0 0 0 0(2) 0 0 0 PS2 PS1 PS0 1. One-time writable register after each reset. 2. LVITRIP reset to 0 by a power-on reset (POR) only. $0020 $0021 $0022 TIM Status and Control Read: Register (TSC) Write: See page 132. Reset: TOF $0024 $0025 $0026 0 0 1 0 0 0 0 0 TIM Counter Register High Read: (TCNTH) Write: See page 134. Reset: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 TIM Counter Register Low Read: (TCNTL) Write: See page 134. Reset: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 TIM Counter Modulo Register High (TMODH) Write: See page 134. Reset: TIM Counter Modulo Read: Register Low (TMODL) Write: See page 134. Reset: TIM Channel 0 Status and Read: Control Register (TSC0) Write: See page 135. Reset: TIM Channel 0 Read: Register High (TCH0H) Write: See page 137. Reset: Read: $0027 0 TSTOP Read: $0023 0 TOIE TIM Channel 0 Register Low (TCH0L) Write: See page 137. Reset: 0 CH0F 0 TRST Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 24 Freescale Semiconductor Direct Page Registers Addr. Register Name Bit 7 Read: $0028 $0029 $002A $002B ↓ $0035 $0036 $0037 $0038 $0039 ↓ $003B $003C TIM Channel 1 Status and Control Register (TSC1) Write: See page 135. Reset: TIM Channel 1 Read: Register High (TCH1H) Write: See page 137. Reset: TIM Channel 1 Read: Register Low (TCH1L) Write: See page 137. Reset: $003E $003F 0 6 5 0 CH1IE 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset Reserved Oscillator Status and Read: OSCOPT1 OSCOPT0 Control Register (OSCSC) Write: See page 100. Reset: 0 0 ECGST ICFS1 ICFS0 ECFS1 ECFS0 ECGON 1 0 0 0 0 0 Reserved Oscillator Trim Register (OSCTRIM) See page 101. Read: Write: Reset: TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0 1 0 0 0 0 0 0 0 COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 AD9 AD8 R R R R R R R R 0 0 0 0 0 0 0 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R R R R R R R R 0 0 0 0 0 0 0 0 ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ACLKEN 0 0 0 0 0 0 0 0 R = Reserved Reserved ADC10 Status and Control Read: Register (ADSCR) Write: See page 46. Reset: Read: $003D CH1F ADC10 Data Register High (ADRH) Write: See page 48. Reset: ADC10 Data Register Low Read: (ADRL) Write: See page 48. Reset: ADC10 Clock Register Read: (ADCLK) Write: See page 48. Reset: = Unimplemented U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 25 Memory Addr. Register Name Bit 7 Read: $FE00 $FE01 $FE02 $FE03 Break Status Register (BSR) Write: See page 143. Reset: $FE05 $FE06 $FE07 $FE08 $FE0A $FE0B R R 3 R 2 1 SBSW R 0 Bit 0 R 0 PIN COP ILOP ILAD MODRST LVI 0 POR: 1 0 0 0 0 0 0 0 Break Auxiliary Read: Register (BRKAR) Write: See page 143. Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCFE R R R R R R R Interrupt Status Register 1 (INT1) Write: See page 119. Reset: IF6 IF5 IF4 IF3 IF2 IF1 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 Interrupt Status Register 2 Read: (INT2) Write: See page 119. Reset: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 R R R R R R R R 0 0 0 0 0 0 0 0 Interrupt Status Register 3 Read: (INT3) Write: See page 119. Reset: IF22 IF21 IF20 IF19 IF18 IF17 IF16 IF15 R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 HVEN MASS ERASE PGM 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 BRKE BRKA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R = Reserved Break Flag Control Read: Register (BFCR) Write: See page 143. Reset: BDCOP 0 Reserved FLASH Control Register Read: (FLCR) Write: See page 29. Reset: Read: $FE09 R 4 Write: Read: $FE04 5 POR SIM Reset Status Register (SRSR) See page 122. Read: R 6 Break Address High Register (BRKH) Write: See page 142. Reset: Break Address low Read: Register (BRKL) Write: See page 142. Reset: Break Status and Control Read: Register (BRKSCR) Write: See page 143. Reset: = Unimplemented U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 26 Freescale Semiconductor Direct Page Registers Addr. Register Name Read: $FE0C $FE0D ↓ $FE0F $FFBE $FFBF $FFC0 $FFC1 $FFFF LVI Status Register (LVISR) Write: See page 91. Reset: Bit 7 6 5 4 3 2 1 Bit 0 LVIOUT 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 TRIM2 TRIM1 TRIM0 TRIM2 TRIM1 TRIM0 Reserved FLASH Block Protect Read: Register (FLBPR) Write: See page 34. Reset: Unaffected by reset Reserved Internal Oscillator Trim Read: (Factory Programmed Write: VDD = 3.0 V) Reset: Internal Oscillator Trim Read: (Factory Programmed Write: VDD = 5.0 V) Reset: COP Control Register Read: (COPCTL) Write: See page 63. Reset: TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 Unaffected by reset TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 Unaffected by reset LOW BYTE OF RESET VECTOR WRITING CLEARS COP COUNTER (ANY VALUE) Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 27 Memory Table 2-1. Vector Addresses Vector Priority Vector Address Lowest IF22IF16 $FFD0,1$FFDC,D Not used IF15 $FFDE,F ADC conversion complete vector IF14 $FFE0,1 Keyboard vector IF13 — Not used IF12 — Not used IF11 — Not used IF10 — Not used IF9 — Not used IF8 — Not used IF7 — Not used IF6 — Not used IF5 $FFF2,3 TIM overflow vector IF4 $FFF4,5 TIM channel 1 vector IF3 $FFF6,7 TIM channel 0 vector IF2 — IF1 $FFFA,B IRQ vector — $FFFC,D SWI vector — $FFFE,F Reset vector Highest Vector Not used 2.5 Random-Access Memory (RAM) This MCU includes static RAM. The locations in RAM below $0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait or stop mode. At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HC08 resets the stack pointer to $00FF. In the devices that have RAM above $00FF, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM). LDHX TXS #RamLast+1 ;point one past RAM ;SP<-(H:X-1) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 28 Freescale Semiconductor FLASH Memory (FLASH) 2.6 FLASH Memory (FLASH) The FLASH memory is intended primarily for program storage. In-circuit programming allows the operating program to be loaded into the FLASH memory after final assembly of the application product. It is possible to program the entire array through the single-wire monitor mode interface. Because no special voltages are needed for FLASH erase and programming operations, in-application programming is also possible through other software-controlled communication paths. This subsection describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from the internal VDD supply. The program and erase operations are enabled through the use of an internal charge pump. The minimum size of FLASH memory that can be erased is 64 bytes; and the maximum size of FLASH memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase operations are facilitated through control bits in the FLASH control register (FLCR). Details for these operations appear later in this section. NOTE An erased bit reads as a 1 and a programmed bit reads as a 0. A security feature prevents viewing of the FLASH contents.(1) 2.6.1 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations. Read: Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 = Unimplemented Figure 2-3. FLASH Control Register (FLCR) HVEN — High Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM =1 or ERASE =1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS — Mass Erase Control Bit This read/write bit configures the memory for mass erase operation. 1 = Mass erase operation selected 0 = Mass erase operation unselected 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 29 Memory ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation unselected PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation unselected 2.6.2 FLASH Page Erase Operation Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The user interrupt vector area resides in the $FFC0–$FFFF page. Any FLASH memory page can be erased alone. 1. Set the ERASE bit and clear the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH location within the address range of the block to be erased. 4. Wait for a time, tNVS. 5. Set the HVEN bit. 6. Wait for a time, tErase. 7. Clear the ERASE bit. 8. Wait for a time, tNVH. 9. Clear the HVEN bit. 10. After time, tRCV, the memory can be accessed in read mode again. NOTE The COP register at location $FFFF should not be written between steps 5-9, when the HVEN bit is set. Since this register is located at a valid FLASH address, unpredictable behavior may occur if this location is written while HVEN is set. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, other unrelated operations may occur between the steps. CAUTION A page erase of the vector page will erase the internal oscillator trim values at $FFC0 and $FFC1. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 30 Freescale Semiconductor FLASH Memory (FLASH) 2.6.3 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory to read as a 1: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address(1) within the FLASH memory address range. 4. Wait for a time, tNVS. 5. Set the HVEN bit. 6. Wait for a time, tMErase. 7. Clear the ERASE and MASS bits. NOTE Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF). 8. Wait for a time, tNVHL. 9. Clear the HVEN bit. 10. After time, tRCV, the memory can be accessed in read mode again. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, other unrelated operations may occur between the steps. CAUTION A mass erase will erase the internal oscillator trim values at $FFC0 and $FFC1. 2.6.4 FLASH Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, or $XXE0. Use the following step-by-step procedure to program a row of FLASH memory Figure 2-4 shows a flowchart of the programming algorithm. NOTE Do not program any byte in the FLASH more than once after a successful erase operation. Reprogramming bits to a byte which is already programmed is not allowed without first erasing the page in which the byte resides or mass erasing the entire FLASH memory. Programming without first erasing may disturb data stored in the FLASH. 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read the FLASH block protect register. 3. Write any data to any FLASH location within the address range desired. 4. Wait for a time, tNVS. 5. Set the HVEN bit. 1. When in monitor mode, with security sequence failed (see 15.3.2 Security), write to the FLASH block protect register instead of any FLASH address. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 31 Memory 6. 7. 8. 9. 10. 11. 12. 13. Wait for a time, tPGS. Write data to the FLASH address being programmed(1). Wait for time, tPROG. Repeat step 7 and 8 until all desired bytes within the row are programmed. Clear the PGM bit (1). Wait for time, tNVH. Clear the HVEN bit. After time, tRCV, the memory can be accessed in read mode again. NOTE The COP register at location $FFFF should not be written between steps 5-12, when the HVEN bit is set. Since this register is located at a valid FLASH address, unpredictable behavior may occur if this location is written while HVEN is set. This program sequence is repeated throughout the memory until all data is programmed. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed tPROG maximum, see 16.15 Memory Characteristics. 2.6.5 FLASH Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations. NOTE In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit. When the FLBPR is programmed with all 0 s, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase. When bits within the FLBPR are programmed, they lock a block of memory. The address ranges are shown in 2.6.6 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be erased or programmed only with an external voltage, VTST, present on the IRQ pin. This voltage also allows entry from reset into the monitor mode. 1. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, tPROG maximum. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 32 Freescale Semiconductor FLASH Memory (FLASH) Algorithm for Programming a Row (32 Bytes) of FLASH Memory 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 WAIT FOR A TIME, tNVS 5 SET HVEN BIT 6 WAIT FOR A TIME, tPGS 7 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED 8 WAIT FOR A TIME, tPROG 9 COMPLETED PROGRAMMING THIS ROW? Y N 10 11 12 NOTES: The time between each FLASH address change (step 7 to step 7 loop), or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step 10) must not exceed the maximum programming time, tPROG max. 13 This row program algorithm assumes the row/s to be programmed are initially erased. CLEAR PGM BIT WAIT FOR A TIME, tNVH CLEAR HVEN BIT WAIT FOR A TIME, tRCV END OF PROGRAMMING Figure 2-4. FLASH Programming Flowchart MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 33 Memory 2.6.6 FLASH Block Protect Register The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting address of the protected range within the FLASH memory. Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Reset: Unaffected by reset. Initial value from factory is 1. Write to this register is by a programming sequence to the FLASH memory. Figure 2-5. FLASH Block Protect Register (FLBPR) BPR[7:0] — FLASH Protection Register Bits [7:0] These eight bits in FLBPR represent bits [13:6] of a 16-bit memory address. Bits [15:14] are 1s and bits [5:0] are 0s. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 within the FLASH memory. See Figure 2-6 and Table 2-2. 16-BIT MEMORY ADDRESS START ADDRESS OF FLASH BLOCK PROTECT 1 1 FLBPR VALUE 0 0 0 0 0 0 Figure 2-6. FLASH Block Protect Start Address Table 2-2. Examples of Protect Start Address BPR[7:0] Start of Address of Protect Range $00–$B8 The entire FLASH memory is protected. $B8 (1011 1000) $EE00 (1110 1110 0000 0000) $B9 (1011 1001) $EE40 (1110 1110 0100 0000) $BA (1011 1010) $EE80 (1110 1110 1000 0000) $BB (1011 1011) $EFC0 (1110 1110 1100 0000) and so on... $DE (1101 1110) $F780 (1111 0111 1000 0000) $DF (1101 1111) $F7C0 (1111 0111 1100 0000) $FE (1111 1110) $FF80 (1111 1111 1000 0000) FLBPR, internal oscillator trim values, and vectors are protected $FF The entire FLASH memory is not protected. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 34 Freescale Semiconductor FLASH Memory (FLASH) 2.6.7 EEPROM Memory Emulation Using FLASH Memory In some applications, the user may want to repeatedly store and read a set of data from an area of nonvolatile memory. This is easily implemented in EEPROM memory because single byte erase is allowed in EEPROM. When using FLASH memory, the minimum erase size is a page. However, the FLASH can be used as EEPROM memory. This technique is called “EEPROM emulation”. The basic concept of EEPROM emulation using FLASH is that a page is continuously programmed with a new data set without erasing the previously programmed locations. Once the whole page is completely programmed or the page does not have enough bytes to program a new data set, the user software automatically erases the page and then programs a new data set in the erased page. In EEPROM emulation when data is read from the page, the user software must find the latest data set in the page since the previous data still remains in the same page. There are many ways to monitor the page erase timing and the latest data set. One example is unprogrammed FLASH bytes are detected by checking programmed bytes (non-$FF value) in a page. In this way, the end of the data set will contain unprogrammed data ($FF value). A couple of application notes, describing how to emulate EEPROM using FLASH, are available on our web site. Titles and order numbers for these application notes are given at the end of this subsection. For EEPROM emulation software to work successfully, the following items must be taken care of in the user software: 1. Each FLASH byte in a page must be programmed only one time until the page is erased. 2. A page must be erased before the FLASH cumulative program HV period (tHV) is beyond the maximum tHV. tHV is defined as the cumulative high-voltage programming time to the same row before the next erase. For more detailed information, refer to 16.15 Memory Characteristics. 3. FLASH row erase and program cycles should not exceed 10,000 cycles, respectively. The above EEPROM emulation software can be easily developed by using the on-chip FLASH routines implemented in the MCU. These routines are located in the ROM memory and support FLASH program and erase operations. Proper utilization of the on-chip FLASH routines guarantee conformance to the FLASH specifications. In the on-chip FLASH programming routine called PRGRNGE, the high-voltage programming time is enabled for less than 125 μs when programming a single byte at any operating bus frequency between 1.0 MHz and 8.4 MHz. Therefore, even when a row is programmed by 32 separate single-byte programming operations, tHV is less than the maximum tHV. Hence, item 2 listed above is already taken care of by using this routine. A page erased operation is provided in the FLASH erase routine called ERARNGE. Application note AN2635 (On-Chip FLASH Programming Routines) describes how to use these routines. The following application notes, available at www.freescale.com, describe how EERPOM emulation is implemented using FLASH: AN2183 — Using FLASH as EEPROM on the MC68HC908GP32 AN2346 — EEPROM Emulation Using FLASH in MC68HC908QY/QT MCUs AN2690 — Low Frequency EEPROM Emulation on the MC68HC908QY4 An EEPROM emulation driver, available at www.freescale.com, has been developed and qualified: AN3040 — M68HC08 EEPROM Emulation Driver MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 35 Memory MC68HC908QYA/QTA Family Data Sheet, Rev. 3 36 Freescale Semiconductor Chapter 3 Analog-to-Digital Converter (ADC10) Module 3.1 Introduction This section describes the 10-bit successive approximation analog-to-digital converter (ADC10). The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. See Figure 3-1 for port location of these shared pins. The ADC10 on this MCU uses VDD and VSS as its supply and reference pins. This MCU uses BUSCLKX4 as its alternate clock source for the ADC. This MCU does not have a hardware conversion trigger. 3.2 Features Features of the ADC10 module include: • Linear successive approximation algorithm with 10-bit resolution • Output formatted in 10- or 8-bit right-justified format • Single or continuous conversion (automatic power-down in single conversion mode) • Configurable sample time and conversion speed (to save power) • Conversion complete flag and interrupt • Input clock selectable from up to three sources • Operation in wait and stop modes for lower noise operation • Selectable asynchronous hardware conversion trigger 3.3 Functional Description The ADC10 uses successive approximation to convert the input sample taken from ADVIN to a digital representation. The approximation is taken and then rounded to the nearest 10- or 8-bit value to provide greater accuracy and to provide a more robust mechanism for achieving the ideal code-transition voltage. Figure 3-2 shows a block diagram of the ADC10 For proper conversion, the voltage on ADVIN must fall between VREFH and VREFL. If ADVIN is equal to or exceeds VREFH, the converter circuit converts the signal to $3FF for a 10-bit representation or $FF for a 8-bit representation. If ADVIN is equal to or less than VREFL, the converter circuit converts it to $000. Input voltages between VREFH and VREFL are straight-line linear conversions. NOTE Input voltage must not exceed the analog supply voltages. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 37 Analog-to-Digital Converter (ADC10) Module PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT VDD POWER SUPPLY MONITOR ROM BREAK MODULE VSS RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device PTA[0:5]: Higher current sink and source capability PTB[0:7]: Not available on 8-pin devices Figure 3-1. Block Diagram Highlighting ADC10 Block and Pins MC68HC908QYA/QTA Family Data Sheet, Rev. 3 38 Freescale Semiconductor Functional Description ADIV ADLPC ADLSMP MODE COMPLETE 2 ADCO COCO AIEN ADCH 1 ADCK MCU STOP CONTROL SEQUENCER ADHWT ADICLK ADCLK ADSCR ACLKEN ASYNC CLOCK GENERATOR ACLK CLOCK DIVIDE BUS CLOCK ••• ADVIN ABORT CONVERT TRANSFER AD0 SAMPLE INITIALIZE ALTERNATE CLOCK SOURCE SAR CONVERTER AIEN 1 COCO 2 INTERRUPT ADn VREFH VREFL DATA REGISTERS ADRH:ADRL Figure 3-2. ADC10 Block Diagram The ADC10 can perform an analog-to-digital conversion on one of the software selectable channels. The output of the input multiplexer (ADVIN) is converted by a successive approximation algorithm into a 10-bit digital result. When the conversion is completed, the result is placed in the data registers (ADRH and ADRL). In 8-bit mode, the result is rounded to 8 bits and placed in ADRL. The conversion complete flag is then set and an interrupt is generated if the interrupt has been enabled. 3.3.1 Clock Select and Divide Circuit The clock select and divide circuit selects one of three clock sources and divides it by a configurable value to generate the input clock to the converter (ADCK). The clock can be selected from one of the following sources: • The asynchronous clock source (ACLK) — This clock source is generated from a dedicated clock source which is enabled when the ADC10 is converting and the clock source is selected by setting the ACLKEN bit. When the ADLPC bit is clear, this clock operates from 1–2 MHz; when ADLPC is set it operates at 0.5–1 MHz. This clock is not disabled in STOP and allows conversions in stop mode for lower noise operation. • Alternate Clock Source — This clock source is equal to the external oscillator clock or a four times the bus clock. The alternate clock source is MCU specific, see 3.1 Introduction to determine source and availability of this clock source option. This clock is selected when ADICLK and ACLKEN are both low. • The bus clock — This clock source is equal to the bus frequency. This clock is selected when ADICLK is high and ACLKEN is low. Whichever clock is selected, its frequency must fall within the acceptable frequency range for ADCK. If the available clocks are too slow, the ADC10 will not perform according to specifications. If the available MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 39 Analog-to-Digital Converter (ADC10) Module clocks are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV[1:0] bits and can be divide-by 1, 2, 4, or 8. 3.3.2 Input Select and Pin Control Only one analog input may be used for conversion at any given time. The channel select bits in ADSCR are used to select the input signal for conversion. 3.3.3 Conversion Control Conversions can be performed in either 10-bit mode or 8-bit mode as determined by the MODE bits. Conversions can be initiated by either a software or hardware trigger. In addition, the ADC10 module can be configured for low power operation, long sample time, and continuous conversion. 3.3.3.1 Initiating Conversions A conversion is initiated: • Following a write to ADSCR (with ADCH bits not all 1s) if software triggered operation is selected. • Following a hardware trigger event if hardware triggered operation is selected. • Following the transfer of the result to the data registers when continuous conversion is enabled. If continuous conversions are enabled a new conversion is automatically initiated after the completion of the current conversion. In software triggered operation, continuous conversions begin after ADSCR is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. 3.3.3.2 Completing Conversions A conversion is completed when the result of the conversion is transferred into the data result registers, ADRH and ADRL. This is indicated by the setting of the COCO bit. An interrupt is generated if AIEN is high at the time that COCO is set. A blocking mechanism prevents a new result from overwriting previous data in ADRH and ADRL if the previous data is in the process of being read while in 10-bit mode (ADRH has been read but ADRL has not). In this case the data transfer is blocked, COCO is not set, and the new result is lost. When a data transfer is blocked, another conversion is initiated regardless of the state of ADCO (single or continuous conversions enabled). If single conversions are enabled, this could result in several discarded conversions and excess power consumption. To avoid this issue, the data registers must not be read after initiating a single conversion until the conversion completes. 3.3.3.3 Aborting Conversions Any conversion in progress will be aborted when: • A write to ADSCR occurs (the current conversion will be aborted and a new conversion will be initiated, if ADCH are not all 1s). • A write to ADCLK occurs. • The MCU is reset. • The MCU enters stop mode with ACLK not enabled. When a conversion is aborted, the contents of the data registers, ADRH and ADRL, are not altered but continue to be the values transferred after the completion of the last successful conversion. In the case that the conversion was aborted by a reset, ADRH and ADRL return to their reset states. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 40 Freescale Semiconductor Functional Description Upon reset or when a conversion is otherwise aborted, the ADC10 module will enter a low power, inactive state. In this state, all internal clocks and references are disabled. This state is entered asynchronously and immediately upon aborting of a conversion. 3.3.3.4 Total Conversion Time The total conversion time depends on many factors such as sample time, bus frequency, whether ACLKEN is set, and synchronization time. The total conversion time is summarized in Table 3-1. Table 3-1. Total Conversion Time versus Control Conditions Conversion Mode ACLKEN Maximum Conversion Time 8-Bit Mode (short sample — ADLSMP = 0): Single or 1st continuous Single or 1st continuous Subsequent continuous (fBus ≥ fADCK) 0 1 X 18 ADCK + 3 bus clock 18 ADCK + 3 bus clock + 5 μs 16 ADCK 8-Bit Mode (long sample — ADLSMP = 1): Single or 1st continuous Single or 1st continuous Subsequent continuous (fBus ≥ fADCK) 0 1 X 38 ADCK + 3 bus clock 38 ADCK + 3 bus clock + 5 μs 36 ADCK 10-Bit Mode (short sample — ADLSMP = 0): Single or 1st continuous Single or 1st continuous Subsequent continuous (fBus ≥ fADCK) 0 1 X 21 ADCK + 3 bus clock 21 ADCK + 3 bus clock + 5 μs 19 ADCK 10-Bit Mode (long sample — ADLSMP = 1): Single or 1st continuous Single or 1st continuous Subsequent continuous (fBus ≥ fADCK) 0 1 X 41 ADCK + 3 bus clock 41 ADCK + 3 bus clock + 5 μs 39 ADCK The maximum total conversion time for a single conversion or the first conversion in continuous conversion mode is determined by the clock source chosen and the divide ratio selected. The clock source is selectable by the ADICLK and ACLKEN bits, and the divide ratio is specified by the ADIV bits. For example, if the alternate clock source is 16 MHz and is selected as the input clock source, the input clock divide-by-8 ratio is selected and the bus frequency is 4 MHz, then the conversion time for a single 10-bit conversion is: Maximum Conversion time = 21 ADCK cycles 16 MHz/8 + 3 bus cycles 4 MHz = 11.25 μs Number of bus cycles = 11.25 μs x 4 MHz = 45 cycles NOTE The ADCK frequency must be between fADCK minimum and fADCK maximum to meet A/D specifications. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 41 Analog-to-Digital Converter (ADC10) Module 3.3.4 Sources of Error Several sources of error exist for ADC conversions. These are discussed in the following sections. 3.3.4.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 15 kΩ and input capacitance of approximately 10 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles / 2 MHz maximum ADCK frequency) provided the resistance of the external analog source (RAS) is kept below 10 kΩ. Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time. 3.3.4.2 Pin Leakage Error Leakage on the I/O pins can cause conversion error if the external analog source resistance (RAS) is high. If this error cannot be tolerated by the application, keep RAS lower than VADVIN / (4096*ILeak) for less than 1/4LSB leakage error (at 10-bit resolution). 3.3.4.3 Noise-Induced Errors System noise which occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC10 accuracy numbers are guaranteed as specified only if the following conditions are met: • There is a 0.1μF low-ESR capacitor from VREFH to VREFL (if available). • There is a 0.1μF low-ESR capacitor from VDDA to VSSA (if available). • If inductive isolation is used from the primary supply, an additional 1μF capacitor is placed from VDDA to VSSA (if available). • VSSA and VREFL (if available) is connected to VSS at a quiet point in the ground plane. • The MCU is placed in wait mode immediately after initiating the conversion (next instruction after write to ADSCR). • There is no I/O switching, input or output, on the MCU during the conversion. There are some situations where external system activity causes radiated or conducted noise emissions or excessive VDD noise is coupled into the ADC10. In these cases, or when the MCU cannot be placed in wait or I/O activity cannot be halted, the following recommendations may reduce the effect of noise on the accuracy: • Place a 0.01 μF capacitor on the selected input channel to VREFL or VSSA (if available). This will improve noise issues but will affect sample rate based on the external analog source resistance. • Operate the ADC10 in stop mode by setting ACLKEN, selecting the channel in ADSCR, and executing a STOP instruction. This will reduce VDD noise but will increase effective conversion time due to stop recovery. • Average the input by converting the output many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. • Reduce the effect of synchronous noise by operating off the asynchronous clock (ACLKEN=1) and averaging. Noise that is synchronous to the ADCK cannot be averaged out. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 42 Freescale Semiconductor Functional Description 3.3.4.4 Code Width and Quantization Error The ADC10 quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step ideally has the same height (1 code) and width. The width is defined as the delta between the transition points from one code to the next. The ideal code width for an N bit converter (in this case N can be 8 or 10), defined as 1LSB, is: 1LSB = (VREFH–VREFL) / 2N Because of this quantization, there is an inherent quantization error. Because the converter performs a conversion and then rounds to 8 or 10 bits, the code will transition when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. Therefore, the quantization error will be ± 1/2LSB in 8- or 10-bit mode. As a consequence, however, the code width of the first ($000) conversion is only 1/2LSB and the code width of the last ($FF or $3FF) is 1.5LSB. 3.3.4.5 Linearity Errors The ADC10 may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors but the user should be aware of them because they affect overall accuracy. These errors are: • Zero-Scale Error (EZS) (sometimes called offset) — This error is defined as the difference between the actual code width of the first conversion and the ideal code width (1/2LSB). Note, if the first conversion is $001, then the difference between the actual $001 code width and its ideal (1LSB) is used. • Full-Scale Error (EFS) — This error is defined as the difference between the actual code width of the last conversion and the ideal code width (1.5LSB). Note, if the last conversion is $3FE, then the difference between the actual $3FE code width and its ideal (1LSB) is used. • Differential Non-Linearity (DNL) — This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. • Integral Non-Linearity (INL) — This error is defined as the highest-value the (absolute value of the) running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. • Total Unadjusted Error (TUE) — This error is defined as the difference between the actual transfer function and the ideal straight-line transfer function, and therefore includes all forms of error. 3.3.4.6 Code Jitter, Non-Monotonicity and Missing Codes Analog-to-digital converters are susceptible to three special forms of error. These are code jitter, non-monotonicity, and missing codes. • Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the converter yields the lower code (and vice-versa). However, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. This range is normally around ±1/2LSB but will increase with noise. • Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Non-monotonicity is present if the apparent code jitter covers three codes (when the converter’s output is indeterminate between three values for a given input voltage) or is greater than 1LSB. • Missing codes are those which are never converted for any input value. In 8-bit or 10-bit mode, the ADC10 is guaranteed to be monotonic and to have no missing codes. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 43 Analog-to-Digital Converter (ADC10) Module 3.4 Interrupts When AIEN is set, the ADC10 is capable of generating a CPU interrupt after each conversion. A CPU interrupt is generated when the conversion completes (indicated by COCO being set). COCO will set at the end of a conversion regardless of the state of AIEN. 3.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 3.5.1 Wait Mode The ADC10 will continue the conversion process and will generate an interrupt following a conversion if AIEN is set. If the ADC10 is not required to bring the MCU out of wait mode, ensure that the ADC10 is not in continuous conversion mode by clearing ADCO in the ADC10 status and control register before executing the WAIT instruction. In single conversion mode the ADC10 automatically enters a low-power state when the conversion is complete. It is not necessary to set the channel select bits (ADCH[4:0]) to all 1s to enter a low power state. 3.5.2 Stop Mode If ACLKEN is clear, executing a STOP instruction will abort the current conversion and place the ADC10 in a low-power state. Upon return from stop mode, a write to ADSCR is required to resume conversions, and the result stored in ADRH and ADRL will represent the last completed conversion until the new conversion completes. If ACLKEN is set, the ADC10 continues normal operation during stop mode. The ADC10 will continue the conversion process and will generate an interrupt following a conversion if AIEN is set. If the ADC10 is not required to bring the MCU out of stop mode, ensure that the ADC10 is not in continuous conversion mode by clearing ADCO in the ADC10 status and control register before executing the STOP instruction. In single conversion mode the ADC10 automatically enters a low-power state when the conversion is complete. It is not necessary to set the channel select bits (ADCH[4:0]) to all 1s to enter a low-power state. If ACLKEN is set, a conversion can be initiated while in stop using the external hardware trigger ADEXTCO when in external convert mode. The ADC10 will operate in a low-power mode until the trigger is asserted, at which point it will perform a conversion and assert the interrupt when complete (if AIEN is set). 3.6 ADC10 During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. BCFE in the break flag control register (BFCR) enables software to clear status bits during the break state. See BFCR in the SIM section of this data sheet. To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the MC68HC908QYA/QTA Family Data Sheet, Rev. 3 44 Freescale Semiconductor I/O Signals break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. 3.7 I/O Signals The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. See Figure 3-1 for port location of these shared pins. The ADC10 on this MCU uses VDD and VSS as its supply and reference pins. This MCU does not have an external trigger source. 3.7.1 ADC10 Analog Power Pin (VDDA) The ADC10 analog portion uses VDDA as its power pin. In some packages, VDDA is connected internally to VDD. If externally available, connect the VDDA pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDA for good results. NOTE If externally available, route VDDA carefully for maximum noise immunity and place bypass capacitors as near as possible to the package. 3.7.2 ADC10 Analog Ground Pin (VSSA) The ADC10 analog portion uses VSSA as its ground pin. In some packages, VSSA is connected internally to VSS. If externally available, connect the VSSA pin to the same voltage potential as VSS. In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies should be at the VSSA pin. This should be the only ground connection between these supplies if possible. The VSSA pin makes a good single point ground location. 3.7.3 ADC10 Voltage Reference High Pin (VREFH) VREFH is the power supply for setting the high-reference voltage for the converter. In some packages, VREFH is connected internally to VDDA. If externally available, VREFH may be connected to the same potential as VDDA, or may be driven by an external source that is between the minimum VDDA spec and the VDDA potential (VREFH must never exceed VDDA). NOTE Route VREFH carefully for maximum noise immunity and place bypass capacitors as near as possible to the package. AC current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the VREFH and VREFL loop. The best external component to meet this current demand is a 0.1 μF capacitor with good high frequency characteristics. This capacitor is connected between VREFH and VREFL and must be placed as close as possible to the package pins. Resistance in the path is not recommended because the current will cause a voltage drop which could result in conversion errors. Inductance in this path must be minimum (parasitic only). 3.7.4 ADC10 Voltage Reference Low Pin (VREFL) VREFL is the power supply for setting the low-reference voltage for the converter. In some packages, VREFL is connected internally to VSSA. If externally available, connect the VREFL pin to the same voltage potential as VSSA. There will be a brief current associated with VREFL when the sampling capacitor is MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 45 Analog-to-Digital Converter (ADC10) Module charging. If externally available, connect the VREFL pin to the same potential as VSSA at the single point ground location. 3.7.5 ADC10 Channel Pins (ADn) The ADC10 has multiple input channels. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. 0.01 μF capacitors with good high-frequency characteristics are sufficient. These capacitors are not necessary in all cases, but when used they must be placed as close as possible to the package pins and be referenced to VSSA. 3.8 Registers These registers control and monitor operation of the ADC10: • ADC10 status and control register, ADSCR • ADC10 data registers, ADRH and ADRL • ADC10 clock register, ADCLK 3.8.1 ADC10 Status and Control Register This section describes the function of the ADC10 status and control register (ADSCR). Writing ADSCR aborts the current conversion and initiates a new conversion (if the ADCH[4:0] bits are equal to a value other than all 1s). Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 0 0 1 1 1 1 1 Figure 3-3. ADC10 Status and Control Register (ADSCR) COCO — Conversion Complete Bit COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever the status and control register is written or whenever the data register (low) is read. 1 = Conversion completed 0 = Conversion not completed AIEN — ADC10 Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of a conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. 1 = ADC10 interrupt enabled 0 = ADC10 interrupt disabled ADCO — ADC10 Continuous Conversion Bit When this bit is set, the ADC10 will begin to convert samples continuously (continuous conversion mode) and update the result registers at the end of each conversion, provided the ADCH[4:0] bits do not decode to all 1s. The ADC10 will continue to convert until the MCU enters reset, the MCU enters stop mode (if ACLKEN is clear), ADCLK is written, or until ADSCR is written again. If stop is entered (with ACLKEN low), continuous conversions will cease and can be restarted only with a write to ADSCR. Any write to ADSCR with ADCO set and the ADCH bits not all 1s will abort the current conversion and begin continuous conversions. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 46 Freescale Semiconductor Registers If the bus frequency is less than the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in short-sample mode (ADLSMP = 0). If the bus frequency is less than 1/11th of the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in long-sample mode (ADLSMP = 1). When clear, the ADC10 will perform a single conversion (single conversion mode) each time ADSCR is written (assuming the ADCH[4:0] bits do not decode all 1s). 1 = Continuous conversion following a write to ADSCR 0 = One conversion following a write to ADSCR ADCH[4:0] — Channel Select Bits The ADCH[4:0] bits form a 5-bit field that is used to select one of the input channels. The input channels are detailed in Table 3-2. The successive approximation converter subsystem is turned off when the channel select bits are all set to 1. This feature allows explicit disabling of the ADC10 and isolation of the input channel from the I/O pad. Terminating continuous conversion mode this way will prevent an additional, single conversion from being performed. It is not necessary to set the channel select bits to all 1s to place the ADC10 in a low-power state, however, because the module is automatically placed in a low-power state when a conversion completes. Table 3-2. Input Channel Select ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select(1) 0 0 0 0 0 AD0 0 0 0 0 1 AD1 0 0 0 1 0 AD2 0 0 0 1 1 AD3 0 0 1 0 0 AD4 0 0 1 0 1 AD5 0 0 1 1 0 Unused 1 1 0 0 1 Unused 1 1 0 1 0 BANDGAP REF(2) 1 1 0 1 1 Reserved 1 1 1 0 0 Reserved 1 1 1 0 1 VREFH 1 1 1 1 0 VREFL 1 1 1 1 1 Low-power state Continuing through Unused 1. If any unused or reserved channels are selected, the resulting conversion will be unknown. 2. Requires LVI to be powered (LVIPWRD =0, in CONFIG1) 3.8.2 ADC10 Result High Register (ADRH) This register holds the MSBs of the result and is updated each time a conversion completes. All other bits read as 0s. Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the result registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then the intermediate conversion result will be lost. In 8-bit mode, this register contains no interlocking with ADRL. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 47 Analog-to-Digital Converter (ADC10) Module Read: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 3-4. ADC10 Data Register High (ADRH), 8-Bit Mode Read: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 AD9 AD8 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 3-5. ADC10 Data Register High (ADRH), 10-Bit Mode 3.8.3 ADC10 Result Low Register (ADRL) This register holds the LSBs of the result. This register is updated each time a conversion completes. Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the result registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then the intermediate conversion result will be lost. In 8-bit mode, there is no interlocking with ADRH. Read: Bit 7 6 5 4 3 2 1 Bit 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 3-6. ADC10 Data Register Low (ADRL) 3.8.4 ADC10 Clock Register (ADCLK) This register selects the clock frequency for the ADC10 and the modes of operation. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ACLKEN 0 0 0 0 0 0 0 0 Figure 3-7. ADC10 Clock Register (ADCLK) ADLPC — ADC10 Low-Power Configuration Bit ADLPC controls the speed and power configuration of the successive approximation converter. This is used to optimize power consumption when higher sample rates are not required. 1 = Low-power configuration: The power is reduced at the expense of maximum clock speed. 0 = High-speed configuration MC68HC908QYA/QTA Family Data Sheet, Rev. 3 48 Freescale Semiconductor Registers ADIV[1:0] — ADC10 Clock Divider Bits ADIV1 and ADIV0 select the divide ratio used by the ADC10 to generate the internal clock ADCK. Table 3-3 shows the available clock configurations. Table 3-3. ADC10 Clock Divide Ratio ADIV1 ADIV0 Divide Ratio (ADIV) Clock Rate 0 0 1 Input clock ÷ 1 0 1 2 Input clock ÷ 2 1 0 4 Input clock ÷ 4 1 1 8 Input clock ÷ 8 ADICLK — Input Clock Select Bit If ACLKEN is clear, ADICLK selects either the bus clock or an alternate clock source as the input clock source to generate the internal clock ADCK. If the alternate clock source is less than the minimum clock speed, use the internally-generated bus clock as the clock source. As long as the internal clock ADCK, which is equal to the selected input clock divided by ADIV, is at a frequency (fADCK) between the minimum and maximum clock speeds (considering ALPC), correct operation can be guaranteed. 1 = The internal bus clock is selected as the input clock source 0 = The alternate clock source IS SELECTED MODE[1:0] — 10- or 8-Bit or Hardware Triggered Mode Selection These bits select 10- or 8-bit operation. The successive approximation converter generates a result that is rounded to 8- or 10-bit value based on the mode selection. This rounding process sets the transfer function to transition at the midpoint between the ideal code voltages, causing a quantization error of ± 1/2LSB. Reset returns 8-bit mode. 00 = 8-bit, right-justified, ADSCR software triggered mode enabled 01 = 10-bit, right-justified, ADSCR software triggered mode enabled 10 = Reserved 11 = 10-bit, right-justified, hardware triggered mode enabled ADLSMP — Long Sample Time Configuration This bit configures the sample time of the ADC10 to either 3.5 or 23.5 ADCK clock cycles. This adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall power consumption in continuous conversion mode if high conversion rates are not required. 1 = Long sample time (23.5 cycles) 0 = Short sample time (3.5 cycles) ACLKEN — Asynchronous Clock Source Enable This bit enables the asynchronous clock source as the input clock to generate the internal clock ADCK, and allows operation in stop mode. The asynchronous clock source will operate between 1 MHz and 2 MHz if ADLPC is clear, and between 0.5 MHz and 1 MHz if ADLPC is set. 1 = The asynchronous clock is selected as the input clock source (the clock generator is only enabled during the conversion) 0 = ADICLK specifies the input clock source and conversions will not continue in stop mode MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 49 Analog-to-Digital Converter (ADC10) Module MC68HC908QYA/QTA Family Data Sheet, Rev. 3 50 Freescale Semiconductor Chapter 4 Auto Wakeup Module (AWU) 4.1 Introduction This section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during stop mode to wake the part up without requiring an external signal. Figure 4-1 is a block diagram of the AWU. COPRS (FROM CONFIG1) VDD AUTOWUGEN OSCENINSTOP (FROM CONFIG2) BUSCLKX2 EN 32 kHz TO PTA READ, BIT 6 1 = DIV 29 SHORT 0 = DIV 214 D OVERFLOW M U X CLK E RST AWUL Q AWUIREQ R TO KBI INTERRUPT LOGIC (SEE Figure 9-2) INT RC OSC CLRLOGIC RESET CLEAR BUSCLKX2 CLK ACKK RST RESET RESET ISTOP AWUIE Figure 4-1. Auto Wakeup Interrupt Request Generation Logic 4.2 Features Features of the auto wakeup module include: • One internal interrupt with separate interrupt enable bit, sharing the same keyboard interrupt vector and keyboard interrupt mask bit • Exit from low-power stop mode without external signals • Selectable timeout periods • Dedicated low-power internal oscillator separate from the main system clock sources • Option to allow bus clock source to run the AWU if enabled in STOP MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 51 Auto Wakeup Module (AWU) 4.3 Functional Description The function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller unit (MCU) out of stop mode. The wakeup requests are treated as regular keyboard interrupt requests, with the difference that instead of a pin, the interrupt signal is generated by an internal logic. Entering stop mode will enable the auto wakeup generation logic. Writing the AWUIE bit in the keyboard interrupt enable register enables or disables the auto wakeup interrupt input (see Figure 4-1). A 1 applied to the AWUIREQ input with auto wakeup interrupt request enabled, latches an auto wakeup interrupt request. Auto wakeup latch, AWUL, can be read directly from the bit 6 position of port A data register (PTA). This is a read-only bit which is occupying an empty bit position on PTA. No PTA associated registers, such as PTA6 data direction or PTA6 pullup exist for this bit. There are two clock sources for the AWU. An internal RC oscillator (INTRCOSC, exclusive for the auto wakeup feature) drives the wakeup request generator provided the OSCENINSTOP bit in the CONFIG2 register Figure 4-1 is cleared. More accurate wakeup periods are possible using the BUSCLKX2 signal (from the oscillator module) which is selected by setting OSCENINSTOP. Once the overflow count is reached in the generator counter, a wakeup request, AWUIREQ, is latched and sent to the KBI logic. See Figure 4-1. Wakeup interrupt requests will only be serviced if the associated interrupt enable bit, AWUIE, in KBIER is set. The AWU shares the keyboard interrupt vector. The overflow count can be selected from two options defined by the COPRS bit in CONFIG1. This bit was “borrowed” from the computer operating properly (COP) using the fact that the COP feature is idle (no MCU clock available) in stop mode. COPRS = 1 selects the short wakeup period while COPRS = 0 selects the long wakeup period. The auto wakeup RC oscillator (INTRCOSC) is highly dependent on operating voltage and temperature. This feature is not recommended for use as a time-keeping function. The wakeup request is latched to allow the interrupt source identification. The latched value, AWUL, can be read directly from the bit 6 position of PTA data register. This is a read-only bit which is occupying an empty bit position on PTA. No PTA associated registers, such as PTA6 data, PTA6 direction, and PTA6 pullup exist for this bit. The latch can be cleared by writing to the ACKK bit in the KBSCR register. Reset also clears the latch. AWUIE bit in KBI interrupt enable register (see Figure 4-1) has no effect on AWUL reading. The AWU oscillator and counters are inactive in normal operating mode and become active only upon entering stop mode. 4.4 Interrupts The AWU can generate an interrupt request: AWU Latch (AWUL) — The AWUL bit is set when the AWU counter overflows. The auto wakeup interrupt mask bit, AWUIE, is used to enable or disable AWU interrupt requests. The AWU shares its interrupt with the KBI vector. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 52 Freescale Semiconductor Low-Power Modes 4.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 4.5.1 Wait Mode The AWU module is inactive in wait mode. 4.5.2 Stop Mode When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable register) it is activated automatically upon entering stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. The AWU counters start from 0 each time stop mode is entered. 4.6 Registers The AWU shares registers with the keyboard interrupt (KBI) module, the port A I/O module and configuration register 2. The following I/O registers control and monitor operation of the AWU: • Port A data register (PTA) • Keyboard interrupt status and control register (KBSCR) • Keyboard interrupt enable register (KBIER) • Configuration register 1 (CONFIG1) • Configuration register 2 (CONFIG2) 4.6.1 Port A I/O Register The port A data register (PTA) contains a data latch for the state of the AWU interrupt request, in addition to the data latches for port A. Read: Bit 7 6 0 AWUL 0 0 Write: Reset: 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 Bit 0 PTA1 PTA0 Unaffected by reset = Unimplemented Figure 4-2. Port A Data Register (PTA) AWUL — Auto Wakeup Latch This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup request signal is generated internally. There is no PTA6 port or any of the associated bits such as PTA6 data direction or pullup bits. 1 = Auto wakeup interrupt request is pending 0 = Auto wakeup interrupt request is not pending NOTE PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see 12.3.1 Port A Data Register. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 53 Auto Wakeup Module (AWU) 4.6.2 Keyboard Status and Control Register The keyboard status and control register (KBSCR): • Flags keyboard/auto wakeup interrupt requests • Acknowledges keyboard/auto wakeup interrupt requests • Masks keyboard/auto wakeup interrupt requests Read: Bit 7 6 5 4 3 0 0 0 0 KEYF Write: Reset: 2 0 ACKK 0 0 0 0 0 0 1 Bit 0 IMASKK MODEK 0 0 = Unimplemented Figure 4-3. Keyboard Status and Control Register (KBSCR) Bits 7–4 — Not used These read-only bits always read as 0s. KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears the KEYF bit. 1 = Keyboard/auto wakeup interrupt pending 0 = No keyboard/auto wakeup interrupt pending ACKK — Keyboard Acknowledge Bit Writing a 1 to this write-only bit clears the keyboard/auto wakeup interrupt request on port A and auto wakeup logic. ACKK always reads as 0. Reset clears ACKK. IMASKK— Keyboard Interrupt Mask Bit Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port A or auto wakeup. Reset clears the IMASKK bit. 1 = Keyboard/auto wakeup interrupt requests masked 0 = Keyboard/auto wakeup interrupt requests not masked NOTE MODEK is not used in conjuction with the auto wakeup feature. To see a description of this bit, see 9.8.1 Keyboard Status and Control Register (KBSCR). 4.6.3 Keyboard Interrupt Enable Register The keyboard interrupt enable register (KBIER) enables or disables the auto wakeup to operate as a keyboard/auto wakeup interrupt input. Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 = Unimplemented Figure 4-4. Keyboard Interrupt Enable Register (KBIER) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 54 Freescale Semiconductor Registers AWUIE — Auto Wakeup Interrupt Enable Bit This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears AWUIE. 1 = Auto wakeup enabled as interrupt input 0 = Auto wakeup not enabled as interrupt input NOTE KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see 9.8.2 Keyboard Interrupt Enable Register (KBIER). 4.6.4 Configuration Register 2 The configuration register 2 (CONFIG2), is used to allow the bus clock source to run in STOP. In this case, the clock, BUSCLKX2 will be used to drive the AWU request generator. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 IRQPUD IRQEN R R R R OSCENINSTOP RSTEN 0 0 0 0 0 0 0 0 Figure 4-5. Configuration Register 2 (CONFIG2) OSCENINSTOP — Oscillator Enable in Stop Mode Bit OSCENINSTOP, when set, will allow the bus clock source (BUSCLKX2) to generate clocks for the AWU in stop mode. See 11.8.1 Oscillator Status and Control Register for information on enabling the external clock sources. 1 = Oscillator enabled to operate during stop mode 0 = Oscillator disabled during stop mode NOTE IRQPUD, IRQEN, and RSTEN bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see Chapter 5 Configuration Register (CONFIG). 4.6.5 Configuration Register 1 The configuration register 1 (CONFIG1), is used to select the period for the AWU. The timeout will be based on the COPRS bit along with the clock source for the AWU. Read: Write: Reset: POR: Bit 7 6 5 4 3 2 1 Bit 0 COPRS LVISTOP LVIRSTD LVIPWRD LVITRIP SSREC STOP COPD 0 0 0 0 0 0 0 0 U 0 0 0 0 0 0 0 U = Unaffected Figure 4-6. Configuration Register 1 (CONFIG1) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 55 Auto Wakeup Module (AWU) COPRS (In Stop Mode) — Auto Wakeup Period Selection Bit, depends on OSCSTOPEN in CONFIG2 and bus clock source (BUSCLKX2). 1 = Auto wakeup short cycle = 512 × (INTRCOSC or BUSCLKX2) 0 = Auto wakeup long cycle = 16,384 × (INTRCOSC or BUSCLKX2) SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096 BUSCLKX4 cycle delay. 1 = Stop mode recovery after 32 BUSCLKX4 cycles 0 = Stop mode recovery after 4096 BUSCLKX4 cycles NOTE LVISTOP, LVIRST, LVIPWRD, LVITRIP, and COPD bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see Chapter 5 Configuration Register (CONFIG) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 56 Freescale Semiconductor Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers enable or disable the following options: • Stop mode recovery time (32 × BUSCLKX4 cycles or 4096 × BUSCLKX4 cycles) • STOP instruction • Computer operating properly module (COP) • COP reset period (COPRS): 8176 × BUSCLKX4 or 262,128 × BUSCLKX4 • Low-voltage inhibit (LVI) enable and trip voltage selection • Auto wakeup timeout period • Allow clock source to remain enabled in STOP • Enable IRQ pin • Disable IRQ pin pullup device • Enable RST pin 5.2 Functional Description The configuration registers are used in the initialization of various options. The configuration registers can be written once after each reset. Most of the configuration register bits are cleared during reset. Since the various options affect the operation of the microcontroller unit (MCU) it is recommended that this register be written immediately after reset. The configuration registers are located at $001E and $001F, and may be read at anytime. NOTE The CONFIG registers are one-time writable by the user after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 5-1 and Figure 5-2. Bit 7 6 5 4 3 2 1 Bit 0 IRQPUD IRQEN R R R R OSCENINSTOP RSTEN Reset: 0 0 0 0 0 0 0 U POR: 0 0 0 0 0 0 0 0 R = Reserved Read: Write: U = Unaffected Figure 5-1. Configuration Register 2 (CONFIG2) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 57 Configuration Register (CONFIG) IRQPUD — IRQ Pin Pullup Control Bit 1 = Internal pullup is disconnected 0 = Internal pullup is connected between IRQ pin and VDD IRQEN — IRQ Pin Function Selection Bit 1 = Interrupt request function active in pin 0 = Interrupt request function inactive in pin OSCENINSTOP— Oscillator Enable in Stop Mode Bit OSCENINSTOP, when set, will allow the clock source to continue to generate clocks in stop mode. This function can be used to keep the auto-wakeup running while the rest of the microcontroller stops. When clear, the clock source is disabled when the microcontroller enters stop mode. 1 = Oscillator enabled to operate during stop mode 0 = Oscillator disabled during stop mode RSTEN — RST Pin Function Selection 1 = Reset function active in pin 0 = Reset function inactive in pin NOTE The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected. Read: Write: Reset: POR: Bit 7 6 5 4 3 2 1 Bit 0 COPRS LVISTOP LVIRSTD LVIPWRD LVITRIP SSREC STOP COPD 0 0 0 0 U 0 0 0 0 0 0 0 0 0 0 0 U = Unaffected Figure 5-2. Configuration Register 1 (CONFIG1) COPRS (Out of Stop Mode) — COP Reset Period Selection Bit 1 = COP reset short cycle = 8176 × BUSCLKX4 0 = COP reset long cycle = 262,128 × BUSCLKX4 COPRS (In Stop Mode) — Auto Wakeup Period Selection Bit, depends on OSCSTOPEN in CONFIG2 and external clock source 1 = Auto wakeup short cycle = 512 × (INTRCOSC or BUSCLKX2) 0 = Auto wakeup long cycle = 16,384 × (INTRCOSC or BUSCLKX2) LVISTOP — LVI Enable in Stop Mode Bit When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP. 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. 1 = LVI module resets disabled 0 = LVI module resets enabled MC68HC908QYA/QTA Family Data Sheet, Rev. 3 58 Freescale Semiconductor Functional Description LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. 1 = LVI module power disabled 0 = LVI module power enabled LVITRIP — LVI Trip Point Selection Bit LVITRIP selects the voltage operating mode of the LVI module. The voltage mode selected for the LVI should match the operating VDD for the LVI’s voltage trip points for each of the modes. 1 = LVI operates for a 5-V protection 0 = LVI operates for a 3-V protection NOTE The LVITRIP bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected. SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096 BUSCLKX4 cycle delay. 1 = Stop mode recovery after 32 BUSCLKX4 cycles 0 = Stop mode recovery after 4096 BUSCLKX4 cycles NOTE Exiting stop mode by an LVI reset will result in the long stop recovery. When using the LVI during normal operation but disabling during stop mode, the LVI will have an enable time of tEN. The system stabilization time for power-on reset and long stop recovery (both 4096 BUSCLKX4 cycles) gives a delay longer than the LVI enable time for these startup scenarios. There is no period where the MCU is not protected from a low-power condition. However, when using the short stop recovery configuration option, the 32 BUSCLKX4 delay must be greater than the LVI’s turn on time to avoid a period in startup where the LVI is not protecting the MCU. STOP — STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 59 Configuration Register (CONFIG) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 60 Freescale Semiconductor Chapter 6 Computer Operating Properly (COP) 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the configuration 1 (CONFIG1) register. 6.2 Functional Description SIM MODULE STOP INSTRUCTION RESET STATUS REGISTER COP TIMEOUT CLEAR STAGES 5–12 CLEAR ALL STAGES INTERNAL RESET SOURCES(1) SIM RESET CIRCUIT 12-BIT SIM COUNTER BUSCLKX4 COPCTL WRITE COP CLOCK COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COPD (FROM CONFIG1) RESET CLEAR COP COUNTER COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) 1. See Chapter 13 System Integration Module (SIM) for more details. Figure 6-1. COP Block Diagram MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 61 Computer Operating Properly (COP) The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in configuration register 1. With a 262,128 BUSCLKX4 cycle overflow option, the internal 12.8-MHz oscillator gives a COP timeout period of 20.48 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12–5 of the SIM counter. NOTE Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low (if the RSTEN bit is set in the CONFIG1 register) for 32 × BUSCLKX4 cycles and sets the COP bit in the reset status register (RSR). See 13.8.1 SIM Reset Status Register. NOTE Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly. 6.3 I/O Signals The following paragraphs describe the signals shown in Figure 6-1. 6.3.1 BUSCLKX4 BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is equal to the crystal frequency or the RC-oscillator frequency. 6.3.2 STOP Instruction The STOP instruction clears the SIM counter. 6.3.3 COPCTL Write Writing any value to the COP control register (COPCTL) (see Figure 6-2) clears the COP counter and clears stages 12–5 of the SIM counter. Reading the COP control register returns the low byte of the reset vector. 6.3.4 Power-On Reset The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 × BUSCLKX4 cycles after power up. 6.3.5 Internal Reset An internal reset clears the SIM counter and the COP counter. 6.3.6 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). See Chapter 5 Configuration Register (CONFIG). MC68HC908QYA/QTA Family Data Sheet, Rev. 3 62 Freescale Semiconductor Interrupts 6.3.7 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1 (CONFIG1). See Chapter 5 Configuration Register (CONFIG). 6.4 Interrupts The COP does not generate CPU interrupt requests. 6.5 Monitor Mode The COP is disabled in monitor mode when VTST is present on the IRQ pin. 6.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 6.6.1 Wait Mode The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter. 6.6.2 Stop Mode Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. 6.7 COP Module During Break Mode The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). 6.8 Register The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Bit 7 6 5 4 3 Read: LOW BYTE OF RESET VECTOR Write: CLEAR COP COUNTER Reset: Unaffected by reset 2 1 Bit 0 Figure 6-2. COP Control Register (COPCTL) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 63 Computer Operating Properly (COP) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 64 Freescale Semiconductor Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 7.2 Features Features of the CPU include: • Object code fully upward-compatible with M68HC05 Family • 16-bit stack pointer with stack manipulation instructions • 16-bit index register with x-register manipulation instructions • 8-MHz CPU internal bus frequency • 64-Kbyte program/data memory space • 16 addressing modes • Memory-to-memory data moves without using accumulator • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • Enhanced binary-coded decimal (BCD) data handling • Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 65 Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Unaffected by reset Figure 7-2. Accumulator (A) 7.3.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 X X X X X X X X Read: Write: Reset: X = Indeterminate Figure 7-3. Index Register (H:X) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 66 Freescale Semiconductor CPU Registers 7.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Read: Write: Reset: Figure 7-4. Stack Pointer (SP) NOTE The location of the stack is arbitrary and may be relocated anywhere in random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations. 7.3.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Loaded with vector from $FFFE and $FFFF Figure 7-5. Program Counter (PC) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 67 Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 7-6. Condition Code Register (CCR) V — Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H — Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result MC68HC908QYA/QTA Family Data Sheet, Rev. 3 68 Freescale Semiconductor Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 7.4 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU. 7.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 7.5.1 Wait Mode The WAIT instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock 7.5.2 Stop Mode The STOP instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. 7.6 CPU During Break Interrupts If a break module is present on the MCU, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 69 Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set. ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP V H I N Z C A ← (A) + (M) + (C) Add with Carry A ← (A) + (M) Add without Carry IMM DIR EXT IX2 – IX1 IX SP1 SP2 A9 B9 C9 D9 E9 F9 9EE9 9ED9 ii dd hh ll ee ff ff IMM DIR EXT – IX2 IX1 IX SP1 SP2 AB BB CB DB EB FB 9EEB 9EDB ii dd hh ll ee ff ff ff ee ff Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1. Instruction Set Summary (Sheet 1 of 6) 2 3 4 4 3 2 4 5 ff ee ff 2 3 4 4 3 2 4 5 AIS #opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) – – – – – – IMM A7 ii 2 AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) – – – – – – IMM AF ii 2 A ← (A) & (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 A4 B4 C4 D4 E4 F4 9EE4 9ED4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 0 DIR INH INH – – IX1 IX SP1 38 dd 48 58 68 ff 78 9E68 ff 4 1 1 4 3 5 C DIR INH – – INH IX1 IX SP1 37 dd 47 57 67 ff 77 9E67 ff 4 1 1 4 3 5 AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP Logical AND Arithmetic Shift Left (Same as LSL) C b7 ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP Arithmetic Shift Right BCC rel Branch if Carry Bit Clear b0 b7 BCLR n, opr Clear Bit n in M b0 PC ← (PC) + 2 + rel ? (C) = 0 Mn ← 0 ff ee ff – – – – – – REL 24 rr 3 DIR (b0) DIR (b1) DIR (b2) – – – – – – DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3 BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 – – – – – – REL 27 rr 3 BGE opr Branch if Greater Than or Equal To (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 – – – – – – REL 90 rr 3 BGT opr Branch if Greater Than (Signed Operands) PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 – – – – – – REL 92 rr 3 BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 – – – – – – REL 28 rr BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 – – – – – – REL 29 rr BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 – – – – – – REL 22 rr 3 3 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 70 Freescale Semiconductor Instruction Set Summary V H I N Z C BHS rel Branch if Higher or Same (Same as BCC) BIH rel BIL rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 (A) & (M) BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1. Instruction Set Summary (Sheet 2 of 6) 24 rr 3 – – – – – – REL 2F rr 3 – – – – – – REL 2E rr 3 IMM DIR EXT 0 – – – IX2 IX1 IX SP1 SP2 A5 B5 C5 D5 E5 F5 9EE5 9ED5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 rr 3 PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 – – – – – – REL 93 BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3 BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 – – – – – – REL 23 rr 3 BLT opr Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) =1 – – – – – – REL 91 rr 3 BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 – – – – – – REL 2C rr 3 BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 – – – – – – REL 2B rr 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 – – – – – – REL 2D rr 3 3 BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 – – – – – – REL 26 rr BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 – – – – – – REL 2A rr 3 BRA rel Branch Always PC ← (PC) + 2 + rel – – – – – – REL 20 rr 3 DIR (b0) DIR (b1) DIR (b2) DIR (b3) – – – – – DIR (b4) DIR (b5) DIR (b6) DIR (b7) 01 03 05 07 09 0B 0D 0F dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 BRCLR n,opr,rel Branch if Bit n in M Clear BRN rel PC ← (PC) + 2 Branch Never BRSET n,opr,rel Branch if Bit n in M Set BSET n,opr Set Bit n in M BSR rel Branch to Subroutine PC ← (PC) + 3 + rel ? (Mn) = 0 CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel – – – – – – REL 21 rr 3 PC ← (PC) + 3 + rel ? (Mn) = 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) – – – – – DIR (b4) DIR (b5) DIR (b6) DIR (b7) 00 02 04 06 08 0A 0C 0E dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 Mn ← 1 DIR (b0) DIR (b1) DIR (b2) – – – – – – DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) + rel – – – – – – REL AD rr 4 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (X) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 2 + rel ? (A) – (M) = $00 PC ← (PC) + 4 + rel ? (A) – (M) = $00 DIR IMM – – – – – – IMM IX1+ IX+ SP1 31 41 51 61 71 9E61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 CLC Clear Carry Bit C←0 – – – – – 0 INH 98 1 CLI Clear Interrupt Mask I←0 – – 0 – – – INH 9A 2 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 71 Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Clear Compare A with M Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A Decrement DIV Divide INC opr INCA INCX INC opr,X INC ,X INC opr,SP Exclusive OR M with A Increment DIR INH INH 0 – – 0 1 – INH IX1 IX SP1 3F dd 4F 5F 8C 6F ff 7F 9E6F ff (A) – (M) IMM DIR EXT IX2 – – IX1 IX SP1 SP2 A1 B1 C1 D1 E1 F1 9EE1 9ED1 DIR INH INH 0 – – 1 IX1 IX SP1 33 dd 43 53 63 ff 73 9E63 ff M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) (H:X) – (M:M + 1) (X) – (M) (A)10 DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP M ← $00 A ← $00 X ← $00 H ← $00 M ← $00 M ← $00 M ← $00 ff ee ff 2 3 4 4 3 2 4 5 4 1 1 4 3 5 ii ii+1 dd 3 4 IMM DIR EXT IX2 – – IX1 IX SP1 SP2 A3 B3 C3 D3 E3 F3 9EE3 9ED3 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 U – – INH 72 A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1 PC ← (PC) + 3 + rel ? (result) ≠ 0 DIR PC ← (PC) + 2 + rel ? (result) ≠ 0 INH PC ← (PC) + 2 + rel ? (result) ≠ 0 – – – – – – INH PC ← (PC) + 3 + rel ? (result) ≠ 0 IX1 PC ← (PC) + 2 + rel ? (result) ≠ 0 IX PC ← (PC) + 4 + rel ? (result) ≠ 0 SP1 3B 4B 5B 6B 7B 9E6B ff ee ff 2 dd rr rr rr ff rr rr ff rr M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 M ← (M) – 1 DIR INH INH – – – IX1 IX SP1 A ← (H:A)/(X) H ← Remainder – – – – INH 52 A ← (A ⊕ M) IMM DIR EXT 0 – – – IX2 IX1 IX SP1 SP2 A8 B8 C8 D8 E8 F8 9EE8 9ED8 DIR INH – – – INH IX1 IX SP1 3C dd 4C 5C 6C ff 7C 9E6C ff M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 M ← (M) + 1 3 1 1 1 3 2 4 65 75 – – IMM DIR ii dd hh ll ee ff ff Cycles V H I N Z C COM opr COMA COMX COM opr,X COM ,X COM opr,SP EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1. Instruction Set Summary (Sheet 3 of 6) 3A dd 4A 5A 6A ff 7A 9E6A ff 5 3 3 5 4 6 4 1 1 4 3 5 7 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 4 1 1 4 3 5 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 72 Freescale Semiconductor Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine LDHX #opr LDHX opr Load H:X from M 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT – – – – – – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A ← (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 H:X ← (M:M + 1) MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr Move MUL Unsigned multiply C b7 b7 0 DIR INH INH – – IX1 IX SP1 38 dd 48 58 68 ff 78 9E68 ff 4 1 1 4 3 5 C DIR INH – – 0 INH IX1 IX SP1 34 dd 44 54 64 ff 74 9E64 ff 4 1 1 4 3 5 b0 H:X ← (H:X) + 1 (IX+D, DIX+) DD DIX+ 0 – – – IMD IX+D X:A ← (X) × (A) – 0 – – – 0 INH M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M) DIR INH INH – – IX1 IX SP1 (M)Destination ← (M)Source Negate (Two’s Complement) 45 55 AE BE CE DE EE FE 9EEE 9EDE b0 0 IMM DIR IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 X ← (M) Logical Shift Left (Same as ASL) Logical Shift Right 0 – – – 4E 5E 6E 7E dd dd dd ii dd dd 42 No Operation None – – – – – – INH 9D NSA Nibble Swap A A ← (A[3:0]:A[7:4]) – – – – – – INH 62 A ← (A) | (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 AA BA CA DA EA FA 9EEA 9EDA Inclusive OR A and M ff ee ff 5 4 4 4 5 30 dd 40 50 60 ff 70 9E60 ff NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP Cycles dd hh ll ee ff ff Load X from M LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP BC CC DC EC FC Jump Load A from M LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP PC ← Jump Address DIR EXT – – – – – – IX2 IX1 IX Effect on CCR Description V H I N Z C LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP Operand JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Operation Address Mode Source Form Opcode Table 7-1. Instruction Set Summary (Sheet 4 of 6) 4 1 1 4 3 5 1 3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 PSHA Push A onto Stack Push (A); SP ← (SP) – 1 – – – – – – INH 87 2 PSHH Push H onto Stack Push (H); SP ← (SP) – 1 – – – – – – INH 8B 2 PSHX Push X onto Stack Push (X); SP ← (SP) – 1 – – – – – – INH 89 2 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 73 Central Processor Unit (CPU) V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1. Instruction Set Summary (Sheet 5 of 6) PULA Pull A from Stack SP ← (SP + 1); Pull (A) – – – – – – INH 86 2 PULH Pull H from Stack SP ← (SP + 1); Pull (H) – – – – – – INH 8A 2 PULX Pull X from Stack SP ← (SP + 1); Pull (X) – – – – – – INH C DIR INH INH – – IX1 IX SP1 39 dd 49 59 69 ff 79 9E69 ff 4 1 1 4 3 5 DIR INH – – INH IX1 IX SP1 36 dd 46 56 66 ff 76 9E66 ff 4 1 1 4 3 5 ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP Rotate Left through Carry b7 b0 88 2 ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP Rotate Right through Carry RSP Reset Stack Pointer SP ← $FF – – – – – – INH 9C 1 RTI Return from Interrupt SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) INH 80 7 RTS Return from Subroutine SP ← SP + 1; Pull (PCH) SP ← SP + 1; Pull (PCL) – – – – – – INH 81 4 A ← (A) – (M) – (C) IMM DIR EXT – – IX2 IX1 IX SP1 SP2 A2 B2 C2 D2 E2 F2 9EE2 9ED2 SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP C b7 Subtract with Carry b0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 SEC Set Carry Bit C←1 – – – – – 1 INH 99 1 SEI Set Interrupt Mask I←1 – – 1 – – – INH 9B 2 M ← (A) DIR EXT IX2 0 – – – IX1 IX SP1 SP2 B7 C7 D7 E7 F7 9EE7 9ED7 (M:M + 1) ← (H:X) 0 – – – DIR 35 I ← 0; Stop Processing – – 0 – – – INH 8E M ← (X) DIR EXT IX2 0 – – – IX1 IX SP1 SP2 BF CF DF EF FF 9EEF 9EDF dd hh ll ee ff ff IMM DIR EXT – – IX2 IX1 IX SP1 SP2 A0 B0 C0 D0 E0 F0 9EE0 9ED0 ii dd hh ll ee ff ff STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP Store A in M STHX opr Store H:X in M STOP Enable Interrupts, Stop Processing, Refer to MCU Documentation STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP Store X in M Subtract A ← (A) – (M) dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 dd 4 1 ff ee ff ff ee ff 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 74 Freescale Semiconductor Opcode Map SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte – – 1 – – – INH 83 9 CCR ← (A) INH 84 2 X ← (A) – – – – – – INH 97 1 A ← (CCR) – – – – – – INH 85 (A) – $00 or (X) – $00 or (M) – $00 DIR INH INH 0 – – – IX1 IX SP1 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH 9F 1 (SP) ← (H:X) – 1 – – – – – – INH 94 2 I bit ← 0; Inhibit CPU clocking until interrupted – – 0 – – – INH 8F 1 TAP Transfer A to CCR Transfer A to X TPA Transfer CCR to A Test for Negative or Zero TSX Transfer SP to H:X TXA Transfer X to A TXS Transfer H:X to SP WAIT A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N Cycles V H I N Z C TAX TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1. Instruction Set Summary (Sheet 6 of 6) Enable Interrupts; Wait for Interrupt Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & | ⊕ () –( ) # « ← ? : — 3D dd 4D 5D 6D ff 7D 9E6D ff 1 3 1 1 3 2 4 Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two’s complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected 7.8 Opcode Map See Table 7-2. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 75 MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL Read-Modify-Write INH IX1 5 6 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1 SP1 IX 9E6 7 Control INH INH 8 9 Register/Memory IX2 SP2 IMM DIR EXT A B C D 9ED 4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT 4 SUB 3 IX2 4 CMP 3 IX2 4 SBC 3 IX2 4 CPX 3 IX2 4 AND 3 IX2 4 BIT 3 IX2 4 LDA 3 IX2 4 STA 3 IX2 4 EOR 3 IX2 4 ADC 3 IX2 4 ORA 3 IX2 4 ADD 3 IX2 4 JMP 3 IX2 6 JSR 3 IX2 4 LDX 3 IX2 4 STX 3 IX2 5 SUB 4 SP2 5 CMP 4 SP2 5 SBC 4 SP2 5 CPX 4 SP2 5 AND 4 SP2 5 BIT 4 SP2 5 LDA 4 SP2 5 STA 4 SP2 5 EOR 4 SP2 5 ADC 4 SP2 5 ORA 4 SP2 5 ADD 4 SP2 IX1 SP1 IX E 9EE F LSB 0 1 2 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 4 5 6 7 8 9 A B C D E Freescale Semiconductor F 4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH INH Inherent REL Relative IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD Direct-Direct IMD Immediate-Direct IX+D Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions 5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment 7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH 2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM 3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR MSB 0 3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX 4 SP2 2 IX1 5 3 STX STX 4 SP2 2 IX1 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1 2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX High Byte of Opcode in Hexadecimal LSB Low Byte of Opcode in Hexadecimal 0 5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode Central Processor Unit (CPU) 76 Table 7-2. Opcode Map Bit Manipulation DIR DIR Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. IRQ functionality is enabled by setting configuration register 2 (CONFIG2) IRQEN bit accordingly. A zero disables the IRQ function and IRQ will assume the other shared functionalities. A one enables the IRQ function. See Chapter 5 Configuration Register (CONFIG) for more information on enabling the IRQ pin. The IRQ pin shares its pin with general-purpose input/output (I/O) port pins. See Figure 8-1 for port location of this shared pin. 8.2 Features Features of the IRQ module include: • A dedicated external interrupt pin IRQ • IRQ interrupt control bits • Programmable edge-only or edge and level interrupt sensitivity • Automatic interrupt acknowledge • Internal pullup device 8.3 Functional Description A low level applied to the external interrupt request (IRQ) pin can latch a CPU interrupt request. Figure 8-2 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. The IRQ latch remains set until one of the following actions occurs: • IRQ vector fetch. An IRQ vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch. • Software clear. Software can clear the IRQ latch by writing a 1 to the ACK bit in the interrupt status and control register (INTSCR). • Reset. A reset automatically clears the IRQ latch. The external IRQ pin is falling edge sensitive out of reset and is software-configurable to be either falling edge or falling edge and low level sensitive. The MODE bit in INTSCR controls the triggering sensitivity of the IRQ pin. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 77 External Interrupt (IRQ) PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE VDD POWER SUPPLY VSS RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device PTA[0:5]: Higher current sink and source capability PTB[0:7]: Not available on 8-pin devices Figure 8-1. Block Diagram Highlighting IRQ Block and Pin When set, the IMASK bit in INTSCR masks the IRQ interrupt request. A latched interrupt request is not presented to the interrupt priority logic unless IMASK is clear. NOTE The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including the IRQ interrupt request. A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. An IRQ vector fetch, software clear, or reset clears the IRQ latch. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 78 Freescale Semiconductor Functional Description RESET ACK TO CPU FOR BIL/BIH INSTRUCTIONS INTERNAL ADDRESS BUS IRQ VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE VDD IRQF D CLR Q CK IRQ IRQ LATCH SYNCHRONIZER IRQ INTERRUPT REQUEST IMASK MODE HIGH VOLTAGE DETECT TO MODE SELECT LOGIC Figure 8-2. IRQ Module Block Diagram 8.3.1 MODE = 1 If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive. With MODE set, both of the following actions must occur to clear the IRQ interrupt request: • Return of the IRQ pin to a high level. As long as the IRQ pin is low, the IRQ request remains active. • IRQ vector fetch or software clear. An IRQ vector fetch generates an interrupt acknowledge signal to clear the IRQ latch. Software generates the interrupt acknowledge signal by writing a 1 to ACK in INTSCR. The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to ACK prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to ACK latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the IRQ vector address. The IRQ vector fetch or software clear and the return of the IRQ pin to a high level may occur in any order. The interrupt request remains pending as long as the IRQ pin is low. A reset will clear the IRQ latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. Use the BIH or BIL instruction to read the logic level on the IRQ pin. 8.3.2 MODE = 0 If the MODE bit is clear, the IRQ pin is falling edge sensitive only. With MODE clear, an IRQ vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in INTSCR can be read to check for pending interrupts. The IRQF bit is not affected by IMASK, which makes it useful in applications where polling is preferred. NOTE When using the level-sensitive interrupt trigger, avoid false IRQ interrupts by masking interrupt requests in the interrupt routine. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 79 External Interrupt (IRQ) 8.4 Interrupts The following IRQ source can generate interrupt requests: • Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode. The IRQ interrupt mask bit, IMASK, is used to enable or disable IRQ interrupt requests. 8.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 8.5.1 Wait Mode The IRQ module remains active in wait mode. Clearing IMASK in INTSCR enables IRQ interrupt requests to bring the MCU out of wait mode. 8.5.2 Stop Mode The IRQ module remains active in stop mode. Clearing IMASK in INTSCR enables IRQ interrupt requests to bring the MCU out of stop mode. 8.6 IRQ Module During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See BFCR in the SIM section of this data sheet. To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. 8.7 I/O Signals The IRQ module does not share its pin with any module on this MCU. 8.7.1 IRQ Input Pins (IRQ) The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup device. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 80 Freescale Semiconductor Registers 8.8 Registers The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • Masks the IRQ interrupt request • Controls triggering sensitivity of the IRQ interrupt pin Read: Bit 7 6 5 4 3 2 0 0 0 0 IRQF 0 Write: Reset: ACK 0 0 0 0 0 1 Bit 0 IMASK MODE 0 0 0 = Unimplemented Figure 8-3. IRQ Status and Control Register (INTSCR) IRQF — IRQ Flag Bit This read-only status bit is set when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK — IRQ Interrupt Request Acknowledge Bit Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads 0. IMASK — IRQ Interrupt Mask Bit Writing a 1 to this read/write bit disables the IRQ interrupt request. 1 = IRQ interrupt request disabled 0 = IRQ interrupt request enabled MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. 1 = IRQ interrupt request on falling edges and low levels 0 = IRQ interrupt request on falling edges only MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 81 External Interrupt (IRQ) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 82 Freescale Semiconductor Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides independently maskable external interrupts. The KBI shares its pins with general-purpose input/output (I/O) port pins. See Figure 9-1 for port location of these shared pins. 9.2 Features Features of the keyboard interrupt module include: • Keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask • Programmable edge-only or edge and level interrupt sensitivity • Edge sensitivity programmable for rising or falling edge • Level sensitivity programmable for high or low level • Pullup or pulldown device automatically enabled based on the polarity of edge or level detect • Exit from low-power modes 9.3 Functional Description The keyboard interrupt module controls the enabling/disabling of interrupt functions on the KBI pins. These pins can be enabled/disabled independently of each other. See Figure 9-2. 9.3.1 Keyboard Operation Writing to the KBIEx bits in the keyboard interrupt enable register (KBIER) independently enables or disables each KBI pin. The polarity of the keyboard interrupt is controlled using the KBIPx bits in the keyboard interrupt polarity register (KBIPR). Edge-only or edge and level sensitivity is controlled using the MODEK bit in the keyboard status and control register (KBISCR). Enabling a keyboard interrupt pin also enables its internal pullup or pulldown device based on the polarity enabled. On falling edge or low level detection, a pullup device is configured. On rising edge or high level detection, a pulldown device is configured. The keyboard interrupt latch is set when one or more enabled keyboard interrupt inputs are asserted. • If the keyboard interrupt sensitivity is edge-only, for KBIPx = 0, a falling (for KBIPx = 1, a rising) edge on a keyboard interrupt input does not latch an interrupt request if another enabled keyboard pin is already asserted. To prevent losing an interrupt request on one input because another input remains asserted, software can disable the latter input while it is asserted. • If the keyboard interrupt is edge and level sensitive, an interrupt request is present as long as any enabled keyboard interrupt input is asserted. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 83 Keyboard Interrupt Module (KBI) PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH POWER SUPPLY COP MODULE 6-CHANNEL 10-BIT ADC VDD DEVELOPMENT SUPPORT VSS MONITOR ROM BREAK MODULE RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device PTA[0:5]: Higher current sink and source capability PTB[0:7]: Not available on 8-pin devices Figure 9-1. Block Diagram Highlighting KBI Block and Pins 9.3.1.1 MODEK = 1 If the MODEK bit is set, the keyboard interrupt inputs are both edge and level sensitive. The KBIPx bit will determine whether a edge sensitive pin detects rising or falling edges and on level sensitive pins whether the pin detects low or high levels. With MODEK set, both of the following actions must occur to clear a keyboard interrupt request: • Return of all enabled keyboard interrupt inputs to a deasserted level. As long as any enabled keyboard interrupt pin is asserted, the keyboard interrupt remains active. • Vector fetch or software clear. A KBI vector fetch generates an interrupt acknowledge signal to clear the KBI latch. Software generates the interrupt acknowledge signal by writing a 1 to ACKK in KBSCR. The ACKK bit is useful in applications that poll the keyboard interrupt inputs and require software to clear the KBI latch. Writing to ACKK prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt inputs. An edge detect that occurs after writing to ACKK latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the KBI vector address. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 84 Freescale Semiconductor Functional Description INTERNAL BUS VECTOR FETCH DECODER ACKK RESET 1 KBI0 0 S VDD KBIE0 TO PULLUP/ PULLDOWN ENABLE KBIP0 KEYF D CLR Q CK 1 KBIx 0 KBI LATCH S IMASKK KBIEx TO PULLUP/ PULLDOWN ENABLE KBIPx SYNCHRONIZER MODEK KEYBOARD INTERRUPT REQUEST AWUIREQ (SEE Figure 4-1) Figure 9-2. Keyboard Interrupt Block Diagram The KBI vector fetch or software clear and the return of all enabled keyboard interrupt pins to a deasserted level may occur in any order. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt input stays asserted. 9.3.1.2 MODEK = 0 If the MODEK bit is clear, the keyboard interrupt inputs are edge sensitive. The KBIPx bit will determine whether an edge sensitive pin detects rising or falling edges. A KBI vector fetch or software clear immediately clears the KBI latch. The keyboard flag bit (KEYF) in KBSCR can be read to check for pending interrupts. The KEYF bit is not affected by IMASKK, which makes it useful in applications where polling is preferred. NOTE Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a 0 for software to read the pin. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 85 Keyboard Interrupt Module (KBI) 9.3.2 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup or pulldown device to pull the pin to its deasserted level. Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting IMASKK in KBSCR. 2. Enable the KBI polarity by setting the appropriate KBIPx bits in KBIPR. 3. Enable the KBI pins by setting the appropriate KBIEx bits in KBIER. 4. Write to ACKK in KBSCR to clear any false interrupts. 5. Clear IMASKK. An interrupt signal on an edge sensitive pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge and level sensitive pin must be acknowledged after a delay that depends on the external load. 9.4 Interrupts The following KBI source can generate interrupt requests: • Keyboard flag (KEYF) — The KEYF bit is set when any enabled KBI pin is asserted based on the KBI mode and pin polarity. The keyboard interrupt mask bit, IMASKK, is used to enable or disable KBI interrupt requests. 9.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 9.5.1 Wait Mode The KBI module remains active in wait mode. Clearing IMASKK in KBSCR enables keyboard interrupt requests to bring the MCU out of wait mode. 9.5.2 Stop Mode The KBI module remains active in stop mode. Clearing IMASKK in KBSCR enables keyboard interrupt requests to bring the MCU out of stop mode. 9.6 KBI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See BFCR in the SIM section of this data sheet. To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 86 Freescale Semiconductor I/O Signals 9.7 I/O Signals The KBI module can share its pins with the general-purpose I/O pins. See Figure 9-1 for the port pins that are shared. 9.7.1 KBI Input Pins (KBIx:KBI0) Each KBI pin is independently programmable as an external interrupt source. KBI pin polarity can be controlled independently. Each KBI pin when enabled will automatically configure the appropriate pullup/pulldown device based on polarity. 9.8 Registers The following registers control and monitor operation of the KBI module: • KBSCR (keyboard interrupt status and control register) • KBIER (keyboard interrupt enable register) • KBIPR (keyboard interrupt polarity register) 9.8.1 Keyboard Status and Control Register (KBSCR) Features of the KBSCR: • Flags keyboard interrupt requests • Acknowledges keyboard interrupt requests • Masks keyboard interrupt requests • Controls keyboard interrupt triggering sensitivity Read: Bit 7 6 5 4 3 2 0 0 0 0 KEYF 0 Write: ACKK Reset: 0 0 0 0 0 0 1 Bit 0 IMASKK MODEK 0 0 = Unimplemented Figure 9-3. Keyboard Status and Control Register (KBSCR) Bits 7–4 — Not used KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK — Keyboard Acknowledge Bit Writing a 1 to this write-only bit clears the KBI request. ACKK always reads 0. IMASKK— Keyboard Interrupt Mask Bit Writing a 1 to this read/write bit prevents the output of the KBI latch from generating interrupt requests. 1 = Keyboard interrupt requests disabled 0 = Keyboard interrupt requests enabled MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. 1 = Keyboard interrupt requests on edge and level 0 = Keyboard interrupt requests on edge only MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 87 Keyboard Interrupt Module (KBI) 9.8.2 Keyboard Interrupt Enable Register (KBIER) KBIER enables or disables each keyboard interrupt pin. Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 = Unimplemented Figure 9-4. Keyboard Interrupt Enable Register (KBIER) KBIE5–KBIE0 — Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch KBI interrupt requests. 1 = KBIx pin enabled as keyboard interrupt pin 0 = KBIx pin not enabled as keyboard interrupt pin NOTE AWUIE bit is not used in conjunction with the keyboard interrupt feature. To see a description of this bit, see Chapter 4 Auto Wakeup Module (AWU). 9.8.3 Keyboard Interrupt Polarity Register (KBIPR) KBIPR determines the polarity of the enabled keyboard interrupt pin and enables the appropriate pullup or pulldown device. Read: Bit 7 6 0 0 0 0 Write: Reset: 5 4 3 2 1 Bit 0 KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0 0 0 0 0 0 0 = Unimplemented Figure 9-5. Keyboard Interrupt Polarity Register (KBIPR) KBIP5–KBIP0 — Keyboard Interrupt Polarity Bits Each of these read/write bits enables the polarity of the keyboard interrupt detection. 1 = Keyboard polarity is high level and/or rising edge 0 = Keyboard polarity is low level and/or falling edge MC68HC908QYA/QTA Family Data Sheet, Rev. 3 88 Freescale Semiconductor Chapter 10 Low-Voltage Inhibit (LVI) 10.1 Introduction The low-voltage inhibit (LVI) module is provided as a system protection mechanism to prevent the MCU from operating below a certain operating supply voltage level. The module has several configuration options to allow functionality to be tailored to different system level demands. The configuration registers (see Chapter 5 Configuration Register (CONFIG)) contain control bits for this module. 10.2 Features Features of the LVI module include: • Programmable LVI reset • Selectable LVI trip voltage • Programmable stop mode operation 10.3 Functional Description Figure 10-1 shows the structure of the LVI module. LVISTOP, LVIPWRD, LVITRIP, and LVIRSTD are user selectable options found in the configuration register. VDD STOP INSTRUCTION LVISTOP FROM CONFIGURATION REGISTER FROM CONFIGURATION REGISTER LVIRSTD LVIPWRD FROM CONFIGURATION REGISTER LOW VDD DETECTOR 0 IF VDD > VTRIPR LVI RESET 1 IF VDD ≤ VTRIPF LVIOUT LVITRIP FROM CONFIGURATION REGISTER Figure 10-1. LVI Module Block Diagram MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 89 Low-Voltage Inhibit (LVI) The LVI module contains a bandgap reference circuit and comparator. When the LVITRIP bit is cleared, the default state at power-on reset, VTRIPF is configured for the lower VDD operating range. The actual trip points are specified in 16.5 5-V DC Electrical Characteristics and 16.8 3-V DC Electrical Characteristics. Because the default LVI trip point after power-on reset is configured for low voltage operation, a system requiring high voltage LVI operation must set the LVITRIP bit during system initialization. VDD must be above the LVI trip rising voltage, VTRIPR, for the high voltage operating range or the MCU will immediately go into LVI reset. After an LVI reset occurs, the MCU remains in reset until VDD rises above VTRIPR. See Chapter 13 System Integration Module (SIM) for the reset recovery sequence. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and can be used for polling LVI operation when the LVI reset is disabled. The LVI is enabled out of reset. The following bits located in the configuration register can alter the default conditions. • Setting the LVI power disable bit, LVIPWRD, disables the LVI. • Setting the LVI reset disable bit, LVIRSTD, prevents the LVI module from generating a reset. • Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode. • Setting the LVI trip point bit, LVITRIP, configures the trip point voltage (VTRIPF) for the higher VDD operating range. 10.3.1 Polled LVI Operation In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling the LVIOUT bit. In the configuration register, LVIPWRD must be cleared to enable the LVI module, and LVIRSTD must be set to disable LVI resets. 10.3.2 Forced Reset Operation In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, LVIPWRD and LVIRSTD must be cleared to enable the LVI module and to enable LVI resets. 10.3.3 LVI Hysteresis The LVI has hysteresis to maintain a stable operating condition. After the LVI has triggered (by having VDD fall below VTRIPF), the MCU will remain in reset until VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the typical hysteresis voltage, VHYS. 10.3.4 LVI Trip Selection LVITRIP in the configuration register selects the LVI protection range. The default setting out of reset is for the low voltage range. Because LVITRIP is in a write-once configuration register, the protection range cannot be changed after initialization. NOTE The MCU is guaranteed to operate at a minimum supply voltage. The trip point (VTRIPF) may be lower than this. See the Electrical Characteristics section for the actual trip point voltages. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 90 Freescale Semiconductor LVI Interrupts 10.4 LVI Interrupts The LVI module does not generate interrupt requests. 10.5 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 10.5.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 10.5.2 Stop Mode If the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration register is set, the LVI module remains active. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. 10.6 Registers The LVI status register (LVISR) contains a status bit that is useful when the LVI is enabled and LVI reset is disabled. Read: Bit 7 6 5 4 3 2 1 Bit 0 LVIOUT 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 R = Reserved Write: Reset: = Unimplemented Figure 10-2. LVI Status Register (LVISR) LVIOUT — LVI Output Bit This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage and is cleared when VDD voltage rises above VTRIPR. (See Table 10-1). Table 10-1. LVIOUT Bit Indication VDD LVIOUT VDD > VTRIPR 0 VDD < VTRIPF 1 VTRIPF < VDD < VTRIPR Previous value MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 91 Low-Voltage Inhibit (LVI) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 92 Freescale Semiconductor Chapter 11 Oscillator (OSC) Module 11.1 Introduction The oscillator (OSC) module is used to provide a stable clock source for the MCU system and bus. The OSC shares its pins with general-purpose input/output (I/O) port pins. See Figure 11-1 for port location of these shared pins. The OSC2EN bit is located in the port A pull enable register (PTAPUEN) on this MCU. See Chapter 12 Input/Output Ports (PORTS) for information on PTAPUEN register. 11.2 Features The bus clock frequency is one fourth of any of these clock source options: 1. Internal oscillator: An internally generated, fixed frequency clock, trimmable to ± 0.4%. There are three choices for the internal oscillator,12.8 MHz, 8 MHz, or 4 MHz. The 12.8-MHz internal oscillator is the default option out of reset. 2. External oscillator: An external clock that can be driven directly into OSC1. 3. External RC: A built-in oscillator module (RC oscillator) that requires an external R connection only. The capacitor is internal to the chip. 4. External crystal: A built-in XTAL oscillator that requires an external crystal or ceramic-resonator. There are three crystal frequency ranges supported, 8–32 MHz, 1–8 MHz, and 32–100 kHz. 11.3 Functional Description The oscillator contains these major subsystems: • Internal oscillator circuit • Internal or external clock switch control • External clock circuit • External crystal circuit • External RC clock circuit MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 93 Oscillator (OSC) Module PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT VDD POWER SUPPLY MONITOR ROM BREAK MODULE VSS RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device PTA[0:5]: Higher current sink and source capability PTB[0:7]: Not available on 8-pin devices Figure 11-1. Block Diagram Highlighting OSC Block and Pins 11.3.1 Internal Signal Definitions The following signals and clocks are used in the functional description and figures of the OSC module. 11.3.1.1 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and disables the XTAL oscillator circuit, the RC oscillator, or the internal oscillator in stop mode. OSCENINSTOP in the configuration register can be used to override this signal. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 94 Freescale Semiconductor Functional Description 11.3.1.2 XTAL Oscillator Clock (XTALCLK) XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 11-2 shows only the logical relation of XTALCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may depend on the crystal and other external factors. The frequency of XTALCLK can be unstable at start up. 11.3.1.3 RC Oscillator Clock (RCCLK) RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of the external R (REXT) and internal C. Figure 11-3 shows only the logical relation of RCCLK to OSC1 and may not represent the actual circuitry. 11.3.1.4 Internal Oscillator Clock (INTCLK) INTCLK is the internal oscillator output signal. INTCLK is software selectable to be nominally 12.8 MHz, 8.0 MHz, or 4.0 MHz. INTCLK can be digitally adjusted using the oscillator trimming feature of the OSCTRIM register (see 11.3.2.1 Internal Oscillator Trimming). 11.3.1.5 Bus Clock Times 4 (BUSCLKX4) BUSCLKX4 is the same frequency as the input clock (XTALCLK, RCCLK, or INTCLK). This signal is driven to the SIM module and is used during recovery from reset and stop and is the clock source for the COP module. 11.3.1.6 Bus Clock Times 2 (BUSCLKX2) The frequency of this signal is equal to half of the BUSCLKX4. This signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU. BUSCLKX2 will be divided by two in the SIM. The internal bus frequency is one fourth of the XTALCLK, RCCLK, or INTCLK frequency. 11.3.2 Internal Oscillator The internal oscillator circuit is designed for use with no external components to provide a clock source with a tolerance of less than ±25% untrimmed. An 8-bit register (OSCTRIM) allows the digital adjustment to a tolerance of ACCINT. See the oscillator characteristics in the Electrical section of this data sheet. The internal oscillator is capable of generating clocks of 12.8 MHz, 8.0 MHz, or 4.0 MHz (INTCLK) resulting in a bus frequency (INTCLK divided by 4) of 3.2 MHz, 2.0 MHz, or 1.0 MHz respectively. The bus clock is software selectable and defaults to the 3.2-MHz bus out of reset. Users can increase the bus frequency based on the voltage range of their application. Figure 11-3 shows how BUSCLKX4 is derived from INTCLK and OSC2 can output BUSCLKX4 by setting OSC2EN. 11.3.2.1 Internal Oscillator Trimming OSCTRIM allows a clock period adjustment of +127 and –128 steps. Increasing the OSCTRIM value increases the clock period, which decreases the clock frequency. Trimming allows the internal clock frequency to be fine tuned to the target frequency. All devices are factory programmed with trim values that are stored in FLASH memory at locations $FFC0 and $FFC1. The trim value is not automatically loaded into the OSCTRIM register. User software must MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 95 Oscillator (OSC) Module copy the trim value from $FFC0 or $FFC1 into OSCTRIM if needed. The factory trim value provides the accuracy required for communication using forced monitor mode. Some production programmers erase the factory trim values, so confirm with your programmer vendor that the trim values at $FFC0 and $FFC1 are preserved, or are re-trimmed. Trimming the device in the user application board will provide the most accurate trim value. 11.3.2.2 Internal to External Clock Switching When external clock source (external OSC, RC, or XTAL) is desired, the user must perform the following steps: 1. For external crystal circuits only, configure OSCOPT[1:0] to external crystal. To help precharge an external crystal oscillator, momentarily configure OSC2 as an output and drive it high for several cycles. This can help the crystal circuit start more robustly. 2. Configure OSCOPT[1:0] and ECFS[1:0] according to 11.8.1 Oscillator Status and Control Register. The oscillator module control logic will then enable OSC1 as an external clock input and, if the external crystal option is selected, OSC2 will also be enabled as the clock output. If RC oscillator option is selected, enabling the OSC2 output may change the bus frequency. 3. Create a software delay to provide the stabilization time required for the selected clock source (crystal, resonator, RC). A good rule of thumb for crystal oscillators is to wait 4096 cycles of the crystal frequency; i.e., for a 4-MHz crystal, wait approximately 1 ms. 4. After the stabilization delay has elapsed, set ECGON. After ECGON set is detected, the OSC module checks for oscillator activity by waiting two external clock rising edges. The OSC module then switches to the external clock. Logic provides a coherent transition. The OSC module first sets ECGST and then stops the internal oscillator. 11.3.2.3 External to Internal Clock Switching After following the procedures to switch to an external clock source, it is possible to go back to the internal source. By clearing the OSCOPT[1:0] bits and clearing the ECGON bit, the external circuit will be disengaged. The bus clock will be derived from the selected internal clock source based on the ICFS[1:0] bits. 11.3.3 External Oscillator The external oscillator option is designed for use when a clock signal is available in the application to provide a clock source to the MCU. The OSC1 pin is enabled as an input by the oscillator module. The clock signal is used directly to create BUSCLKX4 and also divided by two to create BUSCLKX2. In this configuration, the OSC2 pin cannot output BUSCLKX4. The OSC2EN bit will be forced clear to enable alternative functions on the pin. 11.3.4 XTAL Oscillator The XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an accurate clock source. In this configuration, the OSC2 pin is dedicated to the external crystal circuit. The OSC2EN bit has no effect when this clock mode is selected. In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator configuration, as shown in Figure 11-2. This figure shows only the logical representation of the internal components and may not represent actual circuitry. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 96 Freescale Semiconductor Functional Description The oscillator configuration uses five components: • Crystal, X1 • Fixed capacitor, C1 • Tuning capacitor, C2 (can also be a fixed capacitor) • Feedback resistor, RB • Series resistor, RS (optional) NOTE The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the oscillator characteristics table in the Electricals section for more information. SIMOSCEN (INTERNAL SIGNAL) OR OSCENINSTOP (BIT LOCATED IN CONFIGURATION REGISTER) BUSCLKX4 XTALCLK BUSCLKX2 ÷2 MCU OSC1 OSC2 RB RS X1 C1 C2 See the electrical section for details. Figure 11-2. XTAL Oscillator External Connections MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 97 Oscillator (OSC) Module 11.3.5 RC Oscillator The RC oscillator circuit is designed for use with an external resistor (REXT) to provide a clock source with a tolerance within 25% of the expected frequency. See Figure 11-3. The capacitor (C) for the RC oscillator is internal to the MCU. The REXT value must have a tolerance of 1% or less to minimize its effect on the frequency. In this configuration, the OSC2 pin can be used as general-purpose input/output (I/O) port pins or other alternative pin function. The OSC2EN bit can be set to enable the OSC2 output function on the pin. Enabling the OSC2 output can affect the external RC oscillator frequency, fRCCLK. SIMOSCEN (INTERNAL SIGNAL) OR OSCENINSTOP (BIT LOCATED IN CONFIGURATION REGISTER) OSCOPT = EXTERNAL RC SELECTED INTCLK BUSCLKX2 BUSCLKX4 0 1 EXTERNAL RC OSCILLATOR EN RCCLK ÷2 1 0 ALTERNATIVE PIN FUNTION OSC2EN MCU OSC1 VDD OSC2 — AVAILABLE FOR ALTERNATIVE PIN FUNCTION REXT See the electricals section for component value. Figure 11-3. RC Oscillator External Connections 11.4 Interrupts There are no interrupts associated with the OSC module. 11.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 11.5.1 Wait Mode The OSC module remains active in wait mode. 11.5.2 Stop Mode The OSC module can be configured to remain active in stop mode by setting OSCENINSTOP located in a configuration register. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 98 Freescale Semiconductor OSC During Break Interrupts 11.6 OSC During Break Interrupts There are no status flags associated with the OSC module. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See BFCR in the SIM section of this data sheet. To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. 11.7 I/O Signals The OSC shares its pins with general-purpose input/output (I/O) port pins. See Figure 11-1 for port location of these shared pins. 11.7.1 Oscillator Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier, an input to the RC oscillator circuit, or an input from an external clock source. When the OSC is configured for internal oscillator, the OSC1 pin can be used as a general-purpose input/output (I/O) port pin or other alternative pin function. 11.7.2 Oscillator Output Pin (OSC2) For the XTAL oscillator option, the OSC2 pin is the output of the crystal oscillator amplifier. When the OSC is configured for internal oscillator, external clock, or RC, the OSC2 pin can be used as a general-purpose I/O port pin or other alternative pin function. When the oscillator is configured for internal or RC, the OSC2 pin can be used to output BUSCLKX4. Table 11-1. OSC2 Pin Function Option OSC2 Pin Function XTAL oscillator Inverting OSC1 External clock General-purpose I/O or alternative pin function Internal oscillator or RC oscillator Controlled by OSC2EN bit OSC2EN = 0: General-purpose I/O or alternative pin function OSC2EN = 1: BUSCLKX4 output MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 99 Oscillator (OSC) Module 11.8 Registers The oscillator module contains two registers: • Oscillator status and control register (OSCSC) • Oscillator trim register (OSCTRIM) 11.8.1 Oscillator Status and Control Register The oscillator status and control register (OSCSC) contains the bits for switching between internal and external clock sources. If the application uses an external crystal, bits in this register are used to select the crystal oscillator amplifier necessary for the desired crystal. While running off the internal clock source, the user can use bits in this register to select the internal clock source frequency. Read: Write: Bit 7 6 5 4 3 2 1 OSCOPT1 OSCOPT0 ICFS1 ICFS0 ECFS1 ECFS0 ECGON 0 0 1 0 0 0 0 Reset: Bit 0 ECGST 0 = Unimplemented Figure 11-4. Oscillator Status and Control Register (OSCSC) OSCOPT1:OSCOPT0 — OSC Option Bits These read/write bits allow the user to change the clock source for the MCU. The default reset condition has the bus clock being derived from the internal oscillator. See 11.3.2.2 Internal to External Clock Switching for information on changing clock sources. OSCOPT1 OSCOPT0 Oscillator Modes 0 0 Internal oscillator (frequency selected using ICFSx bits) 0 1 External oscillator clock 1 0 External RC 1 1 External crystal (range selected using ECFSx bits) ICFS1:ICFS0 — Internal Clock Frequency Select Bits These read/write bits enable the frequency to be increased for applications requiring a faster bus clock when running off the internal oscillator. The WAIT instruction has no effect on the oscillator logic. BUSCLKX2 and BUSCLKX4 continue to drive to the SIM module. ICFS1 ICFS0 Internal Clock Frequency 0 0 4.0 MHz 0 1 8.0 MHz 1 0 12.8 MHz — default reset condition 1 1 Reserved MC68HC908QYA/QTA Family Data Sheet, Rev. 3 100 Freescale Semiconductor Registers ECFS1:ECFS0 — External Crystal Frequency Select Bits These read/write bits enable the specific amplifier for the crystal frequency range. Refer to oscillator characteristics table in the Electricals section for information on maximum external clock frequency versus supply voltage. ECFS1 ECFS0 External Crystal Frequency 0 0 8 MHz – 32 MHz 0 1 1 MHz – 8 MHz 1 0 32 kHz – 100 kHz 1 1 Reserved ECGON — External Clock Generator On Bit This read/write bit enables the OSC1 pin as the clock input to the MCU, so that the switching process can be initiated. This bit is cleared by reset. This bit is ignored in monitor mode with the internal oscillator bypassed. 1 = External clock enabled 0 = External clock disabled ECGST — External Clock Status Bit This read-only bit indicates whether an external clock source is engaged to drive the system clock. 1 = An external clock source engaged 0 = An external clock source disengaged 11.8.2 Oscillator Trim Register (OSCTRIM) Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0 1 0 0 0 0 0 0 0 Figure 11-5. Oscillator Trim Register (OSCTRIM) TRIM7–TRIM0 — Internal Oscillator Trim Factor Bits These read/write bits change the internal capacitance used by the internal oscillator. By measuring the period of the internal clock and adjusting this factor accordingly, the frequency of the internal clock can be fine tuned. Increasing (decreasing) this factor by one increases (decreases) the period by approximately 0.2% of the untrimmed oscillator period. The oscillator period is based on the oscillator frequency selected by the ICFS bits in OSCSC. Applications using the internal oscillator should copy the internal oscillator trim value at location $FFC0 or $FFC1 into this register to trim the clock source. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 101 Oscillator (OSC) Module MC68HC908QYA/QTA Family Data Sheet, Rev. 3 102 Freescale Semiconductor Chapter 12 Input/Output Ports (PORTS) 12.1 Introduction The MC68HC08QY1A, MC68HC08QY2A and MC68HC08QY4A have thirteen bidirectional input-output (I/O) pins and one input only pin. The MC68HC08QT1A, MC68HC08QT2A and MC68HC08QT4A has five bidirectional I/O pins and one input only pin. All I/O pins are programmable as inputs or outputs. 12.2 Unused Pin Termination Input pins and I/O port pins that are not used in the application must be terminated. This prevents excess current caused by floating inputs, and enhances immunity during noise or transient events. Termination methods include: 1. Configuring unused pins as outputs and driving high or low; 2. Configuring unused pins as inputs and enabling internal pull-ups; 3. Configuring unused pins as inputs and using external pull-up or pull-down resistors. Never connect unused pins directly to VDD or VSS. Since some general-purpose I/O pins are not available on all packages, these pins must be terminated as well. Either method 1 or 2 above are appropriate. 12.3 Port A Port A is an 6-bit special function port that shares its pins with the keyboard interrupt (KBI) module (see Chapter 9 Keyboard Interrupt Module (KBI), the 2-channel timer interface module (TIM) (see Chapter 14 Timer Interface Module (TIM)), the 10-bit ADC (see Chapter 3 Analog-to-Digital Converter (ADC10) Module), the external interrupt (IRQ) pin (see Chapter 8 External Interrupt (IRQ)), the reset (RST) pin enabled using a configuration register (see Chapter 5 Configuration Register (CONFIG)) and the oscillator pins (see Chapter 11 Oscillator (OSC) Module). Each port A pin also has a software configurable pullup device if the corresponding port pin is configured as an input port. NOTE PTA2 is input only. When the IRQ function is enabled in the configuration register 2 (CONFIG2), bit 2 of the port A data register (PTA) will always read a logic 0. In this case, the BIH and BIL instructions can be used to read the logic level on the PTA2 pin. When the IRQ function is disabled, these instructions will behave as if the PTA2 pin is a logic 1. However, reading bit 2 of PTA will read the actual logic level on the pin. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 103 Input/Output Ports (PORTS) 12.3.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the six port A pins. Bit 7 Read: Write: R 6 AWUL 5 4 3 PTA5 PTA4 PTA3 Reset: 2 PTA2 1 Bit 0 PTA1 PTA0 Unaffected by reset = Unimplemented Figure 12-1. Port A Data Register (PTA) PTA[5:0] — Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. AWUL — Auto Wakeup Latch Data Bit This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup request signal is generated internally (see Chapter 4 Auto Wakeup Module (AWU)). There is no PTA6 port nor any of the associated bits such as PTA6 data register, pullup enable or direction. 12.3.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer. Read: Write: Reset: Bit 7 6 5 4 3 R R DDRA5 DDRA4 DDRA3 0 0 0 0 R = Reserved 0 2 0 1 Bit 0 DDRA1 DDRA0 0 0 0 = Unimplemented Figure 12-2. Data Direction Register A (DDRA) DDRA[5:0] — Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[5:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 12-3 shows the port A I/O logic. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 104 Freescale Semiconductor Port A READ DDRA PTAPUEx INTERNAL DATA BUS WRITE DDRA DDRAx RESET WRITE PTA PULLUP PTAx PTAx READ PTA Figure 12-3. Port A I/O Circuit NOTE Figure 12-3 does not apply to PTA2 When DDRAx is a 1, reading PTA reads the PTAx data latch. When DDRAx is a 0, reading PTA reads the logic level on the PTAx pin. The data latch can always be written, regardless of the state of its data direction bit. 12.3.3 Port A Input Pullup Enable Register The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each of the port A pins. Each bit is individually configurable and requires the corresponding data direction register, DDRAx, to be configured as input. Each pullup device is automatically and dynamically disabled when its corresponding DDRAx bit is configured as output. Bit 7 Read: Write: 6 OSC2EN Reset: 0 0 5 4 3 2 1 Bit 0 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 0 0 0 0 0 0 = Unimplemented Figure 12-4. Port A Input Pullup Enable Register (PTAPUE) OSC2EN — Enable PTA4 on OSC2 Pin This read/write bit configures the OSC2 pin function when internal oscillator or RC oscillator option is selected. This bit has no effect for the XTAL or external oscillator options. 1 = OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4) 0 = OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup functions PTAPUE[5:0] — Port A Input Pullup Enable Bits These read/write bits are software programmable to enable pullup devices on port A pins. 1 = Corresponding port A pin configured to have internal pullup if its DDRA bit is set to 0 0 = Pullup device is disconnected on the corresponding port A pin regardless of the state of its DDRA bit MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 105 Input/Output Ports (PORTS) 12.3.4 Port A Summary Table The following table summarizes the operation of the port A pins when used as a general-purpose input/output pins. Table 12-1. Port A Pin Functions PTAPUE Bit DDRA Bit PTA Bit I/O Pin Mode Accesses to DDRA Accesses to PTA Read/Write Read Write 1 0 X(1) Input, VDD(2) DDRA5–DDRA0 Pin PTA5–PTA0(3) 0 0 X Input, Hi-Z(4) DDRA5–DDRA0 Pin PTA5–PTA0(3) X 1 X Output DDRA5–DDRA0 PTA5–PTA0 PTA5–PTA0(5) 1. X = don’t care 2. I/O pin pulled to VDD by internal pullup. 3. Writing affects data register, but does not affect input. 4. Hi-Z = high impedance 5. Output does not apply to PTA2 12.4 Port B Port B is an 8-bit special function port that shares two of its pins with the 10-bit ADC (see Chapter 3 Analog-to-Digital Converter (ADC10) Module). Each port B pin also has a software configurable pullup device if the corresponding port pin is configured as an input port. 12.4.1 Port B Data Register The port B data register (PTB) contains a data latch for each of the port B pins. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 Unaffected by reset Figure 12-5. Port B Data Register (PTB) PTB[7:0] — Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 106 Freescale Semiconductor Port B 12.4.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Figure 12-6. Data Direction Register B (DDRB) DDRB[7:0] — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 12-7 shows the port B I/O logic. READ DDRB PTBPUEx INTERNAL DATA BUS WRITE DDRB RESET WRITE PTB DDRBx PULLUP PTBx PTBx READ PTB Figure 12-7. Port B I/O Circuit When DDRBx is a 1, reading PTB reads the PTBx data latch. When DDRBx is a 0, reading PTB reads the logic level on the PTBx pin. The data latch can always be written, regardless of the state of its data direction bit. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 107 Input/Output Ports (PORTS) 12.4.3 Port B Input Pullup Enable Register The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each of the eight port B pins. Each bit is individually configurable and requires the corresponding data direction register, DDRBx, be configured as input. Each pullup device is automatically and dynamically disabled when its corresponding DDRBx bit is configured as output. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE2 PTBPUE0 0 0 0 0 0 0 0 0 Figure 12-8. Port B Input Pullup Enable Register (PTBPUE) PTBPUE[7:0] — Port B Input Pullup Enable Bits These read/write bits are software programmable to enable pullup devices on port B pins 1 = Corresponding port B pin configured to have internal pull if its DDRB bit is set to 0 0 = Pullup device is disconnected on the corresponding port B pin regardless of the state of its DDRB bit. 12.4.4 Port B Summary Table Table 12-2 summarizes the operation of the port A pins when used as a general-purpose input/output pins. Table 12-2. Port B Pin Functions DDRB Bit PTB Bit I/O Pin Mode Accesses to DDRB Accesses to PTB Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRB7–DDRB0 Pin PTB7–PTB0(3) 1 X Output DDRB7–DDRB0 Pin PTB7–PTB0 1. X = don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect the input. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 108 Freescale Semiconductor Chapter 13 System Integration Module (SIM) 13.1 Introduction This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 13-1. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: • Bus clock generation and control for CPU and peripherals – Stop/wait/reset/break entry and recovery – Internal clock control • Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout • Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation • CPU enable/disable timing Table 13-1. Signal Name Conventions Signal Name Description BUSCLKX4 Buffered clock from the internal, RC or XTAL oscillator circuit. BUSCLKX2 The BUSCLKX4 frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks (bus clock = BUSCLKX4 ÷ 4). Address bus Internal address bus Data bus Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal 13.2 RST and IRQ Pins Initialization RST and IRQ pins come out of reset as PTA3 and PTA2 respectively. RST and IRQ functions can be activated by programing CONFIG2 accordingly. Refer to Chapter 5 Configuration Register (CONFIG). MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 109 System Integration Module (SIM) MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK BUSCLKX4 (FROM OSCILLATOR) BUSCLKX2 (FROM OSCILLATOR) ÷2 VDD INTERNAL PULL-UP RESET PIN LOGIC CLOCK CONTROL INTERNAL CLOCKS CLOCK GENERATORS POR CONTROL ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) MASTER RESET CONTROL RESET PIN CONTROL LVI RESET (FROM LVI MODULE) SIM RESET STATUS REGISTER FORCED MON MODE ENTRY (FROM MENRST MODULE) RESET INTERRUPT SOURCES INTERRUPT CONTROL AND PRIORITY DECODE CPU INTERFACE Figure 13-1. SIM Block Diagram 13.3 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, BUSCLKX2, as shown in Figure 13-2. FROM OSCILLATOR BUSCLKX4 FROM OSCILLATOR BUSCLKX2 SIM COUNTER BUS CLOCK GENERATORS ÷2 SIM Figure 13-2. SIM Clock Signals MC68HC908QYA/QTA Family Data Sheet, Rev. 3 110 Freescale Semiconductor Reset and System Initialization 13.3.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four. 13.3.2 Clock Start-Up from POR When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 BUSCLKX4 cycle POR time out has completed. The IBUS clocks start upon completion of the time out. 13.3.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt or reset, the SIM allows BUSCLKX4 to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay time out. This time out is selectable as 4096 or 32 BUSCLKX4 cycles. See 13.7.2 Stop Mode. In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. 13.4 Reset and System Initialization The MCU has these reset sources: • Power-on reset module (POR) • External reset pin (RST) • Computer operating properly module (COP) • Low-voltage inhibit module (LVI) • Illegal opcode • Illegal address All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 13.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). See 13.8 SIM Registers. 13.4.1 External Pin Reset The RST pin circuits include an internal pullup device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for at least the minimum tRL time. Figure 13-3 shows the relative timing. The RST pin function is only available if the RSTEN bit is set in the CONFIG2 register. BUSCLKX2 RST ADDRESS BUS PC VECT H VECT L Figure 13-3. External Reset Timing MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 111 System Integration Module (SIM) 13.4.2 Active Resets from Internal Sources The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the CONFIG2 register enables the pin for the reset function. This section assumes the RSTEN bit is set when describing activity on the RST pin. NOTE For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 13-4. The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. All internal reset sources actively pull the RST pin low for 32 BUSCLKX4 cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 13-4). An internal reset can be caused by an illegal address, illegal opcode, COP time out, LVI, or POR (see Figure 13-5). IRST RST RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES BUSCLKX4 ADDRESS BUS VECTOR HIGH Figure 13-4. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR LVI INTERNAL RESET Figure 13-5. Sources of Internal Reset Table 13-2. Reset Recovery Timing Reset Recovery Type Actual Number of Cycles POR/LVI 4163 (4096 + 64 + 3) All others 67 (64 + 3) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 112 Freescale Semiconductor Reset and System Initialization 13.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power on, the following events occur: • A POR pulse is generated. • The internal reset signal is asserted. • The SIM enables the oscillator to drive BUSCLKX4. • Internal clocks to the CPU and modules are held inactive for 4096 BUSCLKX4 cycles to allow stabilization of the oscillator. • The POR bit of the SIM reset status register (SRSR) is set. See Figure 13-6. OSC1 PORRST 4096 CYCLES 32 CYCLES 32 CYCLES BUSCLKX4 BUSCLKX2 (RST PIN IS A GENERAL-PURPOSE INPUT AFTER A POR) RST ADDRESS BUS $FFFE $FFFF Figure 13-6. POR Recovery 13.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module time out, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and stages 12–5 of the SIM counter. The SIM counter output, which occurs at least every 4080 BUSCLKX4 cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first time out. The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). 13.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 113 System Integration Module (SIM) If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 13.4.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. See Figure 2-1. Memory Map for memory ranges. 13.4.2.5 Low-Voltage Inhibit (LVI) Reset The LVI asserts its output to the SIM when the VDD voltage falls to the LVI trip voltage VTRIPF. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 BUSCLKX4 cycles after VDD rises above VTRIPR. Sixty-four BUSCLKX4 cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the (RST) pin for all internal reset sources. 13.5 SIM Counter The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP module. The SIM counter is clocked by the falling edge of BUSCLKX4. 13.5.1 SIM Counter During Power-On Reset The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine. 13.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the configuration register 1 (CONFIG1). If the SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles down to 32 BUSCLKX4 cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared in the configuration register 1 (CONFIG1). 13.5.3 SIM Counter and Reset States External reset has no effect on the SIM counter (see 13.7.2 Stop Mode for details.) The SIM counter is free-running after all reset states. See 13.4.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 114 Freescale Semiconductor Exception Control 13.6 Exception Control Normal sequential program execution can be changed in three different ways: 1. Interrupts a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) 2. Reset 3. Break interrupts 13.6.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 13-7 flow charts the handling of system interrupts. Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 13-8 shows interrupt entry timing. Figure 13-9 shows interrupt recovery timing. 13.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 13-10 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. The LDA opcode is prefetched by both the INT1 and INT2 return-from-interrupt (RTI) instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 115 System Integration Module (SIM) FROM RESET BREAK INTERRUPT? I BIT SET? YES NO YES I BIT SET? NO IRQ INTERRUPT? YES NO TIMER INTERRUPT? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR (AS MANY INTERRUPTS AS EXIST ON CHIP) FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 13-7. Interrupt Processing MC68HC908QYA/QTA Family Data Sheet, Rev. 3 116 Freescale Semiconductor Exception Control MODULE INTERRUPT I BIT ADDRESS BUS DUMMY DATA BUS SP DUMMY SP – 1 SP – 2 PC – 1[7:0] PC – 1[15:8] SP – 3 X SP – 4 A VECT H CCR VECT L V DATA H START ADDR V DATA L OPCODE R/W Figure 13-8. Interrupt Entry MODULE INTERRUPT I BIT ADDRESS BUS SP – 4 DATA BUS SP – 3 CCR SP – 2 A SP – 1 X SP PC PC + 1 PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND R/W Figure 13-9. Interrupt Recovery CLI LDA #$FF INT1 BACKGROUND ROUTINE PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 13-10. Interrupt Recognition Example MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 117 System Integration Module (SIM) 13.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. 13.6.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 13-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Table 13-3. Interrupt Sources Flag Mask(1) INT Register Flag Vector Address Reset — — — $FFFE–$FFFF SWI instruction — — — $FFFC–$FFFD IRQ pin IRQF IMASK IF1 $FFFA–$FFFB Timer channel 0 interrupt CH0F CH0IE IF3 $FFF6–$FFF7 Timer channel 1 interrupt CH1F CH1IE IF4 $FFF4–$FFF5 TOF TOIE IF5 $FFF2–$FFF3 Keyboard interrupt KEYF IMASKK IF14 $FFE0–$FFE1 ADC conversion complete interrupt COCO AIEN IF15 $FFDE–$FFDF Priority Highest Source Timer overflow interrupt Lowest 1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 118 Freescale Semiconductor Exception Control 13.6.2.1 Interrupt Status Register 1 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 13-11. Interrupt Status Register 1 (INT1) IF1–IF6 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 13-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0, 1 — Always read 0 13.6.2.2 Interrupt Status Register 2 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Write: R R R R R R R R 0 0 0 0 0 0 0 0 R = Reserved Reset: Figure 13-12. Interrupt Status Register 2 (INT2) IF7–IF14 — Interrupt Flags This flag indicates the presence of interrupt requests from the sources shown in Table 13-3. 1 = Interrupt request present 0 = No interrupt request present 13.6.2.3 Interrupt Status Register 3 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF22 IF21 IF20 IF19 IF18 IF17 IF16 IF15 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 13-13. Interrupt Status Register 3 (INT3) IF15–IF22 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 13-3. 1 = Interrupt request present 0 = No interrupt request present MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 119 System Integration Module (SIM) 13.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 13.6.4 Break Interrupts The break module can stop normal program flow at a software programmable break point by asserting its break interrupt output. (See Chapter 15 Development Support.) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. 13.6.5 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the break flag control register (BFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example, a read of one register followed by the read or write of another — are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal. 13.7 Low-Power Modes Executing the WAIT or STOP instruction puts the MCU in a low power- consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 13.7.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 13-14 shows the timing for wait mode entry. ADDRESS BUS DATA BUS WAIT ADDR WAIT ADDR + 1 PREVIOUS DATA NEXT OPCODE SAME SAME SAME SAME R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 13-14. Wait Mode Entry Timing A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 120 Freescale Semiconductor Low-Power Modes In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset (or break in emulation mode). A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD, in the configuration register is 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. Figure 13-15 and Figure 13-16 show the timing for wait recovery. ADDRESS BUS DATA BUS $6E0B $A6 $A6 $6E0C $A6 $00FF $01 $0B $00FE $00FD $00FC $6E EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt Figure 13-15. Wait Recovery from Interrupt 32 CYCLES ADDRESS BUS DATA BUS 32 CYCLES $6E0B $A6 $A6 RSTVCT H RSTVCT L $A6 RST(1) BUSCLKX4 1. RST is only available if the RSTEN bit in the CONFIG1 register is set. Figure 13-16. Wait Recovery from Internal Reset 13.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop mode, stopping the CPU and peripherals. If OSCENINSTOP is set, BUSCLKX2 will remain running in STOP and can be used to run the AWU. Stop recovery time is selectable using the SSREC bit in the configuration register 1 (CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles down to 32. This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do not require long start-up times from stop mode. NOTE External crystal applications should use the full stop recovery time by clearing the SSREC bit. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 121 System Integration Module (SIM) The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 13-17 shows stop mode entry timing and Figure 13-18 shows the stop mode recovery time from interrupt or break NOTE To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0. CPUSTOP ADDRESS BUS STOP ADDR + 1 STOP ADDR DATA BUS PREVIOUS DATA SAME SAME NEXT OPCODE SAME SAME R/W NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction. Figure 13-17. Stop Mode Entry Timing STOP RECOVERY PERIOD BUSCLKX4 INTERRUPT ADDRESS BUS STOP + 2 STOP +1 STOP + 2 SP SP – 1 SP – 2 SP – 3 Figure 13-18. Stop Mode Recovery from Interrupt 13.8 SIM Registers The SIM has two memory mapped registers. 13.8.1 SIM Reset Status Register The SRSR register contains flags that show the source of the last reset. The status register will automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the register. All other reset sources set the individual flag bits but do not clear the register. More than one reset source can be flagged at any time depending on the conditions at the time of the internal or external reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time. Read: Bit 7 6 5 4 3 2 1 Bit 0 POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 Write: POR: = Unimplemented Figure 13-19. SIM Reset Status Register (SRSR) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 122 Freescale Semiconductor SIM Registers POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (illegal attempt to fetch an opcode from an unimplemented address) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR MODRST — Monitor Mode Entry Module Reset bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ ≠ VTST 0 = POR or read of SRSR LVI — Low Voltage Inhibit Reset bit 1 = Last reset caused by LVI circuit 0 = POR or read of SRSR 13.8.2 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 13-20. Break Flag Control Register (BFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 123 System Integration Module (SIM) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 124 Freescale Semiconductor Chapter 14 Timer Interface Module (TIM) 14.1 Introduction This section describes the timer interface module (TIM). The TIM module is a 2-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. The TIM module shares its pins with general-purpose input/output (I/O) port pins. See Figure 14-1 for port location of these shared pins. 14.2 Features Features include the following: • Two input capture/output compare channels – Rising-edge, falling-edge, or any-edge input capture trigger – Set, clear, or toggle output compare action • Buffered and unbuffered output compare pulse-width modulation (PWM) signal generation • Programmable clock input – 7-frequency internal bus clock prescaler selection – External clock input pin if available, See Figure 14-1 • Free-running or modulo up-count operation • Toggle any channel pin on overflow • Counter stop and reset bits 14.3 Functional Description Figure 14-2 shows the structure of the TIM. The central component of the TIM is the 16-bit counter that can operate as a free-running counter or a modulo up-counter. The counter provides the timing reference for the input capture and output compare functions. The counter modulo registers, TMODH:TMODL, control the modulo value of the counter. Software can read the counter value, TCNTH:TCNTL, at any time without affecting the counting sequence. The two TIM channels are programmable independently as input capture or output compare channels. 14.3.1 TIM Counter Prescaler The TIM clock source is one of the seven prescaler outputs or the external clock input pin, TCLK if available. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the clock source. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 125 Timer Interface Module (TIM) PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE VDD POWER SUPPLY VSS RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device PTA[0:5]: Higher current sink and source capability PTB[0:7]: Not available on 8-pin devices Figure 14-1. Block Diagram Highlighting TIM Block and Pins 14.3.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can be enabled to generate interrupt requests. 14.3.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can be enabled to generate interrupt requests. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 126 Freescale Semiconductor Functional Description TCLK TCLK (IF AVAILABLE) PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TCNTH:TCNTL TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 TOV0 ELS0B ELS0A CH0MAX 16-BIT COMPARATOR TCH0H:TCH0L PORT LOGIC TCH0 CH0F 16-BIT LATCH CH0IE MS0A INTERRUPT LOGIC MS0B INTERNAL BUS TOV1 CHANNEL 1 ELS1B ELS1A CH1MAX 16-BIT COMPARATOR TCH1H:TCH1L PORT LOGIC TCH1 CH1F 16-BIT LATCH MS1A CH1IE INTERRUPT LOGIC Figure 14-2. TIM Block Diagram 14.3.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 14.3.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: • When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. • When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 127 Timer Interface Module (TIM) the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 14.3.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares. 14.3.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 14-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the polarity of the PWM pulse is 1 (ELSxA = 0). Program the TIM to set the pin if the polarity of the PWM pulse is 0 (ELSxA = 1). OVERFLOW OVERFLOW OVERFLOW PERIOD POLARITY = 1 T1CHx (ELSxA = 0) PULSE WIDTH POLARITY = 0 T1CHx (ELSxA = 1) OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 14-3. PWM Period and Pulse Width The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000. See 14.8.1 TIM Status and Control Register. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 128 Freescale Semiconductor Functional Description The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 14.3.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 14.3.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written to the timer channel (TCHxH:TCHxL). Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. • When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 14.3.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 129 Timer Interface Module (TIM) channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 14.3.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the counter by setting the TIM stop bit, TSTOP. b. Reset the counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. See Table 14-2. b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. See Table 14-2. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. See 14.8.1 TIM Status and Control Register. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 130 Freescale Semiconductor Interrupts 14.4 Interrupts The following TIM sources can generate interrupt requests: • TIM overflow flag (TOF) — The TOF bit is set when the counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow interrupt requests. TOF and TOIE are in the TSC register. • TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM interrupt requests are enabled when CHxIE =1. CHxF and CHxIE are in the TSCx register. 14.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 14.5.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not accessible by the CPU. Any enabled interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 14.5.2 Stop Mode The TIM module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. TIM operation resumes after an external interrupt. If stop mode is exited by reset, the TIM is reset. 14.6 TIM During Break Interrupts A break interrupt stops the counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See BFCR in the SIM section of this data sheet. To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 131 Timer Interface Module (TIM) 14.7 I/O Signals The TIM module can share its pins with the general-purpose I/O pins. See Figure 14-1 for the port pins that are shared. 14.7.1 TIM Channel I/O Pins (TCH1:TCH0) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. TCH0 can be configured as buffered output compare or buffered PWM pin. 14.7.2 TIM Clock Pin (TCLK) TCLK is an external clock input that can be the clock source for the counter instead of the prescaled internal bus clock. Select the TCLK input by writing 1s to the three prescaler select bits, PS[2:0]. 14.8.1 TIM Status and Control Register The minimum TCLK pulse width is specified in the Timer Interface Module Characteristics table in the Electricals section. The maximum TCLK frequency is the least of 4 MHz or bus frequency ÷ 2. 14.8 Registers The following registers control and monitor operation of the TIM: • TIM status and control register (TSC) • TIM control registers (TCNTH:TCNTL) • TIM counter modulo registers (TMODH:TMODL) • TIM channel status and control registers (TSC0 and TSC1) • TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L) 14.8.1 TIM Status and Control Register The TIM status and control register (TSC) does the following: • Enables TIM overflow interrupts • Flags TIM overflows • Stops the counter • Resets the counter • Prescales the counter clock Bit 7 Read: TOF Write: 0 Reset: 0 6 5 TOIE TSTOP 0 1 4 3 0 0 TRST 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 = Unimplemented Figure 14-4. TIM Status and Control Register (TSC) TOF — TIM Overflow Flag Bit This read/write flag is set when the counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TSC register when TOF is set and then writing a 0 to TOF. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 132 Freescale Semiconductor Registers If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Writing a 1 to TOF has no effect. 1 = Counter has reached modulo value 0 = Counter has not reached modulo value TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP — TIM Stop Bit This read/write bit stops the counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the counter until software clears the TSTOP bit. 1 = Counter stopped 0 = Counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. Also, when the TSTOP bit is set and the timer is configured for input capture operation, input captures are inhibited until the TSTOP bit is cleared. TRST — TIM Reset Bit Setting this write-only bit resets the counter and the TIM prescaler. Setting TRST has no effect on any other timer registers. Counting resumes from $0000. TRST is cleared automatically after the counter is reset and always reads as 0. 1 = Prescaler and counter cleared 0 = No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the counter at a value of $0000.PS[2:0] — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the counter as Table 14-1 shows. Table 14-1. Prescaler Selection PS2 PS1 PS0 TIM Clock Source 0 0 0 Internal bus clock ÷ 1 0 0 1 Internal bus clock ÷ 2 0 1 0 Internal bus clock ÷ 4 0 1 1 Internal bus clock ÷ 8 1 0 0 Internal bus clock ÷ 16 1 0 1 Internal bus clock ÷ 32 1 1 0 Internal bus clock ÷ 64 1 1 1 TCLK (if available) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 133 Timer Interface Module (TIM) 14.8.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. NOTE If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break. Read: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 14-5. TIM Counter High Register (TCNTH) Read: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 14-6. TIM Counter Low Register (TCNTL) 14.8.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the counter. When the counter reaches the modulo value, the overflow flag (TOF) becomes set, and the counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 1 1 1 1 1 1 1 1 Figure 14-7. TIM Counter Modulo High Register (TMODH) Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 1 1 1 1 1 1 1 Figure 14-8. TIM Counter Modulo Low Register (TMODL) NOTE Reset the counter before writing to the TIM counter modulo registers. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 134 Freescale Semiconductor Registers 14.8.4 TIM Channel Status and Control Registers Each of the TIM channel status and control registers does the following: • Flags input captures and output compares • Enables input capture and output compare interrupts • Selects input capture, output compare, or PWM operation • Selects high, low, or toggling output on output compare • Selects rising edge, falling edge, or any edge as the active input capture trigger • Selects output toggling on TIM overflow • Selects 0% and 100% PWM duty cycle • Selects buffered or unbuffered output compare/PWM operation Bit 7 Read: CH0F Write: 0 Reset: 0 6 5 4 3 2 1 Bit 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 Figure 14-9. TIM Channel 0 Status and Control Register (TSC0) Bit 7 Read: CH1F Write: 0 Reset: 0 6 CH1IE 0 5 0 0 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 = Unimplemented Figure 14-10. TIM Channel 1 Status and Control Register (TSC1) CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the counter registers matches the value in the TIM channel x registers. Clear CHxF by reading the TSCx register with CHxF set and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Writing a 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE — Channel x Interrupt Enable Bit This read/write bit enables TIM interrupt service requests on channel x. 1 = Channel x interrupt requests enabled 0 = Channel x interrupt requests disabled MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TSC0. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 135 Timer Interface Module (TIM) Setting MS0B causes the contents of TSC1 to be ignored by the TIM and reverts TCH1 to general-purpose I/O. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA — Mode Select Bit A When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 14-2. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see Table 14-2). 1 = Initial output level low 0 = Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). ELSxB and ELSxA — Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 14-2 shows how ELSxB and ELSxA work. Table 14-2. Mode, Edge, and Level Selection MSxB MSxA ELSxB ELSxA X 0 0 0 X 1 0 0 Mode Output preset Configuration Pin under port control; initial output level high Pin under port control; initial output level low 0 0 0 1 0 0 1 0 0 0 1 1 Capture on rising or falling edge 0 1 0 0 Software compare only 0 1 0 1 0 1 1 0 0 1 1 1 1 X 0 1 1 X 1 0 1 X 1 1 Capture on rising edge only Input capture Output compare or PWM Capture on falling edge only Toggle output on compare Clear output on compare Set output on compare Buffered output compare or buffered PWM Toggle output on compare Clear output on compare Set output on compare NOTE After initially enabling a TIM channel register for input capture operation and selecting the edge sensitivity, clear CHxF to ignore any erroneous edge detection flags. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 136 Freescale Semiconductor Registers TOVx — Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the counter overflows. When channel x is an input capture channel, TOVx has no effect. 1 = Channel x pin toggles on TIM counter overflow. 0 = Channel x pin does not toggle on TIM counter overflow. NOTE When TOVx is set, a counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 14-11 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD T1CHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE CHxMAX Figure 14-11. CHxMAX Latency 14.8.5 TIM Channel Registers These read/write registers contain the captured counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written. Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate after reset Figure 14-12. TIM Channel x Register High (TCHxH) Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset Figure 14-13. TIM Channel Register Low (TCHxL) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 137 Timer Interface Module (TIM) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 138 Freescale Semiconductor Chapter 15 Development Support 15.1 Introduction This section describes the break module, the monitor module (MON), and the monitor mode entry methods. 15.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. Features include: • Accessible input/output (I/O) registers during the break Interrupt • Central processor unit (CPU) generated break interrupts • Software-generated break interrupts • Computer operating properly (COP) disabling during break interrupts 15.2.1 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the system integration module (SIM). The SIM then causes the CPU to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: • A CPU generated address (the address in the program counter) matches the contents of the break address registers. • Software writes a 1 to the BRKA bit in the break status and control register. When a CPU generated address matches the contents of the break address registers, the break interrupt is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the microcontroller unit (MCU) to normal operation. Figure 15-2 shows the structure of the break module. When the internal address bus matches the value written in the break address registers or when software writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 139 Development Support PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE VDD POWER SUPPLY VSS RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device PTA[0:5]: Higher current sink and source capability PTB[0:7]: Not available on 8-pin devices Figure 15-1. Block Diagram Highlighting BRK and MON Blocks ADDRESS BUS[15:8] BREAK ADDRESS REGISTER HIGH ADDRESS BUS[15:0] 8-BIT COMPARATOR CONTROL 8-BIT COMPARATOR BKPT (TO SIM) BREAK ADDRESS REGISTER LOW ADDRESS BUS[7:0] Figure 15-2. Break Module Block Diagram MC68HC908QYA/QTA Family Data Sheet, Rev. 3 140 Freescale Semiconductor Break Module (BRK) The break interrupt timing is: • When a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. • When a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. • When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction is executed. By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can be generated continuously. CAUTION A break address should be placed at the address of the instruction opcode. When software does not change the break address and clears the BRKA bit in the first break interrupt routine, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers. 15.2.1.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See 13.8.2 Break Flag Control Register and the Break Interrupts subsection for each module. 15.2.1.2 TIM During Break Interrupts A break interrupt stops the timer counter. 15.2.1.3 COP During Break Interrupts The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). 15.2.2 Break Module Registers These registers control and monitor operation of the break module: • Break status and control register (BRKSCR) • Break address register high (BRKH) • Break address register low (BRKL) • Break status register (BSR) • Break flag control register (BFCR) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 141 Development Support 15.2.2.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Read: Write: Reset: Bit 7 6 BRKE BRKA 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 15-3. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = Break address match 0 = No break address match 15.2.2.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 15-4. Break Address Register High (BRKH) Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 15-5. Break Address Register Low (BRKL) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 142 Freescale Semiconductor Break Module (BRK) 15.2.2.3 Break Auxiliary Register The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the MCU is in a state of break interrupt with monitor mode. Read: Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: Bit 0 BDCOP 0 = Unimplemented Figure 15-6. Break Auxiliary Register (BRKAR) BDCOP — Break Disable COP Bit This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit. 1 = COP disabled during break interrupt 0 = COP enabled during break interrupt 15.2.2.4 Break Status Register The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode. Read: Write: Bit 7 6 5 4 3 2 R R R R R R Reset: 1 SBSW Note(1) Bit 0 R 0 R = Reserved 1. Writing a 0 clears SBSW. Figure 15-7. Break Status Register (BSR) SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 1 = Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt 15.2.2.5 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 15-8. Break Flag Control Register (BFCR) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 143 Development Support BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break 15.2.3 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. If enabled, the break module will remain enabled in wait and stop modes. However, since the internal address bus does not increment in these modes, a break interrupt will never be triggered. 15.3 Monitor Module (MON) The monitor module allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. Features include: • Normal user-mode pin functionality • One pin dedicated to serial communication between MCU and host computer • Standard non-return-to-zero (NRZ) communication with host computer • Standard communication baud rate (7200 @ 2-MHz bus frequency) • Execution of code in random-access memory (RAM) or FLASH • FLASH memory security feature(1) • FLASH memory programming interface • Use of external 9.8304 MHz oscillator to generate internal frequency of 2.4576 MHz • Simple internal oscillator mode of operation (no external clock or high voltage) • Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain $FF) • Normal monitor mode entry if VTST is applied to IRQ 15.3.1 Functional Description Figure 15-9 shows a simplified diagram of monitor mode entry. The monitor module receives and executes commands from a host computer. Figure 15-10, Figure 15-11, and Figure 15-12 show example circuits used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 144 Freescale Semiconductor Monitor Module (MON) POR RESET NO CONDITIONS FROM Table 15-1 PTA0 = 1, RESET VECTOR BLANK? IRQ = VTST? YES PTA0 = 1, PTA1 = 1, AND PTA4 = 0? NO NO YES YES FORCED MONITOR MODE NORMAL USER MODE NORMAL MONITOR MODE INVALID USER MODE HOST SENDS 8 SECURITY BYTES IS RESET POR? YES NO YES ARE ALL SECURITY BYTES CORRECT? ENABLE FLASH NO DISABLE FLASH MONITOR MODE ENTRY DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) EXECUTE MONITOR CODE YES DOES RESET OCCUR? NO Figure 15-9. Simplified Monitor Mode Entry Flowchart MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 145 Development Support VDD VDD 10 kΩ* VDD RST (PTA3) MAX232 1 1 μF + 3 4 1 μF + VDD 16 C1+ + 1 kΩ 9.1 V 1 μF 10 kΩ + 74HC125 3 2 9 8 PTA4 74HC125 5 6 10 10 kΩ* PTA0 4 VSS 1 5 10 kΩ* IRQ (PTA2) VDD V– 6 7 VDD PTA1 DB9 3 1 μF V+ 2 C2+ OSC1 (PTA5) 1 μF 15 C1– 0.1 μF VTST + 5 C2– 2 9.8304 MHz CLOCK * Value not critical Figure 15-10. Monitor Mode Circuit (External Clock, with High Voltage) VDD N.C. 1 1 μF 3 4 1 μF + C1+ C1– C2+ 5 C2– VDD 16 + 9.8304 MHz CLOCK 1 μF 15 + 10 kΩ* VDD V– 6 1 μF 2 7 10 3 8 9 10 kΩ 74HC125 5 6 + 2 OSC1 (PTA5) 1 μF V+ 2 DB9 5 VDD 0.1 μF MAX232 + RST (PTA3) 74HC125 3 IRQ (PTA2) PTA1 N.C. PTA4 N.C. PTA0 4 VSS 1 * Value not critical Figure 15-11. Monitor Mode Circuit (External Clock, No High Voltage) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 146 Freescale Semiconductor Monitor Module (MON) VDD N.C. RST (PTA3) VDD 0.1 μF MAX232 1 1 μF + 3 4 1 μF + C1+ C1– C2+ 5 C2– VDD + 3 1 μF 15 + OSC1 (PTA5) IRQ (PTA2) 1 μF VDD V– 6 1 μF 7 10 8 9 10 kΩ 74HC125 5 6 + 74HC125 3 2 PTA1 N.C. PTA4 N.C. 10 kΩ* V+ 2 DB9 2 N.C. 16 PTA0 VSS 4 1 5 * Value not critical Figure 15-12. Monitor Mode Circuit (Internal Clock, No High Voltage) The monitor code has been updated from previous versions of the monitor code to allow enabling the internal oscillator to generate the internal clock. This addition, which is enabled when IRQ is held low out of reset, is intended to support serial communication/programming at 9600 baud in monitor mode by using the internal oscillator, and the internal oscillator user trim value OSCTRIM (FLASH location $FFC0, if programmed) to generate the desired internal frequency (3.2 MHz). Since this feature is enabled only when IRQ is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value is not $FFFF) because entry into monitor mode in this case requires VTST on IRQ. The IRQ pin must remain low during this monitor session in order to maintain communication. Table 15-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one of the following sets of conditions is met: • If $FFFE and $FFFF do not contain $FF (programmed state): – The external clock is 9.8304 MHz – IRQ = VTST • If $FFFE and $FFFF contain $FF (erased state): – The external clock is 9.8304 MHz – IRQ = VDD (this can be implemented through the internal IRQ pullup) • If $FFFE and $FFFF contain $FF (erased state): – IRQ = VSS (internal oscillator is selected, no external clock required) The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the values on PTA1 and PTA4 pins can be changed. Once out of reset, the MCU waits for the host to send eight security bytes (see 15.3.2 Security). After the security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to receive a command. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 147 Development Support Table 15-1. Monitor Mode Signal Requirements and Options Mode Serial Mode CommuniSelection RST Reset IRQ cation (PTA2) (PTA3) Vector PTA0 PTA1 PTA4 Communication Speed COP External Bus Clock Frequency Comments Baud Rate VTST VDD X 1 1 0 Disabled 9.8304 MHz 2.4576 MHz 9600 Provide external clock at OSC1. VDD X $FFFF (blank) 1 X X Disabled 9.8304 MHz 2.4576 MHz 9600 Provide external clock at OSC1. VSS X $FFFF (blank) 1 X X Disabled X 3.2 MHz (Trimmed) 9600 Internal clock is active. User X X Not $FFFF X X X Enabled X X X MON08 Function [Pin No.] VTST [6] RST [4] — COM [8] — OSC1 [13] — — Normal Monitor Forced Monitor MOD0 MOD1 [12] [10] 1. PTA0 must have a pullup resistor to VDD in monitor mode. 2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus frequency / 256 and baud rate using internal oscillator is bus frequency / 335. 3. External clock is a 9.8304 MHz oscillator on OSC1. 4. Lowering VTST once monitor mode is entered allows the clock source to be controlled by the OSCSC register. 5. X = don’t care 6. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector. NC 1 2 GND NC 3 4 RST NC 5 6 IRQ NC 7 8 PTA0 NC 9 10 PTA4 NC 11 12 PTA1 OSC1 13 14 NC VDD 15 16 NC 15.3.1.1 Normal Monitor Mode RST and OSC1 functions will be active on the PTA3 and PTA5 pins respectively as long as VTST is applied to the IRQ pin. If the IRQ pin is lowered (no longer VTST) then the chip will still be operating in monitor mode, but the pin functions will be determined by the settings in the configuration registers (see Chapter 5 Configuration Register (CONFIG)) when VTST was lowered. With VTST lowered, the BIH and BIL instructions will read the IRQ pin state only if IRQEN is set in the CONFIG2 register. If monitor mode was entered with VTST on IRQ, then the COP is disabled as long as VTST is applied to IRQ. 15.3.1.2 Forced Monitor Mode If entering monitor mode without high voltage on IRQ, then startup port pin requirements and conditions, (PTA1/PTA4) are not in effect. This is to reduce circuit requirements when performing in-circuit programming. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 148 Freescale Semiconductor Monitor Module (MON) NOTE If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (POR). Once the reset vector has been programmed, the traditional method of applying a voltage, VTST, to IRQ must be used to enter monitor mode. If monitor mode was entered as a result of the reset vector being blank, the COP is always disabled regardless of the state of IRQ. If the voltage applied to the IRQ is less than VTST, the MCU will come out of reset in user mode. Internal circuitry monitors the reset vector fetches and will assert an internal reset if it detects that the reset vectors are erased ($FF). When the MCU comes out of reset, it is forced into monitor mode without requiring high voltage on the IRQ pin. Once out of reset, the monitor code is initially executing with the internal clock at its default frequency. If IRQ is held high, all pins will default to regular input port functions except for PTA0 and PTA5 which will operate as a serial communication port and OSC1 input respectively (refer to Figure 15-11). That will allow the clock to be driven from an external source through OSC1 pin. If IRQ is held low, all pins will default to regular input port function except for PTA0 which will operate as serial communication port. Refer to Figure 15-12. Regardless of the state of the IRQ pin, it will not function as a port input pin in monitor mode. Bit 2 of the Port A data register will always read 0. The BIH and BIL instructions will behave as if the IRQ pin is enabled, regardless of the settings in the configuration register. See Chapter 5 Configuration Register (CONFIG). The COP module is disabled in forced monitor mode. Any reset other than a power-on reset (POR) will automatically force the MCU to come back to the forced monitor mode. 15.3.1.3 Monitor Vectors In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. NOTE Exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (POR). Pulling RST (when RST pin available) low will not exit monitor mode in this situation. Table 15-2 summarizes the differences between user mode and monitor mode regarding vectors. Table 15-2. Mode Difference Functions Modes Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 149 Development Support 15.3.1.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT Figure 15-13. Monitor Data Format 15.3.1.5 Break Signal A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal. MISSING STOP BIT 2-STOP BIT DELAY BEFORE ZERO ECHO 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Figure 15-14. Break Transaction 15.3.1.6 Baud Rate The monitor communication baud rate is controlled by the frequency of the external or internal oscillator and the state of the appropriate pins as shown in Table 15-1. Table 15-1 also lists the bus frequencies to achieve standard baud rates. The effective baud rate is the bus frequency divided by 256 when using an external oscillator. When using the internal oscillator in forced monitor mode, the effective baud rate is the bus frequency divided by 335. 15.3.1.7 Commands The monitor ROM firmware uses these commands: • READ (read memory) • WRITE (write memory) • IREAD (indexed read) • IWRITE (indexed write) • READSP (read stack pointer) • RUN (run user program) The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command. NOTE Wait one bit time after each echo before sending the next byte. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 150 Freescale Semiconductor Monitor Module (MON) FROM HOST 4 ADDRESS HIGH READ READ 4 1 ADDRESS HIGH 1 ADDRESS LOW 4 ECHO Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times ADDRESS LOW DATA 1 3, 2 4 RETURN 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte. Figure 15-15. Read Transaction FROM HOST 3 ADDRESS HIGH WRITE WRITE 3 1 ADDRESS HIGH 1 ADDRESS LOW 3 ADDRESS LOW 1 DATA DATA 3 1 2, 3 ECHO Notes: 1 = Echo delay, approximately 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte. Figure 15-16. Write Transaction A brief description of each monitor mode command is given in Table 15-3 through Table 15-8. Table 15-3. READ (Read Memory) Command Description Read byte from memory Operand 2-byte address in high-byte:low-byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR READ READ ADDRESS ADDRESS ADDRESS HIGH HIGH LOW ADDRESS LOW ECHO DATA RETURN MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 151 Development Support Table 15-4. WRITE (Write Memory) Command Description Operand Data Returned Opcode Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence FROM HOST WRITE WRITE ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 15-5. IREAD (Indexed Read) Command Description Operand Data Returned Opcode Read next 2 bytes in memory from last address accessed None Returns contents of next two addresses $1A Command Sequence FROM HOST IREAD IREAD DATA ECHO DATA RETURN Table 15-6. IWRITE (Indexed Write) Command Description Operand Data Returned Opcode Write to last address accessed + 1 Single data byte None $19 Command Sequence FROM HOST IWRITE IWRITE DATA DATA ECHO A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 152 Freescale Semiconductor Monitor Module (MON) Table 15-7. READSP (Read Stack Pointer) Command Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence FROM HOST READSP SP HIGH READSP SP LOW ECHO RETURN Table 15-8. RUN (Run User Program) Command Description Executes PULH and RTI instructions Operand None Data Returned None Opcode $28 Command Sequence FROM HOST RUN RUN ECHO The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6. SP HIGH BYTE OF INDEX REGISTER SP + 1 CONDITION CODE REGISTER SP + 2 ACCUMULATOR SP + 3 LOW BYTE OF INDEX REGISTER SP + 4 HIGH BYTE OF PROGRAM COUNTER SP + 5 LOW BYTE OF PROGRAM COUNTER SP + 6 SP + 7 Figure 15-17. Stack Pointer at Monitor Mode Entry MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 153 Development Support 15.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTA0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. See Figure 15-18. Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command. NOTE The MCU does not transmit a break character until after the host sends the eight security bytes. VDD 4096 + 32 BUSCLKX4 CYCLES COMMAND BYTE 8 BYTE 2 FROM HOST BYTE 1 RST PA0 3 BREAK 2 1 COMMAND ECHO 1 BYTE 8 ECHO Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times 3 = Wait 1 bit time before sending next byte 4 = Wait until clock is stable and monitor runs 1 BYTE 2 ECHO FROM MCU 3 1 BYTE 1 ECHO 4 Figure 15-18. Monitor Mode Entry Timing To determine whether the security code entered is correct, check to see if bit 6 of RAM address $80 is set. If it is, then the correct security code has been entered and FLASH can be accessed. If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). MC68HC908QYA/QTA Family Data Sheet, Rev. 3 154 Freescale Semiconductor Chapter 16 Electrical Specifications 16.1 Introduction This section contains electrical and timing specifications. 16.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 16.5 5-V DC Electrical Characteristics and 16.8 3-V DC Electrical Characteristics for guaranteed operating conditions. Characteristic(1) Symbol Value Unit Supply voltage VDD –0.3 to +6.0 V Input voltage VIN VSS –0.3 to VDD +0.3 V VTST VSS –0.3 to +9.1 V I ±15 mA IPTA0—IPTA5 ±25 mA Storage temperature TSTG –55 to +150 °C Maximum current out of VSS IMVSS 100 mA Maximum current into VDD IMVDD 100 mA Mode entry voltage, IRQ pin Maximum current per pin excluding PTA0–PTA5, VDD, and VSS Maximum current for pins PTA0–PTA5 1. Voltages references to VSS. NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD.) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 155 Electrical Specifications 16.3 Functional Operating Range Characteristic Operating temperature range Operating voltage range Symbol Value Unit Temperature Code TA (TL to TH) – 40 to +125 – 40 to +105 – 40 to +85 °C M V C VDD 2.7 to 5.5 V — 16.4 Thermal Characteristics Characteristic Symbol Value Unit Thermal resistance 8-pin PDIP 8-pin SOIC 16-pin PDIP 16-pin SOIC 16-pin TSSOP θJA I/O pin power dissipation PI/O User determined W Power dissipation(1) PD PD = (IDD x VDD) + PI/O = K/(TJ + 273°C) W Constant(2) K Average junction temperature Maximum junction temperature 105 142 76 90 133 °C/W PD x (TA + 273°C) + PD2 x θJA W/°C TJ TA + (PD x θJA) °C TJM 150 °C 1. Power dissipation is a function of temperature. 2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 156 Freescale Semiconductor 5-V DC Electrical Characteristics 16.5 5-V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.4 VDD –1.5 VDD –0.8 — — — — — — — — 50 — — — — — — 0.4 1.5 0.8 Unit Output high voltage ILoad = –2.0 mA, all I/O pins ILoad = –10.0 mA, all I/O pins ILoad = –15.0 mA, PTA0, PTA1, PTA3–PTA5 only VOH Maximum combined IOH (all I/O pins) IOHT Output low voltage ILoad = 1.6 mA, all I/O pins ILoad = 10.0 mA, all I/O pins ILoad = 15.0 mA, PTA0, PTA1, PTA3–PTA5 only VOL Maximum combined IOL (all I/O pins) IOHL — — 50 mA Input high voltage PTA0–PTA5, PTB0–PTB7 VIH 0.7 x VDD — VDD V Input low voltage PTA0–PTA5, PTB0–PTB7 VIL VSS — 0.3 x VDD V VHYS 0.06 x VDD — — V IINJ –2 — +2 mA IINJTOT –25 — +25 mA Ports Hi-Z leakage current IIL –1 ±0.1 +1 μA Capacitance Ports (as input)(3) CIN — — 8 pF POR rearm voltage VPOR 750 — — mV RPOR 0.035 — — V/ms Monitor mode entry voltage (3) VTST VDD + 2.5 — 9.1 V Pullup resistors(6) PTA0–PTA5, PTB0–PTB7 RPU 16 26 36 kΩ Pulldown resistors(7) PTA0–PTA5 RPD 16 26 36 kΩ Low-voltage inhibit reset, trip falling voltage VTRIPF 3.90 4.20 4.50 V Low-voltage inhibit reset, trip rising voltage VTRIPR 4.00 4.30 4.60 V Low-voltage inhibit reset/recover hysteresis VHYS — 100 — mV Input hysteresis(3) DC injection current, all ports(4) (4) Total dc current injection (sum of all I/O) POR rise time ramp rate(3)(5) V mA V 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25•C only. 3. Values are based on characterization results, not tested in production. 4. Guaranteed by design, not tested in production. 5. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum VDD is reached. 6. RPU is measured at VDD = 5.0 V. 7. RPD is measured at VDD = 5.0 V, Pulldown resistors only available when KBIx is enabled with KBIxPOL =1. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 157 Electrical Specifications 16.6 Typical 5-V Output Drive Characteristics 1.6 1.4 VDD-VOH (V) 1.2 1.0 5V PTA 0.8 5V PTB 0.6 0.4 0.2 0.0 0 -5 -10 -15 -20 -25 -30 IOH (mA) Figure 16-1. Typical 5-Volt Output High Voltage versus Output High Current (25°C) 1.6 1.4 1.2 VOL (V) 1.0 5V PTA 0.8 5V PTB 0.6 0.4 0.2 0.0 0 5 10 15 20 25 30 IOL (mA) Figure 16-2. Typical 5-Volt Output Low Voltage versus Output Low Current (25°C) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 158 Freescale Semiconductor 5-V Control Timing 16.7 5-V Control Timing Characteristic(1) Symbol Min Max Unit Internal operating frequency fOP (fBUS) — 8 MHz Internal clock period (1/fOP) tcyc 125 — ns RST input pulse width low(2) tRL 100 — ns IRQ interrupt pulse width low (edge-triggered)(2) tILIH 100 — ns — tcyc (2) tILIL IRQ interrupt pulse period (3) Note 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2. Values are based on characterization results, not tested in production. 3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc. tRL RST tILIL tILIH IRQ Figure 16-3. RST and IRQ Timing MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 159 Electrical Specifications 16.8 3-V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.3 VDD –1.0 VDD –0.8 — — — — — — — — 50 — — — — — — 0.3 1.0 0.8 Unit Output high voltage ILoad = –0.6 mA, all I/O pins ILoad = –4.0 mA, all I/O pins ILoad = –10.0 mA, PTA0, PTA1, PTA3–PTA5 only VOH Maximum combined IOH (all I/O pins) IOHT Output low voltage ILoad = 0.5 mA, all I/O pins ILoad = 6.0 mA, all I/O pins ILoad = 10.0 mA, PTA0, PTA1, PTA3–PTA5 only VOL Maximum combined IOL (all I/O pins) IOHL — — 50 mA Input high voltage PTA0–PTA5, PTB0–PTB7 VIH 0.7 x VDD — VDD V Input low voltage PTA0–PTA5, PTB0–PTB7 VIL VSS — 0.3 x VDD V VHYS 0.06 x VDD — — V IINJ –2 — +2 mA IINJTOT –25 — +25 mA Ports Hi-Z leakage current IIL –1 ±0.1 +1 μA Capacitance Ports (as input)(3) CIN — — 8 pF POR rearm voltage VPOR 750 — — mV POR rise time ramp rate(3)(5) RPOR 0.035 — — V/ms Monitor mode entry voltage (3) VTST VDD + 2.5 — VDD + 4.0 V Pullup resistors(6) PTA0–PTA5, PTB0–PTB7 RPU 16 26 36 kΩ Pulldown resistors(7) PTA0–PTA5 RPD 16 26 36 kΩ Low-voltage inhibit reset, trip falling voltage VTRIPF 2.40 2.55 2.70 V Low-voltage inhibit reset, trip rising voltage(6) VTRIPR 2.475 2.625 2.775 V Low-voltage inhibit reset/recover hysteresis VHYS — 75 — mV Input hysteresis(3) DC injection current, all ports(4) Total dc current injection (sum of all I/O)(4) V mA V 1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25•C only. 3. Values are based on characterization results, not tested in production. 4. Guaranteed by design, not tested in production. 5. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum VDD is reached. 6. RPU is measured at VDD = 3.0 V 7. RPD is measured at VDD = 3.0 V, Pulldown resistors only available when KBIx is enabled with KBIxPOL =1. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 160 Freescale Semiconductor Typical 3-V Output Drive Characteristics 16.9 Typical 3-V Output Drive Characteristics 1.2 1.0 VDD-VOH (V) 0.8 3V PTA 0.6 3V PTB 0.4 0.2 0.0 0 -5 -10 -15 -20 -25 IOH (mA) Figure 16-4. Typical 3-Volt Output High Voltage versus Output High Current (25°C) 1.2 1.0 0.8 VOL (V) 3V PTA 0.6 3V PTB 0.4 0.2 0.0 0 5 10 15 20 25 IOL (mA) Figure 16-5. Typical 3-Volt Output Low Voltage versus Output Low Current (25°C) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 161 Electrical Specifications 16.10 3-V Control Timing Characteristic(1) Symbol Min Max Unit Internal operating frequency fOP (fBus) — 4 MHz Internal clock period (1/fOP) tcyc 250 — ns tRL 200 — ns IRQ interrupt pulse width low (edge-triggered)(2) tILIH 200 — ns IRQ interrupt pulse period(2) tILIL Note(3) — tcyc RST input pulse width low (2) 1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Values are based on characterization results, not tested in production. 3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc. tRL RST tILIL tILIH IRQ Figure 16-6. RST and IRQ Timing MC68HC908QYA/QTA Family Data Sheet, Rev. 3 162 Freescale Semiconductor Oscillator Characteristics 16.11 Oscillator Characteristics Characteristic Symbol Min Typ Max — — — 4 8 12.8 — — — Unit (1) Internal oscillator frequency ICFS1:ICFS0 = 00 ICFS1:ICFS0 = 01 ICFS1:ICFS0 = 10 (not allowed if VDD <2.7V) fINTCLK MHz Trim accuracy(2)(3) ΔTRIM_ACC — ± 0.4 — % Deviation from trimmed Internal oscillator(3)(4) 4, 8, 12.8MHz, VDD ± 10%, 0 to 70°C 4, 8, 12.8MHz, VDD ± 10%, –40 to 125°C ΔINT_TRIM — — ±2 — — ±5 % External RC oscillator frequency, RCCLK (1)(3) fRCCLK 2 — 10 MHz fOSCXCLK dc dc — 32 16 MHz External clock reference frequencyy(1)(5)(6) VDD ≥ 4.5V VDD < 4.5V RC oscillator external resistor(3) VDD = 5 V VDD = 3 V REXT Crystal frequency, XTALCLK(1)(7)(8) ECFS1:ECFS0 = 00 ( VDD ≥ 4.5 V) ECFS1:ECFS0 = 00 ECFS1:ECFS0 = 01 ECFS1:ECFS0 = 10 fOSCXCLK ECFS1:ECFS0 = 00 (9) Feedback bias resistor Crystal load capacitance(10) Crystal capacitors(10) RB CL C1,C2 See Figure 16-7 See Figure 16-8 8 8 1 30 — — 32 16 8 100 MHz MHz MHz kHz — — — 1 20 (2 x CL) – 5pF — — — MΩ pF pF 20 10 0 5 18 (2 x CL) –10 pF — — — — — — kΩ kΩ kΩ MΩ pF pF 32 — kHz ECFS1:ECFS0 = 01(9) Crystal series damping resistor fOSCXCLK = 1 MHz fOSCXCLK = 4 MHz fOSCXCLK = 8 MHz Feedback bias resistor Crystal load capacitance(10) Crystal capacitors(10) RB CL C1,C2 — — — — — — AWU module internal RC oscillator frequency fINTRC — RS 1. Bus frequency, fOP, is oscillator frequency divided by 4. 2. Factory trimmed to provided 12.8MHz accuracy requirement (± 5%, @25•C) for forced monitor mode communication. User should trim in-circuit to obtain the most accurate internal oscillator frequency for the application. 3. Values are based on characterization results, not tested in production. 4. Deviation values assumes trimming in target application @25•C and midpoint of voltage range, for example 5.0 V for 5 V ± 10% operation. 5. No more than 10% duty cycle deviation from 50%. 6. When external oscillator clock is greater than 1MHz, ECFS1:ECFS0 must be 00 or 01 7. Use fundamental mode only, do not use overtone crystals or overtone ceramic resonators 8. Due to variations in electrical properties of external components such as, ESR and Load Capacitance, operation above 16 MHz is not guaranteed for all crystals or ceramic resonators. Operation above 16 MHz requires that a Negative Resistance Margin (NRM) characterization and component optimization be performed by the crystal or ceramic resonator vendor for every different type of crystal or ceramic resonator which will be used. This characterization and optimization must be performed at the extremes of voltage and temperature which will be applied to the microcontroller in the application. The NRM must meet or exceed 10x the maximum ESR of the crystal or ceramic resonator for acceptable performance. 9. Do not use damping resistor when ECFS1:ECFS0 = 00 or 10 10. Consult crystal vendor data sheet. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 163 Electrical Specifications 12 5V 25 oC RC FREQUENCY,RCCLK f (MHz) 10 8 6 4 2 0 0 10 20 30 40 50 60 Rext (k ohms) Figure 16-7. RC versus Frequency (5 Volts @ 25°C) 12 3V 25 oC RC FREQUENCY,RCCLK f (MHz) 10 8 6 4 2 0 0 10 20 30 40 50 60 Rext (k ohms) Figure 16-8. RC versus Frequency (3 Volts @ 25°C) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 164 Freescale Semiconductor Supply Current Characteristics 16.12 Supply Current Characteristics Voltage Bus Frequency (MHz) Symbol Typ(2) Max Unit Run mode VDD supply current(3) 5.0 3.0 3.2 3.2 RIDD 6.0 3.1 7.0 3.8 mA Wait mode VDD supply current(4) 5.0 3.0 3.2 3.2 WIDD 1.8 1.1 2.5 1.75 mA 0.5 — — 20 150 1.2 2.0 5.0 — — 0.36 — — 4 130 1.0 1.2 4.0 — — Characteristic(1) Stop mode VDD supply current(5) –40 to 85°C –40 to 105°C(6) –40 to 125°C 25°C with auto wake-up enabled Incremental current with LVI enabled at 25°C Stop mode VDD supply current(4) –40 to 85°C –40 to 105°C(6) –40 to 125°C 25°C with auto wake-up enabled Incremental current with LVI enabled at 25°C 5.0 μA SIDD 3.0 μA 1. VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurement at 25°C only. 3. Run (operating) IDD measured using trimmed internal oscillator, ADC off, all modules enabled. All pins configured as inputs and tied to 0.2 V from rail. 4. Wait IDD measured using trimmed internal oscillator, ADC off, all modules enabled. All pins configured as inputs and tied to 0.2 V from rail. 5. Stop IDD measured with all pins configured as inputs and tied to 0.2 V from rail. On the 8-pin versions, port B is configured as inputs with pullups enabled. 6. For automotive applications only. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 165 Electrical Specifications 12 11 10 9 Internal OSC (No A/D, ESCI, SPI) 8 Internal OSC all Modules enabled IDD 7 6 External Reference No A/D 5 External Reference All modules enabled 4 3 2 1 0 0 1 2 3 4 5 FREQUENCY 6 7 8 9 Figure 16-9. Typical 5-Volt Run Current versus Bus Frequency (25•C) 3 2.5 2 Internal OSC (No A/D, ESCI, SPI) Idd(mA) Internal OSC all Modules enabled External OSC (No A/D) 1.5 External OSC all Modules Enabled 1 0.5 0 0 1 2 3 4 5 BUS FREQUENCY (MHz) Figure 16-10. Typical 3-Volt Run Current versus Bus Frequency (25•C) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 166 Freescale Semiconductor ADC10 Characteristics 16.13 ADC10 Characteristics Characteristic Conditions Supply voltage Absolute Supply Current ADLPC = 1 ADLSMP = 1 ADCO = 1 VDD < 3.3 V (3.0 V Typ) Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 VDD < 3.3 V (3.0 V Typ) Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 VDD < 3.3 V (3.0 V Typ) Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 VDD < 3.3 V (3.0 V Typ) VDD < 5.5 V (5.0 V Typ) VDD < 5.5 V (5.0 V Typ) Symbol Min Typ(1) Max Unit VDD 2.7 — 5.5 V — 55 — — 75 — — 120 — — 175 — — 140 — — 180 — — 340 — — 440 615 0.40(3) — 2.00 0.40(3) — 1.00 19 19 21 39 39 41 16 16 18 36 36 38 4 4 4 24 24 24 tADCK cycles IDD (2) IDD (2) IDD(2) VDD < 5.5 V (5.0 V Typ) IDD VDD < 5.5 V (5.0 V Typ) fADCK Low power (ADLPC = 1) Conversion time (4) 10-bit Mode Conversion time (4) 8-bit Mode Short sample (ADLSMP = 0) Long sample (ADLSMP = 1) Short sample (ADLSMP = 0) Long sample (ADLSMP = 1) Short sample (ADLSMP = 0) Sample time Long sample (ADLSMP = 1) μA μA μA μA (2) High speed (ADLPC = 0) ADC internal clock tADC tADC tADS Comment MHz tADCK = 1/fADCK tADCK cycles tADCK cycles Input voltage VADIN VSS — VDD V Input capacitance CADIN — 7 10 pF Not tested Input impedance RADIN — 5 15 kΩ Not tested RAS — — 10 kΩ External to MCU 1.758 5 5.371 mV 7.031 20 21.48 VREFH/2N 0 ±1.5 ±2.5 LSB Includes quantization Analog source impedance 10-bit mode Ideal resolution (1 LSB) RES 8-bit mode 10-bit mode Total unadjusted error 8-bit mode ETUE 10-bit mode 0 ±0.7 ±1.0 0 ±0.5 — 0 ±0.3 — DNL Differential non-linearity 8-bit mode LSB Monotonicity and no-missing-codes guaranteed — Continued on next page MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 167 Electrical Specifications Characteristic Conditions Symbol 10-bit mode Integral non-linearity Typ(1) Max 0 ±0.5 — 0 ±0.3 — 0 ±0.5 — 0 ±0.3 — 0 ±0.5 — 0 ±0.3 — — — ±0.5 — — ±0.5 0 ±0.2 ±5 INL 8-bit mode 10-bit mode Zero-scale error 8-bit mode 10-bit mode Full-scale error 8-bit mode 10-bit mode Quantization error 8-bit mode 10-bit mode Input leakage error 8-bit mode Bandgap voltage input(6) Min EZS EFS EQ EIL VBG Unit Comment LSB 0 ±0.1 ±1.2 1.17 1.245 1.32 LSB VADIN = VSS LSB VADIN = VDD LSB 8-bit mode is not truncated LSB Pad leakage(5) * RAS V 1. Typical values assume VDD = 5.0 V, temperature = 25•C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. Incremental IDD added to MCU mode current. 3. Values are based on characterization results, not tested in production. 4. Reference the ADC module specification for more information on calculating conversion times. 5. Based on typical input pad leakage current. 6. LVI must be enabled, (LVIPWRD = 0, in CONFIG1). Voltage input to ADCH4:0 = $1A, an ADC conversion on this channel allows user to determine supply voltage. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 168 Freescale Semiconductor Timer Interface Module Characteristics 16.14 Timer Interface Module Characteristics Characteristic Symbol Min Max Unit tTH, tTL 2 — tcyc tTLTL Note(2) — tcyc tTCL, tTCH tcyc + 5 — ns Timer input capture pulse width(1) Timer input capture period Timer input clock pulse width(1) 1. Values are based on characterization results, not tested in production. 2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc. tTLTL tTH INPUT CAPTURE RISING EDGE tTLTL tTL INPUT CAPTURE FALLING EDGE tTLTL tTH tTL INPUT CAPTURE BOTH EDGES tTCH TCLK tTCL Figure 16-11. Timer Input Timing MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 169 Electrical Specifications 16.15 Memory Characteristics Characteristic Symbol Min Typ Max Unit VRDR 1.3 — — V — 1 — — MHz VPGM/ERASE 2.7 — 5.5 V fRead(2) 0 — 8M Hz FLASH page erase time <1 K cycles >1 K cycles tErase 0.9 3.6 1 4 1.1 5.5 ms FLASH mass erase time tMErase 4 — — ms FLASH PGM/ERASE to HVEN setup time tNVS 10 — — μs FLASH high-voltage hold time tNVH 5 — — μs FLASH high-voltage hold time (mass erase) tNVHL 100 — — μs FLASH program hold time tPGS 5 — — μs FLASH program time tPROG 30 — 40 μs FLASH return to read time tRCV(3) 1 — — μs FLASH cumulative program hv period tHV(4) — — 4 ms FLASH endurance(5) — 10 k 100 k — Cycles FLASH data retention time(6) — 15 100 — Years RAM data retention voltage (1) FLASH program bus clock frequency FLASH PGM/ERASE supply voltage (VDD) FLASH read bus clock frequency 1. Values are based on characterization results, not tested in production. 2. fRead is defined as the frequency range for which the FLASH memory can be read. 3. tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to 0. 4. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tNVS + tNVH + tPGS + (tPROG x 32) ≤ tHV maximum. 5. Typical endurance was evaluated for this product family. For additional information on how Freescale Semiconductor defines Typical Endurance, please refer to Engineering Bulletin EB619. 6. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25•C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines Typical Data Retention, please refer to Engineering Bulletin EB618. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 170 Freescale Semiconductor Chapter 17 Ordering Information and Mechanical Specifications 17.1 Introduction This section contains order numbers for the MC68HC908QY1A, MC68HC908QY2A, MC68HC908QY4A, MC68HC908QT1A, MC68HC908QT2A, and MC69HC908QT4A. Dimensions are given for: • 8-pin plastic dual in-line package (PDIP) • 8-pin small outline integrated circuit (SOIC) package • 8-pin dual flat no lead (DFN) package • 16-pin PDIP • 16-pin SOIC • 16-pin thin shrink small outline package (TSSOP) 17.2 Ordering Information Table 17-1. Consumer and Industrial Device Numbering System Device Number ADC FLASH Memory Packages(1) MC908QT1A — 1536 bytes MC908QT2A Yes 1536 bytes MC908QT4A Yes 4096 bytes 8-pins PDIP, SOIC, and DFN MC908QY1A — 1536 bytes MC908QY2A Yes 1536 bytes MC908QY4A Yes 4096 bytes 16-pins PDIP, SOIC, and TSSOP 1. See Table 17-3 for package information. Table 17-2. Automotive Device Numbering System Device Number ADC FLASH Memory Packages(1) S908QY2A Yes 1536 bytes S908QY4A Yes 4096 bytes 16-pins TSSOP and SOIC 1. See Table 17-3 for package information. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 171 Ordering Information and Mechanical Specifications 17.3 Orderable Part Numbering System 17.3.1 Consumer and Industrial Orderable Part Numbering System MC 9 08 QY2A C XX E STATUS (MC = CONSUMER AND INDUSTRIAL FULLY QUALIFIED) Pb FREE INDICATOR PACKAGE DESIGNATOR FQ = 8-PIN DFN DW = 8-PIN SOIC P = 8-PIN DIP DT = 16-PIN TSSOP DW = 16 PIN SOIC P = 16-PIN DIP MEMORY (9 = FLASH BASED) CORE FAMILY TEMPERATURE RANGE C = –40°C to +85°C M = –40°C to +125°C 17.3.2 Automotive Orderable Part Number System S 9 08 QY2A D 1 C XX E STATUS (S = AUTOMOTIVE FULLY QUALIFIED) RoHS COMPLIANCE DESIGNATOR (E = YES) PACKAGE DESIGNATOR DT = 16-PIN TSSOP DW = 16-PIN SOIC MEMORY (9 = FLASH BASED) CORE TEMPERATURE RANGE C = –40°C to +85°C V = –40°C to +105°C M = –40°C to +125°C FAMILY MASK REVISION WAFER FAB 17.4 Mechanical Drawings The following pages contain mechanical specifications for MC68HC908QY4/QTA series package options. See Table 17-3 for the document numbers that correspond to each package type. Table 17-3. Package Information Pin Count Type Designator Document No. 8 PDIP P 98ASB42420B 8 SOIC DW 98ASH70107A 8 DFN FQ 98ARL10557D 16 PDIP P 98ASB42431B 16 SOIC DW 98ASB42567B 16 TSSOP DT 98ASH70247A MC68HC908QYA/QTA Family Data Sheet, Rev. 3 172 Freescale Semiconductor Mechanical Drawings Case 626 page 1 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 173 Ordering Information and Mechanical Specifications Case 626 page 2 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 174 Freescale Semiconductor Mechanical Drawings Case 626 page 3 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 175 Ordering Information and Mechanical Specifications Case 968 page 1 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 176 Freescale Semiconductor Mechanical Drawings Case 968 page 2 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 177 Ordering Information and Mechanical Specifications Case 968 page 3 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 178 Freescale Semiconductor Mechanical Drawings Case 1452 page 1 of 4 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 179 Ordering Information and Mechanical Specifications Case 1452 page 2 of 4 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 180 Freescale Semiconductor Mechanical Drawings Case 1452 page 3 of 4 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 181 Ordering Information and Mechanical Specifications Case 1452 page 4 of 4 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 182 Freescale Semiconductor Mechanical Drawings Case 648 page 1 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 183 Ordering Information and Mechanical Specifications Case 648 page 2 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 184 Freescale Semiconductor Mechanical Drawings Case 648 page 3 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 185 Ordering Information and Mechanical Specifications Case 751G page 1 of 2 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 186 Freescale Semiconductor Mechanical Drawings Case 751G page 2 of 2 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 187 Ordering Information and Mechanical Specifications Case 948F page 1 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 188 Freescale Semiconductor Mechanical Drawings Case 948F page 2 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 189 Ordering Information and Mechanical Specifications Case 948F page 3 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 190 Freescale Semiconductor Appendix A 908QTA/QYxA Conversion Guidelines A.1 Introduction This engineering bulletin describes the 908QTA/QYxA. The 908QTA/QYxA is an enhanced device intended to replace the 908QT/QYx series of devices (referred to as the QY Classic in this document). Customer requests have led to the advanced design of the QYxA that has added adaptability, new features, and contains lead-free packaging. This document: • Provides information needed to convert from QY Classic to the enhanced QYxA • Highlights the benefits of making this change Sections: • A.2 Benefits of the Enhanced QYxA • A.3 Conversion Considerations • A.4 Code Changes Checklist • A.5 Development Tools • A.6 Differences in Packaging A.2 Benefits of the Enhanced QYxA The QYxA contains new and enhanced modules that add more flexibility and new features to the QY Classic. These benefits can improve the operation of an application or lead to new features for an application. For more information regarding these features refer to the QYxA data sheet (Freescale document order number MC68HC908QYxA). A.2.1 New Analog-to-Digital Converter Module (ADC) The QYxA contains a 10-bit ADC which replaces the 8-bit ADC on the QY Classic. This module allows both 10-bit and 8-bit conversion modes. The increased precision for ADC readings can be very useful in many applications. Features of the ADC new 10-bit module include: • There are two new ADC channels that have been placed on PTB0 and PTB1 allowing added flexibility especially when debugging in Monitor Mode. – A limitation of QY Classic debugging is that access to the ADC channels is limited because many of the QY Classic pins are multiplexed. Having extra ADC channels on the PTB pins resolves this limitation. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 191 • The ADC that is on the QYxA can operate while the MCU is in stop mode allowing lower power operation. This also adds a lower noise environment for precise ADC results. • Enabling an ADC channel no longer overrides the digital I/O function of the associated pin. To prevent the digital I/O from interfering with the ADC read of the pin, the data direction bit associated with the port pin must be set as input. • Finally, the new ADC can be configured to select two different reference clock sources: – The internal bus x 4 – An internal asynchronous source The internal asynchronous clock source allows the ADC to be clocked for operation in stop mode. A.2.1.1 Registers Affected Bit 7 Read: COCO Write: Reset: 0 6 5 4 3 2 1 Bit 0 AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 0 1 1 1 1 1 = Unimplemented Figure A-1. ADC10 Status and Control Register (ADSCR) The ADCHx bits can be used to select additional ADC channels or bandgap measurement. Read: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 AD9 AD8 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure A-2. ADC10 Data Register High (ADRH), 10-Bit Mode 10-bit ADC uses the new ADRH register for the upper 2 bits. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ACLKEN 0 0 0 0 0 0 0 0 Figure A-3. ADC10 Clock Register (ADCLK) A long sample time option has been added to conserve power at the expense of longer conversion times. This option is selected using the new ADLSMP bit in the ADCLK register. (The bit location was previously reserved.) The ADC will now run in stop mode if the ACLKEN bit is set to enable the asynchronous clock inside the ADC module. Utilizing stop mode for an ADC conversion gives the quietest operating mode to get extremely accurate ADC readings. (This bit location now used by ACLKEN was reserved — it always read as a 0 and writes to that location had no affect.) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 192 Freescale Semiconductor A.2.2 Enhanced Oscillator Module (OSC) The QYxA contains a much enhanced oscillator module that allows more options than the QYx Classic. • The ICFS bits in the Oscillator Status and Control Register (OSCSC) allow the Internal Oscillator to be configured for 1-, 2-, or 3.2-MHz operation. Also, the ECFS bits in the same register allow a low, medium, or high crystal frequency range to be selected for the source of the system clock. With this option you can choose to use a 32-kHz (low range) or a 16-MHz (high range) crystal. • Another improvement to the Oscillator Module design is that you can switch between internal oscillator and external oscillator options at any time. For example, if you wanted the low power advantage of running from a 32-kHz crystal but still needed some processing power to perform math calculations you could switch back and forth between internal and external clock. The same is true for switching between 1-, 2-, and 3.2-MHz internal oscillator options. A.2.2.1 Registers Affected Bit 7 Read: Write: 6 OSCOPT1 OSCOPT0 Reset: 0 0 5 4 3 2 1 ICFS1 ICFS0 ECFS1 ECFS0 ECGON 1 0 0 0 0 Bit 0 ECGST 0 = Unimplemented Figure A-4. Oscillator Status and Control Register (OSCSC) The OSCOPT bits are no longer in the CONFIG2 register and now reside in the OSCSC register. Also, the ICFSx and ECFSx bits now reside in this register. The IFS bits are used to select different Internal Oscillator speeds. The ECFS bits are used to select the range of crystal that should be used to provide the reference clock. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 193 A.2.3 Improved Auto Wakeup Module (AWU) The QYxA contains an AWU that has improved accuracy across voltage and temperature for typical testing. • A new feature provides ability to run the AWU from an alternate source (internal oscillator or external crystal). This is an advantage for an application that needs more accurate AWU operation. • On the QYxA AWU approximate time out will be 16 ms for short time out and 512 ms for long time out when running from the internal 32-kHz RC source. • Finally, at lower voltages typical measurements have shown lower power consumption by the QYxA AWU. A.2.3.1 Registers Affected Bit 7 6 5 4 3 2 1 Bit 0 IRQPUD IRQEN R R R R OSCENINSTOP RSTEN Reset: 0 0 0 0 0 0 0 U POR: 0 0 0 0 0 0 0 0 R = Reserved Read: Write: U = Unaffected Figure A-5. Configuration Register 2 (CONFIG2) Setting the OSCENINSTOP bit forces the AWU to use BUSCLKX2 as the source to this timeout. A.2.4 New Power-on Reset Module (POR) The QYxA POR re-arm voltage will have a minimum specification of 0.7 V while the QYx Classic POR re-arm was 0.1 V. The higher POR re-arm voltage provides added protection against brown out conditions. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 194 Freescale Semiconductor A.2.5 Keyboard Interface Module (KBI) Functionality The KBI module for the QYxA has the added capability of: • Triggering a KBI interrupt on the rising or falling edge of an input while the QYx Classic has the capability of triggering on falling edges only. – A new register (Keyboard Interrupt Polarity Register) determines the polarity of KBI and the default state of this register configures the QYxA for triggering on falling edges to be compatible with QYx Classic. – The QYxA now has pull down resistors for the input pins that are configured for rising edge operation. A.2.5.1 Registers Affected Read: Bit 7 6 0 0 0 0 Write: Reset: 5 4 3 2 1 Bit 0 KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0 0 0 0 0 0 0 = Unimplemented Figure A-6. Keyboard Interrupt Polarity Register (KBIPR) The KBIPR allows the selection of polarity, if any of these bits are set the corresponding interrupt pin will be configured for rising edge and a pulldown resistor will be added to the pin. A.2.6 On-Chip Routine Enhancements Enhancements have been made to the on-chip routines that are used for FLASH as EEPROM. Refer to AN2346 for information about using FLASH as EEPROM. • A new mass erase routine requires a valid FLASH address loaded into the H:X register to perform an erase. This added step helps ensure that the erase routine is not inadvertently used to cause an unwanted erase. Also, on-chip FLASH programming routine ERARNGE variable CTRLBYT requires $00 for page erase and $40 for mass erase. The entire control byte must be set for proper operation. • Separate routines will allow easy access to perform software SCI (Serial Communications Interface). For information on how to use on-chip FLASH programming routines refer to AN2635. • Finally, there is improved security and robustness. The latest Monitor ROM implements updated security checks to make the program memory more secure. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 195 A.3 Conversion Considerations Enhancements lead to slight differences in operation from QYx Classic to the QYxA. There are a few points that should be considered in the conversion process. • The Monitor ROM changed from 2 K to 1 K in size. This has led to the limitation that programming across page boundaries is no longer supported by the on-chip program range routine. Also, in very rare cases, ROM code improvements could cause customers to have to modify a few instructions in their application code. For example, when performing a mass erase, a valid address is required instead of an unspecified address. • The QYxA contains new modules like the 10-bit ADC and OSC. In rare cases, new modules could cause customers to have to modify a few instructions in their application code. For example, if ADC code was written so that entire registers are configured without respect to reserve bits, then the ADC code will need to be revised to work correctly on the QYxA. • The Reference Clock for ADC conversions has changed from the bus clock to the system clock (Bus Clock * 4). A change to the divide register may be necessary to set the reference clock to a specified value. A.4 Code Changes Checklist Below is a checklist that should be reviewed in the conversion process. This checklist will point out all the issues that should be addressed as your code is ported. 1. Does the original software use Auxiliary ROM routines (for example, Getbyte, Putbyte, delnus)? If so, the software will have to be changed to handle new Auxiliary ROM routines, addresses of these routines have changed in QYxA. Code will have to be changed to use the proper addresses. 2. Does the software use FLASH as EEPROM? If so, there are several possible issues for the page erase and mass erase routine. Software will have to be checked to ensure that proper procedure is used and the CTRLBYT is set with a MOV instruction not a BSET. Also, on-chip FLASH programming routines can no longer program across row boundaries 3. Does the code use the auto wake up timer and does the application depend on the typical auto wake time out? Since the timeout has been improved for QYxA it may be necessary to modify software to compensate for the change in timeout. 4. Bits changed in the OSCSC, CONFIG2, and ADC registers? Any code that writes to these registers should be reviewed to ensure that the writes are not affecting the changed bits 5. Does the code use external OSC, crystal, or RC? If so, since the OSCOPT bits have changed locations code will have to be updated to update these bits in their proper locations. 6. Does the code use the ADC? If so, because on QYxA the ADC clock is driven from 4XBUSCLK instead of BUSCLK changes to the ADC clock divider bits may be needed to maintain proper operation. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 196 Freescale Semiconductor A.5 Development Tools Development hardware used for QYx can be used with QYxA. The QYxA is pin-for-pin compatible with QY Classic and can be placed on existing QY4 Classic hardware. Existing Cyclone/Multilink tools and any programming or evaluation boards will work for the QYxA. Emulation can be done using the EML08QCBLTYE. A.6 Differences in Packaging All QYxA packages will be lead free. All packages that the QYx classic supported will be supported by the QYxA. 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