MDT10C23 XTAL－Standard crystal oscillator 1. General Description HFXT－High frequency crystal oscillator This ROM-Based 8-bit micro-controller uses a fully u 4 oscillator start-up time can be selected by static CMOS design technology to achieve high programming option: speed, small size, low power and high noise 150 µs, 20 ms, 40 ms, 80 ms u immunity. Timer(WDT) can be operated freely On chip memory includes 2K words ROM and80 u bytes static RAM. On-chip RC oscillator based Watchdog 12 I/O(for 18 pins package),14 I/O(for 20 pins Four comparator inputs with external Vref (not for 18 package),16 I/O(for 22/24 pins package) pins pin package) are also provided. with their own independent direction control 3. Applications 2. Features u Fully CMOS static design The application areas of this MDT10C23 range from u 8-bit data bus appliance motor control and high speed automotive u On chip ROM size : 2 K words to low power remote transmitters/receivers, pointing u Internal RAM size : 80 bytes devices, and telecommunications processors, such (72 general purpose registers, 8 special as Remote controller, small instruments, chargers, registers) toy, automobile and PC peripheral … etc u 36 single word instructions u 14-bit instructions u 2-level stacks u Operating voltage : 2.3V ~ 5.5 V u Operating frequency : 0 ~ 20 MHz u The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction u Addressing modes include direct, indirect and relative addressing modes u Built-in Power-on Reset u 4 Channel comparator u Power edge-detector Reset u Sleep Mode for power saving u 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler u 4 types of oscillator can be selected by programming option: RC－Low cost RC oscillator LFXT－Low frequency crystal oscillator This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 1 2005/6 Ver. 1.2 MDT10C23 4. Pin Assignment ※ A1：20PINS, A2：22PINS, A3：24PINS, A5 :18 PINS ※ P－PDIP,S－SOP, K－SKINNY A1P,A1S A3S PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 NC PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 A2K PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 A5P,A5S PA2CIC2 1 PA3/CIC3 2 RTCC 3 /MCLR 4 Vss 5 PB0 6 PB1 7 PB2 8 PB3 9 18 17 16 15 14 13 12 11 10 PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 2 2005/6 Ver. 1.2 MDT10C23 5. Block Diagram Stack Two Levels Port PB0 ~P B7 8 bits RAM 72×8 ROM 2K×14 (MDT10C23) Port B 11 bits 14 bits 11 bits Program Counters Instruction Register Special Register D0~D 7 OS OS C1 C2 MC LR Oscillator Circuit Port A Instruction Decoder Control Circuit Port PA 0~P A7 (22,24 pins) PA0~P A5 (20 pins) PA0~P A3 (18 pins) 8 bits CMR0~C MR5 Data 8-bit Power on Reset Power Down Reset Working Register Status Register ALU 8-bit Timer/Counter Comparat or mode Register WDT/OST Timer Prescale RTCC This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 3 2005/6 Ver. 1.2 MDT10C23 6. Pin Function Description Pin Name I/O PA0~PA7 I/O Function Description PA0~PA3 : TTL input level or comparator input PA4 : TTL input level or comparator VREF input PA5~PA7 : TTL input level PB0~PB7 I/O Port B, TTL input level RTCC I Real Time Clock/Counter, Schmitt Trigger input levels /MCLR I Master Clear, Schmitt Trigger input levels OSC1 I Oscillator Input OSC2 O Oscillator Output Vdd Power supply Vss Ground NC Unused ,do not connect 7. Memory Map (A) Register Map Address Description 00 Indirect Addressing Register 01 RTCC 02 PC 03 STATUS 04 MSR 05 Port A 06 Port B 07 Control register for comparator 08~0F Internal RAM, General Purpose Register 10~1F Internal RAM, Memory bank 0 30~3F Internal RAM, Memory bank 1 50~5F Internal RAM, Memory bank 2 70~7F Internal RAM, memory bank 3 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 4 2005/6 Ver. 1.2 MDT10C23 (1)IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (2) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTWI, RET --- from STACK A10 A9 A8 A7~A0 Write PC, JUMP, CALL --- from STATUS B6 b5 LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTWI, RET --- from STACK (4) STATUS (Status register) : R3 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 PF Power loss Flag bit 4 TF Time overflow Flag bit page ROM Page select bit : 6-5 00 : 000H --- 1FFH 01 : 200H --- 3FFH 10 : 400H --- 5FFH 11 : 600H --- 7FFH 7 —— General purpose bit This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 5 2005/6 Ver. 1.2 MDT10C23 (5) MSR (Memory Select Register) : R4 Memory Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F b7 b6 b5 b4 b3 b2 b1 b0 Read only “1” Indirect Addressing Mode (6) PORT A : R5 PA7~PA0, I/O Register for 22, 24 pins PA5~PA0, I/O Register for 20 pins PA3~PA0, I/O Register for 18 pins (7) PORT B : R6 PB7~PB0, I/O Register (8) CMR(Comparator Mode Register) : R7 Bit 0 Function 0: Define PA0 as TTL input 1: Define PA0 as comparator input 1 0: Define PA1 as TTL input 1: Define PA1 as comparator input 2 0: Define PA2 as TTL input 1: Define PA2 as comparator input 3 0: Define PA3 as TTL input 1: Define PA3 as comparator input 5:4 Reference Voltage select 00: 1/4 VDD 01: 1/2 VDD 10: 3/4 VDD 11: VREF (External pin and PA4 must be set to input) 7:6 Register bits This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 6 2005/6 Ver. 1.2 MDT10C23 (9) TMR (Time Mode Register) Bit Symbol Function Prescaler Value RTCC rate WDT rate 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1 : 16 1:8 1 0 0 1 : 32 1 : 16 1 0 1 1 : 64 1 : 32 1 1 0 1 : 128 1 : 64 0 0 2—0 PS2—0 3 PSC 4 TCE 5 TCS 1 1 1 1 : 256 1 : 128 Prescaler assignment bit : 0 — RTCC 1 — Watchdog Timer RTCC signal Edge : 0 — Increment on low-to-high transition on RTCC pin 1 — Increment on high-to-low transition on RTCC pin RTCC signal set : 0 — Internal instruction cycle clock 1 — Transition on RTCC pin (10) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is “write-only” ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode. (11) ROM Option by writer programming : Oscillator Type Oscillator Start-up Time Oscillator 150 µs LFXT Oscillator 20 ms XTAL Oscillator 40 ms HFXT Oscillator 80 ms RC Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time Power Edge Detect PED Disable PED Enable This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 7 2005/6 Ver. 1.2 MDT10C23 (B) Program Memory Address Description 000- 7FF Program memory The starting address of the power on, external reset or WDT 7FF 8. Reset Condition for all Registers Register Address Power-On Reset /MCLR Reset WDT Reset CPIO A －－ 1111 1111 1111 1111 1111 1111 CPIO B －－ 1111 1111 1111 1111 1111 1111 TMR －－ --11 1111 --11 1111 --11 1111 IAR 00h － － － RTCC 01h xxxx xxxx uuuu uuuu uuuu uuuu PC 02h 1111 1111 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000# #uuu 000# #uuu MSR 04h 100x xxxx 100u uuuu 1uuu uuuu PORT A 05h xxxx xxxx uuuuuuuu uuuu uuuu PORT B 06h xxxx xxxx uuuu uuuu uuuu uuuu CMR 07h 0000 0000 uuuu uuuu uuuu uuuu Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0” #＝value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 /MCLR reset (not during SLEEP) U u /MCLR reset during SLEEP 1 0 WDT reset (not during SLEEP) 0 1 WDT reset during SLEEP 0 0 9. Instruction Set Instruction Code Mnemonic Operands Function Operating Status 010000 00000000 NOP No operation None 010000 00000001 CLRWT Clear Watchdog timer 0→WT TF, PF 010000 00000010 SLEEP Sleep mode 0→WT, stop OSC TF, PF This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 8 2005/6 Ver. 1.2 MDT10C23 Instruction Code Mnemonic Operands Function Operating Status 010000 00000011 TMODE Load W to TMODE register W→TMODE None 010000 00000100 RET Return Stack→PC None 010000 00000rrr CPIO R Control I/O port register W→CPIO r None 010001 1rrrrrrr STWR R Store W to register W→R None 011000 trrrrrrr LDR R, t Load register R→t Z 111010 iiiiiiii LDWI I Load immediate to W I→W None 010111 trrrrrrr SWAPR R, t Swap halves register [R(0~3)↔R(4~7)]→t None 011001 trrrrrrr INCR R, t Increment register R + 1→t Z 011010 trrrrrrr INCRSZ R, t Increment register, skip if zero R + 1→t None 011011 trrrrrrr ADDWR R, t Add W and register W + R→t C, HC, Z 011100 trrrrrrr SUBWR R, t Subtract W from register R ﹣W→t (R+/W+1→ t) C, HC, Z 011101 trrrrrrr DECR R, t Decrement register R ﹣1→t Z 011110 trrrrrrr DECRSZ R, t Decrement register, skip if zero R ﹣1→t None 010010 trrrrrrr ANDWR R, t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI i AND W and immediate i ∩ W→W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii IORWI i Inclu. OR W and immediate i ∪ W→W Z 010100 trrrrrrr XORWR R, t Exclu. OR W and register R ⊕ W→t Z 110110 iiiiiiii XORWI i Exclu. OR W and immediate i ⊕ W→W Z 011111 trrrrrrr COMR R, t Complement register /R→t Z 010110 trrrrrrr RRR R, t Rotate right register R(n) →R(n-1), C→ R(7), R(0)→C C 010101 trrrrrrr RLR R, t Rotate left register R(n)→r(n+1), C C→R(0), R(7)→C 010000 1xxxxxxx CLRW Clear working register 0→W Z 010001 0rrrrrrr CLRR Clear register 0→R Z 0000bb brrrrrrr BCR R, b Bit clear 0→R(b) None 0010bb brrrrrrr BSR R, b Bit set 1→R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 100nnn nnnnnnnn LCALL n Long CALL subroutine n→PC, PC+1→Stack None 101nnn nnnnnnnn LJUMP n Long JUMP to address n→PC None 110000 nnnnnnnn CALL n Call subroutine n→PC, PC+1→Stack None 110001 iiiiiiii RTWI i Return, place immediate to W Stack→PC,i→W None 11001n nnnnnnnn JUMP JUMP to address n→PC None R n This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 9 2005/6 Ver. 1.2 MDT10C23 Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘⊕’ Logic AND ‘∩’ b t R C HC Z / x i n : : 0 1 : : : : : : : : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don’t care Immediate data ( 8 bits ) Immediate address 10. Electrical Characteristics (Operating temperature at 25℃). Sym Description Condition Vdd Operating voltage VIL Min Typ Max Unit 2.3 6.3 V Input Low Voltage PA, PB Vdd=5V -0.6 1.0 V RTCC, /MCLR Vdd=5V -0.6 1.0 V PA, PB Vdd=5V 2.0 Vdd V RTCC, /MCLR Vdd=5V 3.2 Vdd V IIL Input leakage current Vdd=5V +/-1 µA VOL Output Low Voltage VIH Input high Voltage PA, PB Vdd=5V, IOL=20mA 0.4 V Vdd=5V, IOL=5mA 0.1 V Vdd=5V, IOH= -20mA 3.8 V Vdd=5V, IOH= -5mA 4.5 V 0.1 VOH Output High Voltage PA, PB µA Islp Sleep current (WDT disable) Vdd＝2.3 ~ 6.3 V Islp Sleep current (WDT enable) Vdd＝2.3 V 1 µA Vdd＝3.0 V 15 µA Vdd＝4.0 V 5 µA Vdd＝5.0 V 9 µA Vdd＝6.3 V 20 µA Vpr Power Edge-detector Reset Voltage Twdt The basic WDT time-out cycle time 1.1 1.0 1.3 V Vdd＝2.3 V 32.8 mS Vdd＝3.0 V 27.2 mS Vdd＝4.0 V 22.8 mS Vdd＝5.0 V 20.3 mS Vdd＝6.3 V 17.8 mS This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 10 2005/6 Ver. 1.2 MDT10C23 Sym Description TFLT /MCLR filter Icc Comparator Supply current (one Condition Min Typ Max Unit Vdd＝5.0 V 600 nS Vdd=5.0v 15 µA comparator) Vref Input reference voltage --- Vdd=2.5v ~6.3v Comparator Response time Vdd=5.0v , V- = Vref V-=Vdd/4, V+=V- ± 0.2v V+ = (PA0~PA3) Vdd-0.8v V 8 µS V-=Vdd/2, V+=V- ± 0.2v 8 µS V-=Vdd3/4, V+=V- ± 0.2v 8 µS V-=VDD-0.8,V+=V± 0.2v 8 µS 11. Operating Current Temperature＝25 ℃, the typical value as followings : 11.1 OSC Type＝RC ; WDT－Enable; Comparator － Disable @ Vdd＝5.0 V Cext. (F) 3P 20P 300P Rext. (Ohm) Frequency (Hz) Current (A) 4.7 K 11.4M 1.3 mA 10.0 K 6.44 M 750 µA 47.0 K 1.53 M 210 µA 100.0 K 732 K 120 µA 300.0 K 250.8 K 60 µA 470.0 K 155.6 K 50 µA 4.7 K 5.6 M 660 µA 10.0 K 2.89 M 360 µA 47.0 K 654.4 K 110 µA 100.0 K 306.8 K 70 µA 300.0 K 104.4 K 45 µA 470.0 K 65.2 K 40 µA 4.7 K 748K 200 µA 10.0 K 367K 155 µA 47.0 K 80K 115 µA 100.0 K 38K 110 µA 300.0 K 12.8K 105 µA 470.0 K 8K 100 µA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 11 2005/6 Ver. 1.2 MDT10C23 11.2 OSC Type＝LF (C=20 p); WDT－Disable ; Comparator － Disable Voltage/Frequency 32 K 455 K 2.3 V 3 µA 3.0 V 4 µA 40 µA 4.0 V 8 µA 5.0 V 6.3 V 1M Sleep ＜0.1 µA X 75 µA ＜0.1 µA 65 µA 100 µA ＜0.1 µA 12 µA 90 µA 150 µA ＜0.1 µA 25 µA 120 µA 210 µA ＜0.1 µA @3.5v 11.3 OSC Type＝XT (C=10 p); WDT－Enable ; Comparator － Disable Voltage/Frequency 1M 4M 10 M Sleep 2.1 V 60 µA 180 µA 450 µA ＜0.1 µA 3.0 V 100 µA 280 µA 700 µA 1.5 µA 4.0 V 200 µA 450 µA 1.0 mA 4.0 µA 5.0 V 400 µA 650 µA 1.2 mA 8.0 µA 6.3 V 600 µA 900 µA 1.8 mA 18.0 µA 11.4 OSC Type＝HF (C=10 p); WDT－Enable ; Comparator － Disable Voltage/Frequency 4M 10 M 165 µA 2.1 V 3.0 V 320 µA 4.0 V 550 µA 5.0 V 700 µA 6.3 V 1.0 mA 400 µA 700 µA 20 M @2.3v 850 µA Sleep ＜0.1 µA 1.2 mA 1.5 µA 1.0mA 1.9 mA 4 µA 1.4 mA 2.6 mA 8 µA 3.5 mA 18 µA 2.0 mA 11.5 Power Edge-detector Reset Voltage (Not in Sleep Mode), @ Vdd＝5.0 V Vpr ≦1.6~1.7 V Vpr ﹕Vdd (Power Supply) This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 12 2005/6 Ver. 1.2 MDT10C23 12. Port A Equivalent Circuit PA0-PA3 D I/O Control Q I/O Control Latch C K Q B Port I/O Pin D Data O/P Latch Write G QB Input Resistor Data Bus 0 TTL input level D QB Data I/P Latch Rea d S G + 1 VREF comparator level Compartor Control PA4 D I/O Control C K Q I/O Control Latch Q B Port I/O Pin D Data O/P Latch Write G Q B Input Resistor Data Bus Rea d comparator enable D QB Data I/P Latch TTL Input Level G 3 2 Vref 1 S0 S1 0 CMR_4 CMR_5 3/4 VDD 1/2 VDD 1/4 VDD This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 13 2005/6 Ver. 1.2 MDT10C23 PA5-PA7 D I/O Control C K Q I/O Control Latch Q B Port I/O Pin D Data O/P Latch Write Q B G Data Bus D QB Rea d G Input Resistor Data I/P Latch TTL Input Level Port B Equivalent Circuit D I/O Control C K Q I/O Control Latch Q B Port I/O Pin D Data O/P Latch Write G Data Bus Q B D QB Rea d Data I/P Latch Input Resistor TTL Input Level G This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 14 2005/6 Ver. 1.2 MDT10C23 13. MCLRB and RTCC Input Equivalent Circuit MOS Pull Hi (Long Channel) R≒1K MCLRB Schmitt Trigger Information Sheet Pull Hi/Lo Selection This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 15 2005/6 Ver. 1.2 MDT10C23 MOS Pull Hi (Long Channel) R≒1K RTCC Schmitt Trigger MOS Pull Low (Long Channel) Information Sheet Pull Hi/Lo Selection This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 16 2005/6 Ver. 1.2 MDT10C23 13. Capacitor Selection For Crystal Oscillator (a) With built-in Oscillation Capacitors ( Default for HF,XT,LF ) @ Vdd＝2.3V~5.5 V , C1=C2=10P~15P This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 17 2005/6 Ver. 1.2 MDT10C23 (b) Without built-in Oscillation Capacitors @ Vdd＝3.0 V~ 5.0 V Osc. Type HF XT LF Resonator Freq. C1 C2 20 MHz 5 pF ~10 pF 10 pF~30 pF 10 MHz 10 pF ~50 pF 20 pF ~100 pF 4 MHz 10 pF ~50 pF 20 pF ~100 pF 10 MHz 10 pF ~30 pF 10 pF ~50 pF 4 MHz 10 pF ~50 pF 20 pF ~100 pF 1 MHz 10 pF ~30 pF 20 pF ~50 pF 1 MHz 3 pF ~5 pF 3 pF ~5 pF 455 K 10 pF ~30 pF 20 pF ~50 pF 32 K 10 pF ~20 pF 15 pF ~30 pF This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 18 2005/6 Ver. 1.2 MDT10C23 To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor range are recommended, but the higher capacitance will increase the start-up time. There do not have built-in Oscillation Capacitors for RC type. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 19 2005/6 Ver. 1.2