MDTIC MDT10P73BA 8-bit micro-controller Datasheet

MDT10P73(BA)
1. General Description
-CCP1, CCP2, SCM, USAR, USAT
A/D converter module:
This EPROM-Based 8-bit micro-controller uses a fully
static CMOS technology process to achieve higher
speed
and
smaller
size
with
the
low
power
-5 analog inputs multiplexed into one A/D
converter
-8 bit resolution
consumption and high noise immunity. On chip
TMR0: 8-bit timer/counter
memory includes 4K words of ROM, and 192 bytes of
TMR1: 16-bit timer/counter
static RAM.
TMR2: 8-bit timer
4 types of oscillator can be selected by
2. Features
programming option:
RC－Low cost RC oscillator
The followings are some of the features on the
LFXT－Low frequency crystal oscillator
hardware and software :
XTAL－Standard crystal oscillator
Fully CMOS static design
HFXT－High frequency crystal oscillator
8-bit data bus
On-chip RC oscillator based Watchdog Timer
On chip EPROM size: 4.0 K words
(WDT)
Internal RAM size: 192 bytes
22 I/O pins with their own independent
37 single word instructions
direction control
14-bit instructions
8-level stacks
3. Applications
Operating voltage: 2.5 V ~ 5.5 V (PRD Disable)
4.5 V ~ 5.5 V (PRD Enable)
The application areas of this MDT10P73 range
Operating frequency: DC ~ 20 MHz
from appliance motor control and high speed
The most fast execution time is 200 ns under
auto-motive
20 MHz in all single cycle instructions except
transmitters/receivers,
the branch instruction
telecommunications processors, such as Remote
Addressing modes include direct, indirect and
controller,
relative addressing modes
automobile and PC peripheral … etc.
to
small
low
power
pointing
instruments,
remote
devices,
chargers,
Power-on Reset
Power edge-detector Reset
Power range-detector Reset
Sleep Mode for power saving
Capture, Compare, PWM module
Synchronous serial port with SCM,I2C
11 interrupt sources:
-External INT pin
-TMR0 timer, TMR1 timer, TMR2 timer
-A/D conversion completion
-Port B<7:4> interrupt on change
This specification are subject to be changed without notice. Any latest information
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P. 2
2008/6 Ver. 1.6
and
toy,
MDT10P73(BA)
4. Pin Assignment
/MCLR
PA0/AIC0
PA1/AIC1
PA2/AIC2
PA3/AIC3/Vref
PA4/T0CKI
PA5/SS/AIC4
VSS
OSC1/CLKIN
OSC2/CLKOUT
PC0/T1OSO/T1CKI
PC1/T1OSI
PC2/CCP
PC3/SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0/INT
VDD
VSS
PC7
PC6
PC5/SDO
PC4/SDI
MDT10P73K11(SKINNY)
MDT10P73S11(SOP)
MDT10P73SS11(SSOP)
5. Order Information
Device
MDT10P73K11
MDT10P73S11
MDT10P73SS11
ROM
RAM
I/O
(Words) (Bytes)
4K
192 22
4K
192 22
4K
192 22
A/D
(8 bits)
5-channel
5-channel
5-channel
Timer
SCM/
CCP
Package
(8/16)
USART
2/1
2 YES/YES SKINNY
2/1
2 YES/YES SOP
2/1
2 YES/YES SSOP
6. Pin Function Description
Pin Name
I/O
Function Description
PA0~PA3, PA5
I/O
Port A, TTL input level / Analog input channel
PA4
I/O
PA4, Schmitt Trigger input levels, Open drain output
PB0~PB7
I/O
Port B, TTL input level / PB0: External interrupt input
PB4~PB7: Interrupt on pin change
PC0~PC7
I/O
Port C, Schmitt Trigger input levels
/MCLR
I
Master Clear, Schmitt Trigger input levels
OSC1/CLKIN
I
Oscillator Input / external clock input
OSC2/CLKOUT
O
Oscillator Output / in RC mode, the CLKOUT pin has 1/4
frequency of CLKIN
VDD
Power supply
VSS
Ground
This specification are subject to be changed without notice. Any latest information
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P. 2
2008/6 Ver. 1.6
MDT10P73(BA)
7. Memory Map
(A) Register Map
Address
Description
BANK0
00
Indirect Addressing Register
01
RTCC
02
PCL
03
STATUS
04
MSR
05
Port A
06
Port B
07
Port C
0A
PCHLAT
0B
INTS
0C
PIFB1
0D
PIFB2
0E
TMR1L
0F
TMR1H
10
T1STA
11
TMR2
12
T2STA
13
SCMBUF
14
SCMCTL
15
CCP1L
16
CCP1H
17
CCP1CTL
18
RCSC
19
TXREG
1A
RCREG
1B
CCP2L
1C
CCP2H
1D
CCP2CTL
1E
ADRES
This specification are subject to be changed without notice. Any latest information
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P. 3
2008/6 Ver. 1.6
MDT10P73(BA)
Address
Description
1F
ADS0
20~7F
General purpose register
BANK1
01
TMR
05
CPIO A
06
CPIO B
07
CPIO C
0C
PIEB1
0D
PIEB2
0E
PSTA
12
T2PER
14
SCMSTA
18
TXSC
19
BRREG
1F
ADS1
A0~FF
General purpose register
(1) IAR (Indirect Address Register): R00
(2) RTCC (Real Time Counter/Counter Register): R01
(3) PC (Program Counter): R02, R0A
Write PC --- from PCHLAT
Write PC --- from PCHLAT
LJUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
A11
A10~A8
A7~A0
Write PC --- from ALU
LJUMP, LCALL --- from instruction word
RTWI, RET, RTFI --- from STACK
This specification are subject to be changed without notice. Any latest information
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P. 4
2008/6 Ver. 1.6
MDT10P73(BA)
(4) STATUS (Status register): R03
Bit
Symbol
Function
0
C
1
HC
2
Z
3
/PF
Power down bit
4
/TF
WDT timer overflow bit
5
RBS0
Register Bank select bit
Carry bit
Half Carry bit
Zero bit
0: 00h~7Fh (Bank0)
1: 80h~FFh (Bank1)
7~6
--
General purpose bit
(5) MSR (Memory Bank Select Register): R04
Memory Bank Select Register:
0: 00h~7Fh (Bank0)
1: 80h~FFh (Bank1)
b7
b6
b5
b4
b3
b2
b1
b0
Indirect Addressing Mode
(6) PORT A: R05
PA5~PA0, I/O Register
(7) PORT B: R06
PB7~PB0, I/O Register
(8) PORT C: R07
PC7~PC0, I/O Register
(9) PCHLAT: R0A
(10) INTS (Interrupt Status Register): R0B
Bit
Symbol
Function
0
RBIF
PORT B change interrupt flag, Set when PB <7:4> inputs change
1
INTF
Set when INT interrupt occurs
2
TIF
3
RBIE
Set when TMR0 overflows
0: Disable PB change interrupt
1: Enable PB change interrupt
4
INTS
0: Disable INT interrupt
1: Enable INT interrupt
This specification are subject to be changed without notice. Any latest information
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P. 5
2008/6 Ver. 1.6
MDT10P73(BA)
Bit
Symbol
5
TIS
Function
0: Disable TMR0 interrupt
1: Enable TMR0 interrupt
6
PEIE
0: Disable all peripheral interrupt
1: Enable all peripheral interrupt
7
GIS
0: Disable global interrupt
1: Enable global interrupt
(11) PIFB1 (Peripheral Interrupt Flag Bit): R0C
Bit
Symbol
0
TMR1IF
Function
TMR1 interrupt flag
0: TMR1 did not overflow
1: TMR1 overflowed
1
TMR2IF
TMR2 interrupt flag
0: No TMR2 to T2PER match occurred
1: TMR2 to T2PER match occurred
2
CCP1IF
CCP1 interrupt flag
0: No TMR1 capture/compare occurred
1: A TMR1 capture/compare occurred
3
SCMIF
SCM interrupt flag
0: Waiting SCM transmit/receive
1: The SCM transmission/reception is complete
4
TXIF
USART transmit interrupt flag
0: The USART transmit buffer is full
1: The USART transmit buffer is empty
5
RCIF
UASRT receive interrupt flag
0: The USART receive buffer is empty
1: The USART receive buffer is full
6
ADIF
A/D interrupt flag
0: A/D conversion is not complete
1: A/D conversion completed
7
--
Unimplemented
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P. 6
2008/6 Ver. 1.6
MDT10P73(BA)
(12) PIFB2 (Peripheral Interrupt Flag Bit): R0D
Bit
Symbol
0
CCP2IF
Function
CCP2 interrupt flag
0: No TMR1 capture/compare occurred
1: A TMR1 capture/compare occurred
7~1
--
Unimplemented
(13) TMR1L: R0E
The LSB of the 16-bit TMR1
(14) TMR1H: R0F
The MSB of the 16-bit TMR1
(15) T1STA: R10
Bit
Symbol
0
TMR1ON
Function
0: Stop TMR1
1: Enable TMR1
1
TMR1CLK 0: Internal clock (Fosc/4)
1: External clock from pin PC0
2
/T1SYNC
TMR1CLK = 1
0: Synchronize external clock
1: Do not synchronize external clock
TMR1CLK = 0
This bit is ignored
3
T1OSCEN 0: TMR1 Oscillator is shut off
1: TMR1 Oscillator is enable
5~4
T1CKPS1
1 1 = 1:8 Prescale value
~
1 0 = 1:4 Prescale value
T1CKPS0
0 1 = 1:2 Prescale value
0 0 = 1:1 Prescale value
7~6
--
Unimplemented
(16) TMR2: R11
TMR2 register
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P. 7
2008/6 Ver. 1.6
MDT10P73(BA)
(17) T2STA: R12
Bit
Symbol
1~0
T2CKPS1
0 0 = Prescaler is 1
~
0 1 = Prescaler is 4
T2CKPS0
1 x = Prescaler is 16
TMR2ON
0: TMR2 is off
2
Function
1: TMR2 is on
7~3
--
Unimplemented
(18) SCMBUF: R13
Serial communication port buffer
(19) SCMCTL: R14
Bit
Symbol
Function
3~0
SCM3
0 0 0 0: SCM master mode, clock = Fosc/4
~
0 0 0 1: SCM master mode, clock = Fosc/16
SCM0
0 0 1 0: SCM master mode, clock = Fosc/64
0 0 1 1: SCM master mode, clock = TMR2 output/2
0 1 0 0: SCM slave mode, clock = SCK pin, /SS control enable
0 1 0 1: SCM slave mode, clock = SCK pin, /SS control disable
0 1 1 0: I2C slave mode, 7 bit address.
0 1 1 1: I2C slave mode, 10 bit address.
1 0 1 1: I2C firmware controlled Master mode.
1 1 1 0: I2C slave mode, 7 bit address with start and stop bit interrupts
enabled.
1 1 1 1: I2C slave mode, 10 bit address. with start and stop bit interrupts
enabled.
4
CKS
0: Transmit happens on rising edge, receive on falling edge, Idle state for
clock is low level.
1: Transmit happens on falling edge, receive on rising edge, Idle state for
clock is high level
5
SCMEN
0: Disable SCM, then PC3, PC4, PC5 is I/O port.
1: Enable SCM
6
SCMROI
0: No overflow
1: Overflow
7
WCOL
0: No collision
1: The SCMBUF is written while it is still transmitting the previous word
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P. 8
2008/6 Ver. 1.6
MDT10P73(BA)
(20) CCP1L: R15
Capture/Compare/PWM LSB
(21) CCP1H: R16
Capture/Compare/PWM MSB
(22) CCP1CTL: R17
Bit
Symbol
3~0
CCP1M3
Function
0 0 0 0: CCP1 off
~
0 1 0 0: Capture1 mode, every falling edge
CCP1M0
0 1 0 1: Capture1 mode, every rising edge
0 1 1 0: Capture1 mode, every 4th rising edge
0 1 1 1: Capture1 mode, every 16th rising edge
1 0 0 0: Compare1 mode, set output on match
1 0 0 1: Compare1 mode, clear output on match
1 0 1 0: Compare1 mode, generate software interrupt on match
1 0 1 1: Compare1 mode, trigger special event
1 1 x x: PWM1 mode
5~4
PWM1LSB These bits are the two LSBs of the PWM1 duty cycle
7~6
--
Unimplemented
(23) RCSC: R18
Bit
Symbol
Function
th
0
RX9DF
9 bit of received data
1
OERF
0: No overrun error
1: Overrun error
2
FERF
0: No framing error
1: Framing error
3
--
4
CRENF
Unimplemented
0: Disable continuous receive
1: Enable continuous receive
5
SRENF
0: Disable single receive
1: Enable single receive
6
RX9ENF
0: Select 8-bit reception
1: Select 9-bit reception
7
SPENF
0: Serial port disable
1: Serial port enable
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P. 9
2008/6 Ver. 1.6
MDT10P73(BA)
(24) TXREG: R19
USART transmit register
(25) RCREG: R1A
USART receive register
(26) CCP2L: R1B
Capture/Compare/PWM LSB
(27) CCP2H: R1C
Capture/Compare/PWM MSB
(28) CCP2CTL: R1D
Bit
Symbol
3~0
CCP2M3
Function
0 0 0 0: CCP2 off
~
0 1 0 0: Capture2 mode, every falling edge
CCP2M0
0 1 0 1: Capture2 mode, every rising edge
0 1 1 0: Capture2 mode, every 4th rising edge
0 1 1 1: Capture2 mode, every 16th rising edge
1 0 0 0: Compare2 mode, set output on match
1 0 0 1: Compare2 mode, clear output on match
1 0 1 0: Compare2 mode, generate software interrupt on match
1 0 1 1: Compare2 mode, trigger special event
1 1 x x: PWM2 mode
5~4
7~6
PWM2LSB These bits are the two LSBs of the PWM2 duty cycle
--
Unimplemented
(29) ADRES: R1E
A/D result register high byte. The ADRES register is not a writable register.
(30) ADS0 ( A/D Status Register ): R1F
Bit
Symbol
0
ADRUN
Function
0: A/D converter module is shut off and consumes no operating current
1: A/D converter module is operating
1
2
--
Unimplemented
GO/DONEB 0: A/D conversion not in progress
1: A/D conversion in progress
5~3
CHS2~0
000: AIC0 001: AIC1 010: AIC2 011: AIC3 100: AIC4
This specification are subject to be changed without notice. Any latest information
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P. 10
2008/6 Ver. 1.6
MDT10P73(BA)
Bit
Symbol
7~6
ASCS1-0
Function
00: fosc/2 01: fosc/8 10: fosc/32 11: f RC (*Note)
*Note: determined by OSC mode, HF: fosc/32, XT: fosc/8, RC: fosc/2, LF: fosc/2
(31) TMR (Time Mode Register): R81
Bit
Symbol
Function
Prescaler Value
2~0
PS2~0
3
PSC
4
TCE
5
TCS
6
IES
7
PBPH
RTCC rate
0 0 0
1:2
0 0 1
1:4
0 1 0
1:8
0 1 1
1 : 16
1 : 32
1 0 0
1 0 1
1 : 64
1 1 0
1 : 128
1 1 1
1 : 256
Prescaler assignment bit
0: RTCC
1: Watchdog Timer
RTCC signal edge
0: Increment on low-to-high transition on RTCC pin
1: Increment on high-to-low transition on RTCC pin
RTCC signal set
0: Internal instruction cycle clock
1: Transition on RTCC pin
Interrupt edge select
0: Interrupt on falling edge on PB0
1: Interrupt on rising edge on PB0
PORTB7~0 pull-hi
0: PORTB7~0 pull-hi are enable
1: PORTB7~0 pull-hi are disable
WDT rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
(32) CPIO A (Control Port I/O Mode Register): R85
＝“0”, I/O pin in output mode;
＝“1”, I/O pin in input mode.
(33) CPIO B (Control Port I/O Mode Register): R86
＝“0”, I/O pin in output mode;
＝“1”, I/O pin in input mode.
(34) CPIO C (Control Port I/O Mode Register): R87
＝“0”, I/O pin in output mode;
＝“1”, I/O pin in input mode.
(35) PIEB1: R8C
Bit
Symbol
0
TMR1IE
Function
TMR1 interrupt enable bit
0: Disable TMR1 interrupt
1: Enable TMR1 interrupt
This specification are subject to be changed without notice. Any latest information
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P. 11
2008/6 Ver. 1.6
MDT10P73(BA)
Bit
Symbol
1
TMR2IE
Function
TMR2 interrupt enable bit
0: Disable TMR2 interrupt
1: Enable TMR2 interrupt
2
CCP1IE
CCP1 interrupt enable bit
0: Disable CCP1 interrupt
1: Enable CCP1 interrupt
3
SCMIE
SCM interrupt enable bit
0: Disable SCM interrupt
1: Enable SCM interrupt
4
TXIE
USART transmit interrupt enable bit
0: Disable the USART transmit interrupt
1: Enable the USART transmit interrupt
5
RCIE
USART receive interrupt enable bit
0: Disable the USART receive interrupt
1: Enable the USART receive interrupt
6
ADIE
A/D interrupt enable bit
0: Disable A/D interrupt
1: Enable A/D interrupt
7
--
Unimplemented
(36) PIEB2: R8D
Bit
0
Symbol
CCP2IE
Function
0: Disable CCP2 interrupt
1: Enable CCP2 interrupt
7~1
--
Unimplemented
(37) PSTA: R8E
Bit
Symbol
Function
0
PRDB
0: Power range-detector Reset occurred
1: No Power range-detector Reset Occurred
1
PORB
0: Power on Reset occurred
1: No Power on Reset occurred
7~2
--
Unimplemented
This specification are subject to be changed without notice. Any latest information
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P. 12
2008/6 Ver. 1.6
MDT10P73(BA)
T2PER: R92
Timer2 period
(38) SCMSTA: R94
Bit
Symbol
0
BF
I2C_UA
1
Function
0: Receive not complete
1: Receive complete
0:Address does not need to be updated.
(10 bit I2C 1:Indicates that the user needs to update the address in the sspadd
mode)
2
I2C_RWB
3
I2C_START
4
I2C_STOP
5
I2C_DAB
7~6
--
register.
0:Write
1:Read
0:Start bit was not detected last.
1:Indicates that a start bit has been detected last.
0:Stop bit was not detected last.
1:Indicates that a stop bit has been detected last.
0:Indicates that the last byte received or transmitted was address.
1:Indicates that the last byte received or transmitted was data.
Unimplemented
(39) TXSC: R98
Bit
Symbol
Function
0
TX9DF
9th bit of transmit data
1
TSRCF
0: TSR full
1: TSR empty
2
HBRCF
0: Low speed
1: High speed
3
--
4
UMSF
Unimplemented
0: USART asynchronous mode
1: USART synchronous mode
5
TXENF
0: Transmit disable
1: Transmit enable
6
TX9ENF
0: Select 8-bit reception
1: Select 9-bit reception
7
CSSF
0: Slave mode
1: Master mode
(40) BRREG: R99
Baud rate register
This specification are subject to be changed without notice. Any latest information
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P. 13
2008/6 Ver. 1.6
MDT10P73(BA)
(41) ADS1 (A/D Status Register): R9F
Bit
2~0
Symbol
Function
PAVM2~0
0 0 0: PA0~3,PA5 = analog input. VREF = VDD
0 0 1: PA0~2,PA5 = analog input. PA3 = ref input, VREF = PA3
0 1 0: PA0~3,PA5 = analog input. VREF = VDD
0 1 1: PA0~2,PA5 = analog input. PA3 = ref input, VREF = PA3
1 0 0: PA0, 1, 3 = analog input. PA2, 5 = digital I/O, VREF = VDD
1 0 1: PA0, 1 = analog input. PA2, 5 = digital I/O, VREF = PA3
1 1 x: PA0~3, 5 = digital I/O
7~3
--
Unimplemented
(42) Configurable options for EPROM (Set by writer)
Oscillator Type
RC
Oscillator
HFXT Oscillator
XTAL Oscillator
LFXT Oscillator
Watchdog Timer control
Watchdog timer disable all the time
Watchdog timer enable all the time
Power-range control
Power-range disable
Power-range enable
Oscillator-start Timer control
0ms
75ms
Power-edge Detect
Security state
PED Disable
Security Disable
PED Enable
Security Enable
This specification are subject to be changed without notice. Any latest information
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P. 14
2008/6 Ver. 1.6
MDT10P73(BA)
(B) Program Memory
Address
000-FFF
Description
Program memory
000
The starting address of power on, external reset or WDT time-out reset.
004
Interrupt vector
8. Reset Condition for all Registers
Register
Address
Power-On Reset,
Power range detector
Reset
/MCLR or WDT Reset
Wake-up from SLEEP
IAR
00h
N/A
N/A
N/A
RTCC
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
0Ah,02h
0000 0000 0000
0000 0000 0000
PC+1
STATUS
03h
0001 1xxx
000# #uuu
000# #uuu
MSR
04h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORT A
05h
--xx xxxx
--uu uuuu
--uu uuuu
PORT B
06h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORT C
07h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCHLAT
0Ah
---0 0000
---0 0000
---u uuuu
INTS
0Bh
0000 000x
0000 000u
uuuu uuuu
PIFB1
0Ch
-000 0000
-000 0000
-uuu uuuu
PIFB2
0Dh
---- ---0
---- ---0
---- ---u
TMR1L
0Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
0Fh
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1STA
10h
--00 0000
--uu uuuu
--uu uuuu
TMR2
11h
0000 0000
0000 0000
uuuu uuuu
T2STA
12h
---- -000
---- -uuu
---- -uuu
SCMBUF
13h
xxxx xxxx
uuuu uuuu
uuuu uuuu
SCMCTL
14h
0000 0000
0000 0000
uuuu uuuu
CCP1L
15h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1H
16h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CTL
17h
--00 0000
--00 0000
--uu uuuu
RCSC
18h
0000 -00x
0000 -00x
uuuu -uuu
TXREG
19h
0000 0000
0000 0000
uuuu uuuu
PC
This specification are subject to be changed without notice. Any latest information
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P. 15
2008/6 Ver. 1.6
MDT10P73(BA)
Register
Address
Power-On Reset,
Power range detector
Reset
/MCLR or WDT Reset
Wake-up from SLEEP
RCREG
1Ah
0000 0000
0000 0000
uuuu uuuu
CCP2L
1Bh
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2H
1Ch
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CTL
1Dh
--00 0000
--00 0000
--uu uuuu
ADRES
1Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADS0
1Fh
0000 00-0
0000 00-0
uuuu uu-u
TMR
81h
1111 1111
1111 1111
uuuu uuuu
CPIOA
85h
--11 1111
--11 1111
--uu uuuu
CPIOB
86h
1111 1111
1111 1111
uuuu uuuu
CPIOC
87h
1111 1111
1111 1111
uuuu uuuu
PIEB1
8Ch
-000 0000
-000 0000
-uuu uuuu
PSTA
8Eh
---- --0u
---- --uu
---- --uu
T2PER
92h
1111 1111
1111 1111
1111 1111
SCMSTA
94h
---- ---0
---- ---0
---- ---u
TXSC
98h
0000 -010
0000 -010
uuuu -uuu
BRREG
99h
0000 0000
0000 0000
uuuu uuuu
ADS1
9Fh
---- -000
---- -000
---- -uuu
Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0”
#＝value depends on the condition of the following table
Condition
Status: bit 4
Status: bit 3
PSTA: bit 1
PSTA: bit 0
/MCLR reset (not during SLEEP)
u
u
u
u
/MCLR reset during SLEEP
1
0
u
u
WDT reset (not during SLEEP)
0
1
u
u
WDT reset during SLEEP
0
0
u
u
Power-on reset
1
1
0
x
Power-range reset
1
1
u
0
Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0”
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 16
2008/6 Ver. 1.6
MDT10P73(BA)
9. Instruction Set
Instruction Code
Mnemonic
Operands
Function
Operating
Status
010000 00000000
NOP
No operation
None
010000 00000001
CLRWT
Clear Watchdog timer
0→WT
TF, PF
010000 00000010
SLEEP
Sleep mode
0→WT, stop OSC
TF, PF
010000 00000011
TMODE
Load W to TMODE register
W→TMODE
None
010000 00000100
RET
Return from subroutine
Stack→PC
None
010000 00000rrr
CPIO R
Control I/O port register
W→CPIO R
None
010001 1rrrrrrr
STWR R
Store W to register
W→R
None
011000 trrrrrrr
LDR R, t
Load register
R→t
Z
111010 iiiiiiii
LDWI i
Load immediate to W
i→W
None
010111 trrrrrrr
SWAPR R, t
Swap halves register
[R(0~3) ↔R(4~7)]→t
None
011001 trrrrrrr
INCR R, t
Increment register
R + 1→t
Z
011010 trrrrrrr
INCRSZ R, t
Increment register, skip if zero
R + 1→t
None
011011 trrrrrrr
ADDWR R, t
Add W and register
W + R→t
C, HC, Z
011100 trrrrrrr
SUBWR R, t
Subtract W from register
R ﹣W→t or (R+/W+1
→t)
C, HC, Z
011101 trrrrrrr
DECR R, t
Decrement register
R ﹣1→t
Z
011110 trrrrrrr
DECRSZ R, t
Decrement register, skip if zero
R ﹣1→t
None
010010 trrrrrrr
ANDWR R, t
AND W and register
R ∩ W→t
Z
110100 iiiiiiii
ANDWI i
AND W and immediate
i ∩ W→W
Z
010011 trrrrrrr
IORWR R, t
Inclu. OR W and register
R ∪ W→t
Z
110101 iiiiiiii
IORWI i
Inclu. OR W and immediate
i ∪ W→W
Z
010100 trrrrrrr
XORWR R, t
Exclu. OR W and register
R ♁ W→t
Z
110110 iiiiiiii
XORWI i
Exclu. OR W and immediate
i ♁ W→W
Z
011111 trrrrrrr
COMR R, t
Complement register
/R→t
Z
010110 trrrrrrr
RRR
R, t
Rotate right register
R(n) →R(n-1),
C→R(7), R(0)→C
C
010101 trrrrrrr
RLR
R, t
Rotate left register
R(n)→r(n+1),
C→R(0), R(7)→C
C
010000 1xxxxxxx
CLRW
Clear working register
0→W
Z
010001 0rrrrrrr
CLRR
Clear register
0→R
Z
0000bb brrrrrrr
BCR
R, b
Bit clear
0→R(b)
None
0010bb brrrrrrr
BSR
R, b
Bit set
1→R(b)
None
0001bb brrrrrrr
BTSC R, b
Bit Test, skip if clear
Skip if R(b)=0
None
0011bb brrrrrrr
BTSS R, b
Bit Test, skip if set
Skip if R(b)=1
None
Long CALL subroutine
n→PC,
PC+1→Stack
None
R
100nnn nnnnnnnn LCALL n
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 17
2008/6 Ver. 1.6
MDT10P73(BA)
Instruction Code
Mnemonic
Operands
Function
Operating
101nnn nnnnnnnn LJUMP n
Long JUMP to address
n→PC
110111 iiiiiiii
ADDWI i
Add immediate to W
W+i→W
110001 iiiiiiii
RTWI
Return, place immediate to W
Stack→PC,i→W
111000 iiiiiiii
SUBWI i
Subtract W from immediate
i-W→W
Reture from interrupt
Stack→PC,1→GIS
i
010000 00001001 RTFI
Status
None
C,HC,Z
None
C,HC,Z
None
Note :
W
WT
TMODE
CPIO
TF
PF
PC
OSC
Inclu.
Exclu.
AND
:
:
:
:
:
:
:
:
:
:
:
Working register
Watchdog timer
TMODE mode register
Control I/O port register
Timer overflow flag
Power loss flag
Program Counter
Oscillator
Inclusive ‘∪’
Exclusive ‘♁’
Logic AND ‘∩’
b
t
:
:
0
1
R
:
C
:
HC :
Z
:
/
:
x
:
i
:
n
:
Bit position
Target
: Working register
: General register
General register address
Carry flag
Half carry
Zero flag
Complement
Don’t care
Immediate data ( 8 bits )
Immediate address
10. Electrical Characteristics
*Note: Temperature=25°C
1. Operation Current:
(1) HF (C=10p), WDT – disable, PRD – disable
4M
10M
20M
Sleep
2.5V
480uA
1mA
2.1mA
1uA
3.0V
600uA
1.3mA
2.5mA
1uA
4.0V
1mA
2mA
4mA
1uA
5.0V
1.5mA
2.9mA
5.3mA
1uA
5.5V
1.8mA
4mA
6.8mA
1uA
These parameters are for reference only.
(2) XT (C=10p), WDT – disable, PRD – disable
1M
4M
10M
Sleep
2.5V
130uA
440uA
1mA
1uA
3.0V
160uA
560uA
1.2mA
1uA
4.0V
400uA
900uA
2mA
1uA
5.0V
700uA
1.3mA
2.8mA
1uA
5.5V
940uA
1.6mA
3.3mA
1uA
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 18
2008/6 Ver. 1.6
MDT10P73(BA)
(3) LF (C=10p), WDT – disable, PRD – disable
32K
455K
1M
Sleep
2.5V
30uA
80uA
170uA
1uA
3.0V
40uA
120uA
210uA
1uA
4.0V
90uA
210uA
420uA
1uA
5.0V
180uA
450uA
600uA
1uA
5.5V
270uA
600uA
900uA
1uA
These parameters are for reference only.
(4) RC, WDT – disable, PRD – disable, @VDD = 5.0V
C
3p
20p
100p
300p
R
Freq.
Current
4.7k
11.8M
4mA
10k
5.8M
2mA
47k
1.35M
600uA
100k
644K
400uA
300k
196K
250uA
470k
136K
200uA
4.7k
6M
2.7mA
10k
3.04M
1.5mA
47k
692K
500uA
100k
327K
350uA
300k
98K
250uA
470k
70K
200uA
4.7k
2.18M
1.7mA
10k
1.09M
900uA
47k
240K
300uA
100k
112K
250uA
300k
34K
200uA
470k
25K
200uA
4.7k
963K
1.4mA
10k
464K
700uA
47k
101K
250uA
100k
47K
200uA
300k
14K
200uA
470k
10K
200uA
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 19
2008/6 Ver. 1.6
MDT10P73(BA)
(5) RC, WDT – disable, PRD – disable, @VDD = 3.0V
C
3p
20p
100p
300p
R
Freq.
Current
4.7k
11.6M
2mA
10k
6.52M
1.2mA
47k
1.62M
300uA
100k
784K
160uA
300k
242K
60uA
470k
173K
60uA
4.7k
6.88M
1.5mA
10k
3.65M
800uA
47k
868K
170uA
100k
415K
100uA
300k
127K
60uA
470k
91K
60uA
4.7k
2.94M
1mA
10k
1.52M
500uA
47k
348K
120uA
100k
116K
60uA
300k
50K
60uA
470k
36K
60uA
4.7k
1.42M
800uA
10k
724K
400uA
47k
164K
100uA
100k
79K
60uA
300k
24K
60uA
470k
17K
60uA
These parameters are for reference only.
2. Input Voltage (VDD = 5V):
Vil
Vih
PA~PC
Min
Max
TTL
VSS
0.8V
Schmitt trigger
VSS
0.6V
TTL
3.0V
VDD
Schmitt trigger
3.8V
VDD
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 20
2008/6 Ver. 1.6
MDT10P73(BA)
Input Voltage (VDD = 3V):
Vil
Vih
PA~PC
Min
Max
TTL
VSS
0.4V
Schmitt trigger
VSS
0.2V
TTL
2.0V
VDD
Schmitt trigger
2.6V
VDD
These parameters are for reference only.
3. Output Voltage (VDD = 5V):
PA~PC
Condition
Voh
3.3V
Ioh = -20mA
Vol
0.9V
Iol = 20mA
Voh
4.2V
Ioh = -5mA
Vol
0.6V
Iol = 5mA
These parameters are for reference only.
Output Voltage (VDD = 3V):
PA~PC
Condition
Voh
1.6V
Ioh = -10mA
Vol
0.6V
Iol = 10mA
Voh
2.4V
Ioh = -5mA
Vol
0.5V
Iol = 5mA
These parameters are for reference only.
4. Output Current (Max.) (VDD = 5V):
Current
Source current
25mA
Sink current
40mA
These parameters are for reference only.
5. The basic WDT time-out cycle time:
Time
2.5V
25ms
3.0V
23ms
4.0V
20ms
5.0V
18ms
5.5V
17ms
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 21
2008/6 Ver. 1.6
MDT10P73(BA)
These parameters are for reference only.
6. PRD:
(1) PRD reset voltage:
Voltage
Vih
4.2V±10%
Vil
3.8V±10%
These parameters are for reference only.
(2) PRD reset current:
Current
5.0V
120uA
4.0V
100uA
These parameters are for reference only.
7. Pull high resistor:
VDD
5V
3V
PB7~0
50KΩ±20%
100KΩ±20%
These parameters are for reference only.
8. MCLR filter time:
VDD
5V
Time
1000ns±20%
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 22
2008/6 Ver. 1.6