AVAGO MGA-633P8-TR1G Ultra low noise, high linearity active bias low noise amplifi er Datasheet

MGA-633P8
Ultra Low Noise, High Linearity Active Bias Low Noise Amplifier
Data Sheet
Description
Features
Avago Technologies’ MGA-633P8 is an economical, easyto-use GaAs MMIC Low Noise Amplifier (LNA). The LNA has
low noise and high linearity achieved through the use of
Avago Technologies’ proprietary 0.25um GaAs Enhancement-mode pHEMT process. It is housed in a miniature
2.0 x 2.0 x 0.75mm3 8-pin Quad-Flat-Non-Lead (QFN)
package. It is designed for optimum use from 450MHz up
to 2GHz. The compact footprint and low profile coupled
with low noise, high gain and high linearity make the
MGA-633P8 an ideal choice as a low noise amplifier for
cellular infrastructure for GSM and CDMA. For optimum
performance at higher frequency from 1.5GHz to 2.3GHz,
the MGA-634P8 is recommended, and from 2.3GHz to
4GHz, the MGA-635P8 is recommended. Both MGA-634P8
and MGA-635P8 share the same package and pinout as
MGA-633P8
 Ultra Low noise Figure
 High linearity performance
 GaAs E-pHEMT Technology [1]
 Low cost small package size: 2.0 x 2.0 x 0.75 mm3
 Excellent uniformity in product specifications
 Tape-and-Reel packaging option available
Specifications
900MHz; 5V, 54mA
 18 dB Gain
 0.37 dB Noise Figure
 15dB Input Return Loss
 37 dBm Output IP3
Pin Configuration and Package Marking
 22 dBm Output Power at 1dB gain compression
2.0 x 2.0 x 0.75 mm3 8-lead QFN
Applications
[1]
[2]
[3]
[4]
33X
Top View
Pin1
Pin2
Pin3
Pin4
–
–
–
–
Vbias
RFinput
Not Used
Not Used
[8]
[7]
[6]
[5]
[8]
[7]
[6]
[5]
[1]
[2]
[3]
[4]
 Low noise amplifier for cellular infrastructure for GSM
and CDMA.
 Other ultra low noise application.
Simplified Schematic
Bottom View
Vdd
Pin5 – Not Used
Pin6 – Not Used
Pin7 – RFoutput / Vdd
Pin8 – Not Used
Centre tab - Ground
Note:
Package marking provides orientation and identification
“33” = Device Code
“X” = Month Code
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 90 V (Class A)
ESD Human Body Model = 600 V (Class 1B)
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Rbias
C3
RFin
C1
C6
R2
R1
C5
L1
L2
[1]
[2]
[3]
[4]
bias
[8]
[7]
C4
C2
RFout
[6]
[5]
Notes:
 The schematic is shown with the assumption that similar PCB is used
for all MGA-633P8, MGA-634P8 and MGA-635P8.
 Detail of the components needed for this product is shown in Table 1.
 Enhancement mode technology employs positive gate voltage,
thereby eliminating the need of negative gate voltage associated
with conventional depletion mode devices.
 Good RF practice requires all unused pins to be earthed.
Absolute Maximum Rating[1] TA=25°C
Thermal Resistance
Symbol
Parameter
Units
Absolute Max.
Vdd
Device Voltage, RF output to ground
V
5.5
Idd
Drain Current
mA
90
Pmax
CW RF Input Power
(Vdd = 5.0 V, Idd = 54 mA)
dBm
+20
Pdiss
Total Power Dissipation [3]
W
0.495
Tj
Junction Temperature
°C
150
TSTG
Storage Temperature
°C
-65 to 150
Thermal Resistance [2]
(Vdd = 5.0 V, Idd = 54 mA), jc = 72°C/W
Notes:
1. Operation of this device in excess of any of
these limits may cause permanent damage.
2. Thermal resistance measured using InfraRed Measurement Technique.
3. Power dissipation with unit turned on.
Board temperature TB is 25°C. Derate at
13.89mW/°C for TB>114°C.
Electrical Specifications[1, 4]
RF performance at TA = 25°C, Vdd =5V, Rbias=6.8kOhm, 900MHz, measured on demo board in Figure 5 with component
list in Table1 for 900 MHz matching.
Symbol
Parameter and Test Condition
Units
Min.
Typ.
Max.
Idd
Drain Current
mA
39
54
67
Gain
Gain
dB
16.5
18
19.5
OIP3 [2]
Output Third Order Intercept Point
dBm
34
37
NF [3]
Noise Figure
dB
0.37
OP1dB
Output Power at 1dB Gain Compression
dBm
22
IRL
Input Return Loss, 50 source
dB
15
ORL
Output Return Loss, 50 load
dB
21
REV ISOL
Reverse Isolation
dB
21
0.6
Notes:
1. Measurements at 900 MHz obtained using demo board described in Figure 1.
2. OIP3 test condition: FRF1 = 900 MHz, FRF2 = 901 MHz with input power of -15dBm per tone.
3. For NF data, board losses of the input have not been de-embedded.
4. Use proper bias, heatsink and derating to ensure maximum device temperature is not exceeded. See absolute maximum ratings and application
note for more details.
2
Product Consistency Distribution Charts[1, 2]
LSL
USL
USL
Id
Max:67
Min:39
Mean:54
Noise Figure
Max:0.6
Mean:0.37
38 40 42 44 46 48 50 52 54 56 58 60 62 64 66
0.3
Figure 1. Id @ 900MHz, 5V, 54mA
Mean = 54
Figure 2. Noise Figure @ 900MHz, 5V, 54mA
Mean = 0.37
LSL
0.4
0.6
LSL
OIP3
Min:34
Mean:37
34
0.5
35
USL
Gain
Max:19.5
Min:16.5
Mean:18
36
Figure 3. OIP3 @ 900MHz, 5V, 54mA
Mean = 37
37
38
39
16.5
17
17.5
18
17.5
19
19.5
Figure 4. Gain @ 900MHz, 5V, 54mA
Mean = 18
Notes:
1. Distribution data samples are 500 samples taken from 3 different wafers. Future wafers allocated to this product may have nominal values anywhere
between the upper and lower limits.
2. Circuit Losses have not been de-embedded from the actual measurements.
3
Demo Board Layout
Demo Board Schematic
Vdd
Rbias
C3
RFin
L1
C1
C6
R2
R1
C5
L2
[1]
[2]
bias
[3]
[4]
[8]
[7]
C4
C2
RFout
[6]
[5]
Figure 5. Demo Board Layout Diagram
Figure 6. Demo Board Schematic Diagram
– Recommended PCB material is 10 mils Rogers RO4350.
– Suggested component values may vary according to layout and PCB
material.
Note:
 The schematic is shown with the assumption that similar PCB is used
for all MGA-633P8, MGA-634P8 and MGA-635P8.
 Detail of the components needed for this product is shown in Table 1.
Table 1. Component list for 900 MHz matching
Part
Size
Value
Detail Part Number
C1, C2
0402
100pF (Murata)
GRM1555C1H101JD01E
L1, L2
0402
33nH (Toko)
LL1005-FHL33NJ
C4
0402
33pF (Koacera)
CM05CH330J50AH
C3, C6
0402
4.7uF (Murata)
GRM155R60E475ME760
R1
R2
0402
0402
0 Ohm (Kamaya)
10 Ohm (Koa)
RMC1/16S-JPTH
RM73B1ETTP100J
Note:
C1, C2 are DC Blocking capacitors; L1 input match for NF; L2 output match for OIP3; C3, C4, C6 are bypass capacitors; R2 is stabilizing resistor;
Rbias is the biasing resistor; R1, C5 are not use for this product
4
MGA-633P8 Typical Performance
0.5
0.5
0.4
0.4
Fmin (dB)
Fmin (dB)
RF performance at TA = 25°C, Vdd = 5V, Id = 54mA, measured using 50ohm input and output board, unless otherwise stated.
OIP3 test condition: FRF1 = 900 MHz, FRF2 = 901 MHz with input power of -10dBm per tone.
0.3
0.2
0.1
0
0.2
0.1
40
50
55
Idd (mA)
70
0
80
Figure 7. Fmin vs Idd at 5V at 700MHz
20
20
19
19
18
18
17
16
15
40
50
55
Idd (mA)
16
40
55
70
15
80
40
55
55
OIP3(dBm)
80
Figure 11. Gain vs Idd at 5V Tuned for Optimum OIP3 and Fmin at 900MHz
OIP3(dBm)
40
70
Idd(mA)
Figure 10. Gain vs Idd at 5V Tuned for Optimum OIP3 and Fmin at 700MHz
70
80
Idd(mA)
Figure 12. OIP3 vs Idd at 5V Tuned for Optimum OIP3 and Fmin at 700MHz
5
80
17
Idd(mA)
45
44
43
42
41
40
39
38
37
36
35
70
Figure 8. Fmin vs Idd at 5V at 900MHz
Gain (dB)
Gain (dB)
0.3
45
44
43
42
41
40
39
38
37
36
35
40
55
70
80
Idd(mA)
Figure 13. OIP3 vs Idd at 5V Tuned for Optimum OIP3 and Fmin at 900MHz
OP1dB (dBm)
OP1dB (dBm)
25
24
23
22
21
20
19
18
17
16
15
40
55
70
80
25
24
23
22
21
20
19
18
17
16
15
40
55
Figure 14. OP1dB vs Idd at 5V Tuned for Optimum OIP3 and Fmin at 700MHz
0.7
0.5
OIP3(dBm)
Fmin (dB)
0.6
0.4
0.3
0.2
40mA
55mA
80mA
0.1
500
650
700
750
800
900
Frequency (MHz)
1700
1900
Gain(dB)
Figure 16. Fmin vs Frequency and Idd at 5V
22
20
18
16
14
12
10
8
6
4
2
0
700
750
800
900
Frequency (MHz)
1700
1900
Figure 18. Gain vs Frequency and Temperature for Optimum OIP3 and Fmin
at 5V 54mA
6
50
45
40
35
30
25
20
15
10
5
0
40°C
25°C
85°C
500
700
750
800
900
Frequency (MHz)
1700
1900
Figure 17. OIP3 vs Frequency and Temperature for Optimum OIP3 and Fmin
at 5V 54mA
40°C
25°C
85°C
500
80
Figure 15. OP1dB vs Idd at 5V Tuned for Optimum OIP3 and Fmin at 900MHz
0.8
0
70
Idd(mA)
Idd(mA)
40°C
25°C
85°C
OP1dB(dBm)
Fmin (dB)
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
500
700
750
800
900
Frequency (MHz)
1700
1900
Figure 19. Fmin vs Frequency and Temperature for Optimum OIP3 and Fmin
at 5V 54mA
26
24
22
20
18
16
14
12
10
8
6
4
2
0
40°C
25°C
85°C
500
700
750
800
900
Frequency (MHz)
1700
1900
Figure 20. OP1dB vs Frequency and Temperature for Optimum OIP3 and Fmin
at 5V 54mA
Below is the table showing the MGA-633P8 Reflection Coefficient Parameters tuned for Maximum OIP3, Vdd = 5V,
Idd = 54mA.
Gamma Load position
Frequency (GHz)
Magnitude
Angle
OIP3 (dBm)
OP1dB (dBm)
0.50
0.53
122
36.2
22.96
0.70
0.49
115
41.9
21.67
0.75
0.539
113
42.7
20.87
0.80
0.659
123
41.2
21.52
0.90
0.635
145
42.1
20.79
1.70
0.342
-120
41
22.63
1.90
0.333
-74
41.2
23.63
RFinput
Reference Plane
RFoutput
Reference Plane
[1]
Bias
[8]
[2]
[7]
[3]
[6]
[4]
[5]
Figure 21.
Notes:
1. The Maximum OIP3 values are calculated based on Load pull measurements on approximately 100 different impedances using Maury’s Load pull
test system.
2. Measurements are conducted on 0.010 inch thick ROGER 4350. The input reference plane is at the end of the RFin pin and the output reference
plane is at the end of the RFout pin as shown in Figure 21.
3. Gamma Load for maximum OIP3 with biasing of 3V 54mA, 3.5V 54mA, 4V 54mA, 4.5V 54mA, 5V 40mA, 5V 54mA and 5V 70mA from 800 MHz to
1.9GHz are available upon request.
7
MGA-633P8 Typical Performance in Demoboard
RF performance at TA = 25°C, Vdd = 5V, Rbias = 6.8kOhm, measured on demo board in Figure.5 with component list in
Table1 for 900 MHz matching, unless otherwise stated.
0.8
25
-40°C
25°C
85°C
0.7
20
0.5
Gain (dB)
NF (dB)
0.6
0.4
0.3
0.2
-40°C
25°C
85°C
0.1
0
0
500
15
10
5
1000
Frequency (MHz)
1500
0
2000
Figure 22. NF vs Frequency vs Temperature
0
500
1000
Frequency (MHz)
1500
2000
Figure 23. Gain vs Frequency vs Temperature
42
23
40
OP1dB (dBm)
OIP3 (dBm)
22.5
38
36
34
30
0
500
1000
Frequency (MHz)
1500
K-factor
IRL,ORL,Gain,Rev Isol(dB)
IRL
ORL
Gain
Rev Isol
0
1000
2000
3000
4000
Frequency (MHz)
0
500
1000
Frequency (MHz)
1500
2000
Figure 25. OP1dB vs Frequency vs Temperature
5000
6000
Figure 26. Input Return Loss, Output Return Loss, Gain, Reverse Isolation vs
Frequency
8
21
2000
Figure 24. OIP3 vs Frequency vs Temperature
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
-35
-40°C
25°C
85°C
21.5
-40°C
25°C
85°C
32
22
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-40°C
25°C
85°C
0
2
4
6
8
10 12
Frequency (GHz)
Figure 27. K-factor vs Frequency vs Temperature
14
16
18
20
MGA-633P8 Typical Performance in Demoboard
85
80
75
70
65
60
55
50
45
40
35
Idd (mA)
Idd (mA)
RF performance at TA = 25 °C, Vdd =5V, Rbias=6.8kOhm, measured on demo board in Figure.5 with component list in
Table1 for 900 MHz matching, unless otherwise stated.
3
4
5
6
7
8
Rbias (Kohm)
9
10
11
Figure 28. Idd vs Rbias
100
90
80
70
60
50
40
30
20
10
0
-40°C
25°C
85°C
0
2
4
Vdd (V)
6
Figure 29. Idd vs Vdd vs Temperature
0.8
25
40mA
54mA
70mA
0.7
20
0.6
0.5
Gain (dB)
NF (dB)
8
0.4
0.3
0.2
40mA
54mA
70mA
0.1
500
1000
Frequency (MHz)
1500
10
5
0
0
15
0
2000
Figure 30. NF vs Frequency vs Idd
0
500
1000
Frequency (MHz)
1500
2000
Figure 31. Ga vs Frequency vs Idd
23.5
44
42
23
OP1dB (dBm)
OIP3 (dBm)
40
38
36
34
32
40mA
54mA
70mA
30
28
0
500
1000
Frequency (MHz)
Figure 32. OIP3 vs Frequency vs Idd
9
1500
2000
22.5
22
40mA
54mA
70mA
21.5
21
0
500
1000
Frequency (MHz)
Figure 33. OP1dB vs Frequency vs Idd
1500
2000
MGA-633P8 Typical Scattering Parameters, Vdd = 5V, Idd = 54mA
S11
S21
S12
S22
Freq
GHz
Mag.
Ang.
dB
Mag.
Ang.
Mag.
Ang.
Mag.
Ang.
0.1
0.73
-45.42
28.96
28.06
145.48
0.02
62.09
0.27
-43.62
0.5
0.25
-95.49
22.03
12.64
108.20
0.05
59.34
0.10
-4.56
0.9
0.16
-119.26
18.08
8.02
89.72
0.08
60.53
0.14
-16.96
1.0
0.15
-124.97
17.27
7.30
86.35
0.09
60.46
0.15
-18.82
1.5
0.10
-142.55
14.10
5.07
70.97
0.12
56.12
0.19
-39.65
1.9
0.07
-158.30
12.17
4.06
60.60
0.15
51.25
0.19
-56.21
2.0
0.07
-162.64
11.74
3.86
58.17
0.16
49.92
0.19
-60.31
2.5
0.05
177.70
9.88
3.12
46.59
0.20
43.20
0.21
-79.41
3.0
0.03
162.14
8.36
2.62
35.95
0.23
36.08
0.23
-95.09
4.0
0.01
-41.60
6.00
2.00
16.45
0.30
22.04
0.25
-118.55
5.0
0.03
-64.06
4.27
1.64
-1.63
0.36
7.61
0.25
-144.60
6.0
0.04
-129.24
2.96
1.41
-18.89
0.42
-7.19
0.24
-170.64
7.0
0.07
-152.03
1.85
1.24
-35.43
0.47
-22.36
0.26
165.84
8.0
0.12
-154.39
0.87
1.11
-50.92
0.52
-37.15
0.29
150.25
9.0
0.18
-161.44
0.05
1.01
-65.12
0.56
-51.58
0.33
138.58
10.0
0.21
-177.23
-0.57
0.94
-78.96
0.60
-66.28
0.35
124.74
11.0
0.21
156.03
-1.03
0.89
-93.28
0.63
-81.96
0.33
104.27
12.0
0.22
124.49
-1.53
0.84
-108.35
0.66
-98.72
0.33
78.81
13.0
0.26
104.45
-2.13
0.78
-122.84
0.66
-115.13
0.38
62.57
14.0
0.33
95.24
-2.66
0.74
-135.50
0.66
-129.75
0.42
60.19
15.0
0.39
84.99
-2.96
0.71
-146.69
0.66
-143.01
0.43
60.20
16.0
0.42
67.14
-3.10
0.70
-159.52
0.67
-157.83
0.40
50.25
17.0
0.43
44.98
-3.53
0.67
-175.16
0.66
-175.42
0.40
27.20
18.0
0.49
28.99
-4.50
0.60
169.61
0.60
167.43
0.48
10.68
19.0
0.57
17.18
-5.59
0.53
156.86
0.53
152.94
0.56
7.82
20.0
0.62
5.97
-6.14
0.49
145.85
0.50
140.18
0.60
6.77
RFinput
Reference Plane
RFoutput
Reference Plane
[1]
Figure 34
10
Bias
[8]
[2]
[7]
[3]
[6]
[4]
[5]
Typical Noise Parameters, Vdd = 5V, Idd = 54mA
Part Number Ordering Information
Freq
GHz
Fmin
dB
opt
Mag.
opt
Ang.
Part Number
No. of Devices
Container
Rn/50
MGA-633P8-BLKG
100
Antistatic Bag
0.5
0.46
0.169
-37
0.051
MGA-633P8-TR1G
3000
7 inch Reel
0.7
0.38
0.15
-17
0.0586
0.75
0.36
0.144
-15
0.0532
0.8
0.35
0.136
-13
0.0478
0.9
0.33
0.129
-7
0.0446
1.7
0.46
0.048
80.5
0.0644
1.9
0.51
0.028
98.7
0.0498
Notes:
1. The Fmin values are based on noise figure measurements at 100
different impedances using Focus source pull test system. From
these measurements a true Fmin is calculated.
2. Scattering and noise parameters are measured on coplanar waveguide
made on 0.010 inch thick ROGER 4350. The input reference plane is
at the end of the RFinput pin and the output reference plane is at the
end of the RFoutput pin as shown in Figure 30.
3. S2P file with scattering and noise parameters for biasing 3V 54mA,
3.5V 54mA, 4V 54mA, 4.5V 54mA, 5V 40mA, 5V 54mA and 5V 70mA
are available upon request.
SLP2X2 Package
PIN 1 DOT
BY MARKING
2.00±0.050
0.203 Ref.
2.00±0.050
33X
0.000–0.05
0.75±0.05
Top View
Side View
0.60±0.050
Exp. DAP
PIN #1 IDENTIFICATION
R0.100
0.35±0.050
1.20±0.050
Exp. DAP
0.50 Bsc
0.25±0.050
Bottom View
11
1.50
Ref.
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating.
3. Dimensions are exclusive of mold flash and metal burr.
Recommended PCB Land Pattern and Stencil Design
2.20
2.16
1.75
0.56
0.50
1.75
0.00
0.80
0.50
0.50
1.50
0.22
0.25
0.170
0.45
0.40
0.05
(all SM gaps)
0.30
R0.15
Stencil Opening
Land Pattern
1.75
0.56
0.50
0.50
Metal surface
0.21
1.50
Soldermask Open
R0.15
0.17
Combination of Land Pattern and Stencil Opening
Note:
1. Recommended Land Pattern and Stencil Opening
2. Stencil thickness is 0.1mm (4 mils)
3. All dimension are in mm unless otherwise specified
12
1.72
1.50
1.20
0.50
0.48
0.21
Device Orientation
REEL
4 mm
8 mm
33X
CARRIER
TAPE
USER FEED
DIRECTION
33X
COVER TAPE
Tape Dimensions
D
P0
P
P2
E
F
W
+
+
D1
Tt
t1
K0
10° Max
10° Max
A0
DESCRIPTION
Bo
SYMBOL
SIZE (mm)
SIZE (inches)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A0
B0
K0
P1
D
2.30 ± 0.05
2.30 ± 0.05
1.00 ± 0.05
4.00 ± 0.10
1.00 + 0.25
0.091 ± 0.004
0.091 ± 0.004
0.039 ± 0.002
0.157 ± 0.004
0.039 + 0.002
PERFORATION
DIAMETER
PITCH
POSITION
D
P0
E
1.50 ± 0.10
4.00 ± 0.10
1.75 ± 0.10
0.060 ± 0.004
0.157 ± 0.004
0.069 ± 0.004
CARRIER TAPE
WIDTH
W
THICKNESS
t1
8.00 + 0.30
8.00 ± 0.10
0.254 ± 0.02
0.315 ± 0.012
0.315 ± 0.004
0.010 ± 0.0008
COVER TAPE
WIDTH
TAPE THICKNESS
C
Tt
5.4 ± 0.10
0.062 ± 0.001
0.205 ± 0.004
0.0025 ± 0.004
DISTANCE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
3.50 ± 0.05
0.138 ± 0.002
P2
2.00 ± 0.05
0.079 ± 0.002
13
33X
33X
Reel Dimensions – 7 inch
6.25mm EMBOSSED LETTERS
LETTERING THICKNESS: 1.6mm
SLOT HOLE "a"
SEE DETAIL "X"
Ø178.0±0.5
SLOT HOLE "b"
FRONT
BACK
6
PS
SLOT HOLE(2x)
180° APART.
6
PS
RECYCLE LOGO
SLOT HOLE "a": 3.0±0.5mm(1x)
SLOT HOLE "b": 2.5±0.5mm(1x)
FRONT VIEW
45°
+0.5
Ø13.0 -0.2
Ø20.2 MIN.
°
R10.65
120
65°
1.5 MIN.
7.9 - 10.9**
+1.5*
8.4 -0.0
R5.2
FRONT
BACK
DETAIL "X"
SLOT HOLE ‘a’
EMBOSSED RIBS
RAISED: 0.25mm, WIDTH: 1.25mm
14.4 *
MAX.
Ø51.2±0.3
BACK VIEW
For product information and a complete list of distributors, please go to our web site:
SEE DETAIL "Y"
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved.
AV02-2329EN - May 25, 2012
3.5
DETAIL "Y"
(Slot Hole)
1.0
Ø55.0±0.5
60°
Ø178.0±1.0
SLOT HOLE ‘b’