MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM DESCRIPTION PIN CONFIGURATION The MH16V725BATJ is 16777216-word x 72-bit dynamic ram module. This consist of eighteen industry standard 16M x 4 dynamic RAMs in TSOP and three industry standard input buffer in TSSOP. The mounting of TSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module ,suitable for easy interchange or addition of module. FEATURES Type name /RAS /CAS Address /OE access access access access time time time time Cycle Power time dissipation (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) 85pin 1pin 94pin 10pin 95pin 11pin 124pin 40pin 125pin 41pin 168pin 84pin (typ.W) MH16V725BATJ-5 50 18 30 18 84 5.50 MH16V725BATJ-6 60 20 35 20 104 4.60 Utilizes industry standard 16M x 4 RAMs TSOP and industry standard input buffer in TSSOP 168-pin (84-pin dual in-line pacege) Single 3.3V(+/-0.3V) supply operation Low stand-by power dissipation . . . . . . . . 121mW(Max) Low operation power dissipation MH16V725BATJ -5 . . . . . . . . . . . . . . . . . 6.58W(Max) MH16V725BATJ -6 . . . . . . . . . . . . . . . . . 5.94W(Max) All input,output LVTTL compatible Includes(0.22uF x 20) decoupling capacitors 4096 refresh cycle every 64ms (A0~A12) JEDEC standard pin configration & Buffered PD pin Buffered input except /RAS and DQ Gold plating contact pads FRONT SIDE BACK SIDE APPLICATION Main memory unit for computers , Microcomputer memory PD&ID TABLE -5 -6 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1 0 0 0 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 0 1 = NC , 0 = drive to VOL PD pin . . . buffered. When /PDE is low, PD information can be read ID pin . . . non-buffered MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 1 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM PIN CONFIGURATION Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 DQ16 DQ17 Vss Reserved Reserved Vcc /WE0 /CAS0 Reserved /RAS0 /OE0 Vss A0 A2 A4 A6 A8 A10 A12 Vcc RFU RFU 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Vss /OE2 /RAS2 /CAS4 Reserved /WE2 Vcc Reserved Reserved DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 Vss DQ28 DQ29 DQ30 DQ31 Vcc DQ32 DQ33 DQ34 DQ35 Vss PD1 PD3 PD5 PD7 ID0 Vcc 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Vss DQ36 DQ37 DQ38 DQ39 Vcc DQ40 DQ41 DQ42 DQ43 DQ44 Vss DQ45 DQ46 DQ47 DQ48 DQ49 Vcc DQ50 DQ51 DQ52 DQ53 Vss Reserved Reserved Vcc RFU Reserved Reserved Reserved RFU Vss A1 A3 A5 A7 A9 A11 Reserved Vcc RFU B0 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Vss RFU Reserved Reserved Reserved /PDE Vcc Reserved Reserved DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 RFU RFU RFU RFU DQ61 DQ62 DQ63 Vss DQ64 DQ65 DQ66 DQ67 Vcc DQ68 DQ69 DQ70 DQ71 Vss PD2 PD4 PD6 PD8 ID1 Vcc Reserved: Reserved use RFU: Reserved for future use MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 2 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM BLOCK DIAGRAM /RAS0 /RAS2 /CAS0 /CAS4 /WE0 /WE2 /OE0 /OE2 /OE /W /CAS /RAS M5M467405B DQ1 ~DQ4 D1 /OE /W /CAS /RAS M5M467405B DQ1 ~DQ4 D2 /OE /W /CAS /RAS M5M467405B DQ1 ~DQ4 D3 /OE /W /CAS /RAS M5M467405B DQ1 ~DQ4 D4 /OE /W /CAS /RAS M5M467405B DQ1 ~DQ4 D5 /OE /W /CAS /RAS M5M467405B DQ1 ~DQ4 D6 /OE /W /CAS /RAS M5M467405B DQ1 ~DQ4 D7 /OE /W /CAS /RAS M5M467405B DQ1 ~DQ4 D8 /OE /W /CAS /RAS M5M467405B DQ1 ~DQ4 D9 D1~D9 Vcc B0 D10~D18 Vss MIT-DS-0271-0.0 /OE /W /CAS DQ1 M5M467405B DQ2 DQ3 DQ4 /OE /W /CAS DQ5 M5M467405B DQ6 DQ1 ~DQ4 /OE /W /CAS DQ9 M5M467405B DQ10 DQ1 ~DQ4 /OE /W /CAS DQ13 M5M467405B DQ14 DQ1 ~DQ4 /OE /W /CAS DQ17 M5M467405B DQ18 DQ1 ~DQ4 /OE /W /CAS DQ21 M5M467405B DQ22 DQ1 ~DQ4 /OE /W /CAS DQ25 M5M467405B DQ26 DQ1 ~DQ4 /OE /W /CAS DQ29 M5M467405B DQ30 DQ1 ~DQ4 /OE /W /CAS DQ33 M5M467405B DQ34 D18 D1~D18 & INPUT BUFFER D1~D18 MITSUBISHI ELECTRIC ( 3 / 22 ) PIN NAME /RAS0, /RAS2 /CAS0, /CAS2 /WE0, /WE2 /OE0, /OE2 A0~A12, B0 DQ0~DQ71 Vcc Vss DQ49 DQ50 DQ53 DQ54 DQ57 DQ58 DQ61 DQ62 DQ63 DQ64 /RAS DQ1 ~DQ4 D17 DQ31 DQ32 DQ46 DQ59 DQ60 /RAS D16 DQ27 DQ28 DQ45 DQ55 DQ56 /RAS D15 DQ23 DQ24 DQ42 DQ51 DQ52 /RAS D14 DQ19 DQ20 DQ41 DQ47 DQ48 /RAS D13 DQ15 DQ16 DQ38 DQ43 DQ44 /RAS D12 DQ11 DQ12 DQ37 DQ39 DQ40 /RAS D11 DQ7 DQ8 C1.~C . . 20 DQ36 /RAS D10 DQ35 A0 A1~A12 DQ0 DQ65 DQ66 DQ67 DQ68 /RAS DQ1 ~DQ4 DQ69 DQ70 DQ71 FUNCTION ROW ADDRESS STROBE INPUT COLUMN ADDRESS STROBE INPUT WRITE CONTROL INPUT OUTPUT ENABLE INPUT ADDRESS INPUT DATA I/O POWER SUPPLY GROUND Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM FUNCTION The MH16V725BATJ provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., Hyper page mode, /CAS before /RAS refresh, and delayed-write. The input conditions for each are shown in Table 1. Table 1 Input conditions for each mode Operation /RAS ACT Read ACT Write (Early write) ACT Write (Delayed write) ACT Read-modify-write ACT Hidden refresh /CAS before /RAS refresh ACT NAC Standby /CAS ACT ACT ACT ACT ACT ACT DNC Inputs /W /OE NAC ACT ACT DNC ACT DNC ACT ACT DNC ACT NAC DNC DNC DNC Input/Output Row Column address address APD APD APD APD APD APD APD APD DNC DNC DNC DNC DNC DNC Input OPN VLD VLD VLD OPN DNC DNC Output VLD OPN IVD VLD VLD OPN OPN Refresh NO NO NO NO YES YES NO Remark Hyper page mode identical Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 4 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO IO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to Vss Ta=25°C Vcc Vss VIH VIL Parameter Min 3.0 0 2.0 -0.3 Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage Unit V mA W °C °C (Ta=0~70°C, unless otherwise noted) (Note 1) RECOMMENDED OPERATING CONDITIONS Symbol Ratings -0.5~4.6 -0.5~ 4.6 -0.5~ 4.6 50 21.6 0~70 -40~100 Limits Nom 3.3 0 Max 3.6 0 Vcc+0.3 0.8 Unit V V V V Note 1 : All voltage values are with respect to Vss ELECTRICAL CHARACTERISTICS Symbol (Ta=0~70°C, Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted) (Note 2) Parameter Test conditions VOH VOL IOZ II I I (RAS) High-level output voltage Low-level output voltage Off-state output current Input current (except /RAS) Input current (/RAS) Average supply ICC1 (AV) current from Vcc operating (Note 3,4,5) ICC2 IOH=-2mA IOL=2mA Q floating 0V≤VOUT≤Vcc 0V≤VIN≤Vcc+0.3, Other input pins=0V 0V≤VIN≤Vcc+0.3, Other input pins=0V -5 -6 Supply current from Vcc , stand-by Average supply current ICC4(AV) from Vcc Hyper-Page-Mode (Note 3,4,5) Average supply current from Vcc ICC6(AV) /CAS before /RAS refresh mode (Note 3) Min 2.4 0 -10 -10 -90 Limits Typ Max Vcc 0.4 10 10 90 /RAS, /CAS cycling tRC=tWC=min. output open /RAS=/CAS =VIH, output open 1820 -6 -5 -6 V V uA uA uA mA 1640 38 29 /RAS=/CAS=/WE ≥Vcc -0.2, output open -5 Unit /RAS=VIL,/CAS cycling tPC=min. output open /CAS before /RAS refresh cycling tRC=min. output open 1820 mA mA 1640 2360 mA 2180 Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Under condition of colmun address being changed once or less while /RAS=VIL and /CAS=VIH CAPACITANCE Symbol (Ta = 0~70°C, Vcc = 3.3V+/-0.3V, Vss = 0V, unless otherwise noted) Parameter CI (/RAS) Input capacitance, /RAS input CI Input capacitance, except /RAS input C(DQ) Input/Output capacitance,DATA MIT-DS-0271-0.0 Test conditions VI=Vss f=1MHZ Vi=25mVrms MITSUBISHI ELECTRIC ( 5 / 22 ) Min Limits Typ Max 80 15 18 Unit pF pF pF Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM SWITCHING CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15) Limits Symbol -5 Parameter Min tCAC tRAC tAA tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) Access time from /CAS Access time from /RAS Columu address access time Access time from /CAS precharge Access time from /OE Output hold time /CAS high Output hold time /RAS high Output low impedance time from /CAS low Output disable time after /OE high Output disable time after /WE high Output disable time after /CAS high Output disable time after /RAS high (Note 13) (Note 7) (Note 12) (Note 12) (Note 12,13) (Note 12,13) -6 Max 18 50 30 33 18 Min Unit Max 20 60 35 38 20 10 5 10 10 5 10 18 18 18 13 20 20 20 15 ns ns ns ns ns ns ns ns ns ns ns ns Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a /RAS-Only refresh or /CAS before /RAS refresh). Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods (greater than 64 ms) of /RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 1TTL loads and 50pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA). The reference levels for measuring of output signals are 2.0V (VOH) and 0.8V (VOL). 8: Assumes that tRCD≥tRCD(max), tASC≥tASC(max) and tCP≥tCP(max). 9: Assumes that tRCD≤tRCD(max) and tRAD≤tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD≥tRAD(max) and tASC≤tASC(max). 11: Assumes that tCP≤tCP(max) and tASC≥tASC(max). 12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT≤ I+/-10uAI) and is not reference to VOH(min) or VOL(max). 13: Output is disable after both /RAS and /CAS go to high TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles) (Ta=0~70°C, Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted ,see notes 14,15) Limits Symbol -5 Parameter Min tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tRDD tCDD tODD tT Refresh cycle time /RAS high pulse width Delay time, /RAS low to /CAS low Delay time, /CAS high to /RAS low Delay time, /RAS high to /CAS low /CAS high pulse width Column address delay time from /RAS low Row address setup time before /RAS low Column address setup time before /CAS low Row address hold time after /RAS low Column address hold time after /CAS low Delay time, data to /CAS low Delay time, data to /OE low Delay time, /RAS high to data Delay time, /CAS high to data Delay time, /OE high to data Transition time (Note16) (Note17) (Note18) (Note19) (Note19) (Note20) (Note20) (Note20) (Note21) 30 9 10 0 8 5 5 0 3 8 0 0 13 18 18 1 -6 Max 64 32 20 10 50 Min 40 9 10 0 10 7 5 0 5 10 0 0 15 20 20 1 Max 64 40 25 13 50 Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 14: The timing requirements are assumed tT =2ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. . 17: tRAD(max) is specified as a reference point only. If tRAD≥tRAD(max) and tASC≤tASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCD≥tRCD(max) and tASC≥tASC(max), access time is controlled exclusively by tCAC. 19: Either tDZC or tDZO must be satisfied. 20: Either tRDD or tCDD or tODD must be satisfied. 21: tT is measured between VIH(min) and VIL(max). MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 6 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Read and Refresh Cycles Limits Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL tORH tOCH Parameter Read cycle time /RAS iow pulse width /CAS iow pulse width /CAS hold time after /RAS iow /RAS hold time after /CAS iow Read Setup time after /CAS high Read hold time after /CAS iow Read hold time after /RAS iow Column address to /RAS hold time Column address to /CAS hold time /RAS hold time after /OE iow /CAS hold time after /OE iow -5 (Note 22) (Note 22) -6 Min Max Min Max 84 104 50 10000 60 10000 8 10000 10 10000 30 43 18 20 0 0 0 0 0 0 30 35 13 18 18 20 13 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns Note 22: Either tRCH or tRRH must be satisfied for a read cycle. Write Cycle (Early Write and Delayed Write) Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH Parameter Write cycle time /RAS iow pulse width /CAS iow pulse width /CAS hold time after /RAS iow /RAS hold time after /CAS iow Write setup time before /CAS low Write hold time after /CAS iow /CAS hold time after /W iow /RAS hold time after W iow Write pulse width Data setup time before /CAS iow or W iow Data hold time after /CAS iow or W iow -5 (Note 24) -6 Min Max Min Max 84 104 50 10000 60 10000 8 10000 10 10000 30 35 18 20 0 0 8 10 8 10 13 15 8 10 -5 -5 13 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns Read-Write and Read-Modify-Write Cycles Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tOEH -5 Parameter Read write/read modify write cycle time RAS iow pulse width CAS iow pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low Delay time, CAS iow to W iow Delay time, RAS iow to W iow Delay time, address to W iow OE hold time after W iow (Note23) (Note24) (Note24) (Note24) -6 Min Max Min Max 109 133 75 10000 89 10000 38 10000 44 10000 65 77 43 49 0 0 28 32 60 72 40 47 13 15 Unit ns ns ns ns ns ns ns ns ns ns Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 24: tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD≥tCWD(min), tRWD≥tRWD (min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min) (for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE goes back to VIH) is indeteminate. MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 7 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle, Read Write Mix Cycle,Hi-Z control by /OE or /WE) (Note 25) Limits Symbol tHPC tHPRWC tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Parameter -5 Hyper page mode read/write cycle time Hyper page mode read write/read modify write cycle time /RAS iow pulse width for read write cycle /CAS high pulse width /RAS hold time after /CAS precharge Delay time, /CAS precharge to W low Hold time to maintain the data Hi-Z until /CAS access /OE Pulse Width (Hi-Z control) /W Pulse Width (Hi-Z control) Delay time, /CAS low to /W low after read Delay time, Address to /W low after read Delay time, /CAS precharge to /W low after read Delay time, /CAS low to /OE high after read Delay time, Address to /OE high after read Delay time, /CAS prechargeto /OE high after read (Note26) (Note27) (Note24) -6 Min Max Min Max 20 25 55 66 65 100000 77 100000 8 15 10 18 33 38 43 50 7 7 7 7 7 7 28 32 40 47 43 50 13 15 25 30 28 33 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 26: tRAS(min) is specified as two cycles of CAS input are performed. 27: tCP(max) is specified as a reference point only. /CAS before /RAS Refresh Cycle (Note 28) Limits Symbol tCSR tCHR tRSR tRHR Parameter -6 -5 Min 10 5 15 5 /CAS setup time before /RAS low /CAS hold time after /RAS low Read setup time before /RAS low Read hold time after /RAS low Max Min 10 5 15 5 Unit Max ns ns ns ns Note 28: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh mode. MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 8 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Timing Diagrams Read Cycle (Note 29) tRC tRAS /RAS tRP VIH VIL tCSH tCRP tRCD tCRP tRSH tCAS VIH /CAS VIL tRAL tCAL tRAD tASR A0~A12,B0 VIH VIL tRAH tASC ROW ADDRESS tASR tCAH ROW ADDRESS COLUMN ADDRESS tRRH tRCH tRCS /W VIH VIL tCDD tDZC DQ (INPUTS) tRDD VIH Hi-Z VIL tREZ tCAC tAA tOHR tCLZ DQ (OUTPUTS) tWEZ tOFF tOHC VOH Hi-Z VOL Hi-Z DATA VALID tRAC tDZO tOEA tOCH tOEZ tODD VIH /OE VIL tORH Indicates the don't care input. VIH(min)≤VIN≤VIH(max) or VIL(min)≤VIN≤VIL(max) Note 29 Indicates the invalid output. MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 9 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Early Write Cycle tWC tRAS tRP VIH /RAS VIL tCSH tCRP tRCD tRSH tCAS tCRP VIH /CAS VIL tASR VIH A0~A12,B0 VIL tASR tRAH tASC tCAH ROW ADDRESS COLUMN ADDRESS ROW ADDRESS tWCS tWCH VIH /W VIL tDS VIH DQ (INPUTS) DQ (OUTPUTS) tDH DATA VALID VIL VOH Hi-Z VOL VIH /OE VIL MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 10 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Delayed Write Cycle tWC tRP tRAS /RAS VIH VIL tCRP tCSH tCRP tRSH tRCD tCAS VIH /CAS VIL tASR VIH A0~A12,B0 VIL tRAH tCAH tASC ROW ADDRESS tASR ROW ADDRESS COLUMN ADDRESS tCWL tRWL tWP tRCS /W VIH VIL tWCH tDZC DQ (INPUTS) VIH tDS tDH DATA VALID Hi-Z VIL tCLZ DQ (OUTPUTS) VOH Hi-Z Hi-Z VOL tDZO tOEZ tOEH tODD /OE VIH VIL MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 11 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Read-Write, Read-Modify-Write Cycle tRWC tRAS tRP VIH /RAS VIL tCRP tCSH tRCD tCRP tRSH tCAS VIH /CAS VIL tRAD tASR VIH A0~A12,B0 VIL tRAH tCAH tASC tASR COLUMN ADDRESS ROW ADDRESS ROW ADDRESS tAWD tCWD tRWD tRCS tCWL tRWL tWP VIH /W VIL tDH tDS tDZC DQ (INPUTS) VIH Hi-Z VIL DATA VALID tCAC tAA tCLZ DQ (OUTPUTS) VOH DATA VALID Hi-Z VOL tRAC Hi-Z tODD tDZO tOEA tOEH tOEZ /OE VIH VIL MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 12 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle tRAS tRP VIH /RAS VIL tCSH tCRP tCAS tRCD tCP tHPC tCAS tCP tRSH tCAS tASC tCAH tASC VIH /CAS VIL tRAD tASR VIH A0~A12,B0 VIL tRAH ROW ADDRESS tCAH tASC COLUMN-2 COLUMN-1 tCPRH tCAH tASR ROW ADDRESS COLUMN-3 tRCS tRRH tCAL tCAL tCAL tRCH VIH /W VIL tWEZ tDZC DQ (INPUTS) tRDD tCDD VIH Hi-Z tCAC VIL tAA tCLZ DQ (OUTPUTS) VOH VOL tRAC tDZO VIL /OE tAA tAA tDOH tDOH DATA VALID-1 Hi-Z tCAC tCAC tCPA DATA VALID-2 tREZ tOHR tOFF tOHC DATA VALID-3 tCPA tOEA tOCH tOEZ VIH tODD MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 13 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Early Write Cycle tRAS tRP VIH /RAS VIL tCSH tCRP tCAS tRCD tCP tHPC tCAS tASC tCAH tRSH tCP tCAS tCRP VIH /CAS VIL tCAL tASR VIH A0~A12,B0 VIL tRAH ROW ADDRESS tASC tCAH COLUMN-2 COLUMN-1 tWCS tWCH tWCS tWCH tASC tCAL tCAH COLUMN-3 tWCS tASR ROW ADDRESS tWCH VIH /W VIL tDS DQ (INPUTS) DQ (OUTPUTS) VIH VIL tDH tDS tDH DATA VALID-2 DATA VALID-1 tDS tDH DATA VALID-3 VOH Hi-Z VOL VIL /OE VIH MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 14 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Read-Write,Read-Modify-Write Cycle tRAS tRP VIH /RAS VIL tCSH tCRP tRCD tRWL tCRP tHPRWC tCAS tCAS tCP VIH /CAS VIL tRAD tASR VIH A0~A12,B0 VIL tRAH tCAH tASC ROW ADDRESS tASC COLUMN-1 tASR ROW ADDRESS COLUMN-2 tAWD tRCS tCWL tCAH tAWD tCWL tCWD tRCS tCWD tWP tWP VIH /W VIL tRWD tDZC DQ (INPUTS) tCPWD tDS VIH tDZC tCLZ tCLZ VOH DATA VALID-1 Hi-Z VOL tRAC tDZO tODD tOEA tCPA tDZO tOEZ MIT-DS-0271-0.0 DATA VALID-2 Hi-Z VIH /OE DATA VALID-2 Hi-Z tCAC tAA tAA DQ (OUTPUTS) tDH tDS DATA VALID-1 Hi-Z tCAC VIL tDH tOEA Hi-Z tODD tOEH tOEZ VIL MITSUBISHI ELECTRIC ( 15 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Mix Cycle (1) tRP tRAS /RAS tRWL VIH VIL tCRP tCSH tHPC tCRP tCAS tRCD tHPRWC tCAS tCP tCP tCAS VIH /CAS tCWL VIL tRAD tASR A0~A12,B0 VIH VIL tRAH ROW ADDRESS tASC tCAH tASC tCAL ROW ADDRESS COLUMN-3 tCPWD tAWD tWCH tWCS tASR tASC tCAH COLUMN-2 COLUMN-1 tRCS /W tCAH tCAL tCWD tWP VIH VIL tDZC DQ (INPUTS) VIH tDZ tDS C DATA VALID-2 tCAC VIL tDH tDS DATA VALID-3 tAA tCAC tAA tWEZ tCLZ DQ (OUTPUTS) VOH DATA VALID-3 VOL tRAC tDZO tCPA tOEA tOEZ VIL /OE tCLZ DATA VALID-1 Hi-Z tDH tDZO tOEA tOEZ tOEH tOCH VIH tODD MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 16 / 22 ) tODD Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Mix Cycle (2) VIH /RAS VIL tHPC VIH /CAS VIL tCP tASC tCAS tCAS tCAH tASC tCAH tASC tCAH VIH COLUMN-1 A0~A12,B0 COLUMN-2 COLUMN-3 VIL tCAL tRCH tCAL tWCS tWCH VIH /W tHCWD VIL tHAWD tDH tDS tHPWD tDZC VIH DQ (INPUTS) DATA VALID-2 Hi-Z tCAC VIL tAA tCAC Hi-Z tAA tCPA tWEZ tCPA tCLZ DQ (OUTPUTS) VOH DATA VALID-1 VOL DATA VALID-3 Hi-Z tHCOD tHAOD VIL /OE MIT-DS-0271-0.0 tDZC tOEZ tOEA tODD tHPOD VIH MITSUBISHI ELECTRIC ( 17 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle ( Hi-Z control by OE ) tRAS tRP VIH /RAS VIL tCSH tCRP tCAS tRCD tCP tHPC tCAS tRSH tCAS tCP tCRP VIH /CAS VIL tRAD tASR VIH A0~A12,B0 VIL tRAH tASC ROW ADDRESS tASC tCAH COLUMN-1 tCAH tASC COLUMN-2 tCPRH tCAH tASR ROW ADDRESS COLUMN-3 tRAL tRRH tRCS tRCH VIH /W VIL tWEZ tDZC DQ (INPUTS) tRDD tCDD VIH tCAC tCAC VIL tAA tCLZ DQ (OUTPUTS) VOH DATA VALID-1 Hi-Z VOL tRAC tDZO VIL /OE Hi-Z tAA tCAC tAA tDOH tCLZ DATA VALID-1 DATA VALID-2 tOCH DATA VALID-3 tCPA tCPA tOEZ tOEA Hi-Z tREZ tOHR tOFF tOHC tCHOL tOEZ tOEZ tOEA VIH tOEPE MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 18 / 22 ) tOEPE tODD Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle ( Hi-Z control by W ) tRAS tRP VIH /RAS VIL tCSH tCRP tCAS tRCD tHPC tCAS tCP tRSH tCAS tCP tCRP VIH /CAS VIL tRAD tASR VIH A0~A12,B0 VIL tRAH ROW ADDRESS tASC tCAH tASC tASC tCAH COLUMN-2 COLUMN-1 tCPRH tCAH ROW ADDRESS COLUMN-3 tRAL tRCS tASR tRCH tRCS tRRH tRCH VIH /W VIL tDZC tWPE VIH DQ (INPUTS) tCAC tCAC VIL tAA tDOH VOH VIL /OE tCAC tAA tWEZ DATA VALID-2 DATA VALID-1 Hi-Z VOL tRAC tDZO Hi-Z tAA tCLZ DQ (OUTPUTS) tRDD tCDD tCPA tOEA tOCH tCLZ Hi-Z tREZ tOHR tOFF tOHC DATA VALID-3 tCPA tOEZ VIH tODD MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 19 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM /CAS before /RAS Refresh Cycle tRC tRP /RAS tRC tRAS tRAS tRP VIH VIL tRPC tCSR /CAS tCHR tRPC tCSR tCHR tRPC tCRP VIH VIL tCPN tASR VIH ROW ADDRESS A0~A12,B0 VIL COLUMN ADDRESS tRRH tRCH /W tRCS VIH VIL DQ (INPUTS) VIH VIL DQ (OUTPUTS) tREZ tOHR tOFF tOHC VOH Hi-Z VOL tOEZ VIH /OE VIL MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 20 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 31) tRC tRAS /RAS tRC tRP tRAS tRP VIH VIL tCRP tRCD tRSH tCHR VIH /CAS VIL tRAD tASR A0~A12,B0 VIH VIL tRAH tASC COLUMN ADDRESS ROW ADDRESS tRCS /W tASR tCAH ROW ADDRESS tRRH tRAL tRCH VIH VIL tCDD tDZC tRDD DQ (INPUTS) VIH Hi-Z VIL tCAC tAA tOFF tOHC tCLZ DQ (OUTPUTS) tREZ tOHR VOH Hi-Z Hi-Z DATA VALID VOL tRAC tDZO tOEA tORH tOEZ tODD VIH /OE VIL Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. MIT-DS-0271-0.0 MITSUBISHI ELECTRIC ( 21 / 22 ) Oct.1.1998 MITSUBISHI LSIs Preliminary Spec. MH16V725BATJ -5, -6 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM Package Outline Unit:mm 133.35 3.0 3.52MAX 127.35 4.0 3.0 17.78 31.75 17.78 3.0 4.0 2- +/-2.0 2.0 2- +/-3.0 2.0 6.35 1.27 6.35 29x1.27=36.83 8.89 43x1.27=54.61 9x1.27=11.43 23.50 MIT-DS-0271-0.0 43.18 MITSUBISHI ELECTRIC (22 / 22 ) Oct.1.1998