Micrel MIC9130BM High-voltage, high-speed telecom dc-to-dc controller Datasheet

MIC9130
Micrel, Inc.
MIC9130
High-Voltage, High-Speed Telecom DC-to-DC Controller
General Description
Features
The MIC9130 is a current-mode PWM controller that efficiently
converts –48V telecom voltages to logic levels. The MIC9130
features a high voltage start-up circuit that allows the device to
be connected to input voltages as high as 180V. The high input
voltage capability protects the MIC9130 from line transients
that are common in telecom systems. The start-up circuitry
also saves valuable board space and simplifies designs by
integrating several external components.
The MIC9130 is capable of high speed operation. Typically
the MIC9130 can control a sub-25ns pulse width on the gate
out pin. Its internal oscillator can operate over 2.5MHz, with
even higher frequencies available through synchronisation.
The high speed operation of the MIC9130 is made safe by
the very fast, 34ns response from current sense to output,
minimizing power dissipation in a fault condition.
The MIC9130 allows for the designs of high efficiency power
supplies. It can achieve efficiencies over 90% at high output
currents. Its low 1.3mA quiescent current allows high efficiency
even at light loads.
The MIC9130 has a maximum duty cycle of 50%. For designs requiring a high duty cycle, refer to the MIC9131. The
MIC9130 is available in a 16-pin SOP and 16-pin QSOP
package options. The rated junction temperature range is
from –40°C to +125°C.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Typical Application
MBR0540�
40V/0.5A
12V
Input voltages up to 180V
Internal oscillator capable of >2.5MHz operation
Synchronisation capability to 4MHz
Current sense delay of 34ns
Minimum pulse width <25ns
90% efficiency
1.3mA quiescent current
1µA shutdown current
Soft-start
Resistor programmable current sense threshold
Selectable soft-start retry
4Ω sink, 12Ω source output driver
Programmable under-voltage lockout
Constant-frequency PWM current-mode control
16-pin SOIC and 16-pin QSOP
Applications
•
•
•
•
•
Telecom power supplies
Line cards
ISDN network terminators
Micro- and pico-cell base stations
Low power (< 30W) dc-dc converters
20Ω
T1
N=5
1µF
16V
VIN
36V to 72V
2.5µH
0.1µF
1M
N = 20
N=4
Si4800DY
20k
7
6
1.21k
5
8
3
332k
12
9
0.1µF
10
SYNC
CPWR
MIC9130
OUT
ISNS
VBIAS
OSC
AGND
11
FQD10N20
0.2Ω
200V
16
Slope
Compensation
RBIAS
SS
330µF (x2)
6.3V
Si4884DY
FB
COMP
4
10nF
2
EN
LINE
1
UVLO
13
VCC
B330
38.3k
VOUT
3.3V @ 4A
14
332k
0.2Ω
1W
PGND
15
4.75k
47pF
OPTO
FEEDBACK
1.5MHz DSL Power Supply
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 2005
1
M9999-040805
MIC9130
Micrel, Inc.
Ordering Information
Part Number
Max. Duty Cycle
Junction Temp. Range
Package
Standard
Pb-Free
MIC9130BM
MIC9130YM
50%
-40°C to +125°C
16-Pin SOP
MIC9130BQS
MIC9130YQS
50%
-40°C to +125°C
16-Pin QSOP
Pin Configuration
LINE 1
16 OUT
VCC 2
15 PGND
14 ISNS
RBIAS 3
13 UVLO
OSC 4
12 SS
SYNC 5
11 AGND
COMP 6
10 EN
FB 7
9 VBIAS
CPWR 8
16-Pin SOP (M)
16-Pin QSOP (QS)
Pin Description
Pin Number
Pin Name
Pin Function
1
LINE
Line (Input): 180Vdc maximum supply input. May be floated if unused.
2
VCC
Supply (Input): MIC9130 internal supply input.
3
RBIAS
4
OSC
5
SYNC
Synchronization (Input): External oscillator input for slave operation of
controller. See OSC. Do not float.
6
COMP
Compensation (External Components): Error amplifier output for external
compensation network connection.
7
FB
8
CPWR
Current Limit Selection (Input): When CPWR is high, an over-current
condition at the ISNS input will terminate the gate drive and reset the
soft-start latch. If the CPWR pin is low, an over-current condition at the ISNS
input will terminate the gate drive signal, but will not cause a reset of the
soft-start circuit.
9
VBIAS
Reference (Output): Internal 5V supply. Will source 5mA maximum.
10
EN
11
AGND
12
SS
Soft-Start (External Components): Connect external capacitor to slowly ramp
up duty cycle during startup and over-current conditions.
13
UVLO
Undervoltage Lockout (External Components): Connect to unbiased resistive
divider network to set controller’s minimum operating voltage. Connect to
VBIAS if not needed.
14
ISNS
Current Sense (Input): Connect between external switching MOSFET source
and switch current sense resistor.
15
PGND
Power Ground (Return)
16
OUT
M9999-040805
Bias Resistor (External Component): Connect 562KΩ to ground.
Oscillator RC Network (External Components): Connect external resistorcapacitor network to set oscillator frequency.
Feedback (Input): Error amplifier inverting input.
Enable (Input): Logic level enable/shutdown input; logic high = enabled (on),
logic low = shutdown (off).
Analog Ground (Return)
Switch Drive Output (Output): Connect to gate of external switching
MOSFET.
2
April 2005
MIC9130
Micrel, Inc.
Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 2)
Line Input Voltage (VLINE) ......................................... +190V
VCC Input Voltage (VCC) .............................................. +19V
Current Sense Input Voltage (VISNS) .............. –0.3 to +5.3V
Enable Voltage (VEN) ............................ –0.3 to VCC + 0.3V
Feedback Input Voltage (VFB) ........................ –0.3 to +5.3V
Sync Input Voltage (VSYNC) ............................ –0.3 to +5.3V
Soft-Start Voltage (VSS) .................................. –0.3 to +5.3V
UVLO Voltage (VUVLO) ................................... –0.3 to +5.3V
Storage Temperature (TS) ........................ –65°C to +150°C
Power Dissipation (PD)
16-pin SOP ...................................400mW @ TA = +85°C
16-pin QSOP ................................245mW @ TA = +85°C
ESD Rating, Note 3
Line Input Voltage (VLINE) .................VCC to +180V, Note 4
VCC Input Voltage (VCC) .................................. +9V to +18V
Junction Temperature Range (TJ) ............ –40°C to +125°C
Package Thermal Resistance
16-pin SOP (θJA) .............................................. 100°C/W
16-pin QSOP (θJA) ............................................ 163°C/W
Electrical Characteristics
TA = 25°C, VLINE = 48V, VCC = 10V, Rt = 9.47KΩ, Ct = 470pF, RBIAS = 562kΩ, VEN = 10V, VISNS = 0V, VUVLO = 2V, VSYNC = 0V, unless
otherwise noted. Bold values indicate –40 °C ≤TJ ≤ +125°C.
Parameter
Condition
Min
Typ
Max
Units
Output Voltage
IVBIAS = 0mA; VOSC = 0V (Oscillator OFF)
4.7
4.85
5.0
V
Line Regulation
9V ≤ VCC ≤18V, IVBIAS = 0mA; VOSC = 0V
Bias Regulator
Load Regulation
Oscillator Section
Initial Accuracy (fOSC)
Oscillator Output Frequency
4.6
0mA ≤ IVBIAS ≤ 5mA; VOSC = 0V
Rt = 9.47KΩ, Ct = 470pF
180
Maximum Duty Cycle
Voltage Stability (Δf/f)
9V ≤ VCC ≤18V
Temperature Stability
ppm/°C
–40°C ≤ TJ ≤ 125°C
Maximum Sync Frequency
Note 5
5.1
V
24
40
mV
5
30
mV
200
220
kHz
fOSC/2
kHz
50
%
2.5
%
100
4
MHz
Sync Threshold Level
2.5
V
Sync Hysteresis
0.7
V
Sync Minimum Pulse Width
50
ns
Error Amp Section
FB Voltage
VCOMP = VFB
2.475
2.45
Open Loop Voltage Gain, AVOL
Unity Gain Bandwidth
PSRR
COMP Sink Current
COMP Source Current
9V ≤ VCC ≤ 18V
VFB = 2.7V; VCOMP = 5V
80
VFB = 2.3V; VCOMP = 0V
1
2.5
2.525
2.55
V
90
dB
4
MHz
60
dB
100
µA
2.5
VFB = 2.7V; ICOMP = –50µA
4
V
Input Bias Current (IFB)
VFB = VCOMP
160
nA
SINK
1.5
V/µs
SOURCE
1.5
V/µs
VCOMP High
Slew Rate
April 2005
115
mA
VCOMP Low
VFB = 2.3V; ICOMP = +500µA
3.5
3
300
mV
M9999-040805
MIC9130
Parameter
Micrel, Inc.
Condition
Min
Typ
Max
Units
0.1
10
µA
Preregulator
Input Leakage Current
VLINE = 180V, VCC = 10V
VCC Gate Lockout (VGLO(ON))
VLINE = 48V
7.2
7.5
V
VLINE = 48V
700
800
mV
VCC Pre-Regulator Off (VPR(OFF))
VLINE = 48V
7.7
VGLO(ON)
V
VCC Pre-Regulator Hysteresis
(ΔVPR)
VLINE = 48V
500
700
mV
9
12
mA
1.3
1.5
mA
–10
0.1
10
µA
0.1
10
µA
0.83
0.888
VCC Gate Lockout Hysteresis
(ΔVGLO)
Start-up Current
Supply
VLINE = 48V, VCC = 7.5V, Note 4
Supply Current, IVCC
Pin 16 (OUT) = OPEN
Shutdown Supply Current
VEN = 0V ; VCC = 18V
Enable Input Current
Protection and Control
VEN = 0V ,10V; VLINE = 48V
0.772
Current Limit Threshold Voltage
Current Limit Delay to Output
Current Limit Source Current
Enable Input Threshold (Turn-on)
VISNS = 0V to 5V
34
CPWR Threshold
Soft-Start Current
Line UVLO Threshold (Turn-on)
V
ns
VISNS = 0V
30
40
50
µA
1
1.6
2.2
V
VCPWR = 5V, 0V
–1
VSS = 0V
2.5
1.16
Enable Input Hysteresis
CPWR Input Current
+0.5V
150
mV
+1
µA
4
6
µA
1.22
1.28
1.6
V
V
Line UVLO Threshold Hysteresis
140
mV
Thermal Shutdown
145
°C
Thermal Shutdown Hysteresis
25
°C
VISNS = 5V
21
ns
8
12
Ω
SINK ; ISINK = 200mA
4
6
Ω
MOSFET Driver
Output Minimum On-Time
Output Driver Impedance
Rise Time
Fall Time
SOURCE ; ISOURCE = 200mA
COUT = 500pF
COUT = 500pF
12
ns
8
ns
Note 1.
Exceeding the absolute maximum rating may damage the device.
Note 2.
The device is not guaranteed to function outside its operating rating.
Note 3.
Devices are ESD sensitive. Handling precautions recommended.
Note 4.
If a substained DC voltage >150V is applied to the LINE pin, a current-limiting 1.8kΩresistor should be used in series with the LINE pin. This
condition does not apply for transient conditions over 150V.
Note 5.
For oscillator frequencies above 2.5MHz it may be necessary to power to VBIAS pin from an external power source due to the current limitations of the internal 5V regulator. See Applications Information for details
M9999-040805
4
April 2005
MIC9130
Micrel, Inc.
Typical Characteristics
5
0
-0.5
-1.0
-1.5
Error Amp Reference
Voltage vs. Temperature
REFERENCE VOLTAGE (V)
CC
= 10V
0
40
80
120
TEMPERATURE (°C)
160
Line UVLO Threshold
vs. VCC
1.220
THRESHOLD (V)
Quiescent Current
vs. VCC Voltage
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
R = 9.47K
t
C = 470pF
t
2.0
1.8
1.6
1.4
1.2
8
10
12
14
VCC (V)
16
18
1.19
3.5
1.34
1.33
1.32
1.31
1.3
-40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
C = 470pf
t
fOSC = 200kHz
2.5
2
1.5
Quiescent Current
vs. Frequency
C = 470pF
t
Ct = 120pF
200 400 600 800 1000
GATE DRIVE FREQUENCY (kHz)
300
70
60
50
40
30
0
0
160
350
80
250
200
150
100
50
10
200 400 600 800 1000 1200
RBIAS (kΩ)
10
9
8
7
6
5
4
3
2
1
0
0
0
40
80
120
TEMPERATURE (°C)
ISNS to Gate Output Delay
vs. Overdrive
90
20
0
1.18
-40
ISNS to Gate Output Delay
vs. R BIAS
VC C = 10V
Rt = 9.53K
3
8 9 10 11 12 13 14 15 16 17 18
VCC (V)
1.4
V = 10V
1.39 C C
R
= 560K
1.38 B IAS
R = 9.47K
1.37 t
C = 470pF
1.36 t
1.35
Quiescent Current
vs. RBIAS
VC C=10V
RB IAS=560K
1.2
Quiescent Current
vs. Temperature
RB IAS = 560K
2.2
1.24
DELAY (ns)
2.4
Line UVLO Threshold
vs. Temperature
1.21
1.185
1.180
8 9 10 11 12 13 14 15 16 17 18
VCC (V)
1.22
1.190
2.480
-40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
2.499
1.23
1.195
2.485
QUIESCENT CURRENT (mA)
-4
2.500
1.200
2.490
April 2005
-3
1.205
2.495
1
VC C = 10V
RB IAS = 560K
R = 9.47K
t
C = 470pF
t
-2
1.210
2.500
1.0
-1
1.215
2.505 RB IAS = 560K
RB IAS = 560K
2.501
1
0
UVLO THRESHOLD (V)
V
2
QUIESCENT CURRENT (mA)
2.510
2.502
4
3
-5
-40
8 9 10 11 12 13 14 15 16 17 18
VCC (V)
DELAY (ns)
-2.0
Error Amp Reference
Voltage vs. VCC Voltage
200 400 600 800 1000 1200
RBIAS (kΩ)
5
0
RB IAS=560K
RB IAS=360K
RB IAS=160K
0
200
400
600
800
1000
1200
1400
1600
1800
2000
FOSC (NOM)=200kHz
1.5 R =9.47K
t
1.0 Ct=470pF
0.5
OSC FREQ. VARIATION (%)
OSC FREQ. VARIATION (%)
2.0
Oscillator Frequency
vs. Temperature
REFERENCE VOLTAGE (V)
Oscillator Frequency
vs. V CC Voltage
OVERDRIVE (mV)
M9999-040805
MIC9130
Micrel, Inc.
5.06
RB IAS = 560K
5.04
BIAS VOLTAGE (V)
5.006
5.02
5.002
5.000
4.998
8 9 10 11 12 13 14 15 16 17 18
VCC (V)
ISNS Current Limit Threshold
vs. VCC Voltage
822.0
7.8
Vcc G LO On
7.4
7.2
7
Vcc G LO Off
6.8
821.0
820.5
820.0
819.5
819.0
6.6
818.5
6.4
-40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
818.0
8 9 10 11 12 13 14 15 16 17 18
VCC (V)
Enable Threshold
vs. VCC
Gate Drive Current
vs. VCC
SINK/SOURCE CURRENT (A)
2
1.95
1.9
1.85
1.8
1.75
1.7
1.65
1.6
1.55
1.5
8 9 10 11 12 13 14 15 16 17 18
VCC (V)
2.5
2.3
S I NK
2.1
1.9
1.7
1.5
1.3
1.1
S OURC E
0.9
0.7
0.5
8 9 10 11 12 13 14 15 16 17 18
VCC (V)
80
10
70
65
60 –40°C
55 25°C
50
M9999-040805
40
120
80
VLINE (V)
160
200
4.95
8
6
VC C=7.5V
125°C
40
120
80
VLINE (V)
6
160
0
1
2
3
IBIAS (mA)
4
5
ISNS Current Limit Threshold
vs. Temperature
840
VC C= 10V
RB IAS= 560K
835
830
825
820
815
-40
0
40
80
120
TEMPERATURE (°C)
160
Peak Short Circuit Depletion
FET Current vs. Temperature
–40°C
25°C
4
0
0
4.94
Depletion FET Current
vs. VLINE
2
45 125°C
40
0
12
VC C = 0V
CURRENT (mA)
SHORT CIRCUIT CURRENT (mA)
Peak Short Circuit Depletion
FET Current vs. V LINE
75
4.96
RB IAS=560K
821.5
THRESHOLD (mV)
VC C=10V
7.6 R
=560K
B IAS
THRESHOLD (V)
4.97
VC C = 10V
RB IAS = 560K
Rt = 9.47K
C = 470pF
t
4.94
-40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
VCC Turn On/Off Thresholds
vs. Temperature
THRESHOLD VOLTAGE (V)
5
4.96
4.992
4.990
4.98
4.98
4.996
4.994
VC C = 10V
4.99
THRESHOLD (mV)
VBIAS (V)
5.004
Bias Voltage Load
Regulation
5
SHORT CIRCUIT CURRENT (mA)
5.008
CURRENT (mA)
5.010
5V VBIAS Voltage
vs. Temperature
BIAS VOLTAGE (V)
VBIAS vs. VCC
80
75
180V Line
VC C = 0V
70
65
60
55 48V Line
50
45
40
-40
10
9
8
7
6
5
4
3
2
1
0
7
0
40
80
120
TEMPERATURE (°C)
160
Depletion FET Current
vs. Low VLINE Voltage
–40°C
25°C
125°C
7.5
8
8.5
9
VLINE (V)
9.5
10
April 2005
MIC9130
ISNS CURRENT (µA)
ISNS Pin Source Current
vs. VCC
RB IAS=560K
41
40.5
40
39.5
39
38.5
38
8
April 2005
ISNS Pin Source Current
vs. Temperature
ISNS CURRENT (µA)
42
41.5
Micrel, Inc.
10
12
14
VCC (V)
16
18
45
44 RB IAS=560K
43 VC C=10V
42
41
40
39
38
37
36
35
-40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
7
M9999-040805
MIC9130
Micrel, Inc.
Oscillator Frequency vs.
RC Values
1000000
RESISTOR VALUE (Ω)
47pF
100p F
100000 220p F
470p F
680p F
1000p F
10000 2200p F
1000
10000
100000 1000000 10000000
FREQUENCY (Hz)
*See applications section for higher
switching frequencies
Functional Block Diagram
FB
COMP
7
6
OSC
4
SYNC
5
Oscillator
1.2V
R
5V
40µA
ISNS 14
VBIAS
EN
S1
16
OUT
15
PGND
11
AGND
0.82V
BIAS
REG
10
RBIAS 3
Peak
Current Limit
1.21V
5V
SS
Q
S2
PWM
9 5V
VCC
SR Latch
2.5V
Error
Amplifier
2
4µA
MAXIMUM DUTY CYCLE
12
Max.
Duty Cycle
Current
Limit
Selection
CPWR 8
Q
R1
R2
VCC 2
S
1-Shot
VCC
UVLO
LINE 1
UNDERVOLTAGE LOCKOUT
Thermal
Shutdown
LINE
UVLO
13
UVLO
Figure 1
M9999-040805
8
April 2005
MIC9130
Micrel, Inc.
Functional Description
• Control loop operation
• Current sensing & overcurrent protection
• Slope compensation
• Error amplifier
High Voltage Start Up Circuit
Many conventional Off-Line and Telecom power supplies
use an external bias resistor and zener diode to supply the
initial start-up voltage for the control IC. The control IC gets
its supply voltage from a bias winding once the power supply is running. This method has the disadvantages of extra
components (diode and power resistor), continuous power
dissipation in the resistor and a large bias capacitor, used to
supply the IC until the bias winding takes over.
The MIC9130 eliminates these problems by using an internal
depletion mode MOSFET as a pre-regulator to provide the
start-up bias voltage from the high voltage input of the power
supply. This approach eliminates the need for external start
up components and reduces the size of the controller’s bias
supply capacitor. The MOSFET is turned off once the external
bias winding takes over, which eliminates power dissipation
in the start-up circuit. In some cases, the MIC9130 may be
run directly from the input voltage rail, eliminating the need
for an external bias winding.
Micrel’s MIC9130 is a high voltage, high speed current mode
switching power supply controller. It uses a BiC/DMOS process to achieve a high voltage input, low quiescent current
and very fast internal delay times. The MIC9130 is designed
to drive an external low side N-channel MOSFET, which
makes it suitable for controlling Boost, Flyback and Forward
converter topologies. The high voltage startup pin eliminates
the requirement for an external start up circuit. This makes
it ideal for use with Telecom converters.
A block diagram of the MIC9130 is shown in Figure 1. The description of the controller is divided into 6 basic functions:
• Power and bias circuitry
• High voltage start-up circuit
• VCC and bias supplies
• Enable and undervoltage monitoring circuits
• VCC and VIN UVLO
• Enable
• Oscillator and sync circuitry
• Soft-start and soft-start reset circuits
• MOSFET gate drive circuits
Transformer
Bias
Winding
MIC9130
Internal
Circuitry
VCC
2
VIN
Line
1
1.21V
180V
DEPLETION
FET
VCC
UVLO
THERMAL
SHUTDOWN
VPR(OFF) Depletion FET Pre-Regultor turn-off threshold
∆VPR
∆VGLO VCC Gate Lockout Hysteresis
Depletion FET turn-on threshold
VGLO(ON) VCC gate lockout turn on threshold
VCC voltage when powered from VLINE
Figure 2
April 2005
9
M9999-040805
MIC9130
Micrel, Inc.
Start-up circuit operation is illustrated in Figure 2. VIN is applied and the depletion FET, which is normally enabled allows
current from VIN to charge the VCC bias capacitor. Once the
VCC voltage reaches the VCC enable threshold, VGLO(ON) ,
the gate drive is enabled and the MIC9130 starts switching.
VCC continues to increase until the Pre-Regulator turn-off
threshold, (VPR(OFF)), is reached and the depletion FET is
turned off. The VCC voltage decreases as energy from the
bias capacitor is used to supply the controller. The depletion FET is turned back on when the pre-regulator turn-on
threshold is reached. A bias winding derived supply voltage,
set higher than the FET turn-off threshold, VPR(OFF), raises
the VCC voltage over the threshold and prevents the FET
from turning on.
In certain designs the MIC9130 may be powered directly from
the Line voltage, eliminating the need for an extra transformer
bias winding. When operating in this fashion the designer
must insure the power dissipation in the IC does not cause
the die temperature to exceed the 125°C maximum. Power
dissipation is calculated by:
for most topologies since the variation is small (equal to the
ΔVPR hysteresis). The bias regulator in the MIC9130 buffers
the internal circuits from VCC variations.
The pre-regulator FET is protected by a thermal shutdown
circuit, which turns the MOSFET off if its temperature exceeds
approximately 150 degrees C.
When operating at input voltages greater than 150V, a fast
input voltage risetime during turn-on (which may occur during
a hot plug operation) may cause a high peak current to flow
through the depletion FET, damaging the MIC9130. A 1.8kΩ
resistor in series between the input voltage and the line pin
(pin 1) is recommended when operating at input voltages
greater than 150V. This resistor limits the maximum peak
current to 100mA (at 180VIN) and protects the part.
The depletion mode MOSFET contains an internal parasitic
diode. The VIN pin voltage must be greater than the VCC
voltage or the VCC voltage will be clamped to a diode drop
greater than the VIN voltage. Excessive power dissipation in
the parasitic diode will destroy the IC.
VCC and Bias Supplies
The power for the controller and gate drive circuitry is supplied through the VCC pin. The gate drive current is returned
to ground through the power ground pin (PGND). The rest of
the supply current is returned to ground through the analog
ground pin (AGND). The two ground pins must be connected
together through the PCB ground plane.
High frequency decoupling is provided at the VCC pin to supply the gate drive’s peak current requirements. Turn-on of the
external MOSFET causes a voltage glitch on the VCC pin. If
the glitch is excessive, this disruption can appear as noise or
jitter in the oscillator circuit or the gate drive waveform. The
decoupling capacitor must be able to supply the MOSFET
gate with the charge required to turn it on. A 0.1µF ceramic
capacitor is usually sufficient for most MOSFETs. Larger
FETs, with a higher gate charge requirement may require a
0.22µF ceramic capacitor or a ceramic capacitor paralleled
with a 2.2µF tantalum or 4.7uF aluminum electrolytic. It is
recommend that if VLINE is greater than 150V DC than the
maximum capacitor recommended on VCC is 2.2µF.The capacitor must be located next to the VCC pin of the MIC9130.
The ground end of the capacitor should be connected to the
ground plane, making a low impedance connection to the
power ground pin (pin 15).
The internal bias regulator block provides several internal and
external bias voltages. Referring to Figure 1, a 2.5V reference is used for the internal error amplifier, a 0.82V bias is
used by the current limit comparator and a 1.21V reference
is used by the Line UVLO circuit. An external 5V bias voltage (VBIAS) powers the oscillator circuit and may be used
as a reference voltage for other external components. The
VBIAS pin requires a minimum 0.1µf capacitor to ground for
decoupling.
Enable and Undervoltage Monitoring circuits
The two undervoltage lockout circuits in the MIC9130 are
shown in Figure 4. One monitors the VCC voltage and the
other monitors the input line voltage. These signals are OR’d
together and either one can disable the gate drive pin and
discharge the voltage on the soft start capacitor.
PDISS = ( VIN − VCC ) × IVCC
Where :
QUIESCENT CURRENT (mA)
VIN is the line input voltage
VCC is the average VCC voltage (typically 8.5V)
IVCC is the total current drawn by the IC
IVCC is the sum of the operating current of the MIC9130 at
a given frequency and the average current required to drive
the external switching MOSFET. A plot of typical operating
current vs. frequency is given in Figure 3. The average MOSFET gate drive current is calculated in the “MOSFET GATE
DRIVE” section of this specification.
10
9
8
7
6
5
4
3
2
1
0
0
Quiescent Current
vs. Frequency
C = 470pF
t
Ct = 120pF
200 400 600 800 1000
GATE DRIVE FREQUENCY (kHz)
Figure 3
The die junction temperature is calculated by
TJ = TA + PDISS × θJA
Where: TJ is the die junction temperature
TA is the ambient temperature of the circuit
θJA is the junction to ambient thermal resistance
of the MIC9130 (listed in the operating ratings
section of the specification.
When powered directly from the Line voltage, the VCC voltage will vary between the upper and lower pre-regulator
thresholds. The amplitude of the output gate drive voltage
will vary with the VCC voltage. This should not be a problem
M9999-040805
10
April 2005
MIC9130
Micrel, Inc.
5V
MIC9130
4µA
12
SS
SET
S
VCC
Q
R
2
1.21V
/Q
RESET
VCC
UVLO
UVLO
VIN
R1
AGND
11
UVLO
13
R2
16
OUT
LINE
UVLO
15
PGND
Figure 4: UVLO and Soft Start Circuits
VCC Undervoltage Lockout
The VCC voltage is internally divided down and compared to
a 1.21V internal bandgap reference. As VCC rises above the
turn-on threshold, it disables the Vcc undervoltage lockout
circuit. Once above the turn-on threshold, hysteresis prevents
the lockout circuit from disabling the IC until the VCC voltage
falls below the lower threshold.
Line Undervoltage Circuit (UVLO)
The line voltage is monitored by an external resistor divider
and fed into the negative input of the line UVLO comparator.
As the comparator trip point is exceeded, the line UVLO circuit
is disabled. Hysteresis built into the comparator prevents the
circuit from toggling on an off in the presence of noise or a
high input line impedance.
The line voltage turn-on trip point is:
R1 + R2
VLINE_ON = VTHRESHOLD ×
R2
Enable
A low level on the enable pin turns off all the functions of the
MIC9130 and places it in a low quiescent current state. The
output driver is in a low state. When the enable pin is pulled
high, the MIC9130 goes through its normal start up sequence
including undervoltage lock out and soft start. When not used,
the pin should be connected to VCC.
Oscillator Block
An external resistor and capacitor set the oscillator frequency.
The MIC9130 contains an internal divide-by-two circuit that
limits the maximum duty cycle at the gate drive to 50%.
The oscillator frequency for the MIC9130 is twice the output
switching frequency.
Oscillator Pin
The operation of the oscillator is shown in Figure 5. The voltage waveform at the OSC pin is a sawtooth whose amplitude
increases as capacitor Cosc is charged up through ROSC from
the 5V bias. When the OSC pin voltage reaches the internal
comparator upper threshold, COSC is quickly discharged to
zero volts by an internal MOSFET. After a brief delay, typically 75ns, the internal MOSFET is turned off and the COSC
charges, repeating the cycle. Figure 5 show the relationship
between the oscillator and gate drive waveforms. The delays
in the IC force the duty cycle of the gate drive signal to be
slightly less than 50% duty cycle (typically 48%).
For VBIAS = 5V and a peak oscillator waveform voltage of
3V, the design equations simplify to:
Charging
t CHARGE = 0. 92 × R t × Ct
where: VTHRESHOLD is the voltage level of the internal
comparator reference, typically 1.21V.
The line hysteresis is equal to:
R1 + R2
VHYSTERESIS = VHYST ×
R2
where: VHYST is the internal hysteresis level, typically
75mV.
VHYSTERESIS is the hysteresis of the line input
voltage
The MIC9130 will be disabled when the line voltage drops
back down to:
V LINE_OFF = V LINE_ON − VHYTERESIS=
Discharging
tDISCHARGE ≈ 40 × C t
+ R2
(VTHRESHOLD − VHYST )× R1R2
April 2005
11
M9999-040805
MIC9130
Micrel, Inc.
TP_OSCILLATOR = t CHARGE + t DISCHARGE + t DELAY
Where t DELAY = 75ns
fS _ OSCILLATOR =
fS _ OUTPU =
1µF
1
2N3904
TP _ OSCILLATOR
1
× fS _ OSCILLATOR
4
4.7µF
The timing capacitor, COSC, should be an NPO ceramic or a
temperature stable film capacitor. Care must be taken when
using capacitor values less than 47pF. The high impedance of
a small value capacitor makes the OSC pin more susceptible
to switching noise. Also, the input capacitance of the OSC pin
and the stray capacitance of the board will have a noticeable
effect on the oscillator frequency.
SYNC
5
VBIAS
9
ROSC
OSC
ROSC
1.6k
COSC
33pF
VCC
2
SYNC
5
VBIAS
9
3V
4.7µF
OSC
AGND
4
75ns
1-shot
11
Figure 5b
Oscillator Synchronization
The switching frequency of the MIC9130 can be synchronized
to an external oscillator or frequency source. Figure 6 shows
the relationship between the sync input, oscillator waveform
and gate drive output. The external frequency should be set
at least 15% greater than the free running oscillator frequency
to account for tolerances in the oscillator circuit and external
components. The positive edge of the sync signal resets the
oscillator. The sync pulse frequency, like the oscillator, is twice
the gate drive frequency. When an external sync signal is
applied, the peak amplitude of the oscillator signal (pin 4) is
less than when it is free running because the oscillator signal
is terminated before it reaches its 3V (typical) amplitude.
When not used, the sync pin should be connected to ground
to prevent noise from erroneously resetting the oscillator.
3V
4
COSC
75ns
1-shot
11
Sync Input
(pin 5)
AGND
Oscillator
Waveform
(pin 4)
VOSC
Gate Drive
(pin 16)
Gate Drive
(pin 16)
tON
tPERIOD
TIME (500ns/div)
Figure 5a
Figure 6. Sync Waveform
Soft Start Circuit
The soft start is programmed by a capacitor on the soft start
pin. A 4µA current source charges up the capacitor. At power
up, the SS pin is discharged. Once the UVLO and enable
functions release the soft start circuit, the voltage of the capacitor increases. The active voltage range of the soft start
pin is from typically from 0.9V to 1.7V. The internal current
source increases the voltage on the soft start capacitor to
approximately 4V. The soft start pin and the current sense
voltage are connected to a comparator in tç
PMIC9130. The voltage from the soft start pin effectively
limits the peak current through the current sense resistor by
prematurely terminating the on-time of the gate drive output.
Referring to Figure 1, with the soft start voltage low, the duty
cycle of the output is at a minimum. As the soft start voltage
increases, the duty cycle of the gate drive output increases
Higher Switching Frequencies
The MIC9130 is capable of very high switching frequencies.
One of the limitations on the maximum frequency is the current capability of the 5V regulator supplying the oscillator
and VBIAS. By powering VBIAS with an external source, e.g.
linear regulator much higher switching frequencies can be
achieved. A simple way of using an external current source
is to set an NPN as an emitter follower. Figure 5b shows the
MIC9130 oscillator frequency set to 4MHz using an external
NPN. The emitter followerj circuit allows the current to be
supplied by VCC while the voltage is regulated to a diode
drop below VBIAS. This configuration is quite stable over
temperature and voltage variations.
M9999-040805
12
April 2005
MIC9130
Micrel, Inc.
until the error amplifier takes control of the duty cycle. The
soft start capacitor is discharged by an internal MOSFET in
the MIC9130.
The soft start circuit is activated by the following events:
1. Line undervoltage pin less than the 1.21V threshold
2. VCC becomes less than the pre-regulator voltage turn
.................................................................off threshold.
3. The current limit comparator threshold is exceeded.
This can be disabled with a low level on the
CPWR
pin.
4. A low level on the enable pin.
Calculating the soft capacitor depends on many parameters
such as the current limit of the circuit input voltage, output
power and output loading. A starting value of capacitor should
be chosen and the value can be adjusted later in the design.
Recommended starting values of soft start capacitance is
typically 10nF to 100nF. Values below 1nF may be ineffective
in slowing the output voltage turn on time.
CPWR Current Limit Selection
This pin controls whether the soft start circuit is reset if the
voltage on the Isns pin exceeds the overcurrent threshold.
When the CPWR pin is high, an overcurrent condition at the
ISNS pin will terminate the on-time of the gate drive pulse
and discharge the soft start capacitor to zero volts. This delay
in start up contributes to a reduction in the average output
current during an overcurrent or short circuit condition. A
smaller MOSFET may be used since the power dissipation
in the MOSFET is minimized under short circuit or overcurrent conditions.
If the CPWR pin is low an overcurrent or short circuit conditions will not trip the soft start circuit. The pulse-by-pulse
current limit, inherent in current mode control, provides a
“brick wall” or constant current limit. With the power supply
operating in this mode, a smaller soft start capacitor can be
used to increase the turn on speed of the supply.
If the CPWR in is held low during the initial turn on at power
up and then raised high, the power supply can maximize
the turn-on time at start up and still provide a high level of
overcurrent and short circuit protection. The circuit shown
in Figure 7 performs this function.
A resistor placed in series with the gate drive output attenuates ringing in the etch connection between the MIC9130
and the MOSFET. Figure 8 shows a single resistor in series
between the driver output and the gate of the MOSFET. The
zener value should be greater than the gate drive voltage
to prevent excessive power dissipation, but less than the
maximum gate to source voltage rating.
Gate Drive
Output
GND
Figure 8
The circuitry shown in figure 9 allow different rise and fall times.
R1 and the input capacitance of the MOSFET determine the
rise-time of the gate voltage and therefore the turn-on time of
the MOSFET. The diode, D1 is reversed biased, which removes
R2 from the circuit. At turn-off, D1 is forward biased and the
parallel combination of R1 and R2 controls the turn-off time
of the MOSFET. The turn on-time is slower, which reduces
switching noise and ringing during turn-on. The turn-off time
is faster, which minimizes switching losses during turn-off and
improves efficiency. If the turn-on time is to be faster than
the turn-off time, the diode should be reversed.
R2
R1
Gate Drive
Output
GND
Figure 9
A gate drive transformer is used where an increase in drive
voltage, isolation and/or voltage level shifting are required.
Gate drive transformers can have multiple windings and drive
multiple MOSFETs, including MOSFETs that require a drive
signal 180 degrees out of phase with the ICs drive signal.
Figure 10 shows a gate drive transformer circuit. The capacitor, C1 removes DC from the drive circuit and prevents
transformer saturation. R1 provides damping to eliminate
ringing in the circuit. R1 is usually in the 5 to 20Ω range,
depending on the amount of damping necessary. D1 and
D2 form a clamp circuit, which prevents the voltage from
exceeding the VGMAX level. If the gate drive is well damped,
the diodes may be removed R2 is used to allow the transformer to reset properly.
MIC9130
VREF
D1
D1
R1
CPWR
C1
AGND
Figure 7
MOSFET Gate Drive Output
The MIC9130 has the capability to directly drive the gate of
a MOSFET. The output driver consists of a complimentary
P-channel and N-channel pair. The typical switching time
of the output is dependent on the IC supply voltage and the
gate charge required to turn the MOSFET on and off.
April 2005
13
M9999-040805
MIC9130
Micrel, Inc.
C1
T1
Current Sense Circuit
The current sense input of the MIC9130 has three unique
features, which are advantageous in a high speed, high efficiency power supply.
1. The overcurrent threshold is nominally 0.82V instead
of the typical 1.0V found in most switching control
ICs.
2. The current sense pin sources a nominal 40µA of
current out of the pin. This is used to raise the current
limit threshold of the pin, which allows a smaller
current sense resistor to be used. This improves the
efficiency of the power supply, especially in lower
current applications.
3. The delay from the current sense input to the output
is typically 50ns.
The current limit threshold of the ISNS pin was set at 0.82V,
allowing the use of a smaller current sense resistor. A stable,
bandgap derived 40µA current is sourced from the ISNS pin.
A voltage drop across a series resistor placed between the
pin and the current sense resistor level increases the current
sense signal at the ISNS pin. This allows the use of a smaller
current sense resistor if the full 0.82V peak to peak current
signal is not required. Decreasing the value of the current
sense resistor decreases the power dissipation in the resistor,
which improves the efficiency of the power supply.
The delay between the input of the overcurrent comparator
and the output gate drive is nominally 50ns. This very fast
response time allows the MIC9130 to operate at higher frequencies and still have adequate overcurrent protection.
The operation of the current sense input is as follows. The
sensed current in the power supply is converted to a voltage by a resistor or current sense transformer. Referring to
Figure 1, this voltage is compared to the output of the error
amplifier, which sets the duty cycle of the gate drive output.
The current signal is also connected to an Imax comparator.
Comparing the current sense signal to the reference voltage
sets a maximum current limit. If the maximum amplitude of the
current sense signal exceeds the reference, the comparator
terminates the gate drive output pulse. It aslo discharges the
soft start capacitor when the CPWR pin is high.
Leading Edge Current Spike
The current signal in a power circuit will often have a leading
edge spike caused by leakage inductance, parasitic inductance and capacitance, diode reverse recovery effects and
snubbers. These spikes can cause premature termination of
the switching cycle if they are not eliminated.
A resistor may be added in series between the current sense
resistor and the Isns input. The input and board trace capacitance of the ISNS pin (pin 14) is approximately 25pF. A
1k resistor is a good choice, since it attenuates most of the
ripple without distorting the current sense waveform. It has
a minimal effect on level, offsetting the current sense signal
by only 40mV.
A typical rule of thumb is the bandwidth of the RC filter
should be at least 6 times the switching frequency. This
avoids distorting the current sense waveform and adding
excessive delays in the current loop that will interfering with
overcurrent protection. For a 100kHz switcher, the maximum
R1
Gate Drive
Output
D2
R2
GND
D1
1:N
Figure 10
The gate impedance of a MOSFET is capacitive and the
power required to drive the gate is proportional to the charge
required to turn on the MOSFET, the peak gate voltage and
the switching frequency. Assuming the total gate charge for
turn on and turn off is equal, the power used to switch the
MOSFET on and off is:
PDRIVE = QG × VGS × fS
where: QG is the total gate charge at VGS
VGS is the gate to source voltage of the MOSFET
usually equal to VCC
fS is the output switching frequency
The power required to drive the MOSFET is dissipated in the
drive circuitry of the MIC9130. This power must not cause
the die temperature to exceed the maximum rated junction
temperature of 125 degrees C.
MOSFET Driver IC’s are used when the drive requirement for
the MOSFETs is greater than the capability of the MIC9130
gate drive output. While the peak current of the MIC9130
gate drive is typically 1.2A at VIN =12V, a gate driver ICs
will sink or source between 1.2A and 12A of peak current.
The higher peak current allows faster rise and fall times for
larger MOSFETs.
The drive requirements for selecting a MOSFET driver are
determined using the following equation:
Q
IPK = 2 × G
t
where: QG is the total gate charge required to turn on
the MOSFET at a specified ID, VG and VDS. This
information is usually given in the MOSFET
specification sheet.
t is the gate voltage transition time (risetime or fall
time)
IPK is the peak current requirement of the
MOSFET driver IC.
For example, if a MOSFET is chosen with a QG of 60nC and
it is desired to have a 50nS gate to source risetime/falltime,
the peak current requirement of the MOSFET driver is:
2 × 60nC
IPK =
= 2. 4A
50ns
A driver such as the MIC4424 will meet this requirement.
For more information on choosing a MOSFET driver, see
the Micrel application note AN-24, “Designing with Low Side
MOSFET Drivers.”
M9999-040805
14
April 2005
MIC9130
Micrel, Inc.
Sensing Current with a Current Sense Transformer
At higher power levels, the power dissipation in a current sense
resistor is excessive. A current sense transformer can be
used to sense the current while minimizing power dissipation.
See Figure 11. The schematic shows the circuitry necessary
when using a current sense transformer. The resistor, R1,
provides a path to reset the current sense transformer. The
resistor, R2, converts the scaled down current to a voltage,
which is sent to the ISNS pin.
series resistance is 10K, for a 500kHz switcher, the maximum
series resistance is 2K.
Sensing Current with a Resistor
The fast transition times of the current signal prohibit the use
of inductive resistors. Standard wire wound power resistors
will not work. Carbon composition or metal film resistors or
low inductance power resistors may be used. The overcurrent
range of the power supply and component tolerances must be
considered when selecting the current sense resistor value.
The power supply specification may call for an overcurrent
limit, which must be accounted for when selecting the current sense resistor value. The relationship between the peak
primary current and the current sense resistor is:
VISNS = IP × RISENSE + IISNS × R f
VIN
where: Ip is the current in the sense resistor
RISENSE is the current sense resistance
IISNS is the current sourced from the ISNS pin
(40µA)
Rf is the series resistor between the ISNS pin and
the current sense resistor.
The current sense resistor must not be too small or the current sense signal will be susceptible to noise. If noise is a
problem, the current signal level should be increased.
An example is illustrated below.
The maximum peak current, IPMAX= 1A at 120% overcurrent
and minimum input voltage
The maximum rms current, IRMS=0.65A
The desired current sense signal amplitude is 500mV at 1A
output current.
The current sense resistor value and power dissipation is:
V
0.5
RSENSE = SENSE =
= 0.5 Ω
ISENSE
1
R2
IISNS
=
Figure 11
The voltage at the ISNS pin is calculated by:
I
VISNS = P × R2 + IISNS × R f
N
where: IP is the current in the primary of the current sense
transformer
R2 is the current sense resistance at the
secondary of the current sense transformer
N is the turns ratio of the current sense
transformer (N=Nsec/Npri)
IISNS is the current sourced from the ISNS pin
(40µA)
Rf is the series resistor between the ISNS pin and
the current sense resistor.
Current Transformer example:
The maximum peak current, IPMAX = 5A at 120% overcurrent and minimum input voltage
The maximum rms current, IRMS = 3.25A
The full 0.82V peak signal a the ISNS input can be used
since very little power is dissipation in the secondary
side sense resistor. The maximum peak to peak voltage at the sense pin (pin 14) is 0.82V at the 5A maximum
output current.
The current sense resistor value and power dissipation
is:
V
× N 0. 82 × 100
= 16.4 Ω
R2 = SENSE
=
IP
5
0. 82 − (1× 0 .5)
= 10.25k Ω
40µ A
The next lower value of 10kΩ is selected.
The bandwidth of the 10K resistor and the 25pF input capacitance is calculated. The resistor value must be lowered if the
bandwidth is too low for the switching frequency.
1
BW =
= 630kHz
2 × π × 10k × 25 pF
The maximum switching frequency of this power supply
should be approximately six times less than the BW to prevent current waveform distortion and excessive delays in
the current loop. This limits the switching frequency to the
range of 100kHz.
April 2005
IPRI
OUT
(pin 16)
A 0.5Ω, non inductive resistor with at least a 1/2W rating
should be selected.
The series resistor is calculated to allow the 500mV-peak
signal to reach 0.82V.
VISNS − ( IP × RISENSE )
R1
MIC9130
PDISS = IRMS2 × RSENSE = 0. 65 2 × 0 .5 = 0.21W
Rf
Current Sense
Transformer
Rf
ISNS
(pin 14)
2
2
I

 3. 25 
PDISS =  PRMS  × R2 = 
 × 16.4 = 17 .4 mW
 100 
 N 
15
M9999-040805
MIC9130
Micrel, Inc.
A 16.2 ohm, 1%, non inductive resistor with at least a 50mW
rating should be selected. A good choice would be an 0805
size metal film or a 1/8 watt leaded metal film resistor. A
series resistor between the current sense transformer and
the Isns input is not necessary unless it is used for low pass
filtering.
If the current sense transformer were not used, the sense
resistor would dissipate 1.7 watts.
V
0. 82
RSENSE = SENSE =
= 0.164 Ω
ISENSE
5
where :
VO is the output voltage
VD is the forward voltage drop of the rectifier diode
L is the inductance of the output inductor (or the
secondary winding inductance for the flyback
topology)
M2 is the inductor current downslope
For a boost topology, the inductor downslope is:
di VOUT − VIN + VD
M2 =
=
dt
L
PDISS = IRMS2 × RSENSE = 3. 25 2 × 0 .164 = 1. 7 W
In a transformer isolated topology, the downslope must be
reflected back to the primary by the turns ratio of the transformer. The reflected downslope is:
Ns
M2REFLECTED = M2 ×
Np
Slope Compensation
Power supplies using peak current mode control techniques
require slope compensation when they are operating in
continuous mode and have a duty cycle greater than 50%.
Without slope compensation, the duty cycle of the power supply will alternate wide and narrow pulses commonly referred
to as subharmonic oscillations. Even though the MIC9130
operates below a 50% duty cycle, slope compensation adds
the benefits of improved transient response and greater
noise immunity in the current sense loop (especially when
the current ramp is shallow). Slope compensation can be
implemented by adding an optimum 1/2 of the inductor current downslope, reflected back to the current sense input. In
real world applications, 2/3 of the inductor current downslope
is used to allow for component tolerances.
Slope compensation at the ISNS input may be implemented
by using a resistor and capacitor as shown in Figure 12. The
rectangular waveshape of the gate drive output is integrated
by the resistor/capacitor filter, which results in a ramp used
for the slope compensation signal. When the gate drive and
the current signal at the sense resistor goes low, the capacitor is discharged to 0V.
where : Ns/Np is the turns ratio of the secondary winding
to the primary winding.
M2REFLECTED is the inductor curent downslope
reflected to the secondary side of the current
sense transformer.
The reflected downslope is multiplied by the current sense
resistor to obtain the downslope at the current sense input
pin (ISNS).
ISNS _ SLOPE = M2REFLECTED × RS
where Rs is the value of the current sense resistor.
The required downslope of the compensation ramp at the
ISNS input is:
M3 = ISNS _ SLOPE × 0.67
R1 is know if a value for the resistor between the current
sense resistor and the Isns pin, has already been selected.
If not chose a value of 1k, which will minimize any offset
and signal degradation at the ISNS pin. Select a value of
C1 to minimize signal degradation from the cutoff frequency
of R1/C1. The bandwidth should be at least six times the
switching frequency.
1
C1 =
2 × π × fS × R1
Gate Drive
(pin 16)
R2
MIC9130
ISNS
(pin 14)
R1
C1
RSENSE
where: fS is the switching frequency of the power
supply (not the oscillator frequency)
The slope of the generated compensation ramp is:
R1
1
M3 = VGATE_DRIVE ×
×
R2 + R1 R2 × C1
Figure 12
The procedure outlined below demonstrates how to calculate
the component values.
Compute the inductor current downslope as seen at the current sense input.
For a flyback, buck or forward mode topology the
inductor downslope is equal to:
di VO + VD
M2 =
=
dt
L
M9999-040805
Solving for R2 and assuming R2 is much greater than R1.
R2 =
VGATE _ DRIVE × R1
M3 × C1
where: VGATE_DRIVE is the amplitude of the gate
drive waveform
16
April 2005
MIC9130
Micrel, Inc.
Error Amplifier
The error amplifier is part of the voltage control loop of the
power supply. The FB pin is the inverting input to the error
amplifier. The non-inverting input is internally connected to
a 2.5V reference. The output of the error amplifier, COMP,
is connected to the PWM comparator. The error amplifier
April 2005
provides the reference to limit and control the peak current
of the power supply. There is a 1.2V level shift between the
output of the error amplifier and the PWM comparator. This
allows the output of the error amplifier to operate in a linear
region and prevents loading on the COMP pin from interfering
with proper control of the current signal.
17
M9999-040805
MIC9130
Micrel, Inc.
Package Information
16-Lead SOIC (M)
0.344 (8.74)
0.337 (8.56)
0.0575 REF
0.157 (3.99)
0.150 (3.81)
8¡
0¡
0.244 (6.20)
0.229 (5.82)
0.009 (0.229)
0.007 (0.178)
0.012 (0.305)
0.008 (0.203)
0.025 BSC
(0.635)
Rev. 04
0.068 (1.73)
0.053 (1.35)
Note:
1. All Dimensions are in Inches (mm) excluding mold flash.
2. Lead coplanarity should be 0.004" max.
3. Max misalignment between top and bottom.
4. The lead width, B to be determined at 0.0075" from lead tip.
0.010 (0.254)
0.004 (0.102)
7¡ BSC
0.050 (1.27)
0.016 (0.40)
16-Lead QSOP (QS)
M9999-040805
18
April 2005
MIC9130
Micrel, Inc.
MICREL INC.
2180 FORTUNE DRIVE
SAN JOSE, CA 95131
USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's
use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2001 Micrel Incorporated
April 2005
19
M9999-040805