May 1997 ML2281, ML2282*, ML2284#, ML2288# Serial I/O 8-Bit A/D Converters with Multiplexer Options GENERAL DESCRIPTION FEATURES The ML2281 family are 8-bit successive approximation A/D converters with serial I/O and configurable input multiplexers with up to 8 input channels. ■ Conversion time: 6µs All errors of the sample-and-hold, incorporated on the ML2281 family are accounted for in the analog-to-digital converters accuracy specification. ■ 2, 4 or 8-input multiplexer options The voltage reference can be externally set to any value between GND and VCC, thus allowing a full conversion over a relatively small voltage span if desired. ■ Operates ratiometrically or with up to 5V voltage reference The ML2281 family is an enhanced double polysilicon CMOS pin compatible second source for the ADC0831, ADC0832, ADC0834, and ADC0838 A/D converters. The ML2281 series enhancements are faster conversion time, true sample-and-hold function, superior power supply rejection, improved AC common mode rejection, faster digital timing, and lower power dissipation. All parameters are guaranteed over temperature with a power supply voltage of 5V ±10%. ■ Total unadjusted error: ±1/2LSB or ±1LSB ■ Sample-and-hold: 375ns acquisition ■ 0 to 5V analog input range with single 5V power supply ■ No zero or full-scale adjust required ■ ML2281 capable of digitizing a 5V, 40kHz sine wave ■ Low power: 12.5mW MAX ■ Superior pin compatible replacement for ADC0831, ADC0832, ADC0834, and ADC0838 ■ Analog input protection: 25mA (min) per input ■ Now in 8-Pin SOIC Package (ML2281, ML2282) (* Indicates Part is Obsolete) (# Indicates Part is End Of Life as Of July 1, 2000) ML2288 (8-Channel SE or 4-Channel Diff Multiplexer) ML2284 (4-Channel SE or 2-Channel Diff Multiplexer) ML2284 (2-Channel SE or 1-Channel Diff Multiplexer) BLOCK DIAGRAM ML2281 CS CONTROL AND TIMING DI INPUT SHIFT-REGISTER CLK SARS A/D WITH SAMPLE & HOLD FUNCTION + SUCCESSIVE + APPROXIMATION COMP – – REGISTER 8pF Σ CS DO CH0 CH1 VREF CH2 CH3 VIN– CH4 8pF CLK OUTPUT SHIFT-REGISTER CH5 D/A CONVERTER CH6 SE MULTIPLEXER (ML2288 SHOWN) VIN+ 4-BIT DO OUTPUT SHIFT-REGISTER CONTROL AND TIMING DGND A/D CONVERTER WITH SAMPLE & HOLD FUNCTION SHUNT REGULATOR CH7 VCC GND COMMON AGND VREF VCC V+ 1 ML2281, ML2282, ML2284, ML2288 PIN CONFIGURATION ML2281 Single Differential Input 8-Pin DIP ML2282 2-Channel MUX 8-Pin DIP CS 1 8 VCC CS 1 8 VCC (VREF) VIN+ 2 7 CLK CH0 2 7 CLK VIN– 3 6 DO CH1 3 6 DO GND 4 5 VREF GND 4 5 DI TOP VIEW TOP VIEW ML2282 8-Pin SOIC ML2281 8-Pin SOIC CS 1 8 VCC CS 1 8 VCC (VREF) VIN+ 2 7 CLK CH0 2 7 CLK VIN– 3 6 DO CH1 3 6 DO GND 4 5 VREF GND 4 5 DI TOP VIEW TOP VIEW ML2284 14-Pin SOIC ML2284 4-Channel MUX 14-Pin DIP V+ 1 14 VCC V+ 1 14 CS 2 13 DI VCC CH0 3 12 CLK CS 2 13 DI CH1 4 11 SARS CH0 3 12 CLK CH2 5 10 DO CH1 4 11 SARS CH3 6 9 VREF DGND 7 8 AGND CH2 5 10 DO CH3 6 9 VREF DGND 7 8 AGND TOP VIEW TOP VIEW CH4 CH5 2 VCC CH0 1 20 CH0 1 20 VCC 19 CH1 2 19 V+ CH2 3 18 CS CH3 4 17 DI CH4 5 16 CLK CH5 6 15 SARS 4 18 5 17 CS DI 6 16 CLK CH6 7 15 SARS CH6 7 14 DO CH7 8 14 DO CH7 8 13 SE COM 9 12 VREF DGND 10 11 AGND TOP VIEW 13 SE 12 VREF 11 AGND 10 DGND COM 9 2 ML2288 8-Channel MUX 20-Pin DIP V+ 3 CH3 CH1 CH2 ML2288 8-Channel MUX 20-Pin PCC TOP VIEW ML2281, ML2282, ML2284, ML2288 PIN DESCRIPTION NAME FUNCTION VCC Positive supply. 5V ± 10% DGND Digital ground. 0 volts. All digital inputs and outputs are referenced to this point. AGND Analog ground. The negative reference voltage for A/D converter. NAME DO Data out. Digital output which contains result of A/D conversion. The serial data is clocked out on falling edges of CLK. SARS Successive approximation register status. Digital output which indicates that a conversion is in progress. When SARS goes to 1, the sampling window is closed and conversion begins. When SARS goes to 0, conversion is completed. When CS = 1, SARS is in high impedance state. CLK Clock. Digital input which clocks data in on DI on rising edges and out on DO on falling edges. Also used to generate clocks for A/D conversion. DI Data input. Digital input which contains serial data to program the MUX and channel assignments. CS Chip select. Selects the chip for multiplexer and channel assignment and A/D conversion. When CS = 1, all digital outputs are in high impedance state. When CS = 0, normal A./D conversion takes place. CH0-7, Analog inputs. Digitally selected to be single VIN+, VIN– ended (VIN) or; VIN+ or VIN– of a differential input. Analog range = GND - VIN - VCC. COM Common reference point for analog inputs. A/D conversion is performed on voltage difference between analog input and this common reference point if single-end conversion is specified. VREF Reference. The positive reference voltage for A/D converter. SE Shift enable. Input controls whether LSB first bit stream is shifted out on serial output DO. If SE = 1, MSB first is shifted out only. If SE = 0, an MSB first bit stream is shifted out, then a second bit stream with LSB first is shifted out after end of conversion. V+ FUNCTION Input to the Shunt Regulator. 3 ML2281, ML2282, ML2284, ML2288 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Current into V+ ...................................................... 15mA Supply Voltage, VCC ................................................. 6.5V Voltage Logic Inputs ........................................... –7 to VCC +7V Analog Inputs ................................ –0.3V to VCC +0.3V Input Current per Pin (Note 1) .............................. ±25mA Storage Temperature ................................ –65°C to 150°C Package Dissipation at TA = 25°C (Board Mount) ............................. 800mW Lead Temperature (Soldering 10 sec.) Dual-In-Line Package (Molded) .......................... 260°C Dual-In-Line Package (Ceramic) ......................... 300°C Molded Chip Carrier Package Vapor Phase (60 sec.) ..................................... 215°C Infrared (15 sec.) ............................................. 220°C OPERATING CONDITIONS Supply Voltage, VCC ............................ 4.5VDC to 6.3VDC Temperature Range (Note 2) ................. T MIN - TA - TMAX ML2281/2/4/8 BIX .................................. –40°C to 85°C ML2281/2/4/8 CIX ML2281/2/4/8 BCX .................................... 0°C to 70°C ML2281/2/4/8 CCX ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = TMIN to TMAX, VCC = VREF = 5V ±10%, and fCLK = 1.333MHz. SYMBOL PARAMETER CONDITIONS ML228XB TYP MIN NOTE 3 MAX MIN ML228XC TYP NOTE 3 MAX UNITS ±1 LSB 20 kW VCC +0.05 V ±1/4 LSB ±1/4 LSB ±1/4 LSB ±1/4 LSB CONVERTER AND MULTIPLEXER CHARACTERISTICS Total Unadjusted Error VREF = VCC (Notes 4, 6) ±1/2 Reference Input Resistance (Notes 4, 7) 10 Common-Mode Input Range (Notes 4, 8) GND –0.05 DC Common-Mode Common mode voltage Error voltage GND to VCC/2 (Note 5) 15 ±1/16 AC Common-Mode Common mode voltage Error GND to VCC/2, 0 to 50kHz (Note 5) 4 DC Power Supply Sensitivity VCC = 5V ±10% VREF - VCC +0.1V (Note 5) AC Power Supply Sensitivity 100mVP-P, 25kHz sine on VCC (Note 5) Change in Zero Error from VCC=5V to Internal Zener Operation 15mA into V+ VCC = N.C. VREF = 5V (Note 5) VZ Internal Diode Regulated Breakdown (at V+) 15mA into V+ V+ Input Resistance (Note 4) 20 10 VCC +0.05 GND –0.05 ±1/4 15 ±1/16 ±1/4 ±1/32 ±1/4 ±1/32 ±1/4 20 ±1/2 ±1/2 LSB 6.9 6.9 V 35 kW 35 20 ML2281, ML2282, ML2284, ML2288 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER CONDITIONS ML228XB TYP MIN NOTE 3 MAX MIN ML228XC TYP NOTE 3 MAX UNITS CONVERTER AND MULTIPLEXER CHARACTERISTICS (CONTINUED) IOFF Off Channel Leakage Current On channel = VCC Off channel = 0V (Notes 4, 9) –1 –1 On channel = 0V Off channel = VCC (Notes 4, 9) ION On Channel Leakage Current On channel = 0V Off channel = VCC (Notes 4, 9) µA +1 –1 +1 –1 On channel = VCC Off channel = 0V (Notes 4, 9) µA µA +1 +1 µA DIGITAL AND DC CHARACTERISTICS VIN(1) Logical “1” Input Voltage (Note 4) 2.0 2.0 V VIN(0) Logical “0” Input Voltage (Note 4) IIN(1) Logical “1” Input Current VIN = VCC (Note 4) IIN(0) Logical “0” Input Current VIN = 0V (Note 4) –1 –1 µA VOUT(1) Logical “1” Output Voltage IOUT = –2mA (Note 4) 4.0 4.0 V VOUT(0) Logical “0” Output Voltage IOUT = 2mA (Note 4) IOUT HI-Z Output Current VOUT = 0V (Note 4) VOUT = VCC –1 ISOURCE Output Source Current VOUT = 0V (Note 4) –6.5 ISINK Output Sink Current VOUT = VCC (Note 4) ICC Supply Current 0.8 0.8 V 1 1 µA 0.4 0.4 V 1 µA µA –1 1 –6.5 mA 8.0 8.0 mA ML2281, ML2284 ML2288 (Note 4) 1.3 2.5 1.3 2.5 mA ML2282 Includes ladder Current (Note 4) 1.8 3.5 1.8 3.5 mA 5 ML2281, ML2282, ML2284, ML2288 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER CONDITIONS MIN TYP NOTE 3 MAX LIMIT UNITS 1.333 kHz AC ELECTRICAL CHARACTERISTICS fCLK Clock Frequency tACQ Sample-and-Hold Acquisition tC Conversion Time SNR (Note 4) 10 1/2 1/fCLK Not including MUX adddressing time 8 1/fCLK Signal to Noise Ratio ML2281 VIN = 40kHz, 5V sine. fCLK = 1.333MHz (fSAMPLING » 120kHz). Noise is sum of all nonfundamental components up to 1/2 of fSAMPLING (Note 11) 47 dB THD Total Harmonic Distortion ML2281 VIN = 40kHz, 5V sine. fCLK = 1.333MHz (fSAMPLING » 120kHz). THD is sum of 2, 3, 4, 5 harmonics relative to fundamental (Note 11) –60 dB IMD Intermodulation Distortion ML2281 VIN = fA + fB. fA = 40kHz, 2.5V sine. fB = 39.8kHz, 2.5V Sine, fCLK = 1.333MHz (fSAMPLING » 120kHz). IMD is (fA + fB), (fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB), (fA – 2fB) relative to fundamental (Note 11) –60 dB Clock Duty Cycle (Notes 4, 10) 40 60 % tSET-UP CS Falling Edge or Data Input (Note 4) Valid to CLK Rising Edge 130 ns tHOLD Data Input Valid after CLK Rising Edge (Note 4) 80 ns tPD1, tPD0 CLK Falling Edge to Output Data Valid CL = 100pF (Note 4 & 12) Data MSB first Data LSB first t1H, t0H Rising Edge of CS to Data Output and SARS Hi-Z 90 50 200 110 ns ns CL = 10pF, RL = 10k (see high impedance test circuits) (Note 5) 40 90 ns CL = 100pF, RL = 2k (Note 4) 80 160 ns CIN Capacitance of Logic Input 5 pF COUT Capacitance of Logic Outputs 5 pF Note 1: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > VCC) the absolute value of current at that pin should be limited to 25mA or less. Note 2: 0°C to 70°C and –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by correlation with worst-case test conditions. Note 3: Typicals are parametric norm at 25°C. Note 4: Parameter guaranteed and 100% production tested. Note 5: Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation. Note 6: Total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors. Note 7: Cannot be tested for ML2282. Note 8: For VIN– ³ VIN+ the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50mV forward bias of either diode. This means that as long as the analog V IN or VREF does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950VDC over temperature variations, initial tolerance and loading. Note 9: Leakage current is measured with the clock not switching. Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the minimum time the clock is high or the minimum time the clock is low must be at least 300ns. The maximum time the clock can be high or low is 60µs. Note 11: Because of multiplexer addressing, test conditions for the ML2282 would be V IN = 34kHz, 5V sine (fSAMPLING » 102kHz); ML2284 VIN = 32kHz, 5V sine (fSAMPLING » 95kHz); ML2288 VIN = 30kHz, 5V sine (fSAMPLING » 89kHz). Note 12: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for comparator response time. 6 ML2281, ML2282, ML2284, ML2288 t1H t1H tr VCC DATA OUTPUT 90% 50% 10% CS RL CL GND t1H DO AND SARS OUTPUTS VOH 90% GND t0H t0H VCC tr VCC 90% 50% 10% CS RL GND DATA OUTPUT t0H CL DO AND SARS OUTPUTS VCC 10% VOL Figure 1. High Impedance Test Circuits and Waveforms Data Output Timing Data Input Timing CLK CLK tPD0, tPD1 tSET-UP CS DATA OUT (DO) tSET-UP tHOLD tPD0, tPD1 tSET-UP tHOLD DATA IN (DI) SE ML2281 Start Conversion Timing CLK tSET-UP CS START CONVERSION DO BIT 7 (MSB) BIT 6 Figure 2. Timing Diagrams 7 ML2281, ML2282, ML2284, ML2288 ML2281 Timing 1 2 3 4 5 6 7 8 9 10 11 4 3 2 1 0 (LSB) CLOCK (CLK) tSET-UP CHIP SELECT (CS) tC DATA OUT (DO) * HI-Z 7 (MSB) SAMPLE & HOLD ACQUISITION (tACQ) 6 5 HI-Z *LSB FIRST OUTPUT NOT AVAILABLE ON ML2281 ML2282 Timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLOCK (CLK) tSET-UP CHIP SELECT (CS) OUTPUT DATA ADDRESS MUX START BIT ODD/ SIGN DATA IN (DI) DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE) SGL/DIF DATA OUT (DO) MSB FIRST DATA LSB FIRST DATA HI-Z HI-Z 7 (MSB) SAMPLE & HOLD ACQUISITION (tACQ) 6 5 4 3 2 1 0 (LSB) 1 2 3 4 5 6 7 (MSB) ML2284 Timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLOCK (CLK) tSET-UP OUTPUT DATA ADDRESS MUX CHIP SELECT (CS) START BIT ODD/SIGN DATA IN (DI) DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE) SGL/DIF SELECT BIT 1 SAR STATUS (SARS) A/D CONVERSION IN PROCESS HI-Z HI-Z MSB FIRST DATA DATA OUT (DO) LSB FIRST DATA HI-Z SAMPLE & HOLD ACQUISITION (tACQ) HI-Z 7 6 (MSB) 5 4 3 2 1 0 (LSB) 1 2 Figure 2. Timing Diagrams (Continued) 8 3 4 5 6 7 (MSB) ML2281, ML2282, ML2284, ML2288 ML2288 Timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 CLOCK (CLK) tSET-UP OUTPUT DATA ADDRESS MUX CHIP SELECT (CS) START BIT ODD/ SELECT SIGN BIT 0 DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE) DATA IN (DI) SGL/DIF SELECT BIT 1 A/D CONVERSION IN PROCESS SAR STATUS (SARS) HI-Z HI-Z MSB FIRST DATA HI-Z SE USING SE TO CONTROL LSB FIRST OUTPUT DO HI-Z 7 6 (MSB) 5 4 3 2 1 0 (LSB) MSB FIRST DATA HI-Z SAMPLE & HOLD ACQUISITION (tACQ) 7 6 (MSB) 5 4 3 2 1 2 3 4 5 6 tSET-UP DATA HELD 1 7 (MSB) LSB FIRST DATA 0 (LSB) 1 2 3 4 5 6 7 (MSB) HI-Z Figure 2. Timing Diagrams (Continued) 1.0 VCC = 5V VREF = 5V LINEARITY ERROR (LSB) SE = “0” DATA OUT (DO) LSB FIRST DATA 0.75 0.5 125 C –55 C 0.25 25 C 0 0 0.01 0.1 1 CLOCK FREQUENCY (MHz) Figure 3. Linearity Error vs fCLK 9 ML2281, ML2282, ML2284, ML2288 1 1 VCC = 5V VIN = 0V fCLK = 1.333MHz TA = 25 C 0.75 0.75 0.5 OFFSET ERROR (LSB) LINEARITY ERROR (LSB) VCC = 5V fCLK = 1.333MHz 125 C –55 C 25 C 0.25 0 0.25 0 1 2 3 4 VREF (VDC) Figure 4. Linearity Error vs VREF Voltage 10 0.5 5 0 0 1 2 3 4 5 VREF (VDC) Figure 5. Unadjusted Offset Error vs VREF Voltage ML2281, ML2282, ML2284, ML2288 DI* CS 17 18 R START R R R 5-BIT SHIFT-REGISTER ODD/ SGL/DIF SELECT 1 SIGN R D SELECT 0 C CS START CLK 16 13 MUX ADDRESS VCC CH0* CH1* CH2 CH3 CH4* CH5* CH6* CH7* COM* VREF VCC 1 + CS SARS* 15 Σ TD – 2 3 TIME DELAY DSTART 2 4 ANALOG MUX (EQUIVALENT) 5 6 – 7 R Q D D Q C R D Q C R CS DSTART 1 CS DEOC CS CS CS 8 CS 9 COMP R C 12 TO INTERNAL CIRCUITRY 20 7V SHUNT REGULATOR R B6 C R Q 14 DO D C B5 R INPUT V CC 13 TO 16 INTERNAL 17 CIRCUITS 18 EOC B7 SAR LOGIC AND LATCH LADDER AND DECODER 9-BIT SHIFT REGISTER B4 B3 B2 B1 B0 EOC COMP AGND* C + C V+* DGND* SE* NOTE 1 NOTE 1 INPUT PROTECTION—ALL LOGIC INPUTS LSB FIRST MSB FIRST PARALLEL XFR TO SHIFT REGISTER *SOME OF THESE FUNCTIONS/PINS ARE NOT AVAILABLE WITH OTHER OPTIONS. NOTE 1: FOR THE ML2284 DI IS INPUT DIRECTLY TO THE D INPUT OF SELECT 1. SELECT 0 IS FORCED TO A “1”. FOR THE ML2282, DI IS INPUT DIRECTLY TO THE D INPUT OF ODD/SIGN. SELECT 0 IS FORCED TO A “1” AND SELECT 1 IS FORCED TO A “0”. Figure 6. ML2288 Functional Block Diagram 11 ML2281, ML2282, ML2284, ML2288 FUNCTIONAL DESCRIPTION SINGLE-ENDED MUX MODE MUX ADDRESS MULTIPLEXER ADDRESSING The design of these converters utilizes a sample data comparator structure which provides for a differential analog input to be converted by a successive approximation routine. The actual voltage converted is always the difference between an assigned “+” input terminal and a “–” input terminal. The polarity of each input terminal of the pair being converted indicates which line the converter expects to be the most positive. If the assigned “+” input is less than the “–” input, the converter responds with an all zeros output code. A unique input multiplexing scheme has been utilized to provide multiple analog channels with software configurable single ended, differential, or pseudo differential options. The pseudo differential option will convert the difference between the voltage at any analog input and a common terminal. One converter package can now accommodate ground referenced inputs and true differential inputs as well as signals with some arbitrary reference voltage. A particular input configuration is assigned during the MUX addressing sequence, prior to the start of a conversion. The MUX address selects which of the analog inputs are to be enabled and whether this input is single ended or differential. In the differential case, it also assigns the polarity of the analog channels. Differential inputs are restricted to adjacent channel pairs. For example, channel 0 and channel 1 may be selected as a different pair but channel 0 or channel 1 cannot act differentially with any other channel. In addition to selecting the differential mode, the sign may also be selected. Channel 0 may be selected as the positive input and channel 1 as the negative input or vice versa. This programmability is illustrated by the MUX addressing codes shown in Tables 1, 2, and 3. The MUX address is shifted into the converter via the DI input. Since the ML2281 contains only one differential input channel with a fixed polarity assignment, it does not require addressing. The common input line on the ML2288 can be used as a pseudo differential input. In this mode, the voltage on the COM pin is treated as the “–” input for any of the other input channels. This voltage does not have to be analog ground; it can be any reference potential which is common to all of the inputs. This feature is most useful in single supply applications where the analog circuitry may be biased at a potential other than ground and the output signals are all referred to this potential. Since the input configuration is under software control, it can be modified, as required, at each conversion. A channel can be treated as a single-ended, ground referenced input for one conversion; then it can be reconfigured as part of a differential channel for another conversion. Figure 7 illustrates these different input modes. 12 SGL/ ODD/ DIF SIGN ANALOG SINGLE-ENDED CHANNEL# SELECT 1 0 0 + 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 2 3 4 5 6 7 COM – + – + – + – + – + – + – + – DIFFERENTIAL MUX MODE MUX ADDRESS SGL/ ODD/ DIF SIGN ANALOG DIFFERENTIAL CHANNEL-PAIR# SELECT 0 1 1 0 0 1 0 0 0 0 + – 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 – 2 2 3 + – 3 4 5 + – 6 7 + – – + + – + – + Table 1. ML2288 MUX Addressing 8 Single-Ended or 4 Differential Channels SINGLE-ENDED MUX MODE MUX ADDRESS SGL/ ODD/ DIF SIGN CHANNEL# SELECT 1 0 1 0 0 + 1 0 1 1 1 0 1 1 1 1 2 3 + + + COM is internally tied to AGND DIFFERENTIAL MUX MODE MUX ADDRESS SGL/ ODD/ DIF SIGN CHANNEL# SELECT 1 0 1 0 0 0 + – 0 0 1 0 1 0 – + 0 1 1 2 3 + – – + Table 2. ML2284 MUX Addressing 4 Single-Ended or 2 Differential Channel ML2281, ML2282, ML2284, ML2288 SINGLE-ENDED MUX MODE DIGITAL INTERFACE MUX ADDRESS CHANNEL# SGL/DIF ODD/SIGN 0 1 0 + 1 1 1 + DIFFERENTIAL MUX MODE MUX ADDRESS CHANNEL# SGL/DIF ODD/SIGN 0 1 0 0 + – 0 1 – + Table 3. ML2282 MUX Addressing 2 Single-Ended or 1 Differential Channel 8 Single-Ended 8 Pseudo-Differential 0 + 0 + 1 + 1 + 2 + 2 + 3 + 3 + 4 + 4 + 5 + 5 + 6 + 6 + 7 + 7 + COM (–) + COM (–) VBIAS 0, 1 Mixed Mode + 0, 1 – – (+) 2, 3 + (–) 4, 5 + + (–) – (+) 6, 7 – 2, 3 – (+) + (–) A conversion is initiated when CS is pulsed low. This line must me held low for the entire conversion. The converter is now waiting for a start bit and its MUX assignment word. A clock is applied to the CLK input. On each rising edge of the clock, the data on DI is clocked into the MUX address shift register. The start bit is the first logic “1” that appears on the DI input (all leading edge zeros are ignored). After the start bit, the device clocks in the next 2 to 4 bits for the MUX assignment word. When the start bit has been shifted into the start location of the MUX register, the input channel has been assigned and a conversion is about to begin. An interval of 1/2 clock period is used for sample & hold settling through the selected MUX channels. The SAR status output goes high at this time to signal that a conversion is now in progress and the DI input is ignored. The DO output comes out of High impedance and provides a leading zero for this one clock period. When the conversion begins, the output of the comparator, which indicates whether the analog input is greater than or less than each successive voltage from the internal DAC, appears at the DO output on each falling edge of the clock. This data is the result of the conversion being shifted out (with MSB coming first) and can be read by external logic or µP immediately. After 8 clock periods, the conversion is completed. The SAR status line returns low to indicate this 1/2 clock cycle later. 4 Differential + (–) The block diagram and timing diagrams in Figures 2-5 illustrate how a conversion sequence is performed. 4 + 5 + 6 + 7 + – (+) + COM (–) VBIAS Figure 7. Analog Input Multiplexer Functional Options for ML2288 The serial data is always shifted out MSB first during the conversion. After the conversion has been completed, the data can be shifted out a second time with LSB first, depending on level of SE input. For the case of ML2288, if SE = 1, the data is shifted out MSB first during the conversion only. If SE is brought low before the end of conversion (which is signalled by the high to low transition of SARS), the data is shifted out again immediately after the end of conversion; this time LSB first. If SE is brought low after end of conversion, the LSB first data is shifted out on falling edges of clock after SE goes low. For ML2282 and 2284, SE is internally tied low, so data is shifted out MSB first, then shifted out a second time LSB first at end of conversion. For ML2281, SE is internally tied high, so data is shifted out only once MSB first. All internal registers are cleared when the CS input is high. If another conversion is desired, CS must make a high to low transition followed by address information. The DI input and DO output can be tied together and controlled through a bidirectional µP I/O bit with one connection. This is possible because the DI input is only latched in during the MUX addressing interval while the DO output is still in the high impedance state. 13 ML2281, ML2282, ML2284, ML2288 REFERENCE The voltage applied to the reference input to these converters defines the voltage span of the analog input (the difference between VIN MAX and VIN MIN) over which the 256 possible output codes apply. The devices can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a voltage source capable of driving the reference input resistance, typically 10k. This pin is the top of a resistor divider string used for the successive approximation conversion. In a ratiometric system, the analog input voltage is proportional to the voltage used for the A/D reference. This voltage is typically the system power supply, so the VREF pin can be tied to VCC. This technique relaxes the stability requirements of the system reference as the analog input and A/D reference move together maintaining the same output code for a given input condition. The signal at the analog input is sampled during the interval when the sampling switch is closed prior to conversion start. The sampling window (S/H acquisition time) is 1/2 CLK period wide and occurs 1/2 CLK period before DO goes from high impedance to active low state. When the sampling switch closes at the start of the S/H acquisition time, 8pF of capacitance is thrown onto the analog input. 1/2 CLK period later, the sampling switch is opened and the signal present at the analog input is stored. Any error on the analog input at the end of the S/H acquisition time will cause additional conversion error. Care should be taken to allow adequate charging or settling time from the source. If more charging or settling time is needed to reduce these analog input errors, a longer CLK period can be used. The ML2281X family has improved latchup immunity. Each analog input has dual diodes to the supply rails, and a minimum of ±25mA (±100mA typically) can be injected into each analog input without causing latchup. DYNAMIC PERFORMANCE For absolute accuracy, where the analog input varies between specific voltage limits, the reference pin can be biased with a time and temperature stable voltage source. The maximum value of the reference is limited to the VCC supply voltage. The minimum value, however, can be quire small to allow direct conversion of inputs with less than 5V of voltage span. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter. Signal-to-Noise-Ratio Signal-to-noise ration (SNR) is the measured signal-to-noise at the output of the converter. The signal is the RMS magnitude of the fundamental. Noise is the RMS sum of all the nonfundamental signals up to half the sampling frequency. SNR is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical SNR for a sine wave is given by SNR = (6.02N + 1.76)dB ANALOG INPUTS AND SAMPLE/HOLD An important feature of the ML2281 family of devices is that they can be located at the source of the analog signal and then communicate with a controlling µP with just a few wires. This avoids bussing the analog inputs long distances and thus reduces noise pickup on these analog lines. However, in some cases, the analog inputs have a large common mode voltage or even some noise present along with the valid analog signal. The differential input of these converters reduces the effects of common mode input noise. Thus, if a common mode voltage is present on both “+” and “–” inputs, such as 60Hz, the converter will reject this common mode voltage since it only converts the difference between “+” and “–” inputs. The ML2281 family have a true sample and hold circuit which samples both “+” and “–” inputs simultaneously. This simultaneous sampling with a true S/H will give common mode rejection and AC linearity performance that is superior to devices where the two input terminals are not sampled at the same instant and where true sample and hold capability does not exist. Thus, the ML2281 family of devices can reject AC common mode signals from DC-50kHz as well as maintain linearity for signals from DC-50kHz. 14 where N is the number of bits. Thus for ideal 8-bit converter, SNR = 49.92dB. Harmonic Distortion Harmonic distortion is the ratio of the RMS sum of harmonics to the fundamental. Total harmonic distortion (THD) of the ML2281 Series is defined as V 2 + V 2 + V 2 + V 2 3 4 5 2 THD = 20 log V1 where V1 is the RMS amplitude of the fundamental and V2, V3, V4, V5 are the RMS amplitudes of the individual harmonics. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fA and fB, any active device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfA + nfB, where m, n = 0, 1, 2, 3… . Intermodulation terms are those for which m or n is not equal to zero. The (IMD) intermodulation distortion specification includes the second order terms (fA + fB) and (fA – fB) and the third order terms (2fA + fB), (2fA – fB), (fA + 2fB) and (fA – 2fB) only. ML2281, ML2282, ML2284, ML2288 ZERO ERROR ADJUSTMENT The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VIN MIN is not ground, a zero offset can be done. The converter can be made to output 00000000 digital code for this minimum input voltage by biasing any VIN– input at this VIN MIN value. This utilizes the differential mode operation of the A/D. The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the VIN– input and applying a small magnitude positive voltage to the VIN+ input. Zero error is the difference between the actual DC input voltage which is necessary to just cause an output digital code transition from 00000000 to 00000001 and the ideal 1/2 LSB value (1/2 LSB = 9.8mV for VREF = 5.000VDC). FULL-SCALE ADJUSTMENT The full-scale adjustment can be made by applying a differential input voltage which is 1-1/2 LSB down from the desired analog full-scale voltage range and then adjusting the magnitude of the VREF input or VCC for a digital output code which is just changing from 11111110 to 11111111. ADJUSTMENT FOR AN ARBITRARY ANALOG INPUT VOLTAGE RANGE If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference should be properly adjusted first. A VIN+ voltage which equals this desired zero reference plus 1/2 LSB 12V The full-scale adjustment should be made by forcing a voltage to the VIN+ input which is given be: (V − VMIN) VIN + fs adjust = VMAX − 1.5 × MAX 256 where VMAX = high end of the analog input range VMIN = low end (offset zero) of the analog range The VREF or VCC voltage is then adjusted to provide a code change from 11111110 to 11111111. SHUNT REGULATOR A unique feature of ML2288 and ML2284 is the inclusion of a shunt regulator connected from V+ terminal to ground which also connects to the VCC terminal (which is the actual converter supply) through a silicon diode as shown in Figure 8. When the regulator is turned on, the V+ voltage is clamped at 11VBE set by the internal resistor ratio. The typical I-V of the shunt regulator is shown in Figure 9. It should be noted that before V+ voltage is high enough to turn on the shunt regulator (which occurs at about 5.5V), 35kW resistance is observed between V+ and GND. When the shunt regulator is not used, V+ pin should be either left floating or tied to GND. The temperature coefficient of the regulator is –22mV/°C. VCC V+ I+→ CURRENT LIMITING RESISTOR, I+ ≤15mA (where the LSB is calculated for the desired analog span, 1 LSB = analog span/256) is applied to selected “+” input and the zero reference voltage at the corresponding “–” input should then be adjusted to just obtain the 00000000 to 00000001 code transition. 28.8k I+ 15mA 3.2k 3.2k GND SLOPE = 1 35k V+ 5.5V 6.9V Figure 8. Shunt Regulator Figure 9. I-V Characteristic of the Shunt Regulator 15 ML2281, ML2282, ML2284, ML2288 APPLICATIONS CH0 ML2288 CH7 CS P13 CLK P12 DI P11 DO P10 8051 8051 Interface and Controlling Software MNEMONIC INSTRUCTION START ANL MOV MOV P1, #0F7H B, #5 A, #ADDR ;SELECT A/D (CS = 0) ;BIT COUNTER ¬ 5 ;A ¬ MUX BIT LOOP 1: RRC JC A ONE ;CY ¬ ADDRESS BIT ;TEST BIT ;BIT = 0 ZERO: ANL SJMP P1, #0FEH CONT ;DI ¬ 0 ;CONTINUE ;BIT = 1 ONE: ORL P1, #1 ;D1 ¬ 1 CONT: ACALL DJNZ ACALL MOV PULSE B, LOOP 1 PULSE B, #8 ;PULSE SK 0 ® 1 ® 0 ;CONTINUE UNTIL DONE ;EXTRA CLOCK FOR SYNC ;BIT COUNTER ¬ 8 LOOP 2: ACALL MOV RRC RRC MOV RLC MOV DJNZ PULSE A, P1 A A A, C A C, A B, LOOP 2 ;PULSE SK 0 ® 1 ® 0 ;CY ¬ DO ;A ¬ RESULT ;A(0) BIT ¬ AND SHIFT ;C ¬ RESULT ;CONTINUE UNTIL DONE RETI ;PULSE SUBROUTINE PULSE: 16 ORL NOP ANL RET P1, #04 P1, #0FBH ;SK ¬ 1 ;DELAY ;SK ¬ 0 ML2281, ML2282, ML2284, ML2288 APPLICATIONS (Continued) MUX ADDRESS 5VDC 51kΩ (4) START BIT SGL/DIF 11 15 CLK 12 13 CLK INT 2 START 3 4 5 6 7 GND 7 NC DO INPUT SHIFT REGISTER 74HC165 CLK 1 SHIFT/ LOAD SIN 10 + 14 PARALLEL INPUTS DO VCC 9 14 NC 5VDC 5VDC (OR VIN) 1kΩ (8) 8 18 START 5 VDC 0.01µF 7 6 5 5 4 CS 10kΩ CLK NC 4 3 3 2 2 1 1 9 COM 17 D1 0 ANALOG INPUTS 16 CLK SE ML2288 5VDC 13 15 SARS 51kΩ VREF 12 CLK CLOSE TO START THE A/D CONVERSION 7 6 1/8 VCC AGND 11 DGND 10 VCC V+ 19 DO 14 20 10kΩ 0.001µF 7 CLOCK GENERATOR 1 CLR 14 VCC SI A GND 1 + 10µF OUTPUT SHIFT REGISTER 74HC164 8 CLK CLK Q 2 CLK QH 13 SI B QA 12 11 10 6 5 4 3 D CLK 1.3kΩ (8) 1/2 74HC74 MSB DATA DISPLAY LSB 5VDC ML2288 “Stand-Alone” or Evaluation Circuit 17 ML2281, ML2282, ML2284, ML2288 VCC (5 VDC) TA 3kΩ VIN (+) LM335 VCC + 10µF ML2281 10kΩ TA MIN ADJ. VIN (–) VREF Low-Cost Remote Temperature Sensor 18 10kΩ TA MAX ADJ. ML2281, ML2282, ML2284, ML2288 APPLICATIONS (Continued) 330Ω VCC (5VDC) VIN (+) + VCC VIN 10V 6.8kΩ + 10µF ML2281 10kΩ FS ADJ. 1.2kΩ 5.1V 1kΩ GAIN STRAIN GAUGE LOAD CELL 300Ω/30mV FS VCC + VREF – CLK DUAL 2.7kΩ 10kΩ 1MΩ ML2281 CS + 1kΩ VIN (–) SETS ZERO CODE VOLTAGE 2.7kΩ VREF 330Ω 3V + 1µF –IN – SET VOLTAGE SPAN DUAL 1MΩ 20kΩ +IN DO 10V 10kΩ OFFSET 1kΩ 2VDC 20kΩ ZERO ADJ. • USES ONE MORE WIRE THAN LOAD CELL ITSELF • TWO MINI-DIPs COULD BE MOUNTED INSIDE LOAD CELL FOR DIGITAL OUTPUT TRANSDUCER • ELECTRONIC OFFSET AND GAIN TRIMS RELAX MECHANICAL SPECS FOR GAUGE FACTOR AND OFFSET • LOW LEVEL CELL OUTPUT IS CONVERTED IMMEDIATELY FOR HIGH NOISE IMMUNITY Digital Load Cell Zero-Shift and Span Adjust: 2V - VIN - 5V T1 + TYPE J tREF + 1kΩ – CH0 VCC – 88.2k ML2288 CH7 22kΩ + TL064 COM – LM335 tREF 1kΩ + TL064 tREF – TL064 – – TYPE J + T8 + VREF + 2kΩ SERIAL I/O 910Ω 88.2kΩ – 1kΩ VCC 820Ω 1kΩ 3kΩ VCC 20kΩ LM385 USES THE PSEUDO-DIFFERENTIAL MODE TO KEEP THE DIFFERENTIAL INPUTS CONSTANT WITH CHANGES IN REFERENCE TEMPERATURE (TREF) Convert 8 Thermocouples with only One Cold-Junction Compensator 19 ML2281, ML2282, ML2284, ML2288 APPLICATIONS (Continued) VCC (5VDC) 15VDC OP AMP + VCC VIN + (( – – R > 2.5V ≤ 2.5V VIN (+) VCC + 10µF –15VDC + ML2281 – – 600Ω VREF + ML2281 VIN (–) R DIODE CLAMPING IS NOT NEEDED IF CURRENT IS LIMITED TO 25mA CONTROLLER PERFORMS A ROUTINE TO DETERMINE WHICH INPUT POLARITY PROVIDES A NON-ZERO OUTPUT CODE. THIS INFORMATION PROVIDES THE EXTRA BITS. Obtaining 9-Bit Resolution Protecting the Input 0.1Ω VCC (5VDC) → ILOAD (2A FULL-SCALE) VCC (5VDC) 100Ω VIN (–) VCC LOAD + 10µF 240kΩ 9.1kΩ ML2281 100Ω ZERO ADJ. 2kΩ LM336 – VREF + VIN (+) + 1µF 3kΩ 1kΩ FS ADJ. 120kΩ Digitizing a Current Flow VCC (5VDC) VCC (5VDC) 20kΩ XDR VXDR VIN (+) 1kΩ ZERO ADJ. VCC VIN (–)* 3kΩ + + 10µF VIN (+) VCC VIN ML2281 10kΩ + 10µF 10kΩ FS ADJ. ML2281 1kΩ – + + 1µF 24kΩ – 0.7 VCC VIN (–) VREF + VREF 1kΩ FS ADJ. + 1µF SET FOR 3V *VIN (–) = 0.15VCC 15% OF VCC ≤VXDR ≤85% OF VCC Operating with Ratiometric Transducers 20 Span Adjust: 0V - VIN - 3V 2kΩ ML2281, ML2282, ML2284, ML2288 APPLICATIONS (Continued) → 4mA–20mA 1N4148 100kΩ = 50kHZ 1/6 74HC14 + 100Ω 1000pF 10µF INP 24kΩ 6.2kΩ 200kΩ VCC VO5 CLK +IN VCC CD4024 47µF 50pF ML2281 LM385–2.5V 10kΩ 5kΩ LM385–2.5V 100kΩ –IN CS VREF DO 6N139 OPTO COUPLER GND 3.9kΩ 2 10kΩ 3 5 6 8 300kΩ 47kΩ VCC → V+ VO GND • ALL POWER SUPPLIED BY LOOP • 1500V ISOLATION AT OUTPUT 4mA–20mA Current Loop Converter TRANSFORMER TRW-TC-SSD-32 3 1N4148 + 10kΩ 1N4148 7 2 2N2222 6V 1 VCC 6 6V 6V 100kΩ CLK 470Ω CS 4N28 10kΩ 100µF 47kΩ 5 CLK VCC OUT VCC VCC 100kΩ 470Ω ML2288 D1 CS 2N2222 4N28 8 ANALOG CHANNELS VCC DO 6.8kΩ 10kΩ DI 2N2222 8 2 6 5 3 6N139 HIGH GAIN OPTOCOUPLER • NO POWER REQUIRED REMOTELY • 1500V ISOLATION Isolated Data Converter 21 ML2281, ML2282, ML2284, ML2288 APPLICATIONS (Continued) START S LS193 LOAD A B B0 COUNT C D DOWN Q R TMS320 SERIES D 5V Q Q D Q DSP Q D Q Q ML2281 VIN+ VIN– FSR CLK CLK CS DO DR CLK Sampling Rate 111kHz, Data Rate 1.33MHz CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 START CS FSR DO HI-Z D7 D6 D5 D4 D3 D2 Interfacing ML2281 to TMS320 Series 22 D1 D0 HI-Z ML2281, ML2282, ML2284, ML2288 PHYSICAL DIMMENSIONS inches (millimeters) Package: P08 8-Pin PDIP 0.365 - 0.385 (9.27 - 9.77) 0.055 - 0.065 (1.39 - 1.65) 8 0.240 - 0.260 0.299 - 0.335 (6.09 - 6.60) (7.59 - 8.50) PIN 1 ID 1 0.020 MIN (0.51 MIN) (4 PLACES) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.020 (0.40 - 0.51) 0º - 15º 0.008 - 0.012 (0.20 - 0.31) SEATING PLANE Package: S08 8-Pin SOIC 0.189 - 0.199 (4.80 - 5.06) 8 PIN 1 ID 0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20) 1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0º - 8º 0.055 - 0.061 (1.40 - 1.55) 0.012 - 0.020 (0.30 - 0.51) 0.004 - 0.010 (0.10 - 0.26) 0.015 - 0.035 (0.38 - 0.89) 0.006 - 0.010 (0.15 - 0.26) SEATING PLANE 23 ML2281, ML2282, ML2284, ML2288 PHYSICAL DIMMENSIONS inches (millimeters) Package: P14 14-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 14 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.25) PIN 1 ID 1 0.070 MIN (1.77 MIN) (4 PLACES) 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S14 14-Pin SOIC 0.337 - 0.347 (8.56 - 8.81) 14 0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20) PIN 1 ID 1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0º - 8º 0.055 - 0.061 (1.40 - 1.55) 24 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.004 - 0.010 (0.10 - 0.26) 0.015 - 0.035 (0.38 - 0.89) 0.006 - 0.010 (0.15 - 0.26) ML2281, ML2282, ML2284, ML2288 PHYSICAL DIMMENSIONS inches (millimeters) Package: P20 20-Pin PDIP 1.010 - 1.035 (25.65 - 26.29) 20 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) PIN 1 ID 1 0.060 MIN (1.52 MIN) (4 PLACES) 0.100 BSC (2.54 BSC) 0.055 - 0.065 (1.40 - 1.65) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) SEATING PLANE 0.016 - 0.022 (0.40 - 0.56) 0.125 MIN (3.18 MIN) 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: Q20 20-Pin PLCC 0.385 - 0.395 (9.78 - 10.03) 0.042 - 0.056 (1.07 - 1.42) 0.350 - 0.356 (8.89 - 9.04) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 1 0.042 - 0.048 (1.07 - 1.22) 6 PIN 1 ID 16 0.350 - 0.356 (8.89 - 9.04) 0.385 - 0.395 (9.78 - 10.03) 0.200 BSC (5.08 BSC) 0.290 - 0.330 (7.36 - 8.38) 11 0.009 - 0.011 (0.23 - 0.28) 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.19 - 4.57) 0.146 - 0.156 (3.71 - 3.96) 0.100 - 0.110 (2.54 - 2.79) 0.013 - 0.021 (0.33 - 0.53) SEATING PLANE 25 ML2281, ML2282, ML2284, ML2288 ORDERING INFORMATION PART NUMBER ALTERNATE PART NUMBER TOTAL UNADJUSTED ERROR TEMPERATURE RANGE PACKAGE SINGLE ANALOG INPUT, 8-PIN PACKAGE ML2281BIP (Obsolete) ML2281BCP ML2281BCS (Obsolete ADC0831CCN ADC0831BCN — ±1/2 LSB –40°C to 85°C 0°C to 70°C 0°C to 70°C Plastic DIP (P08) Molded DIP (P08) Plastic SOIC (S08) ML2281CIP (End of Life) ML2281CCP (End of Life) ML2281CCS (End of Life) ADC0831BCN ADC0831CCN — ±1 LSB –40°C to 85°C 0°C to 70°C 0°C to 70°C Plastic DIP (P08) Molded DIP (P08) Plastic SOIC (S08) TWO ANALOG INPUTS, 8-PIN PACKAGE ML2282BIP (Obsolete) ML2282BCP (Obsolete) ML2282BCS (Obsolete) ADC0832CCN ADC0832BCN — ±1/2 LSB –40°C to 85°C 0°C to 70°C 0°C to 70°C Plastic DIP (P08) Molded DIP (P08) Plastic SOIC (S08) ML2282CIP (Obsolete) ML2282CCP (Obsolete) ML2282CCS (Obsolete) ADC0832BCN ADC0832CCN — ±1 LSB –40°C to 85°C 0°C to 70°C 0°C to 70°C Plastic DIP (P08) Molded DIP (P08) Plastic SOIC (S08) FOUR ANALOG INPUTS, 14-PIN PACKAGE ML2284BIP (Obsolete) ML2284BCP (Obsolete) ML2284BCS (Obsolete) ADC0834CCN ADC0834BCN — ±1/2 LSB –40°C to 85°C 0°C to 70°C 0°C to 70°C Plastic DIP (P14) Molded DIP (P14) Plastic SOIC (S14) ML2284CIP (Obsolete) ML2284CCP (End of Life) ML2284CCS (Obsolete) ADC0834BCN ADC0834CCN — ±1 LSB –40°C to 85°C 0°C to 70°C 0°C to 70°C Plastic DIP (P14) Molded DIP (P14) Plastic SOIC (S14) EIGHT ANALOG INPUTS, 20-PIN PACKAGE ML2288BIP (Obsolete) ML2288BCP (Obsolete) ML2288BCQ (Obsolete) ADC0838CCN ADC0838BCN ADC0838BCV ±1/2 LSB –40°C to 85°C 0°C to 70°C 0°C to 70°C Plastic DIP (P20) Molded DIP (P20) Molded PCC (Q20) ML2288CIP (Obsolete) ML2288CCP (Obsolete) ML2288CCQ (End of Life) ADC0838CCN ADC0838CCN ADC0838CCV ±1 LSB –40°C to 85°C 0°C to 70°C 0°C to 70°C Plastic DIP (P20) Molded DIP (P20) Molded PCC (Q20) DS2281_82_84_88-01 © Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 26 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 5/5/97 Printed in U.S.A.