MM54HC137/MM74HC137 3-to-8 Line Decoder With Address Latches (Inverted Output) General Description This device utilizes advanced silicon-gate CMOS technology, to implement a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are high unless G1 is high and G2 is low. The HC137 is ideally suited for the implementation of glitch-free decoders in stored-address applications in bus oriented systems. The 54HC/74HC logic family is speed, function and pin-out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features Y Y Y Y Typical propagation delay: 20 ns Wide supply range: 2 – 6V Latched inputs for easy interfacing. Fanout of 10 LS-TTL loads. Connection and Functional Block Diagrams Dual-In-Line Package TL/F/5310–1 Order Number MM54HC137 or MM74HC137 C1995 National Semiconductor Corporation TL/F/5310 TL/F/5310 – 2 RRD-B30M115/Printed in U. S. A. MM54HC137/MM74HC137 3-to-8 Line Decoder With Address Latches (Inverted Output) November 1995 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temp. Range (TA) MM74HC MM54HC Input Rise or Fall Times (tr, tf) VCC e 2.0V VCC e 4.5V VCC e 6.0V b 0.5 to a 7.0V DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) b 1.5 to VCC a 1.5V b 0.5 to VCC a 0.5V g 20 mA g 25 mA g 50 mA b 65§ C to a 150§ C Min 2 0 Max 6 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns 600 mW 500 mW (Soldering 10 seconds) 260§ C DC Electrical Characteristics (Note 4) Symbol Parameter Conditions TA e 25§ C VCC 74HC TA eb40 to 85§ C Typ 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 3.98 5.48 3.84 5.34 3.7 5.2 V V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s20 mA VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.5V 6.0V 2.0V 4.5V 6.0V 0 0 0 VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA 4.5V 6.0V 0.26 0.26 0.33 0.33 0.4 0.4 V V IIN Maximum Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V 8.0 80 160 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns Symbol Parameter Conditions Typ Guaranteed Limit Units ns tPLH Maximum Propagation Delay, A, B or C to any Y Output 14 29 tPHL Maximum Propagation Delay, A, B or C to any Y Output 20 42 ns tPLH Maximum Propagation Delay G2 to any Y Output 12 22 ns tPHL Maximum Propagation Delay G2 to any Y Output 15 34 ns tPLH Maximum Propagation Delay G1 to any Output 13 25 ns tPHL Maximum Propagation Delay GL to any Output 17 34 ns tPLH Maximum Propagation GL to Output 15 30 ns tPHL Maximum Propagation Delay GL to Output 22 34 ns tS Minimum Setup Time at A, B and C Inputs 20 ns tH Minimum Hold Time at A, B and C Inputs 0 ns tW Minimum Pulse Width of Enabling Pulse at GL 16 ns AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions TA e 25§ C VCC Typ 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits tPLH Maximum Propagation Delay A, B or C to any Y Output 2.0V 4.5V 6.0V 85 17 14 170 34 29 214 43 36 253 51 43 ns ns ns tPHL Maximum Propagation Delay A, B or C to any Y Output 2.0V 4.5V 6.0V 120 24 20 240 48 41 302 60 51 358 72 61 ns ns ns tPLH Maximum Propagation Delay G2 to any Y Output 2.0V 4.5V 6.0V 65 13 11 130 26 22 164 33 28 194 39 33 ns ns ns tPLH Maximum Propagation Delay G1 to Output 2.0V 4.5V 6.0V 75 15 13 150 30 26 189 38 32 224 45 38 ns ns ns tPHL Maximum Propagation Delay G1 to Output 2.0V 4.5V 6.0V 98 20 17 195 39 33 246 49 42 291 58 49 ns ns ns tPLH Maximum Propagation Delay GL to Output 2.0V 4.5V 6.0V 88 18 15 175 35 30 221 44 37 261 52 44 ns ns ns tPHL Maximum Propagation Delay GL to Output 2.0V 4.5V 6.0V 125 25 21 250 50 43 315 63 54 373 75 63 ns ns ns tPHL Maximum Propagation Delay G2, to any Y Output 2.0V 4.5V 6.0V 98 20 17 195 39 33 246 49 42 291 58 49 ns ns ns tS Minimum Setup Time at A, B and C inputs 2.0V 4.5V 6.0V 100 20 17 125 25 21 150 30 25 ns ns ns tH Minimum Hold Time at A, B and C inputs 2.0V 4.5V 6.0V 50 10 8 63 13 11 75 15 13 ns ns ns tTLH, tTHL Output Rise and Fall Time 2.0V 4.5V 6.0V 75 15 13 95 19 16 110 22 19 ns ns ns tW Minimum Pulse Width of Enabling Pulse at GL 2.0V 4.5V 6.0V 80 16 14 100 20 18 120 24 21 ns ns ns CPD Power Dissipation Capacitance (Note 5) 75 CIN Maximum Input Capacitance 5 30 8 7 pF 10 10 10 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 Typical Application TL/F/5310 – 3 6-Line to 64-Line Decoder with Input Address Storage Truth Table Inputs Outputs Enable Select GL G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X X L H X X X X X X X H H H H H H H H H H H H H H H H L L L L H H H H L L L L L L L L L L H H L H L H L H H H H L H H H H L H H H H L H H H H H H H H H H H H H H H H L L L L H H H H L L L L H H H H L L H H L H L H H H H H H H H H H H H H H H H H L H H H H L H H H H L H H H H L H H L X X X Output corresponding to stored address L; all others, H H e high level, L e low level, X e irrelevant 4 5 MM54HC137/MM74HC137 3-to-8 Line Decoder With Address Latches (Inverted Output) Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54HC137J or MM74HC137J NS Package J16A Molded Dual-In-Line Package (N) Order Number MM74HC137N NS Package N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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