Revised January 1999 MM74C00 • MM74C02 • MM74C04 Quad 2-Input NAND Gate • Quad 2-Input NOR Gate • Hex Inverter General Description The MM74C00, MM74C02, and MM74C04 logic gates employ complementary MOS (CMOS) to achieve wide power supply operating range, low power consumption, high noise immunity and symmetric controlled rise and fall times. With features such as this the 74C logic family is close to ideal for use in digital systems. Function and pin out compatibility with series 74 devices minimizes design time for those designers already familiar with the standard 74 logic family. All inputs are protected from damage due to static discharge by diode clamps to VCC and GND. Features ■ Wide supply voltage range: ■ Guaranteed noise margin: ■ High noise immunity: 3V to 15V 1V 0.45 VCC (typ.) ■ Low power consumption: 10 nW/package (typ.) ■ Low power: TTL compatibility: Fan out of 2 driving 74L Ordering Code: Order Number MM74C00M Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74C00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide MM74C02N M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74C04M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74C04N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP and SOIC MM74C00 MM74C02 Top View Top View MM74C04 Top View © 1999 Fairchild Semiconductor Corporation DS005877.prf www.fairchildsemi.com MM74C00 • MM74C02 • MM74C04 Quad 2-Input NAND Gate • Quad 2-Input NOR Gate • Hex Inverter October 1987 MM74C00 • MM74C02 • MM74C04 Absolute Maximum Ratings(Note 1) Lead Temperature (Soldering, 10 seconds) −0.3V to VCC + 0.3V Voltage at Any Pin Operating Temperature Range Storage Temperature Range Operating VCC Range 300°C −40°C to +85°C −65°C to +150°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. 3.0V to 15V Maximum VCC Voltage 18V Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW DC Electrical Characteristics Min/Max limits apply across the guaranteed temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage VCC = 5.0V 3.5 V VCC = 10V 8.0 V VCC = 5.0V 1.5 V VCC = 10V 2.0 V VCC = 5.0V, IO = −10 µA 4.5 VCC = 10V, IO = −10 µA 9.0 V V VCC = 5.0V, IO = 10 µA 0.5 V VCC = 10V, IO = 10 µA 1.0 V 1.0 µA IIN(1) Logical “1” Input Current VCC = 15V, VIN = 15V IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V ICC Supply Current VCC = 15V 0.005 −1.0 −0.005 0.01 µA 15 µA 0.8 V LOW POWER TO CMOS VIN(1) Logical “1” Input Voltage 74C, VCC = 4.75V VIN(0) Logical “0” Input Voltage 74C, VCC = 4.75V VOUT(1) Logical “1” Output Voltage 74C, VCC = 4.75V, IO = −10 µA VOUT(0) Logical “0” Output Voltage 74C, VCC = 4.75V, IO = 10 µA VCC − 1.5 V 4.4 V 0.4 V CMOS TO LOW POWER VIN(1) Logical “1” Input Voltage 74C, VCC = 4.75V VIN(0) Logical “0” Input Voltage 74C, VCC = 4.75V VOUT(1) Logical “1” Output Voltage 74C, VCC = 4.75V, IO = −360 µA VOUT(0) Logical “0” Output Voltage 74C, VCC = 4.75V, IO = 360 µA 4.0 V 1.0 2.4 V V 0.4 V OUTPUT DRIVE (see Family Characteristics Data Sheet) TA = 25°C (short circuit current) ISOURCE Output Source Current VCC = 5.0V, VIN(0) = 0V, VOUT = 0V −1.75 mA ISOURCE Output Source Current VCC = 10V, VIN(0) = 0V, VOUT = 0V −8.0 mA ISINK Output Sink Current VCC = 5.0V, VIN(1) = 5.0V, VOUT = VCC 1.75 mA ISINK Output Sink Current VCC = 10V, VIN(1) = 10V, VOUT = VCC 8.0 mA AC Electrical Characteristics (Note 2) TA = 25°C, CL = 50 pF, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units MM74C00, MM74C02, MM74C04 Propagation Delay Time to VCC = 5.0V 50 90 ns Logical “1” or “0” VCC = 10V 30 60 ns CIN Input Capacitance (Note 3) 6.0 pF CPD Power Dissipation Capacitance Per Gate or Inverter (Note 4) 12 pF tpd0, tpd1 Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note— AN-90. www.fairchildsemi.com 2 Gate Transfer Characteristics Propagation Delay vs Ambient Temperature MM74C00, MM74C02, MM74C04 Guaranteed Noise Margin Over Temperature vs VCC Propagation Delay vs Ambient Temperature MM74C00, MM74C02, MM74C04 Propagation Delay Time vs Load Capacitance MM74C00, MM74C02, MM74C04 Power Dissipation vs Frequency MM74C00, MM74C02, MM74C04 3 www.fairchildsemi.com MM74C00 • MM74C02 • MM74C04 Typical Performance Characteristics MM74C00 • MM74C02 • MM74C04 Switching Time Waveforms and AC Test Circuit CMOS to CMOS Delays measured with input tr, tf ≤ 20 ns. www.fairchildsemi.com 4 MM74C00 • MM74C02 • MM74C04 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A 5 www.fairchildsemi.com MM74C00 • MM74C02 • MM74C04 Quad 2-Input NAND Gate • Quad 2-Input NOR Gate • Hex Inverter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. 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