Fairchild MM74C922N 16-key encoder â ¢ 20-key encoder Datasheet

Revised April 2001
MM74C922 • MM74C923
16-Key Encoder • 20-Key Encoder
General Description
Features
The MM74C922 and MM74C923 CMOS key encoders provide all the necessary logic to fully encode an array of
SPST switches. The keyboard scan can be implemented
by either an external clock or external capacitor. These
encoders also have on-chip pull-up devices which permit
switches with up to 50 kΩ on resistance to be used. No
diodes in the switch array are needed to eliminate ghost
switches. The internal debounce circuit needs only a single
external capacitor and can be defeated by omitting the
capacitor. A Data Available output goes to a high level
when a valid keyboard entry has been made. The Data
Available output returns to a low level when the entered
key is released, even if another key is depressed. The Data
Available will return high to indicate acceptance of the new
key after a normal debounce period; this two-key roll-over
is provided between any two switches.
■ 50 kΩ maximum switch on resistance
■ On or off chip clock
■ On-chip row pull-up devices
■ 2 key roll-over
■ Keybounce elimination with single capacitor
■ Last key register at outputs
■ 3-STATE output LPTTL compatible
■ Wide supply range:
3V to 15V
■ Low power consumption
An internal register remembers the last key pressed even
after the key is released. The 3-STATE outputs provide for
easy expansion and bus operation and are LPTTL compatible.
Ordering Code:
Order Number
MM74C922WM
Package Number
M20B
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74C922N
N18B
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74C923WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74C923N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignment for DIP
Pin Assignment for SOIC
Top View
MM74C922
Top View
MM74C922
© 2001 Fairchild Semiconductor Corporation
DS006037
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MM74C922 • MM74C923 16-Key Encoder • 20-Key Encoder
October 1987
MM74C922 • MM74C923
Connection Diagrams
(Continued)
Pin Assignment for
DIP and SOIC Package
Top View
MM74C923
Truth Tables
(Pins 0 through 11)
Switch
Position
0
1
2
3
4
5
Y1, X1 Y1, X2 Y1, X3 Y1, X4 Y2, X1 Y2, X2
6
7
Y2, X3 Y2, X4
8
9
10
11
Y3, X1
Y3, X2
Y3, X3
Y3, X4
D
A
A
0
1
0
1
0
1
0
1
0
1
0
1
T
B
0
0
1
1
0
0
1
1
0
0
1
1
A
C
0
0
0
0
1
1
1
1
0
0
0
0
O
D
0
0
0
0
0
0
0
0
1
1
1
1
U
E (Note 1)
0
0
0
0
0
0
0
0
0
0
0
0
T
(Pins 12 through 19)
Switch
12
13
14
15
Position
Y4, X1
Y4, X2
Y4, X3
Y4, X4
16
17
18
19
A
A
0
1
0
1
0
1
0
1
T
B
0
0
1
1
0
0
1
1
A
C
1
1
1
1
0
0
0
0
O
D
1
1
1
1
0
0
0
0
U
E (Note 1)
0
0
0
0
1
1
1
1
Y5(Note 1), X1 Y5 (Note 1), X2 Y5 (Note 1), X3 Y5 (Note 1), X4
D
T
Note 1: Omit for MM74C922
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MM74C922 • MM74C923
Block Diagram
3
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MM74C922 • MM74C923
Absolute Maximum Ratings(Note 2)
Voltage at Any Pin
VCC − 0.3V to V CC + 0.3V
Operating Temperature Range
MM74C922, MM74C923
Storage Temperature Range
−40°C to +85°C
−65°C to +150°C
Power Dissipation (P D)
Dual-In-Line
700 mW
Small Outline
500 mW
Operating VCC Range
3V to 15V
VCC
Note 2: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
18V
Lead Temperature
260°C
(Soldering, 10 seconds)
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
CMOS TO CMOS
VT+
VT−
VIN(1)
VIN(0)
Irp
VOUT(1)
VOUT(0)
Ron
ICC
Positive-Going Threshold Voltage
VCC = 5V, IIN ≥ 0.7 mA
3.0
3.6
4.3
at Osc and KBM Inputs
VCC = 10V, IIN ≥ 1.4 mA
6.0
6.8
8.6
V
VCC = 15V, IIN ≥ 2.1 mA
9.0
10
12.9
V
V
Negative-Going Threshold Voltage
VCC = 5V, IIN ≥ 0.7 mA
0.7
1.4
2.0
at Osc and KBM Inputs
VCC = 10V, IIN ≥ 1.4 mA
1.4
3.2
4.0
V
VCC = 15V, IIN ≥ 2.1 mA
2.1
5
6.0
V
Logical “1” Input Voltage,
VCC = 5V
3.5
4.5
V
Except Osc and KBM Inputs
VCC = 10V
8.0
9
V
VCC = 15V
12.5
13.5
Logical “0” Input Voltage,
VCC = 5V
Except Osc and KBM Inputs
VCC = 10V
VCC = 15V
Row Pull-Up Current at Y1, Y2,
VCC = 5V, VIN = 0.1 VCC
Y3, Y4 and Y5 Inputs
Logical “1” Output Voltage
Logical “0” Output Voltage
V
1.5
V
1
2
V
1.5
2.5
V
−2
−5
µA
VCC = 10V
−10
−20
µA
VCC = 15V
−22
−45
µA
VCC = 5V, IO = −10 µA
4.5
V
VCC = 10V, IO = −10 µA
9
V
VCC = 15V, IO = −10 µA
13.5
V
VCC = 5V, IO = 10 µA
0.5
V
VCC = 10V, IO = 10 µA
1
V
VCC = 15V, IO = 10 µA
1.5
V
1400
Ω
Ω
Column “ON” Resistance at
VCC = 5V, VO = 0.5V
X1, X2, X3 and X4 Outputs
VCC = 10V, VO = 1V
300
700
VCC = 15V, VO = 1.5V
200
500
Ω
VCC = 5V
0.55
1.1
mA
VCC = 10V
1.1
1.9
mA
VCC = 15V
1.7
2.6
mA
0.005
1.0
µA
Supply Current
Osc at 0V, (one Y low)
IIN(1)
0.5
Logical “1” Input Current
500
VCC = 15V, VIN = 15V
at Output Enable
IIN(0)
Logical “0” Input Current
VCC = 15V, VIN = 0V
−1.0
−0.005
µA
at Output Enable
CMOS/LPTTL INTERFACE
Except Osc and KBM Inputs
VCC = 4.75V
VIN(0)
Except Osc and KBM Inputs
VCC = 4.75V
VOUT(1)
Logical “1” Output Voltage
IO = −360 µA
VIN(1)
VCC − 1.5
VCC = 4.75V
2.4
IO = −360 µA
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V
0.8
4
V
V
Symbol
Parameter
VOUT(0)
Logical “0” Output Voltage
(Continued)
Conditions
Min
Typ
Max
Units
0.4
V
IO = −360 µA
VCC = 4.75V
IO = −360 µA
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCE
ISOURCE
ISINK
ISINK
Output Source Current
VCC = 5V, VOUT = 0V,
(P-Channel)
TA = 25°C
Output Source Current
VCC = 10V, VOUT = 0V,
(P-Channel)
TA = 25°C
Output Sink Current
VCC = 5V, VOUT = VCC,
(N-Channel)
TA = 25°C
Output Sink Current
VCC = 10V, VOUT = VCC,
(N-Channel)
TA = 25°C
AC Electrical Characteristics
t0H, t1H
tH0, tH1
Propagation Delay Time to
−3.3
mA
−8
−15
mA
1.75
3.6
mA
8
16
mA
Min
Typ
Max
Units
ns
(Note 3)
TA = 25°C, CL = 50 pF, unless otherwise noted
Symbol
Parameter
tpd0, tpd1
−1.75
Conditions
CL = 50 pF (Figure 1)
Logical “0” or Logical “1”
VCC = 5V
60
150
from D.A.
VCC = 10V
35
80
ns
VCC = 15V
25
60
ns
Propagation Delay Time from
RL = 10k, CL = 10 pF (Figure 2)
Logical “0” or Logical “1”
VCC = 5V, RL = 10k
80
200
ns
into High Impedance State
VCC = 10V, C L = 10 pF
65
150
ns
VCC = 15V
50
110
ns
Propagation Delay Time from
RL = 10k, CL = 50 pF (Figure 2)
High Impedance State to a
VCC = 5V, RL = 10k
100
250
ns
Logical “0” or Logical “1”
VCC = 10V, CL = 50 pF
55
125
ns
VCC = 15V
40
90
ns
CIN
Input Capacitance
Any Input (Note 4)
5
7.5
pF
COUT
3-STATE Output Capacitance
Any Output (Note 4)
10
pF
Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: Capacitance is guaranteed by periodic testing.
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MM74C922 • MM74C923
DC Electrical Characteristics
MM74C922 • MM74C923
Switching Time Waveforms
T1 ≈ T2 ≈ RC, T3 ≈ 0.7 RC, where R ≈ 10k and C is external capacitor at KBM input.
FIGURE 1.
FIGURE 2.
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Typical Irp vs VIN at Any Y Input
Typical Ron vs VOUT at Any X Output
Typical FSCAN vs COSC
Typical Debounce Period vs CKBM
Typical Applications
Synchronous Handshake (MM74C922)
Synchronous Data Entry Onto Bus (MM74C922)
The keyboard may be synchronously scanned by omitting the capacitor at
osc. and driving osc. directly if the system clock rate is lower than 10 kHz
Outputs are enabled when valid entry is made and go into 3-STATE when
key is released.
The keyboard may be synchronously scanned by omitting the capacitor at
osc. and driving osc. directly if the system clock rate is lower than 10 kHz
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MM74C922 • MM74C923
Typical Performance Characteristics
MM74C922 • MM74C923
Asynchronous Data Entry Onto Bus (MM74C922)
Outputs are in 3-STATE until key is pressed, then data is placed on bus. When key is released, outputs return to 3-STATE.
Expansion to 32 Key Encoder (MM74C922)
Theory of Operation
going low also initiates the key bounce circuit timing and
locks out the other Y inputs. The key code to be output is a
combination of the frozen counter value and the decoded Y
inputs. Once the key bounce circuit times out, the data is
latched, and the Data Available (DAV) output goes high.
The MM74C922/MM74C923 Keyboard Encoders implement all the logic necessary to interface a 16 or 20 SPST
key switch matrix to a digital system. The encoder will convert a key switch closer to a 4(MM74C922) or
5(MM74C923) bit nibble. The designer can control both the
keyboard scan rate and the key debounce period by altering the oscillator capacitor, COSE, and the key bounce
mask capacitor, CMSK. Thus, the MM74C922/MM74C923’s
performance can be optimized for many keyboards.
If, during the key closure the switch bounces, Y1 input will
go high again, restarting the scan and resetting the key
bounce circuitry. The key may bounce several times, but as
soon as the switch stays low for a debounce period, the
closure is assumed valid and the data is latched.
The keyboard encoders connect to a switch matrix that is 4
rows by 4 columns (MM74C922) or 5 rows by 4 columns
(MM74C923). When no keys are depressed, the row inputs
are pulled high by internal pull-ups and the column outputs
sequentially output a logic “0”. These outputs are open
drain and are therefore low for 25% of the time and otherwise off. The column scan rate is controlled by the oscillator input, which consists of a Schmitt trigger oscillator, a 2bit counter, and a 2–4-bit decoder.
A key may also bounce when it is released. To ensure that
the encoder does not recognize this bounce as another key
closure, the debounce circuit must time out before another
closure is recognized.
The two-key roll-over feature can be illustrated by assuming a key is depressed, and then a second key is
depressed. Since all scanning has stopped, and all other Y
inputs are disabled, the second key is not recognized until
the first key is lifted and the key bounce circuitry has reset.
When a key is depressed, key 0, for example, nothing will
happen when the X1 input is off, since Y1 will remain high.
When the X1 column is scanned, X1 goes low and Y1 will
go low. This disables the counter and keeps X1 low. Y1
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The output latches feed 3-STATE, which is enabled when
the Output Enable (OE) input is taken low.
8
MM74C922 • MM74C923
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
9
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MM74C922 • MM74C923
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N18B
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MM74C922 • MM74C923 16-Key Encoder • 20-Key Encoder
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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