NSC MM74HC Synchronous decade counter with asynchronous clear Datasheet

MM74HC160 Synchronous
Decade Counter with Asynchronous Clear
MM54HC161/MM74HC161 Synchronous
Binary Counter with Asynchronous Clear
MM54HC162/MM74HC162 Synchronous
Decade Counter with Synchronous Clear
MM54HC163/MM74HC163 Synchronous
Binary Counter with Synchronous Clear
General Description
The MM54HC160/MM74HC160, MM54HC161/
MM74HC161, MM54HC162/MM74HC162, and
MM54HC163/MM74HC163 synchronous presettable counters utilize advanced silicon-gate CMOS technology and internal look-ahead carry logic for use in high speed counting
applications. They offer the high noise immunity and low
power consumption inherent to CMOS with speeds similar
to low power Schottky TTL. The ’HC160 and the ’HC162 are
4 bit decade counters, and the ’HC161 and the ’HC163 are
4 bit binary counters. All flip-flops are clocked simultaneously on the low to high transition (positive edge) of the CLOCK
input waveform.
These counters may be preset using the LOAD input. Presetting of all four flip-flops is synchronous to the rising edge
of CLOCK. When LOAD is held low counting is disabled and
the data on the A, B, C, and D inputs is loaded into the
counter on the rising edge of CLOCK. If the load input is
taken high before the positive edge of CLOCK the count
operation will be unaffected.
All of these counters may be cleared by utilizing the CLEAR
input. The clear function on the MM54HC162/MM74HC162
and MM54HC163/MM74HC163 counters are synchronous
to the clock. That is, the counters are cleared on the positive edge of CLOCK while the clear input is held low.
The MM54HC160/MM74HC160 and MM54HC161/
MM74HC161 counters are cleared asynchronously. When
the CLEAR is taken low the counter is cleared immediately
regardless of the CLOCK.
Two active high enable inputs (ENP and ENT) and a RIPPLE CARRY (RC) output are provided to enable easy cascading of counters. Both ENABLE inputs must be high to
count. The ENT input also enables the RC output. When
enabled, the RC outputs a positive pulse when the counter
overflows. This pulse is approximately equal in duration to
the high level portion of the QA output. The RC output is fed
to successive cascaded stages to facilitate easy implementation of N-bit counters.
All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Connection Diagram
Truth Tables
Features
Y
Y
Y
Y
Y
Typical operating frequency: 40 MHz
Typical propagation delay; clock to Q: 18 ns
Low quiescent current: 80 mA maximum (74HC Series)
Low input current: 1 mA maximum
Wide power supply range: 2 – 6V
’HC160/HC161
CLK
CLR
ENP
ENT
Load
Function
X
X
X
X
L
H
H
H
H
H
X
H
L
L
X
H
X
L
H
L
X
H
X
H
H
H
L
H
Clear
Count & RC disabled
Count disabled
Count & RC disabled
Load
Increment Counter
u
u
H e high level, L e low level
e low to high transition
X e don’t care,
u
’HC162/HC163
TL/F/5008 – 1
Order Number MM54HC161/162/163
or MM74HC160/161/162/163
C1995 National Semiconductor Corporation
TL/F/5008
CLK
CLR
ENP
ENT
Load
Function
u
L
H
H
H
H
H
X
H
L
L
X
H
X
L
H
L
X
H
X
H
H
H
L
H
Clear
Count & RC disabled
Count disabled
Count & RC disabled
Load
Increment Counter
X
X
X
u
u
RRD-B30M115/Printed in U. S. A.
74HC160/MM54/74HC161/MM54/74HC162/MM54/74HC163
January 1992
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
b 0.5 to a 7.0V
Supply Voltage (VCC)
b 1.5 to VCC a 1.5V
DC Input Voltage (VIN)
b 0.5 to VCC a 0.5V
DC Output Voltage (VOUT)
g 20 mA
Clamp Diode Current (IIK, IOK)
g 25 mA
DC Output Current, per pin (IOUT)
g 50 mA
DC VCC or GND Current, per pin (ICC)
b 65§ C to a 150§ C
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temp. (TL) (Soldering 10 seconds)
260§ C
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
Units
V
0
VCC
V
b 40
b 55
a 85
a 125
§C
§C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
VCC e 2.0V
(tr, tf)
VCC e 4.5V
VCC e 6.0V
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA e 25§ C
VCC
74HC
TA eb40 to 85§ C
Typ
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage**
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
VOH
Minimum High Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
IIN
Maximum Input
Current
VIN e VCC or GND
6.0V
g 0.1
g 1.0
g 1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN e VCC or GND
IOUT e 0 mA
6.0V
8.0
80
160
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and
IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.
2
AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns
Typ
Guaranteed Limit
Units
fMAX
Symbol
Maximum Operating Frequency
Parameter
Conditions
43
30
MHz
tPHL, tPLH
Maximum Propagation Delay, Clock to RC
30
35
ns
tPHL, tPLH
Maximum Propagation Delay, Clock to Q
29
34
ns
tPHL, tPLH
Maximum Propagation Delay, ENT to RC
18
32
ns
tPHL
Maximum Propagation Delay, Clear to Q or RC
27
38
ns
tREM
Minimum Removal Time, Clear to Clock
10
20
ns
tS
Minimum Set Up Time Clear, Load,
Enable or Data to Clock
30
ns
tH
Minimum Hold Time, Data from Clock
5
ns
tW
Minimum Pulse Width Clock,
Clear, or Load
16
ns
AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TA e 25§ C
Typ
74HC
TA eb40 to 85§ C
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
10
40
45
5
27
32
4
21
25
4
18
21
MHz
MHz
MHz
tPHL
Maximum Propagation
Delay, Clock to RC
2.0V
4.5V
6.0V
100
32
28
215
43
37
271
54
46
320
64
54
ns
ns
ns
tPLH
Maximum Propagation
Delay, Clock to RC
2.0V
4.5V
6.0V
88
18
15
175
35
30
220
44
37
260
52
44
ns
ns
ns
tPHL
Maximum Propagation
Delay, Clock to Q
2.0V
4.5V
6.0V
95
30
26
205
41
35
258
52
44
305
61
52
ns
ns
ns
tPLH
Maximum Propagation
Delay, Clock to Q
2.0V
4.5V
6.0V
85
17
14
170
34
29
214
43
36
253
51
43
ns
ns
ns
tPHL
Maximum Propagation
Delay, ENT to RC
2.0V
4.5V
6.0V
90
28
24
195
39
33
246
49
42
291
58
49
ns
ns
ns
tPLH
Maximum Propagation
Delay, ENT to RC
2.0V
4.5V
6.0V
80
16
14
160
32
27
202
40
34
238
48
41
ns
ns
ns
tPHL
Maximum Propagation
Delay, Clear to RC
2.0V
4.5V
6.0V
100
32
28
220
44
37
275
55
47
325
66
55
ns
ns
ns
tPHL
Maximum Propagation
Delay, Clear to Q
2.0V
4.5V
6.0V
100
32
28
210
42
36
260
52
45
315
63
54
ns
ns
ns
tREM
Minimum Removal Time
Clear to Clock
2.0V
4.5V
6.0V
125
25
21
158
32
27
186
37
32
ns
ns
ns
tS
Minimum Setup
Time Clear or Data
to Clock
2.0V
4.5V
6.0V
150
30
26
190
38
32
225
45
38
ns
ns
ns
tS
Minimum Setup
Time Load
to Clock
2.0V
4.5V
6.0V
135
27
23
170
34
29
200
41
35
ns
ns
ns
tS
Minimum Setup
Time Enable
to Clock
2.0V
4.5V
6.0V
175
35
30
220
44
37
260
52
44
ns
ns
ns
tH
Minimum Hold Time
Data from Clock
2.0V
4.5V
6.0V
50
10
9
63
13
11
75
15
13
ns
ns
ns
3
AC Electrical Characteristics (Continued) CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TA e 25§ C
Typ
74HC
54HC
TA eb40 to 85§ C TA eb55 to 125§ C Units
Guaranteed Limits
tH
Minimum Hold Time
Enable, Load or Clear
to Clock
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
tW
Minimum Pulse Width
Clock, Clear, or
Load
2.0V
4.5V
6.0V
80
16
14
100
20
17
120
24
20
ns
ns
ns
75
15
13
95
19
16
110
22
19
ns
ns
ns
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
tTLH, tTHL Maximum
Output Rise and
Fall Time
2.0V
4.5V
6.0V
tr, tf
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
CPD
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input Capacitance
(per package)
40
8
7
90
5
pF
10
10
10
pF
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption,
IS e CPD VCC f a ICC.
Logic Diagrams
MM54HC160/MM74HC160 or MM54HC162/MM74HC162
TL/F/5008 – 2
MM54HC161/MM74HC161 or MM54HC163/MM74HC163
TL/F/5008 – 3
4
Logic Waveforms
160, 162 Synchronous Decade Counters Typical Clear, Preset, Count and Inhibit Sequences
Sequence:
(1) Clear outputs to zero
(2) Preset to BCD seven
(3) Count to eight, nine, zero, one, two, and three
(4) Inhibit
TL/F/5008 – 4
161, 163 Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences
Sequence:
(1) Clear outputs to zero
(2) Preset to binary twelve
(3) Count to thirteen, fourteen, fifteen, zero, one and two
(4) Inhibit
5
TL/F/5008 – 5
74HC160/MM54/74HC161/MM54/74HC162/MM54/74HC163
Physical Dimensions inches (millimeters)
Order Number MM54HC160J, MM54HC161J, MM54HC162J, MM54HC163J,
MM74HC160J, MM74HC161J, MM74HC162J, MM74HC163J
NS Package J16A
Order Number MM74HC160N, MM74HC161N, MM74HC162N, MM74HC163N
NS Package N16E
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