MM74HC125, MM74HC126 3-STATE Quad Buffers Features General Description ■ Typical propagation delay: 13ns The MM74HC125 and MM74HC126 are general purpose 3-STATE high speed non-inverting buffers utilizing advanced silicon-gate CMOS technology. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs. ■ Wide operating voltage range: 2V–6V ■ Low input current: 1µA maximum ■ Low quiescent current: 80µA maximum (74HC) ■ Fanout of 15 LS-TTL loads The MM74HC125 require the 3-STATE control input C to be taken high to put the output into the high impedance condition, whereas the MM74HC126 require the control input to be low to put the output into high impedance. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Ordering Information Order Number Package Number Package Description MM74HC125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC125N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74HC126M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC126SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC126MTC MM74HC126N MTC14 N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1983 Fairchild Semiconductor Corporation MM74HC125, MM74HC126 Rev. 1.3.0 www.fairchildsemi.com MM74HC125, MM74HC126 — 3-STATE Quad Buffers February 2008 Pin Assignments for DIP, SOIC, SOP and TSSOP Top View (MM74HC125) Top View (MM74HC126) Truth Tables Inputs Output Inputs Output A C Y A C Y H L H H H H L L L L H L X H Z X L Z MM74HC125 ©1983 Fairchild Semiconductor Corporation MM74HC125, MM74HC126 Rev. 1.3.0 MM74HC126 www.fairchildsemi.com 2 MM74HC125, MM74HC126 — 3-STATE Quad Buffers Connection Diagrams Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage VIN DC Input Voltage –1.5 to VCC+1.5V DC Output Voltage –0.5 to VCC+0.5V VOUT IIK, IOK –0.5 to +7.0V Clamp Diode Current ±20mA IOUT DC Output Current, per pin ICC DC VCC or GND Current, per pin TSTG PD 35mA ±70mA Storage Temperature Range –65°C to +150°C Power Dissipation Note 2 600mW S.O. Package only TL 500mW Lead Temperature (Soldering 10 seconds) 260°C Notes: 1. Unless otherwise specified all voltages are referenced to ground. 2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN, VOUT TA t r, t f Parameter Min. Max. Units Supply Voltage 2 6 V DC Input or Output Voltage 0 VCC V –40 +85 °C Operating Temperature Range Input Rise or Fall Times VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns ©1983 Fairchild Semiconductor Corporation MM74HC125, MM74HC126 Rev. 1.3.0 www.fairchildsemi.com 3 MM74HC125, MM74HC126 — 3-STATE Quad Buffers Absolute Maximum Ratings(1) TA = 25°C Symbol VIH VIL VOH VOL Parameter Conditions VCC (V) Typ. TA = –40°C TA = –40°C to 85°C to 125°C Guaranteed Limits Minimum HIGH Level Input Voltage 2.0 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 Maximum LOW Level Input Voltage 2.0 0.5 0.5 0.5 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 Minimum HIGH Level Output Voltage Maximum LOW Level Output Voltage VIN = VIH or VIL, |IOUT| ≤ 20µA 2.0 2.0 1.9 1.9 1.9 4.5 4.5 4.4 4.4 4.4 6.0 6.0 5.9 5.9 5.9 VIN = VIH or VIL, |IOUT| ≤ 6.0mA 4.5 4.2 3.98 3.84 3.7 VIN = VIH or VIL, |IOUT| ≤ 7.8mA 6.0 5.7 5.48 5.34 5.2 VIN = VIH or VIL, |IOUT| ≤ 20µA 2.0 0 0.1 0.1 0.1 4.5 0 0.1 0.1 0.1 6.0 0 0.1 0.1 0.1 VIN = VIH or VIL, |IOUT| ≤ 6.0mA 4.5 0.2 0.26 0.33 0.4 VIN = VIH or VIL, |IOUT| ≤ 7.8mA 6.0 0.2 0.26 0.33 0.4 Units V V V V IOZ Maximum 3-STATE Output Leakage Current VIN = VIH or VIL, VOUT = VCC or GND, Cn = Disabled 6.0 ±0.5 ±5 ±10 µA IIN Maximum Input Current VIN = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current VIN = VCC or GND, IOUT = 0µA 6.0 8.0 80 160 µA Note: 3. For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. ©1983 Fairchild Semiconductor Corporation MM74HC125, MM74HC126 Rev. 1.3.0 www.fairchildsemi.com 4 MM74HC125, MM74HC126 — 3-STATE Quad Buffers DC Electrical Characteristics(3) Symbol tPHL, tPLH Parameter Conditions Maximum Propagation Delay Time Typ. Guaranteed Limit Units 13 18 ns tPZH Maximum Output Enable Time to HIGH Level RL = 1kΩ 13 25 ns tPHZ Maximum Output Disable Time from HIGH Level RL = 1kΩ, CL = 5pF 17 25 ns tPZL Maximum Output Enable Time to LOW Level RL = 1kΩ 18 25 ns tPLZ Maximum Output Disable Time from LOW Level RL = 1kΩ, CL = 5pF 13 25 ns AC Electrical Characteristics VCC = 2.0V to 6.0V, CL = 50pF, tr = tf = 6ns (unless otherwise specified) TA = 25°C Symbol Parameter tPHL, tPLH Maximum Propagation Delay Time VCC (V) Conditions Typ. 100 125 150 4.5 14 20 25 30 2.0 tPZH, tPZL Maximum Output Enable Time 2.0 CL = 150pF 4.5 6.0 CIN Maximum Output Rise and Fall Time 12 17 21 25 35 130 163 195 14 26 33 39 12 22 28 39 25 125 156 188 4.5 14 25 31 38 6.0 12 21 26 31 25 125 156 188 4.5 14 25 31 38 6.0 12 21 26 31 35 140 175 210 15 28 35 42 13 24 30 36 2.0 2.0 4.5 RL = 1kΩ RL = 1kΩ CL = 150pF, RL = 1kΩ 6.0 tTLH, tTHL Guaranteed Limits 40 6.0 tPZL, tPZH Maximum Output Enable Time TA = –40°C to 125°C 2.0 tPLH, tPHL Maximum Propagation Delay Time tPHZ, tPLZ Maximum Output Disable Time TA = –40°C to 85°C 2.0V CL = 50pF 30 60 75 90 4.5V 7 12 15 18 6.0V 6 10 13 15 Units ns ns ns ns ns ns Input Capacitance 5 10 10 10 pF COUT Output Capacitance Outputs 15 20 20 20 pF CPD Power Dissipation Capacitance (per gate)(4) Enabled 45 Disabled 6 pF Note: 4. CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. ©1983 Fairchild Semiconductor Corporation MM74HC125, MM74HC126 Rev. 1.3.0 www.fairchildsemi.com 5 MM74HC125, MM74HC126 — 3-STATE Quad Buffers AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 45pF, tr = tf = 6ns 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 (0.33) 1.75 MAX 1.50 1.25 1.27 LAND PATTERN RECOMMENDATION M C B A SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45° 0.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1983 Fairchild Semiconductor Corporation MM74HC125, MM74HC126 Rev. 1.3.0 www.fairchildsemi.com 6 MM74HC125, MM74HC126 — 3-STATE Quad Buffers Physical Dimensions MM74HC125, MM74HC126 — 3-STATE Quad Buffers Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1983 Fairchild Semiconductor Corporation MM74HC125, MM74HC126 Rev. 1.3.0 www.fairchildsemi.com 7 MM74HC125, MM74HC126 — 3-STATE Quad Buffers Physical Dimensions (Continued) 0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1983 Fairchild Semiconductor Corporation MM74HC125, MM74HC126 Rev. 1.3.0 www.fairchildsemi.com 8 19.56 18.80 14 8 6.60 6.09 1 7 (1.74) 8.12 7.62 1.77 1.14 3.56 3.30 0.35 0.20 5.33 MAX 0.38 MIN 3.81 3.17 0.58 0.35 8.82 2.54 NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7 Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1983 Fairchild Semiconductor Corporation MM74HC125, MM74HC126 Rev. 1.3.0 www.fairchildsemi.com 9 MM74HC125, MM74HC126 — 3-STATE Quad Buffers Physical Dimensions (Continued) ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ PDP-SPM™ Power220® POWEREDGE® Power-SPM™ PowerTrench® Programmable Active Droop™ QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® ® Fairchild® Fairchild Semiconductor® FACT Quiet Series™ FACT® FAST® FastvCore™ FlashWriter® * ® SupreMOS™ SyncFET™ ® The Power Franchise® TinyBoost™ TinyBuck™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ µSerDes™ UHC® Ultra FRFET™ UniFET™ VCX™ * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I33 ©1983 Fairchild Semiconductor Corporation MM74HC125, MM74HC126 Rev. 1.3.0 www.fairchildsemi.com 10 MM74HC125, MM74HC126 — 3-STATE Quad Buffers TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.