MM54HC533/MM74HC533 TRI-STATEÉ Octal D-Type Latch with Inverted Outputs General Description These high speed OCTAL D-TYPE LATCHES utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the TRI-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. When the LATCH ENABLE input is high, the data present on the D inputs will appear inverted at the Q outputs. When the LATCH ENABLE goes low, the inverted data will be retained at the Q outputs until LATCH ENABLE returns high again. When a high logic level is applied to the OUTPUT CONTROL input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 54HC/74HC logic family is speed, function, and pin-out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features Y Y Y Y Y Y Typical propagation delay: 18 ns Wide operating voltage range: 2 to 6 volts Low input current: 1 mA maximum Low quiescent current: 80 mA, maximum (74HC Series) Compatible with bus-oriented systems Output drive capability: 15 LS-TTL loads Connection Diagram Dual-In-Line Package TL/F/5339 – 1 Top View Order Number MM54HC533 or MM74HC533 Truth Table Output Control L L L H Latch Enable G H H L X Data H L X X Output L H Q0 Z H e high level, L e low level Q0 e level of output before steady-state input conditions were established. Z e high impedance TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/F/5339 RRD-B30M105/Printed in U. S. A. MM54HC533/MM74HC533 TRI-STATE Octal D-Type Latch with Inverted Outputs January 1988 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) b 0.5 to a 7.0V Supply Voltage (VCC) b 1.5 to VCC a 1.5V DC Input Voltage (VIN) b 0.5 to VCC a 0.5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK, IOK) g 35 mA DC Output Current, per pin (IOUT) g 70 mA DC VCC or GND Current, per pin (ICC) b 65§ C to a 150§ C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§ C Operating Temp. Range (TA) MM74HC MM54HC Min 2 Max 6 0 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise or Fall Times VCC e 2.0V (tr, tf) VCC e 4.5V VCC e 6.0V DC Electrical Characteristics Symbol Parameter Conditions VCC TA e 25§ C Typ 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s6.0 mA lIOUTl s7.8 mA 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V VIN e VIH or VIL lIOUTl s6.0 mA lIOUTl s7.8 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA IIN Maximum Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA IOZ Maximum TRI-STATE Output Leakage Current VIN e VIH or VIL, OC e VIH VOUT e VCC or GND 6.0V g 0.5 g5 g 10 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V 8.0 80 160 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCC e 5V, TA e 25§ C, tr e tf e 6 ns Conditions Typ Guaranteed Limit Units tPHL, tPLH Symbol Maximum Propagation Delay, Data to Q Parameter CL e 45 pF 18 25 ns tPHL, tPLH Maximum Propagation Delay, Enable to Q CL e 45 pF 21 30 ns tPZH, tPZL Maximum Output Enable Time RL e 1 kX CL e 45 pF 20 28 ns tPHZ, tPLZ Maximum Output Disable Time RL e 1 kX CL e 5 pF 18 25 ns tS Minimum Set Up Time 5 ns tH Minimum Hold Time 10 ns tW Minimum Pulse Width 16 ns AC Electrical Characteristics VCC e 2.0V – 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC TA e 25§ C Typ tPHL, tPLH tPHL, tPLH tPZH, tPZL Maximum Propagation Delay, Data to Q Maximum Propagation Delay, Enable to Q Maximum Output Enable Time 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits CL e 50 pF CL e 150 pF 2.0V 2.0V 50 80 150 200 188 250 225 300 ns ns CL e 50 pF CL e 150 pF 4.5V 4.5V 22 30 30 40 37 50 45 60 ns ns CL e 50 pF CL e 150 pF 6.0V 6.0V 19 26 26 35 31 44 39 53 ns ns CL e 50 pF CL e 150 pF 2.0V 2.0V 63 110 175 225 220 280 263 338 ns ns CL e 50 pF CL e 150 pF 4.5V 4.5V 25 35 35 45 44 56 52 68 ns ns CL e 50 pF CL e 150 pF 6.0V 6.0V 21 28 30 39 37 49 45 59 ns ns CL e 50 pF CL e 150 pF 2.0V 2.0V 50 80 150 200 188 250 225 300 ns ns CL e 50 pF CL e 150 pF 4.5V 4.5V 21 30 30 40 37 50 45 60 ns ns CL e 50 pF CL e 150 pF 6.0V 6.0V 19 26 26 35 31 44 39 53 ns ns RL e 1 kX CL e 50 pF 2.0V 4.5V 6.0V 50 21 19 150 30 26 188 37 31 225 45 39 ns ns ns RL e 1 kX tPHZ, tPLZ Maximum Output Disable Time tS Minimum Set Up Time 2.0V 4.5V 6.0V 50 9 9 60 13 11 75 15 13 ns ns ns tH Minimum Hold Time 2.0V 4.5V 6.0V 5 5 5 5 5 5 5 5 5 ns ns ns tW Minimum Pulse Width 2.0V 4.5V 6.0V 30 10 9 80 16 14 100 20 18 120 24 20 ns ns ns tTHL, tTLH Maximum Output Rise and Fall Time, Clock CL e 50 pF 2.0V 4.5V 6.0V 25 7 6 60 12 10 75 15 13 90 18 15 ns ns ns CPD Power Dissipation Capacitance (Note 5) (per latch) OC e VCC OC e Gnd 30 50 pF pF CIN Maximum Input Capacitance 5 10 10 10 pF COUT Maximum Output Capacitance 15 20 20 20 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 MM54HC533/MM74HC533 TRI-STATE Octal D-Type Latch with Inverted Outputs Physical Dimensions inches (millimeters) Order Number MM54HC533J or MM74HC533J NS Package J20A Order Number MM74HC533N NS Package N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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