Revised February 1999 MM74HCT540 • MM74HCT541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer General Description The MM74HCT540 and MM74HCT541 3-STATE buffers utilize advanced silicon-gate CMOS technology and are general purpose high speed inverting and non-inverting buffers. They possess high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the low power consumption of CMOS. Both devices are TTL input compatible and have a fanout of 15 LS-TTL equivalent inputs. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. The MM74HCT540 is an inverting buffer and the MM74HCT541 is a non-inverting buffer. The 3-STATE control gate operates as a two-input NOR such that if either G1 or G2 are HIGH, all eight outputs are in the high-impedance state. In order to enhance PC board layout, the MM74HCT540 and MM74HCT541 offers a pinout having inputs and outputs on opposite sides of the package. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features ■ TTL input compatible ■ Typical propagation delay: 12 ns ■ 3-STATE outputs for connection to system buses ■ Low quiescent current: 80 µA ■ Output current: 6 mA (min.) Ordering Code: Order Number Package Number MM74HCT540WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT540SJ MM74HCT540MTC MTC20 Package Description 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HCT540N N20A MM74HCT541WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide MM74HCT541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT541MTC MM74HCT541N 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP, SOIC, SOP and TSSOP Top View MM74HCT540 © 1999 Fairchild Semiconductor Corporation Top View MM74HCT541 DS006040.prf www.fairchildsemi.com MM74HCT540 • MM74HCT541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer February 1984 MM74HCT540 • MM74HCT541 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±35 mA 600 mW 500 mW V 0 VCC V −40 +85 °C 500 ns (tr, tf) Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. Lead Temperature (TL) (Soldering 10 seconds) Units 5.5 Input Rise or Fall Times Power Dissipation (PD) S.O. Package only Max 4.5 (VIN, VOUT) Operating Temperature Range (TA) −65°C to +150°C (Note 3) Min DC Input or Output Voltage ±70 mA DC VCC or GND Current, per pin (ICC ) Storage Temperature Range (TSTG) Supply Voltage (VCC) 260°C DC Electrical Characteristics VCC = 5V ± 10% (unless otherwise specified) Symbol VIH Parameter TA = 25°C Conditions Typ Minimum HIGH Level TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units 2.0 2.0 2.0 V 0.8 0.8 0.8 V Input Voltage VIL Maximum LOW Level Input Voltage VOH VOL IIN Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| = 20 µA VCC VCC− 0.1 VCC− 0.1 VCC− 0.1 V |IOUT| = 6.0 mA, VCC = 4.5V 4.2 3.98 3.84 3.7 V |IOUT| = 7.2 mA, VCC = 5.5V 5.2 4.98 4.84 4.7 V Maximum LOW Level VIN = VIH or VIL Voltage |IOUT| = 20 µA 0 0.1 0.1 0.1 V |IOUT| = 6.0 mA, VCC = 4.5V 0.2 0.26 0.33 0.4 V |IOUT| = 7.2 mA, VCC = 5.5V 0.2 0.26 0.33 0.4 V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum 3-STATE VOUT = VCC or GND ±0.5 ±5.0 ±10 µA Output Leakage G = VIH 8.0 80 160 µA 1.0 1.3 1.5 mA Maximum Input Current IOZ Current ICC Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0 µA VIN = 2.4V or 0.5V (Note 4) 0.6 Note 4: Measured per input. All other inputs at VCC or GND. www.fairchildsemi.com 2 MM74HCT540: VCC = 5.0V, tr = tf = 6 ns, TA = 25°C, (unless otherwise specified) Symbol tPHL, tPLH Parameter Conditions Typ Guaranteed Limits Units CL = 45 pF 12 18 ns Maximum Output CL = 45 pF 14 28 ns Enable Time RL = 1 kΩ Maximum Output CL = 5 pF 13 25 ns Disable Time RL = 1 kΩ Maximum Output Propagation Delay tPZL, tPZH tPLZ, tPHZ AC Electrical Characteristics MM74HCT540: VCC = 5.0V ± 10%, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter tPHL, tPLH Maximum Output Propagation Delay tPZH, tPZL Maximum Output Disable Time tTHL, tTLH Maximum Output Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units CL = 50 pF 12 20 25 30 ns CL = 150 pF 22 30 38 45 ns CL = 50 pF 15 30 38 45 ns CL = 150 pF 20 40 50 60 ns 15 30 38 45 ns 6 12 15 18 ns 5 10 10 10 pF 15 20 20 20 pF RL = 1 kΩ Enable Time tPHZ, tPLZ Maximum Output TA = 25°C Conditions RL = 1 kΩ CL = 50 pF CL = 50 pF Rise and Fall Time CIN Maximum Input Capacitance COUT Maximum Output Capacitance CPD Power Dissipation Capacitance (Note 5) (per output) G = VCC 12 pF G = GND 50 pF Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC,and the no load dynamic current consumption, IS = CPD VCC f + ICC. 3 www.fairchildsemi.com MM74HCT540 • MM74HCT541 AC Electrical Characteristics MM74HCT540 • MM74HCT541 AC Electrical Characteristics MM74HCT541: VCC = 5.0V, tr = tf = 6 ns, TA = 25°C, (unless otherwise specified) Symbol tPHL, tPLH Parameter Conditions Typ Guaranteed Limits Units CL = 45 pF 13 20 ns Maximum Output CL = 45 pF 17 28 ns Enable Time RL = 1 kΩ 15 25 ns Maximum Output Propagation Delay tPZL, tPZH tPLZ, tPHZ Maximum Output CL = 5 pF Disable Time RL = 1 kΩ AC Electrical Characteristics MM74HCT541: VCC = 5.0V ± 10%, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter TA = 25°C Conditions Typ tPHL, tPLH Maximum Output Propagation Delay tPZH, tPZL Maximum Output Disable Time tTHL, tTLH Maximum Output Units Guaranteed Limits CL = 50 pF 14 23 29 34 ns CL = 150 pF 17 33 42 49 ns CL = 50 pF 17 30 38 45 ns CL = 150 pF 22 40 50 60 ns 17 30 38 45 ns 6 12 15 18 ns 5 10 10 10 pF 15 20 20 20 pF RL = 1 kΩ Enable Time tPHZ, tPLZ Maximum Output TA = −40 to 85°C TA = −55 to 125°C RL = 1 kΩ CL = 50 pF CL= 5 0 pF Rise and Fall Time CIN Maximum Input Capacitance COUT Maximum Output Capacitance CPD Power Dissipation Capacitance (Note 6) (per output) G = VCC 12 pF G = GND 45 pF Note 6: CPD determines the no load dynamic power consumption, PD = C PD VCC2 f + ICC VCC,and the no load dynamic current consumption, IS = CPD V CC f + ICC. www.fairchildsemi.com 4 MM74HCT540 • MM74HCT541 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com MM74HCT540 • MM74HCT541 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74HCT540 • MM74HCT541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer Physical Dimensions inches (millimeters) unless otherwise noted (Continued)