Freescale MPC5607BEMLUR Microcontroller Datasheet

Freescale Semiconductor
Data Sheet: Advance Information
MPC5607B
MPC5607B Microcontroller
Data Sheet
Features
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Single issue, 32-bit CPU core complex (e200z0h)
— Compliant with the Power Architecture™
embedded category
— Enhanced instruction set allowing variable
length encoding (VLE) for code size footprint
reduction. With the optional encoding of mixed
16-bit and 32-bit instructions, it is possible to
achieve significant code size footprint
reduction.
Up to 1.5 Mbytes on-chip Flash supported with the
Flash controller
Up to 96 Kbytes on-chip SRAM
Memory protection unit (MPU) with 8 region
descriptors and 32-byte region granularity on certain
family members
Interrupt controller (INTC) capable of handling 204
selectable-priority interrupt sources
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to
peripherals, Flash, or RAM from multiple bus
masters
16-channel eDMA controller with multiple transfer
request sources using DMA multiplexer
Boot assist module (BAM) supports internal Flash
programming via a serial link (CAN or SCI)
Timer supports I/O channels providing a range of
16-bit input capture, output compare, and pulse
width modulation functions (eMIOS)
2 analog-to-digital converters (ADC): one 10-bit and
one 12-bit
Cross Trigger Unit to enable synchronization of
ADC conversions with a timer event from the
eMIOS or PIT
176LQFP (24 x 24)
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144 LQFP (20 x 20 )
Up to 6 serial peripheral interface (DSPI) modules
Up to 10 serial communication interface (LINFlex)
modules
Up to 6 enhanced full CAN (FlexCAN) modules
with configurable buffers
1 inter-integrated circuit (I2C) interface module
Up to 149 configurable general purpose pins
supporting input and output operations (package
dependent)
Real-Time Counter (RTC)
— Clock source from internal 128 kHz or 16 MHz
oscillator supporting autonomous wakeup with
1 ms resolution with maximum timeout of 2
seconds
— Optional support for RTC with clock source
from external 32 kHz crystal oscillator,
supporting wakeup with 1 sec resolution and
maximum timeout of 1 hour
Up to 8 periodic interrupt timers (PIT) with 32-bit
counter resolution
Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class Two Plus
Device/board boundary scan testing supported per
Joint Test Action Group (JTAG) of IEEE (IEEE
1149.1)
On-chip voltage regulator (VREG) for regulation of
input supply for all internal levels
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2010. All rights reserved.
Preliminary—Subject to Change Without Notice
208 MAPBGA (17 x 17 ) 100 LQFP (14 x 14 )
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Document Number: MPC5607B
Rev. 3, 01/2010
1
2
3
General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1 176LQFP pin configuration . . . . . . . . . . . . . . . . . . . . . . .8
2.2 144LQFP pin configuration . . . . . . . . . . . . . . . . . . . . . . .9
2.3 208MAPBGA pin configuration . . . . . . . . . . . . . . . . . . .10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2.1 NVUSRO[PAD3V5V] field description . . . . . . . .11
3.2.2 NVUSRO[OSCILLATOR_MARGIN] field
description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2.3 NVUSRO[WATCHDOG_EN] field description . .12
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .13
3.4 Recommended operating conditions . . . . . . . . . . . . . .14
3.5 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .17
3.5.1 External ballast resistor recommendations . . . .17
3.5.2 Package thermal characteristics . . . . . . . . . . . .17
3.5.3 Power considerations. . . . . . . . . . . . . . . . . . . . .18
3.6 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .18
3.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6.2 I/O input DC characteristics . . . . . . . . . . . . . . . .19
3.6.3 I/O output DC characteristics. . . . . . . . . . . . . . .21
3.6.4 Output pin transition times . . . . . . . . . . . . . . . . .23
3.6.5 I/O pad current specification . . . . . . . . . . . . . . .24
3.7 nRSTIN electrical characteristics . . . . . . . . . . . . . . . . .27
3.8 Power management electrical characteristics. . . . . . . .30
3.8.1 Voltage regulator electrical characteristics . . . .30
3.8.2 Voltage monitor electrical characteristics. . . . . .33
3.9 Low voltage domain power consumption . . . . . . . . . . .35
3.10 Flash memory electrical characteristics . . . . . . . . . . . .37
3.10.1 Program/Erase characteristics. . . . . . . . . . . . . .37
3.10.2 Flash power supply DC characteristics . . . . . . .38
4
5
6
3.10.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 40
3.11 Electromagnetic compatibility (EMC) characteristics. . 40
3.11.1 Designing hardened software to avoid
noise problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11.2 Electromagnetic interference (EMI) . . . . . . . . . 41
3.11.3 Absolute maximum ratings (electrical sensitivity)41
3.12 Fast external crystal oscillator (4 to 16 MHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.13 Slow external crystal oscillator (32 kHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 48
3.15 Fast internal RC oscillator (16 MHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.16 Slow internal RC oscillator (128 kHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 50
3.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.17.2 Input impedance and ADC accuracy . . . . . . . . 51
3.17.3 ADC electrical characteristics . . . . . . . . . . . . . 56
3.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 64
3.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 66
3.18.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . 73
3.18.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 74
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 75
4.1.1 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.1.2 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.1.3 100 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.1.4 208MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
MPC5607B Microcontroller Data Sheet, Rev. 3
2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Table of Contents
General description
General description
The MPC5607B is a new family of next generation microcontrollers built on the Power Architecture™ embedded category.
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the device.
The MPC5607B family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It
belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics
applications within the vehicle. The advanced and cost-efficient host processor core of the MPC5607B automotive controller
family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding)
APU (Auxillary Processor Unit), providing improved code density. It operates at speeds of up to 64 MHz and offers high
performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of
current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist
with users implementations.
Table 1. MPC5607B Family Comparison1
MPC5605B
Feature
Package
100
LQFP
144
LQFP
MPC5606B
176
LQFP
CPU
144
LQFP
176
LQFP
MPC5607B
176
LQFP
208 MAP
BGA2
e200z0h
Execution speed
3
Up to 64 MHz
Code Flash
768 KB
1 MB
Data Flash
1.5 MB
64 (4 x 16) Kbyte
RAM
64 KB
80 KB
MPU
8-entry
DMA
16 ch
10-bit ADC
96 KB
Yes
4
dedicated
7 ch
15 ch
29 ch
shared with 12-bit ADC
15 ch
29 ch
19 ch
12-bit ADC
Yes
5
5 ch
dedicated
shared with 10-bit ADC
6
19 ch
37 ch,
16-bit
Total timer I/O
eMIOS
64 ch,
16-bit
Counter / OPWM / ICOC7
10 ch
O(I)PWM / OPWFMB /
OPWMCB / ICOC8
7 ch
O(I)PWM / ICOC9
10
OPWM / ICOC
7 ch
14 ch
13 ch
33 ch
SCI (LINFlex)
4
6
8
6
SPI (DSPI)
3
5
6
5
CAN (FlexCAN)
8
10
6
6
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
3
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
1
General description
Table 1. MPC5607B Family Comparison1 (continued)
MPC5606B
I2C
MPC5607B
1
32 kHz oscillator
GPIO11
Yes
77
121
Debug
149
121
JTAG
149
149
N2+
1
Feature set dependent on selected peripheral multiplexing; table shows example.
208 MAPBGA package is for debug use only.
3
Based on 105 °C ambient operating temperature.
4
Not shared with 12-bit ADC, but possibly shared with other alternate functions.
5
Not shared with 10-bit ADC, but possibly shared with other alternate functions.
6 Refer to eMIOS section of device reference manual for information on the channel configuration and functions.
7 Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output
Compare.
8 Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output
Compare.
9 Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and
Pulse width measurement.
10 Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare.
11 Maximum I/O count based on multiplexing with peripherals.
2
1.1
Block diagram
Figure 1 shows a top-level block diagram of the MPC5607B.
MPC5607B Microcontroller Data Sheet, Rev. 3
4
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
MPC5605B
Feature
General description
JTAG
eDMA
RAM
96 KB
Code Flash DataFlash
1.5 MB
64 KB
SRAM
Controller
Flash
Controller
Nexus
(Master)
Data
NMI
Nexus 2+
(Master)
SIUL
Voltage
Regulator
Interrupt requests
from peripheral
blocks
NMI
INTC
Clocks
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
e200z0h
MPU
Instructions
Nexus Port
64-bit 2 x 3 Crossbar Switch
(Master)
JTAG Port
(Slave)
(Slave)
(Slave)
MPU
Registers
WKPU
CMU
FMPLL
RTC
STM
SWT
ECSM
MC_RGM MC_CGM MC_ME MC_PCU
PIT
BAM
SSCM
Peripheral Bridge
Interrupt
Request
SIUL
Reset Control
19 ch 10bit/12bit 29 ch 10-bit
ADC
ADC
64 ch
eMIOS
CTU
10 x
LINFlex
6x
DSPI
I2C
6x
FlexCAN
External
Interrupt
Request
IMUX
GPIO &
Pad Control
I/O
...
...
...
...
...
Legend:
ADC
BAM
CAN
CMU
CTU
DSPI
eMIOS
FMPLL
I2C
IMUX
INTC
JTAG
LINFlex
MC_CGM
Analog-to-Digital Converter
Boot Assist Module
Controller Area Network (FlexCAN)
Clock Monitor Unit
Cross Triggering Unit
Deserial Serial Peripheral Interface
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
JTAG controller
Serial Communication Interface (LIN support)
Clock Generation Module
MC_ME
MPU
Nexus
NMI
MC_PCU
MC_RGM
PIT
RTC
SIUL
SRAM
SSCM
STM
SWT
Mode Entry Module
Memory Protection Unit
NexuS Development Interface (NDI) Level
Non-Maskable Interrupt
Power Control Unit
Reset Generation Module
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Figure 1. MPC5607B block diagram
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
5
Preliminary—Subject to Change Without Notice
General description
Table 2 summarizes the functions of the blocks present on the MPC5607B.
Table 2. MPC5607B series block summary
Function
Analog-to-digital converter (ADC) Converts analog voltages to digital values
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Crossbar switch (XBAR)
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices
(DSPI)
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol
Frequency-modulated
phase-locked loop (FMPLL)
Generates high-speed system clocks and supports programmable frequency
modulation
Internal multiplexer (IMUX) SIU
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of
data exchange between devices
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Memory protection unit (MPU)
Provides hardware access control for all memory references generated in a
device
Periodic interrupt timer (PIT)
Produces periodic interrupts and triggers
Real-time counter (RTC)
A free running counter used for time keeping applications, the RTC can be
configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode)
MPC5607B Microcontroller Data Sheet, Rev. 3
6
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Block
Package pinouts
Table 2. MPC5607B series block summary (continued)
Function
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the device
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System timer module (STM)
2
Provides a set of output compare events to support AutoSAR and operating
system tasks
Package pinouts
The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions,
please refer to the device reference manual.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
7
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Block
Package pinouts
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176 LQFP
Top view
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PA[11]/GPIO[11]/E0UC[11]/SCL/EIRQ[16]/LIN2RX/ADC1_S[3]
PA[10]/GPIO[10]/E0UC[10]/SDA/LIN2TX/ADC1_S[2]
PA[9]/GPIO[9]/E0UC[9]/CS2_1/FAB
PA[8]/GPIO[8]/E0UC[8]/E0UC[14]/EIRQ[3]/ABS[0]/LIN3RX
PA[7]/GPIO[7]/E0UC[7]/LIN3TX/EIRQ[2]/ADC1_S[1]
PE[13]/GPIO[77]/SOUT_2/E1UC[20]
PF[14]/GPIO[94]/CAN4TX/E1UC[27]/CAN1TX
PF[15]/GPIO[95]/E1UC[4]/EIRQ[13]/CAN4RX/CAN1RX
VDD_HV
VSS_HV
PG[0]/GPIO[96]/CAN5TX/E1UC[23]
PG[1]/GPIO[97]/E1UC[24]/EIRQ[14]/CAN5RX
PH[3]/GPIO[115]/E1UC[5]/CS0_1
PH[2]/GPIO[114]/E1UC[4]/SCK_1
PH[1]/GPIO[113]/E1UC[3]/SOUT_1
PH[0]/GPIO[112]/E1UC[2]/SIN_1
PG[12]/GPIO[108]/E0UC[26]/SOUT_4
PG[13]/GPIO[109]/E0UC[27]/SCK_4
PA[3]/GPIO[3]/E0UC[3]/LIN5TX/CS4_1/EIRQ[0]/ADC1_S[0]
PI[13]/GPIO[141]/CS1_3/ADC0_S[21]
PI[12]/GPIO[140]/CS0_3/ADC0_S20]
PI[11]/GPIO[139]/ANS[19]/SIN_3
PI[10]/GPIO[138]/ADC0_S[18]
PI[9]/GPIO[137]/ADC0_S[17]
PI[8]/GPIO[136]/ADC0_S[16]
PB[15]/GPIO[31]/E0UC[7]/CS4_0/ADC0_X[3]
PD[15]/GPIO[63]/CS2_1/E0UC[27]/ADC0_S[7]
PB[14]/GPIO[30]/E0UC[6]/CS3_ 0/ADC0_X[2]
PD[14]/GPIO[62]/CS1_1/E0UC[26]/ADC0_S[6]
PB[13]/GPIO[29]/E0UC[5]/CS2_0/ADC0_X[1]
PD[13]/GPIO[61]/CS0_1/E0UC[25]/ADC0_S[5]
PB[12]/GPIO[28]/E0UC[4]/CS1_0/ADC0_X[0]
PD[12]/GPIO[60]/CS5_0/E0UC[24]/ADC0_S[4]
VDD_HV_ADC1
VSS_HV_ADC1
PB[11]/GPIO[27]/E0UC[3]/CS0_0/ADC0_S[3]
PD[11]/GPIO[59]/ADC0_P[15]/ADC1_P[15]
PD[10]/GPIO[58]/ADC0_P[14]/ADC1_P[14]
PD[9]/GPIO[57]/ADC0_P[13]/ADC1_P[13]
PB[7]/GPIO[23]/ADC0_P[3]/ADC1_P[3]
PB[6]/GPIO[22]/ADC0_P[2]/ADC1_P[2]
PB[5]/GPIO[21]/ADC0_P[1]/ADC1_P[1]
VDD_HV_ADC0
VSS_HV_ADC0
ADC0_S[6]/WKUP[8]/ANS[2]/GPIO[26]/PB[10]
ADC0_S[8]/CS3_1/E0UC[10]/GPIO[80]/PF[0]
ADC0_S[9]/CS4_1/E0UC[11]/GPIO[81]/PF[1]
ADC0_S[10]/CS0_2/E0UC[12]/GPIO[82]/PF[2]
ADC0_S[11]/CS1_2/E0UC[13]/GPIO[83]/PF[3]
ADC0_S[12]/CS2_2/E0UC[14]/GPIO[84]/PF[4]
ADC0_S[13]/CS3_2/E0UC[22]/GPIO[85]/PF[5]
ADC0_S14]/CS1_1/E0UC[23]/GPIO[86]/PF[6]
ADC0_S[15]/CS2_1/GPIO[87]/PF[7]
ADC0_S[27]/CS1_5/GPIO[147]/PJ[3]
ADC0_S[26]/CS0_5/GPIO[146]/PJ[2]
SIN_5/ANS[25]/GPIO[145]/PJ[1]
ADC0_S[24]/CS1_4/GPIO[144]/PJ[0]
ADC0_S[23]/CS0_4/GPIO[143]/PI[15]
SIN_4/ANS[22]/GPIO[142]/PI[14]
ANP[4]/WKUP[27]/GPIO[48]/PD[0]
ADC1_P[5]/ADC0_P[5]/WKUP[28]/GPIO[49]/PD[1]
ADC1_P[6]/ADC0_P[6]/GPIO[50]/PD[2]
ADC1_P[8]/ADC0_P[7]/GPIO[51]/PD[3]
ADC1_P[8]/ADC0_P[8]/GPIO[52]/PD[4]
ADC1_P[9]/ADC0_P[9]/GPIO[53]/PD[5]
ADC0_P[10]/ADC0_P[10]/GPIO[54]/PD[6]
ADC1_P[11]/ADC0_P[11]/GPIO[55]/PD[7]
VDD_HV
VSS_HV
ADC1_P[12]/ADC0_P[12]/GPIO[56]/PD[8]
ADC1_P[0]/ADC0_P[0]/GPIO[20]/PB[4]
ADC1_S[5]/OSC32K_EXTAL/WKUP[26]/ADC0_S[1]/GPIO[25]/PB[9]
ADC1_S[4]/OSC32K_XTAL/WKUP[25]/ADC_S[0]/GPIO[24]/PB[8]
LIN1RX/WKUP[12]/E1UC[29]/GPIO[39]/PC[7]
E1UC[2]/LIN4TX/CS1_0/GPIO[90]/PF[10]
LIN4RX/WKUP[15]/E1UC[3]/CS2_0/GPIO[91]/PF[11]
WKUP[10]/E0UC[1]/SCK_0/CS0_0/GPIO[15]/PA[15]
LIN5RX/WKUP[16]/E1UC[26]/GPIO[93]/PF[13]
EIRQ[4]/E0UC[0]/CS0_0/SCK_0/GPIO[14]/PA[14]
LIN5RX/WKUP[9]/CS0_1/E0UC[4]/GPIO[4]/PA[4]
E0UC[29]/SOUT_0/GPIO[13]/PA[13]
EIRQ[17]/SIN_0/CS3_1/E0UC[28]/GPIO[12]/PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
LIN0RX/WKUP[11]/SCL/E0UC[31]/GPIO[19]/PB[3]
LIN2RX/WKUP[13]/E0UC[7]/GPIO[41]/PC[9]
EIRQ[8]/SCK2/E0UC[14]/GPIO[46]/PC[14]
EIRQ[20]/CS0_2/E0UC[15]/GPIO[47]/PC[15]
E1UC[18]/SCK_5/GPIO[148]/PJ[4]
VDD_HV
VSS_HV
E1UC[17]/SOUT_5/GPIO[127]/PH[15]
E1UC[26]/CS0_3/SOUT_4/GPIO[125]/PH[13]
E1UC[27]/CS1_3/SCK_4/GPIO[126]/PH[14]
CS0_4/E1UC[30]/GPIO[134]/PI[6]
CS1_4/E1UC[31]/GPIO[135]/PI[7]
SIN_3/WKUP[18]/E1UC[14]/GPIO[101]/PG[5]
SCK_3/E1UC[13]/GPIO[100]/PG[4]
WKUP[17]/CS0_3/E1UC[12]/GPIO[99]/PG[3]
SOUT_3/E1UC[11]/GPIO[98]/PG[2]
MA[2]/WKUP[3]/E0UC[2]/GPIO[2]/PA[2]
CAN5RX/WKUP[6]/E0UC[16]/GPIO[64]/PE[0]
WKUP[2]/NMI/E0UC[1]/GPIO[1]/PA[1]
CAN5TX/E0UC[17]/GPIO[65]/PE[1]
CAN3TX/E0UC[22]/CAN2TX/GPIO[72]/PE[8]
CAN3RX/CAN2RX/WKUP[7]/E0UC[23]/GPIO[73]/PE[9]
EIRQ[10]/E1UC[30]/CS3_1/LIN3TX/GPIO[74]/PE[10]
WKUP[19]/E0UC[13]/CLKOUT/E0UC[0]/GPIO[0]/PA[0]
LIN3RX/WKUP[14]/CS4_1/E0UC[24]/GPIO[75]/PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
LIN7RX/WKUP[21]/SCK_2/E1UC[18]/GPIO[105]/PG[9]
EIRQ[15]/CS0_2/LIN7TX/E1UC[17]/GPIO[104]/PG[8]
CAN4RX/CAN1RX/WKUP[5]/MA[2]/GPIO[43]/PC[11]
MA[1]/CAN4TX/CAN1TX/GPIO[42]/PC[10]
LIN6RX/WKUP[20]/E1UC[30]/E1UC[16]/GPIO[103]/PG[7]
LIN6TX/E1UC[15]/GPIO[102]/PG[6]
LIN0TX/E0UC[30]/CAN0TX/GPIO[16]/PB[0]
CAN0RX/WKUP[4]/LIN0RX/E0UC[31]/GPIO[17]/PB[1]
CAN2RX/CAN3RX/WKUP[22]/CS5_0/E1UC[1]/GPIO[89]/PF[9]
CAN2TX/CS4_0/CAN3TX/GPIO[88]/PF[8]
LIN5TX/E1UC[25]/GPIO[92]/PF[12]
E1UC[28]/LIN1TX/GPIO[38]/PC[6]
Note:
Availability of port pin alternate functions depends on product selection.
Figure 2. 176 LQFP pin configuration (top view)
MPC5607B Microcontroller Data Sheet, Rev. 3
8
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
176LQFP pin configuration
PB[2]/GPIO[18]/LIN0TX/SDA/E0UC[30]
PC[8]/GPIO[40]/LIN2TX/E0UC[3]
PC[13]/GPIO[45]/E0UC[13]/SOUT_2
PC[12]/GPIO[44]/E0UC[12]/EIRQ[19]/SIN_2
PI[0]/GPIO[128]/E0UC[28]/LIN8TX
PI[1]/GPIO[129]/E0UC[29]/WKUP[24]/LIN8RX
PI[2]/GPIO[130]/E0UC[30]/LIN9TX
PI[3]/GPIO[131]/E0UC[31]/WKUP[23]/LIN9RX
PE[7]/GPIO[71]/E0UC[23]/CS2_0/MA[0]/EIRQ[23]
PE[6]/GPIO[70]/E0UC[22]/CS3_0/MA[1]/EIRQ[22]
PH[8]/GPIO[120]/E1UC[10]/CS2_2/MA[0]
PH[7]/GPIO[119]/E1UC[9]/CS3_2/MA[1]
PH[6]/GPIO[118]/E1UC[8]/MA[2]
PH[5]/GPIO[117]/E1UC[7]
PH[4]/GPIO[116]/E1UC[6]
PE[5]/GPIO[69]/E0UC[21]/CS0_1/MA[2]
PE[4]/GPIO[68]/E0UC[20]/SCK_1/EIRQ[9]
PC[4]/GPIO[36]/E1UC[31]/EIRQ[18]/SIN_1/CAN3RX
PC[5]/GPIO[37]/SOUT_1/CAN3TX/EIRQ[7]
PE[3]/GPIO[67]/E0UC[19]/SOUT_1
PE[2]/GPIO[66]/E0UC[18]/EIRQ[21]/SIN_1
PH[9]/GPIO[121]/TCK
PC[0]/GPIO[32]/TDI
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]/GPIO[33]/TDO
PH[10]/GPIO[122]/TMS
PA[6]/GPIO[6]/E0UC[6]/CS1_1/EIRQ[1]/LIN4RX
PA[5]/GPIO[5]/E0UC[5]/LIN4TX
PC[2]/GPIO[34]/SCK_1/CAN4TX/EIRQ[5]
PC[3]/GPIO[35]/CS0_1/MA[0]/EIRQ[6]/CAN4RX/CAN1RX
PI[4]/GPIO[132]/E1UC[28]/SOUT_4
PI[5]/GPIO[133]/E1UC[29]/SCK_4
PH[12]/GPIO[124]/SCK_3/CS1_4/E1UC[25]
PH[11]/GPIO[123]/SOUT_3/CS0_4/E1UC[5]
PG[11]/GPIO[107]/E0UC[25]/CS0_4
PG[10]/GPIO[106]/E0UC[24]/E1UC[31]/SIN_4
PE[15]/GPIO[79]/CS0_2/E1UC[22]
PE[14]/GPIO[78]/SCK_2/E1UC[21]/EIRQ[12]
PG[15]/GPIO[111]/E1UC[1]/LIN8RX
PG[14]/GPIO[110]/E1UC[0]/LIN8TX
PE[12]/GPIO[76]/E1UC[19]/EIRQ[11]/SIN_2/ADC1_S[7]
2.1
LIN0RX/WKUP[11]/SCL/E0UC[31]/GPIO[19]/PB[3]
LIN2RX/WKUP[13]/E0UC[7]/GPIO[41]/PC[9]
EIRQ[8]/SCK2/E0UC[14]/GPIO[46]/PC[14]
EIRQ[20]/CS0_2/E0UC[15]/GPIO[47]/PC[15]
SIN_3/WKUP[18]/E1UC[14]/GPIO[101]/PG[5]
SCK_3/E1UC[13]/GPIO[100]/PG[4]
WKUP[17]/CS0_3/E1UC[12]/GPIO[99]/PG[3]
SOUT_3/E1UC[11]/GPIO[98]/PG[2]
MA[2]/WKUP[3]/E0UC[2]/GPIO[2]/PA[2]
CAN5RX/WKUP[6]/E0UC[16]/GPIO[64]/PE[0]
WKUP[2]/NMI[0]/E0UC[1]/GPIO[1]/PA[1]
CAN5TX/E0UC[17]/GPIO[65]/PE[1]
CAN3TX/E0UC[22]/CAN2TX/GPIO[72]/PE[8]
CAN3RX/CAN2RX/WKUP[7]/E0UC[23]/GPIO[73]/PE[9]
EIRQ[10]/E1UC[30]/CS3_1/LIN3TX/GPIO[74]/PE[10]
WKUP[19]/E0UC[13]/CLKOUT/E0UC[0]/GPIO[0]/PA[0]
LIN3RX/WKUP[14]/CS4_1/E0UC[24]/GPIO[75]/PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
LIN7RX/EIRQ[21]/SCK_2/E1UC[18]/GPIO[105]/PG[9]
EIRQ[15]/CS0_2/LIN7TX/E1UC[17]/GPIO[104]/PG[8]
CAN4RX/CAN1RX/WKUP[5]/MA[2]/GPIO[43]/PC[11]
MA[1]/CAN4TX/CAN1TX/GPIO[42]/PC[10]
LIN6RX/WKUP[20]/E1UC[30]/E1UC[16]/GPIO[103]/PG[7]
LIN6TX/E1UC[15]/GPIO[102]/PG[6]
E0UC[30]/CAN0TX/GPIO[16]/PB[0]
LIN0RX/CAN0RX/WKUP[4]/E0UC[31]/GPIO[17]/PB[1]
CAN2RX/CAN3RX/WKUP[22]/CS5_0/E1UC[1]/GPIO[89]/PF[9]
CAN2TX/CS4_0/CAN3TX/GPIO[88]/PF[8]
LIN5TX/E1UC[25]/GPIO[92]/PF[12]
E1UC[28]/LIN1TX/GPIO[38]/PC[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144 LQFP
Top view
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
PA[11]/GPIO[11]/E0UC[11]/SCL/EIRQ[16]/LIN2RX/ADC1_S[3]
PA[10]/GPIO[10]/E0UC[10]/SDA/LIN2TX/ADC1_S[2]
PA[9]/GPIO[9]/E0UC[9]/FAB/CS2_1
PA[8]/GPIO[8]/E0UC[8]/E0UC[14]/EIRQ[3]/ABS[0]/LIN3RX
PA[7]/GPIO[7]/E0UC[7]/LIN3TX/EIRQ[2]/ADC1_S[1]
PE[13]/GPIO[77]/SOUT_2/E1UC[20]
PF[14]/GPIO[94]/CAN4TX/E1UC[27]/CAN1TX
PF[15]/GPIO[95]/E1UC[4]/EIRQ[13]/CAN4RX/CAN1RX
VDD_HV
VSS_HV
PG[0]/GPIO[96]/CAN5TX/E1UC[23]
PG[1]/GPIO[97]/E1UC[24]/EIRQ[14]/CAN5RX
PH[3]/GPIO[115]/E1UC[5]/CS0_1
PH[2]/GPIO[114]/E1UC[4]/SCK_1
PH[1]/GPIO[113]/E1UC[3]/SOUT_1
PH[0]/GPIO[112]/E1UC[2]/SIN_1
PG[12]/GPIO[108]/E0UC[26]/SOUT_4
PG[13]/GPIO[109]/E0UC[27]/SCK_4
PA[3]/GPIO[3]/E0UC[3]/LIN5TX/EIRQ[0]/CS4_1/ADC1_S[0]
PB[15]/GPIO[31]/E0UC[7]/CS4_0/ADC0_X[3]
PD[15]/GPIO[63]/CS2_1/E0UC[27]/ADC0_S[7]
PB[14]/GPIO[30]/E0UC[6]/CS3_ 0/ADC0_X[2]
PD[14]/GPIO[62]/CS1_1/E0UC[26]/ADC0_S[6]
PB[13]/GPIO[29]/E0UC[5]/CS2_0/ADC0_X[1]
PD[13]/GPIO[61]/CS0_1/E0UC[25]/ADC0_S[5]
/GPIO[28]/E0UC[4]/CS1_0
VDD_HV_ADC1
VSS_HV_ADC1
PD[11]/GPIO[59]/ADC0_P[15]/ADC1_P[15]
PD[10]/GPIO[58]/ADC0_P[14]/ADC1_P[14]
PD[9]/GPIO[57]/ADC0_P[13]/ADC1_P[13]
PB[7]/GPIO[23]/ADC0_P[3]/ADC1_P[3]
PB[6]/GPIO[22]/ADC0_P[2]/ADC1_P[2]
PB[5]/GPIO[21]/ADC0_P[1]/ADC1_P[1]
VDD_HV_ADC0
VSS_HV_ADC0
Note:
Availability of port pin alternate functions depends on product selection.
Figure 3. 144 LQFP pin configuration (top view)
MPC5607B Microcontroller Data Sheet, Rev. 3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PB[2]/GPIO[18]/LIN0TX/SDA/E0UC[30]
PC[8]/GPIO[40]/LIN2TX/E0UC[3]
PC[13]/GPIO[45]/E0UC[13]/SOUT_2
PC[12]/GPIO[44]/E0UC[12]/EIRQ[19]/SIN_2
PE[7]/GPIO[71]/E0UC[23]/CS2_0/MA[0]/EIRQ[23]
PE[6]/GPIO[70]/E0UC[22]/CS3_0/MA[1]/EIRQ[22]
PH[8]/GPIO[120]/E1UC[10]/CS2_2/MA[0]
PH[7]/GPIO[119]/E1UC[9]/CS3_2/MA[1]
PH[6]/GPIO[118]/E1UC[8]/MA[2]
PH[5]/GPIO[117]/E1UC[7]
PH[4]/GPIO[116]/E1UC[6]
PE[5]/GPIO[69]/E0UC[21]/CS0_1/MA[2]
PE[4]/GPIO[68]/E0UC[20]/SCK_1/EIRQ[9]
PC[4]/GPIO[36]/E1UC[31]/EIRQ[18]/SIN_1/CAN3RX
PC[5]/GPIO[37]/SOUT_1/CAN3TX/EIRQ[7]
PE[3]/GPIO[67]/E0UC[19]/SOUT_1
PE[2]/GPIO[66]/E0UC[18]/EIRQ[21]/SIN_1
PH[9]/GPIO[121]/TCK
PC[0]/GPIO[32]/TDI
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]/GPIO[33]/TDO
PH[10]/GPIO[122]/TMS
PA[6]/GPIO[6]/E0UC[6]/EIRQ[1]/LIN4RX/CS1_1
PA[5]/GPIO[5]/E0UC[5]/LIN4TX
PC[2]/GPIO[34]/SCK_1/CAN4TX/EIRQ[5]
PC[3]/GPIO[35]/CS0_1/MA[0]/EIRQ[6]/CAN4RX/CAN1RX
PG[11]/GPIO[107]/E0UC[25]/CS0_4
PG[10]/GPIO[106]/E0UC[24]/E1UC[31]/SIN_4
PE[15]/GPIO[79]/CS0_2/E1UC[22]
PE[14]/GPIO[78]/SCK_2/E1UC[21]/EIRQ[12]
PG[15]/GPIO[111]/E1UC[1]/LIN8RX
PG[14]/GPIO[110]/E1UC[0]/LIN8TX
PE[12]/GPIO[76]/E1UC[19]/EIRQ[11]/SIN_2\ANS[7]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
EIRQ[25]\OSC32K_XTAL//WKUP[25]/ANS[0]/GPIO[24]/PB[8]
ADC1_S[6]\WKUP[8]/ADC0_S[2]/GPIO[26]/PB[10]
ADC0_S[8]/CS3_1/E0UC[10]/GPIO[80]/PF[0]
ADC0_S[9]/CS4_1/E0UC[11]/GPIO[81]/PF[1]
ADC0_S[10]/CS0_2/E0UC[12]/GPIO[82]/PF[2]
ADC0_S[11]/CS1_2/E0UC[13]/GPIO[83]/PF[3]
ADC0_S[12]/CS2_2/E0UC[14]/GPIO[84]/PF[4]
ADC0_S[13]/CS3_2/E0UC[22]/GPIO[85]/PF[5]
ADC0_S[14]/CS1_1/E0UC[23]/GPIO[86]/PF[6]
ADC0_S[15]/CS2_1/GPIO[87]/PF[7]
EIRQ[27]\ANP[4]//WKUP[27]/GPIO[48]/PD[0]
EIRQ[28]\ANP[5]/WKUP[28]/GPIO[49]/PD[1]
ADC1_P[7]/ADC0_P[6]/GPIO[50]/PD[2]
ADC1_P[7]/ADC0_P[7]/GPIO[51]/PD[3]
ADC1_P[8]/ADC0_P[8]/GPIO[52]/PD[4]
ADC1_P[9]/ADC0_P[9]/GPIO[53]/PD[5]
ADC1_P[10]/ADC0_P[10]/GPIO[54]/PD[6]
ADC1_P[11]/ADC0_P11]/GPIO[55]/PD[7]
ADC1_P[12]/ADC0_P[12]/GPIO[56]/PD[8]
ADC1_P[0]/ADC0_P[0]/GPIO[20]/PB[4]
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
2.2
EIRQ[26]\ADC1_S[5]\OSC32K_EXTAL//WKUP[26]/ADC0_S[1]/GPIO[25]/PB[9]
LIN1RX/WKUP[12]/E1UC[29]/GPIO[39]/PC[7]
E1UC[2]/LIN4TX/CS1_0/GPIO[90]/PF[10]
EMIOS[1]\LIN4RX/WKUP[15]/E1UC[3]/CS2_0/GPIO[91]/PF[11]
WKUP[10]/E0UC[1]/SCK_0/CS0_0/GPIO[15]/PA[15]
LIN5RX/WKUP[16]/E1UC[26]/GPIO[93]/PF[13]
EIRQ[4]/E0UC[0]/CS0_0/SCK_0/GPIO[14]/PA[14]
CSO_1\LIN5RX/WKUP[9]/E0UC[4]/GPIO[4]/PA[4]
E0UC[29]/SOUT_0/GPIO[13]/PA[13]
CS3_1\EIRQ[17]/SIN_0/E0UC[28]/GPIO[12]/PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
Package pinouts
144LQFP pin configuration
9
Package pinouts
208MAPBGA pin configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
NC
A
PC[8] PC[1 PH[1 PJ[4] PH[8] PH[4] PC[5] PC[0] PI[0] PI[1] PC[2] PI[4] PE[1 PH[1
3]
5]
5]
1]
B
PC[9] PB[2] PH[1 PC[1 PE[6] PH[5] PC[4] PH[9] PH[1 PI[2] PC[3] PG[1 PG[1 PG[1 PA[1 PA[1
3]
2]
0]
1]
5]
4]
1]
0]
B
C
PC[14
]
C
D
PH[14 PI[6] PC[1 PI[7] PH[6] PE[4] PE[2] VDD VDD
]
5]
_LV _HV
VDD_
HV
PB[3] PE[7] PH[7] PE[5] PE[3] VSS_ PC[1] PI[3] PA[5] PI[5] PE[1 PE[1 PA[9] PA[8]
LV
4]
2]
PA[6] PH[1 PG[1 PF[1 PE[1 PA[7]
2]
0]
4]
3]
D
PG[4] PG[5] PG[3] PG[2]
PG[1] PG[0] PF[1 VDD
5]
_HV
E
F
PE[0] PA[2] PA[1] PE[1]
PH[0] PH[1] PH[3] PH[2]
F
G
PE[9] PE[8] PE[1 PA[0]
0]
VSS_ VSS_ VSS_ VSS_
HV
HV
HV
HV
VDD PI[12 PI[13 MSE
_HV
]
]
O
G
H
VSS_ PE[1 VDD
HV
1]
_HV
NC
VSS_ VSS_ VSS_ VSS_
HV
HV
HV
HV
MDO MDO MDO MDO
3
2
0
1
H
J
RESE VSS_ NC
T
LV
NC
VSS_ VSS_ VSS_ VSS_
HV
HV
HV
HV
PI[8] PI[9] PI[10 PI[11
]
]
J
VSS_ VSS_ VSS_ VSS_
HV
HV
HV
HV
VDD PG[1 PA[3] PG[1
_HV_ 2]
3]
ADC
1
K
EVT
O
PB[1 PD[1 PD[1 PB[1
5]
5]
4]
4]
L
M
PG[7] PG[6] PC[1 PC[1
0]
1]
PB[1 PD[1 PD[1 PB[1
3]
3]
2]
2]
M
N
PB[1] PF[9] PB[0] VDD PJ[0] PA[4] VSS_ EXTA VDD PF[0] PF[4] VSS_ PB[1 PD[1 PD[9] PD[1
_HV
LV
L
_HV
HV_
1]
0]
1]
ADC
1
N
P
PF[8] PJ[3] PC[7] PJ[2] PJ[1] PA[1 VDD XTAL PB[1 PF[1] PF[5] PD[0] PD[3] VDD PB[6] PB[7]
4]
_LV
0]
_HV_
ADC
0
P
R
PF[12 PC[6] PF[1 PF[1 VDD PA[1 PA[1 PI[14 XTAL PF[3] PF[7] PD[2] PD[4] PD[7] VSS_ PB[5]
]
0]
1]
_HV
5]
3]
]
HV_
ADC
0
R
E
EVTI
NC
K
L
T
VDD VDD
_BV _LV
PG[9] PG[8] NC
NC
NC
NC
MCK
O
NC
1
2
3
4
5
NC
A
PF[1 PA[1 PI[15 EXTA PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4]
3]
2]
]
L
6
7
8
9
10
11
12
NOTE: The 208 MAPBGA is available only as development package for Nexus 2+.
13
14
15
T
16
NC = Not connected
Figure 4. 208 MAPBGA configuration
MPC5607B Microcontroller Data Sheet, Rev. 3
10
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
2.3
Electrical characteristics
Electrical characteristics
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by
the internal pull-up and pull-down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
CAUTION
All of the following figures are indicative and must be confirmed during either silicon validation, silicon characterization or
silicon reliability trial.
3.1
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 3 are used and the parameters are tagged accordingly in the tables where
appropriate.
Table 3. Parameter classifications
Classification tag
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.2
NVUSRO register
Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are
controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register.
3.2.1
NVUSRO[PAD3V5V] field description
Table 4 shows how NVUSRO[PAD3V5V] controls the device configuration.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
11
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
3
Electrical characteristics
Table 4. PAD3V5V field description1
Value2
2
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
See the device reference manual for more information on the NVUSRO register.
'1' is delivery value. It is part of shadow Flash, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V bit value.
3.2.2
NVUSRO[OSCILLATOR_MARGIN] field description
Table 5 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
Table 5. OSCILLATOR_MARGIN field description1
Value2
1
2
Description
0
Low consumption configuration (4 MHz/8 MHz)
1
High margin configuration (4 MHz/16 MHz)
See the device reference manual for more information on the NVUSRO register.
'1' is delivery value. It is part of shadow Flash, thus programmable by customer.
The main external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value.
3.2.3
NVUSRO[WATCHDOG_EN] field description
Table 5 shows how NVUSRO[WATCHDOG_EN] controls the device configuration.
Table 6. WATCHDOG_EN field description1
Value2
1
2
Description
0
Disable after reset
1
Enable after reset
See the device reference manual for more information on the NVUSRO register.
'1' is delivery value. It is part of shadow Flash, thus programmable by customer.
MPC5607B Microcontroller Data Sheet, Rev. 3
12
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
1
Description
Electrical characteristics
3.3
Absolute maximum ratings
Table 7. Absolute maximum ratings
Parameter
Conditions
Unit
Min
Max
VSS
SR
Digital ground
on VSS_HV
pins
—
0
0
V
VDD
SR
Voltage on
VDD_HV pins
with respect to
ground (VSS)
—
-0.3
6.0
V
VSS_LV
SR
Voltage on
VSS_LV (low
voltage digital
supply) pins
with respect to
ground (VSS)
—
VSS-0.1
VSS+0.1
V
VDD_BV
SR
Voltage on
VDD_BV pin
(regulator
supply) with
respect to
ground (VSS)
—
-0.3
6.0
V
Relative to VDD
-0.3
VDD+0.3
—
VSS-0.1
VSS+0.1
V
-0.3
6.0
V
VDD −0.3
VDD+0.3
-0.3
6.0
VDD −0.3
VDD+0.3
VSS_ADC
SR
Voltage on
VSS_HV_ADC
0,
VSS_HV_ADC
1 (ADC
reference) pin
with respect to
ground (VSS)
VDD_ADC
SR
Voltage on
—
VSS_HV_ADC
Relative to VDD
0,
VSS_HV_ADC
1 (ADC
reference) with
respect to
ground (VSS)
VIN
SR
—
Voltage on any
GPIO pin with
Relative to VDD
respect to
ground (VSS)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Value
Symbol
V
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
13
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 7. Absolute maximum ratings (continued)
Value
Parameter
Conditions
Unit
Min
Max
IINJPAD
SR
Injected input
current on any
pin during
overload
condition
—
-10
10
IINJSUM
SR
Absolute sum
of all injected
input currents
during overload
condition
—
-50
50
IAVGSEG
SR
Sum of all the
static I/O
current within a
supply
segment
VDD = 5.0 V ±
10%, PAD3V5V
=0
70
VDD = 3.3 V ±
10%, PAD3V5V
=1
64
TSTORAGE
SR
Storage
temperature
—
-55
mA
mA
150
°C
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. During overload conditions (VIN > VDD or
VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the
recommended values.
3.4
Recommended operating conditions
Table 8. Recommended operating conditions (3.3 V)
Value
Symbol
VSS
Parameter
Conditions
Unit
Min
Max
SR Digital ground on VSS_HV pins
—
0
0
V
SR Voltage on VDD_HV pins with respect
to ground (VSS)
—
3.0
3.6
V
VSS_LV2
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground
(VSS)
—
VDD_BV3
SR Voltage on VDD_BV pin (regulator
supply) with respect to ground (VSS)
—
VDD
1
Relative to VDD
VSS−0.1 VSS+0.1
3.0
3.6
V
V
VDD−0.1 VDD+0.1
MPC5607B Microcontroller Data Sheet, Rev. 3
14
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Symbol
Electrical characteristics
Table 8. Recommended operating conditions (3.3 V) (continued)
Value
Parameter
Conditions
Unit
Min
SR Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC reference) pin
with respect to ground (VSS)
VDD_ADC4
—
SR Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC reference) with
Relative to VDD
respect to ground (VSS)
VIN
2
3
4
5
6
3.05
3.6
V
V
VDD−0.1 VDD+0.1
—
Relative to VDD
VSS−0.1
—
—
VDD+0.1
V
IINJPAD
SR Injected input current on any pin
during overload condition
—
−5
5
IINJSUM
SR Absolute sum of all injected input
currents during overload condition
—
−50
50
SR VDD slope to ensure correct power up6
—
—
0.25
V/µs
−40
125
°C
−40
150
TVDD
1
SR Voltage on any GPIO pin with respect
to ground (VSS)
VSS−0.1 VSS+0.1
—
VSS_ADC
Max
TA
SR Ambient temperature under bias
TJ
SR Junction temperature under bias
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Symbol
fCPU < 64 MHz
—
mA
100 nF capacitance needs to be provided between each VDD/VSS pair
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL,
device is reset.
Guaranteed by device validation
Table 9. Recommended operating conditions (5.0 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
0
V
VDD1
SR Voltage on VDD_HV pins with respect to ground (VSS)
—
4.5
5.5
V
3.0
5.5
Voltage
drop2
VSS_LV3
SR Voltage on VSS_LV (low voltage digital supply) pins with
respect to ground (VSS)
—
VDD_BV4
SR Voltage on VDD_BV pin (regulator supply) with respect
to ground (VSS)
—
VSS-0.1 VSS+0.1
2
Voltage drop
4.5
5.5
3.0
5.5
V
V
Relative to VDD VDD-0.1 VDD+0.1
VSS_ADC
SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC
reference) pin with respect to ground (VSS)
—
VSS-0.1 VSS+0.1
V
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
15
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 9. Recommended operating conditions (5.0 V) (continued)
Value
Parameter
Conditions
VDD_ADC5 SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC
reference) with respect to ground (VSS)
—
2
Voltage drop
Unit
Min
Max
4.5
5.5
3.0
5.5
V
Relative to VDD VDD-0.1 VDD+0.1
VIN
SR Voltage on any GPIO pin with respect to ground (VSS)
—
VSS-0.1
-
Relative to VDD
-
VDD+0.1
V
IINJPAD
SR Injected input current on any pin during overload
condition
—
-5
5
IINJSUM
SR Absolute sum of all injected input currents during
overload condition
—
-50
50
SR VDD slope to ensure correct power up6
—
—
0.25
V/µs
—
3
—
V/s
fCPU < 64 MHz
−40
85
°C
—
−40
110
fCPU < 64 MHz
−40
105
—
−40
130
fCPU < 60 MHz
−40
125
—
−40
150
TVDD
TA C-Grade SR Ambient temperature under bias
mA
Part
TJ C-Grade SR Junction temperature under bias
Part
TA V-Grade SR Ambient temperature under bias
Part
TJ V-Grade SR Junction temperature under bias
Part
TA M-Grade SR Ambient temperature under bias
Part
TJ M-Grade SR Junction temperature under bias
Part
1
2
3
4
5
6
100 nF capacitance needs to be provided between each VDD/VSS pair
Full device operation is guaranteed by design when the voltage drops below 4.5V down to 3.6V. However, certain
analog electrical characteristics will not be guaranteed to stay within the stated limits.
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). This decoupling need to be increased as recommended in
Section 3.5.1, “External ballast resistor recommendations incase external ballast resistor is planned to be used.
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair
Guaranteed by device validation
NOTE
RAM data retention is guaranteed wi‘th VDD_LV not below 1.08 V.
MPC5607B Microcontroller Data Sheet, Rev. 3
16
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Symbol
Electrical characteristics
Thermal characteristics
3.5.1
External ballast resistor recommendations
External ballast resistor on VDD_BV pin helps in reducing the overall power dissipation inside the device. This resistor is
required only when maximum power consumption exceeds the limit imposed by package thermal characteristics.
As stated in Table 10 LQFP thermal characteristics, considering thermal resistance of LQFP144 as 48.3 °C/W, at ambient TA =
125 °C, the junction temp Tj will cross 150 °C if total power dissipation > (150 - 125)/48.3 = 517 mW. Therefore, total device
current IDDMAX at 125 °C/5.5V must not exceed 94.1 mA (i.e. PD/VDD). Assuming an average IDD(VDD_HV) of 15-20 mA
consumption typically during device RUN mode, the LV domain consumption IDD(VDD_BV) is thus limited to IDDMAX IDD(VDD_HV) i.e. 80 mA.
Therefore, respecting the maximum power allowed as explained in Section 3.5.2, “Package thermal characteristics, it is
recommended to use this resistor only in the 125 °C/5.5V operating corner as per the following guidelines:
If IDD(VDD_BV) < 80 mA, then no resistor is required.
If 80 mA < IDD(VDD_BV) < 90 mA, then 4 Ohm resistor can be used along with 14.7 µf decoupling.
If IDD(VDD_BV) > 90 mA, then 8 Ohm resistor can be used along with 33 µf decoupling.
•
•
•
Using resistance in the range of 4-8 Ohm, the gain will be around 10-20% of total consumption on VDD_BV. For example, if 8
Ohm resistor is used, then power consumption when IDD(VDD_BV) is 110 mA is equivalent to power consumption when
IDD(VDD_BV) is 90 mA (approximately) when resistor not used.
3.5.2
Package thermal characteristics
Table 10. LQFP thermal characteristics1
Symbol
RθJA
C
CC
D
Parameter
Conditions2
Single-layer
Thermal
resistance, board—1s
junction-toambient
natural
convection4
Four-layer
board—2s2p
Value3
Pin count
Unit
Min
Typ
Max
100
—
—
64
144
—
—
64
176
—
—
64
100
—
—
49.7
144
—
—
48.3
176
—
—
47.3
°C/W
1
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C.
3 All values need to be confirmed during device validation.
4 Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA.
2
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
17
Preliminary—Subject to Change Without Notice
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not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
3.5
Electrical characteristics
Symbol
RθJA
1
2
3.5.3
CC
C
Parameter
—
Thermal
resistance,
junction-to-am
bient natural
convection2
Conditions
Value
Unit
TBD
°C/W
Single-layer
board—1s
Four-layer
board—2s2p
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA
and RthJMA.
Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1:
TJ = TA + (PD x RθJA)
Eqn. 1
Where:
TA is the ambient temperature in °C.
RθJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PI/O (PD = PINT + PI/O).
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power.
PI/O represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device
is configured to continuously drive external modules and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273 °C)
Eqn. 2
K = PD x (TA + 273 °C) + RθJA x PD2
Eqn. 3
Therefore, solving equations 1 and 2:
Where:
K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2
iteratively for any value of TA.
3.6
3.6.1
I/O pad electrical characteristics
I/O pad types
The device provides four main I/O pad types depending on the associated alternate functions:
•
•
Slow pads - are the most common pads, providing a good compromise between transition time and low
electromagnetic emission.
Medium pads - provide transition fast enough for the serial communication channels with controlled current to reduce
electromagnetic emission.
MPC5607B Microcontroller Data Sheet, Rev. 3
18
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Table 11. 208 MAPBGA thermal characteristics1
Electrical characteristics
Fast pads - provide maximum speed. These are used for improved Nexus debugging capability.
Input only pads - are associated with ADC channels and 32 kHz low power external crystal oscillator providing low
input leakage.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
3.6.2
I/O input DC characteristics
Table 12 provides input DC electrical characteristics as described in Figure 5.
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1
(GPDI register of SIUL)
PDIx = ‘0’
Figure 5. I/O input DC electrical characteristics definition
Table 12. I/O input DC electrical characteristics
Symbol
C
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
VIH
SR P Input high level CMOS (Schmitt
Trigger)
—
0.65VDD
—
VDD+0.4
VIL
SR P Input low level CMOS (Schmitt
Trigger)
—
−0.4
—
0.35VDD
—
0.1VDD
—
—
VHYS CC C Input hysteresis CMOS (Schmitt
Trigger)
V
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
19
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
•
•
Electrical characteristics
Table 12. I/O input DC electrical characteristics (continued)
C
Parameter
Unit
Min
Typ
Max
TA = −40 °C
—
2
—
TA = 25 °C
—
2
—
D
TA = 105 °C
—
12
500
P
TA = 125 °C
—
70
1000
—
—
—
40
ns
—
1000
—
—
ns
ILKG CC P Digital input leakage
P
WFI
Conditions
SR P Width of input pulse surely filtered
by analog filter3
WNFI SR P Width of input pulse surely not
filtered by analog filter3
No injection
on adjacent
pin
nA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 Analog filters are available on all wakeup lines.
1
2
MPC5607B Microcontroller Data Sheet, Rev. 3
20
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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Symbol
Value2
1
Electrical characteristics
3.6.3
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
Table 13 provides weak pull figures. Both pull-up and pull-down resistances are supported.
Table 15 provides output driver characteristics for I/O pads when in SLOW configuration.
Table 16 provides output driver characteristics for I/O pads when in MEDIUM configuration.
Table 14 provides output driver characteristics for I/O pads when in FAST configuration.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
•
•
•
•
Table 13. I/O pull-up/pull-down DC electrical characteristics
Symbol
|IWPU|
C
CC
P
C
Parameter
Weak
pull-up
current
absolute
value
P
|IWPD|
CC
P
C
P
1
2
Weak
pull-down
current
absolute
value
Value
Conditions1
Unit
Min
Typ
Max
10
—
150
10
—
250
VIN = VIL, PAD3V5V
VDD =
=1
3.3 V ±
10%
10
—
150
VIN = VIH, PAD3V5V
=0
VDD =
5.0 V ±
PAD3V5V
10%
=1
10
—
150
10
—
250
10
—
150
VIN = VIL, PAD3V5V
VDD =
=0
5.0 V ±
PAD3V5V
10%
= 12
VIN = VIH, PAD3V5V
VDD =
=1
3.3 V ±
10%
µA
µA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
21
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 14. FAST configuration output buffer electrical characteristics
VOH
VOL
C
CC
CC
Parameter
Value
Conditions1
Unit
Min
Typ
Max
IOH =
−14mA,
VDD =
5.0 V ±
10%,
PAD3V5V
=0
(recomme
nded)
0.8VDD
—
—
C
IOH =
−7mA,
VDD =
5.0 V ±
10%,
PAD3V5V
= 12
0.8VDD
—
—
C
IOH =
−11mA,
VDD =
3.3 V ±
10%,
PAD3V5V
=1
(recomme
nded)
VDD−0.8
—
—
IOL =
14mA,
VDD =
5.0 V ±
10%,
PAD3V5V
=0
(recomme
nded)
—
—
0.1VDD
C
IOL = 7mA,
VDD =
5.0 V ±
10%,
PAD3V5V
= 12
—
—
0.1VDD
C
IOL =
11mA,
VDD =
3.3 V ±
10%,
PAD3V5V
=1
(recomme
nded)
—
—
0.5
P
P
Output
Push Pull
high level
FAST
configurati
on
Output low Push Pull
level
FAST
configurati
on
V
V
MPC5607B Microcontroller Data Sheet, Rev. 3
22
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Symbol
Electrical characteristics
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
3.6.4
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1
Output pin transition times
Table 15. Output pin transition times
Symbol
Ttr
C
CC
D
T
D
Ttr
CC
Parameter
Output
transition
time output
pin3
SLOW
configurati
on
Conditions
CL =
25 pF
CL =
50 pF
CL =
25 pF
T
CL =
50 pF
D
CL =
100 pF
D
T
D
Output
transition
time output
pin3
MEDIUM
configurati
on
VDD =
5.0 V ±
10%,
PAD3V5V
=0
CL =
100 pF
D
CL =
25 pF
CL =
50 pF
CL =
100 pF
D
CL =
25 pF
T
CL =
50 pF
D
CL =
100 pF
Value2
1
VDD =
3.3 V ±
10%,
PAD3V5V
=1
VDD =
5.0 V ±
10%,
PAD3V5V
=0
SIUL.PCR
x.SRC = 1
VDD =
3.3 V ±
10%,
PAD3V5V
=1
SIUL.PCR
x.SRC = 1
Unit
Min
Typ
Max
—
—
50
—
—
100
—
—
125
—
—
50
—
—
100
—
—
125
—
—
10
—
—
20
—
—
40
—
—
12
—
—
25
—
—
40
ns
ns
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
23
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 15. Output pin transition times (continued)
Ttr
C
CC
Parameter
D
Output
transition
time output
pin3
FAST
configurati
on
Conditions
CL =
25 pF
Unit
VDD =
5.0 V ±
10%,
PAD3V5V
=0
CL =
50 pF
CL =
100 pF
CL =
25 pF
VDD =
3.3 V ±
10%,
PAD3V5V
=1
CL =
50 pF
CL =
100 pF
Min
Typ
Max
—
—
4
—
—
6
—
—
12
—
—
4
—
—
7
—
—
12
ns
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 C includes device and package capacitances (C
L
PKG < 5 pF).
1
2
3.6.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as
described in Table 16.
Table 17 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG
maximum value.
In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain
below the IDYNSEG maximum value.
Table 16. I/O supply segments
Supply segment
Package
1
208
MAPBGA1
3
4
5
6
Equivalent to 176 LQFP segment pad distribution
176 LQFP pin7– pin27
1
2
pin28 –
pin57
pin59 –
pin85
pin86 –
pin123
7
8
MCKO
MDOn
/MSEO
pin124 –
pin150
pin151 –
pin6
144 LQFP
pin20 –
pin49
pin51 –
pin99
pin100 –
pin122
pin 123 –
pin19
—
—
—
—
100 LQFP
pin16 –
pin35
pin37 –
pin69
pin70 –
pin83
pin84 –
pin15
—
—
—
—
208 MAPBGA available only as development package for Nexus2+
MPC5607B Microcontroller Data Sheet, Rev. 3
24
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Symbol
Value2
1
Electrical characteristics
Table 17. I/O consumption
IDYNSEG
ISWTSLW,3
ISWTMED3
ISWTFST3
C
SR
CC
CC
CC
D
D
D
D
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
110
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
65
VDD =
5.0 V ±
10%,
PAD3V5V
=0
—
—
20
VDD =
3.3 V ±
10%,
PAD3V5V
=1
—
—
16
Dynamic
CL =
I/O current 25 pF
for
MEDIUM
configurati
on
VDD =
5.0 V ±
10%,
PAD3V5V
=0
—
—
29
VDD =
3.3 V ±
10%,
PAD3V5V
=1
—
—
17
Dynamic
CL =
I/O current 25 pF
for FAST
configurati
on
VDD =
5.0 V ±
10%,
PAD3V5V
=0
—
—
110
VDD =
3.3 V ±
10%,
PAD3V5V
=1
—
—
50
Sum of all
the
dynamic
and static
I/O current
within a
supply
segment
Dynamic
CL =
I/O current 25 pF
for SLOW
configurati
on
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Symbol
mA
mA
mA
mA
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
25
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 17. I/O consumption (continued)
IRMSSLW
C
CC
D
Parameter
Root
medium
square I/O
current for
SLOW
configurati
on
Conditions
CL =
25 pF, 2
MHz
CL =
25 pF, 4
MHz
VDD =
5.0 V ±
10%,
PAD3V5V
=0
CL =
100 pF, 2
MHz
CL =
25 pF, 2
MHz
CL =
25 pF, 4
MHz
VDD =
3.3 V ±
10%,
PAD3V5V
=1
CL =
100 pF, 2
MHz
IRMSMED
CC
D
Root
medium
square I/O
current for
MEDIUM
configurati
on
CL =
25 pF, 13
MHz
CL =
25 pF, 40
MHz
VDD =
5.0 V ±
10%,
PAD3V5V
=0
CL =
100 pF, 13
MHz
CL =
25 pF, 13
MHz
CL =
25 pF, 40
MHz
CL =
100 pF, 13
MHz
VDD =
3.3 V ±
10%,
PAD3V5V
=1
Unit
Min
Typ
Max
—
—
2.3
—
—
3.2
—
—
6.6
—
—
1.6
—
—
2.3
—
—
4.7
—
—
6.6
—
—
13.4
—
—
18.3
—
—
5
—
—
8.5
—
—
11
mA
mA
MPC5607B Microcontroller Data Sheet, Rev. 3
26
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Symbol
Value2
1
Electrical characteristics
Table 17. I/O consumption (continued)
IRMSFST
C
CC
D
Parameter
Root
medium
square I/O
current for
FAST
configurati
on
Conditions
Typ
Max
—
—
22
—
—
33
—
—
56
—
—
14
—
—
20
CL =
100 pF, 40
MHz
—
—
35
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
70
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
65
CL =
25 pF, 40
MHz
CL =
25 pF, 64
MHz
VDD =
5.0 V ±
10%,
PAD3V5V
=0
CL =
100 pF, 40
MHz
CL =
25 pF, 40
MHz
CL =
25 pF, 64
MHz
IAVGSEG
SR
D
Sum of all
the static
I/O current
within a
supply
segment
Unit
Min
VDD =
3.3 V ± 10
%,
PAD3V5V
=1
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Symbol
Value2
1
mA
mA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
1
2
3.7
nRSTIN electrical characteristics
The device implements a dedicated bidirectional RESET pin.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
27
Preliminary—Subject to Change Without Notice
Electrical characteristics
VDDMIN
nRSTIN
VIH
VIL
device reset forced by nRSTIN
device start-up phase
Figure 6. Start-up reset requirements
VRSTIN
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
Figure 7. Noise filtering on reset signal
MPC5607B Microcontroller Data Sheet, Rev. 3
28
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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VDD
Electrical characteristics
Table 18. Reset electrical characteristics
C
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
VIH
SR P Input High Level CMOS
(Schmitt Trigger)
—
0.65VDD
—
VDD+0.4
V
VIL
SR P Input low Level CMOS
(Schmitt Trigger)
—
−0.4
—
0.35VDD
V
VHYS
CC C Input hysteresis CMOS
(Schmitt Trigger)
—
0.1VDD
—
—
V
VOL
CC P Output low level
Push Pull, IOL = 2mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
V
Push Pull, IOL = 1mA,
VDD = 5.0 V ± 10%, PAD3V5V = 13
—
—
0.1VDD
Push Pull, IOL = 1mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
CL = 25pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
10
CL = 50pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
20
CL = 100pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
40
CL = 25pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
12
CL = 50pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
25
CL = 100pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
40
WFRST SR P nRSTIN input filtered
pulse
—
—
—
40
ns
WNFRST SR P nRSTIN input not filtered
pulse
—
1000
—
—
ns
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
—
150
µA
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
—
150
VDD = 5.0 V ± 10%, PAD3V5V = 15
10
—
250
Ttr
CC D Output transition time
output pin4
MEDIUM configuration
|IWPU| CC P Weak pull-up current
absolute value
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Symbol
ns
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
the device reference manual).
4
CL includes device and package capacitance (CPKG < 5 pF).
5
The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
1
2
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
29
Preliminary—Subject to Change Without Notice
Electrical characteristics
Power management electrical characteristics
3.8.1
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage
ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved:
•
•
•
HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD
power pin.
BV: High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV
power pin. Voltage values should be aligned with VDD.
LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the internal
voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure
noise isolation between critical LV modules within the device:
— LV_COR: Low voltage supply for the core. It is also `used to provide supply for FMPLL through double bonding.
— LV_CFLA: Low voltage supply for code Flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_DFLA: Low voltage supply for data Flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
CREG2 (LV_COR/LV_CFLA)
GND
VDD
VSS_LV
VDD_BV
Voltage Regulator
I
VSS_LVn
VDD_BV
CREG1 (LV_COR/LV_DFLA)
VDD_LVn
CDEC1 (Ballast decoupling)
VREF
VDD_LV
VDD_LV
DEVICE
VSS_LV
GND
VSS_LV
DEVICE
GND
VDD_LV
VSS
VDD
GND
CREG3 (LV_COR/LV_PLL)
CDEC2 (supply/IO decoupling)
Figure 8. Voltage regulator capacitance connection
The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable
low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.
Care should also be taken to limit the serial inductance of the board to less than 5 nH.
MPC5607B Microcontroller Data Sheet, Rev. 3
30
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
3.8
Electrical characteristics
Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see
Section 3.4, “Recommended operating conditions).
Symbol
C
Parameter
Typ
Max
—
200
—
330
nF
RREG
SR — Stability capacitor equivalent serial
resistance
—
—
—
0.2
W
CDEC1
SR — Decoupling capacitance3,4 ballast
VDD_BV/VSS_LV pair
400
4705
—
nF
CDEC2
SR — Decoupling capacitance regulator
supply
VDD/VSS pair
10
100
—
nF
VMREG
CC P Main regulator output voltage
Before trimming
—
1.32
—
V
After trimming
—
1.28
—
—
—
150
mA
mA
SR — Main regulator current provided to
VDD_LV domain
—
CC D Main regulator module current
consumption
IMREG = 200 mA
—
—
2
IMREG = 0 mA
—
—
1
VLPREG
CC P Low power regulator output voltage
After trimming
—
1.23
—
V
ILPREG
SR — Low power regulator current provided
to VDD_LV domain
—
—
15
mA
—
—
600
µA
ILPREG = 0 mA;
TA = 55 °C
—
5
TBD
Post trimming
—
1.23
—
V
—
—
5
mA
IULPREG = 5 mA;
TA = 55 °C
—
—
100
µA
IULPREG = 0 mA;
TA = 55 °C
—
2
TBD
CC D Main LVDs and reference current
consumption (low power and main
regulator switched off)
TA = 55 °C
—
17
—
µA
CC D Main LVD current consumption
(switch-off during standby)
TA = 55 °C
—
2
TBD
µA
—
—
4006
mA
ILPREGINT
VULPREG
CC P Ultra low power regulator output
voltage
IULPREG
SR — Ultra low power regulator current
provided to VDD_LV domain
IULPREGINT
CC D Ultra low power regulator module
current consumption
IVREGREF
IVREDLVD12
IDD_BV
—
CC D Low power regulator module current ILPREG = 15 mA;
consumption
TA = 55 °C
—
2
Unit
Min
SR — Internal voltage regulator external
capacitance
IMREGINT
1
Value2
Conditions1
CREGn
IMREG
CC D In-rush current on VDD_BV during
power-up
—
—
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Table 19. Voltage regulator electrical characteristics
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
31
Preliminary—Subject to Change Without Notice
Electrical characteristics
This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage.
A typical value is in the range of 470 nF.
4
In case external ballast resistor is planned to be used, then to avoid a LVD reset during standby mode exit, the
following configuration need to be respected.
- for 8 ohm ballast resistor, decoupling cap of 33 µf is required.
- for 4 ohm ballast resistor, decoupling cap of 14.7µf is required.
These values are only after preliminary validation and are subject to change.
5
External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV
in operating range.
6
In-rush current is seen only for short time during power-up and on standby exit (max 20µs, depending on external
capacitances to be load)
MPC5607B Microcontroller Data Sheet, Rev. 3
32
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
3
Electrical characteristics
3.8.2
Voltage monitor electrical characteristics
•
•
•
•
•
•
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
The device implements a Power-on Reset module to ensure correct power-up initialization, as well as four low voltage detectors
to monitor the VDD and the VDD_LV voltage while device is supplied:
POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state
LVDHV3 monitors VDD to ensure device reset below minimum functional supply
LVDHV3B monitors VDD_BV to ensure device reset below minimum functional supply
LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range
LVDLVCOR monitors power domain No. 1
LVDLVBKP monitors power domain No. 0
NOTE
When enabled, power domain No. 2 is monitored through LVD_DIGBKP.
VDD
VLVDHVxH
VLVDHVxL
RESET
Figure 9. Low voltage monitor vs reset
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
33
Preliminary—Subject to Change Without Notice
Electrical characteristics
Symbol
C
Parameter
Condition
s1
Value2
Unit
Symbol
V
VPORUP
VPORUP
SR
P
Supply for TA = 25 °C,
functional after
POR
trimming
module
1.0
—
5.5
VPORH
CC
P
Power-on
reset
threshold
1.5
—
2.6
VPORH
VLVDHV3H
CC
T
LVDHV3
low voltage
detector
high
threshold
—
—
2.95
VLVDHV3H
VLVDHV3L
CC
P
LVDHV3
low voltage
detector
low
threshold
2.7
—
2.9
VLVDHV3L
VLVDHV3BH
CC
P
LVDHV3B
low voltage
detector
high
threshold
—
—
2.95
VLVDHV3BH
VLVDHV3BL
CC
P
LVDHV3B
L low
voltage
detector
low
threshold
2.7
—
2.9
VLVDHV3BL
VLVDHV5H
CC
T
LVDHV5
low voltage
detector
high
threshold
—
—
4.5
VLVDHV5H
VLVDHV5L
CC
P
LVDHV5
low voltage
detector
low
threshold
3.8
—
4.4
VLVDHV5L
VLVDLVCOR
CC
P
LVDLVCO
R low
voltage
detector
low
threshold
1.07
—
1.11
VLVDLVCOR
L
1
L
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
MPC5607B Microcontroller Data Sheet, Rev. 3
34
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Table 20. Low voltage monitor electrical characteristics
Electrical characteristics
3.9
All values need to be confirmed during device validation.
Low voltage domain power consumption
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
2
Table 21 provides DC electrical characteristics for significant application modes. These values are indicative values; actual
consumption depends on the application.
Table 21. Low voltage power domain electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
IDDMAX2
CC
D
RUN mode
maximum
average
current
—
—
115
1403
mA
IDDRUN4
CC
T
RUN mode
typical
average
current5
—
—
80
100
mA
—
—
TBD
TBD
—
—
8
TBD
mA
TA = 25 °
C
—
350
9008
µA
TA = 55 °
C
—
750
—
TA = 85 °
C
—
2
—
D
TA = 105 °
C
—
4
—
P
TA = 125 °
C
—
9
TBD8
TA = 25 °
C
—
30
100
TA = 55 °
C
—
TBD
—
TA = 85 °
C
—
—
D
TA = 105 °
C
—
—
P
TA = 125 °
C
—
TBD
P
IDDHALT
CC
P
HALT
mode
current6
IDDSTOP
CC
P
STOP
mode
current7
D
D
IDDSTDBY2
CC
P
D
D
Slow
internal
RC
oscillator
(128 kHz)
running
STANDBY Slow
2 mode
internal
current9
RC
oscillator
(128 kHz)
running
mA
µA
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
35
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 21. Low voltage power domain electrical characteristics (continued)
IDDSTDBY1
C
CC
Parameter
Value
Conditions1
Unit
Min
Typ
Max
TA = 25 °
C
—
20
60
TA = 55 °
C
—
TBD
—
TA = 85 °
C
—
—
D
TA = 105 °
C
—
—
D
TA = 125 °
C
—
T
D
D
STANDBY Slow
1 mode
internal
current10 RC
oscillator
(128 kHz)
running
280
µA
TBD
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
Running consumption is given on voltage regulator supply (VDDREG). It does not include consumption linked to I/Os
toggling. This value is highly dependent on the application. The given value is thought to be a worst case value
with all peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to
be noticed that this value can be significantly reduced by application: switch-off not used peripherals (default),
reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode
when possible.
3 Higher current may be sinked by device during power-up and standby exit. please refer to in rush current on
Table 19.
4 RUN current measured with typical application with accesses on both flash and RAM.
5 Only for the “P” classification: Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPi as Master,
PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic
SW/WDG timer reset enabled.
6 Data Flash Power Down. Code Flash in Low Power. RC-osc128kHz & RC-OSC 16MHz on. 10MHz XTAL clock.
FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex:
instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON
(16 channels on PA[0]-PA[11] and PC[12]-PC[15]) with PWM 20KHz, instance: 1 clock gated. DSPI: instance: 0
(clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but not conversion except 2 analogue
watchdog
7
Only for the “P” classification: No clock, RC 16MHz off, RC128kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All
possible peripherals off and clock gated. Flash in power down mode.
8
When going from RUN to STOP mode and the core consumption is > 6 mA , it is normal operation for the main
regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction
temperatures exceeding 125 °C and under these circumstances , it is possible for the current to initially exceed the
maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to
the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA.
9
Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum
consumption, all possible modules switched-off.
10
ULPreg on, HP/LPVreg off, 8KB RAM on, device configured for minimum consumption, all possible modules
switched-off.
1
2
MPC5607B Microcontroller Data Sheet, Rev. 3
36
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Symbol
Electrical characteristics
Flash memory electrical characteristics
3.10.1
Program/Erase characteristics
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
3.10
Table 22 shows the program and erase characteristics.
Table 22. Program and erase specifications
Value
Symbol
C
Parameter
Unit
Min
Typ1
Initial
max2
Max3
Double
word (64
bits)
program
time4
—
22
TBD
500
µs
T16Kpperase
16 KB block
pre-progra
m and
erase time
—
300
500
5000
ms
T32Kpperase
32 KB block
pre-progra
m and
erase time
—
400
600
5000
ms
T128Kpperas
128 KB
block
pre-progra
m and
erase time
—
800
1300
7500
ms
Tdwprogram
CC
e
C
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4 Actual hardware programming times. This does not include software overhead.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
37
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 23. Flash module life
C
Parameter
Conditions
2
Typ
—
P/E
CC C Number of program/erase cycles per
block for 16 Kbyte blocks over the
operating temperature range (TJ)
—
100,000
P/E
CC C Number of program/erase cycles per
block for 32 Kbyte blocks over the
operating temperature range (TJ)
—
10,000
100,0001 cycles
P/E
CC C Number of program/erase cycles per
block for 128 Kbyte blocks over the
operating temperature range (TJ)
—
1,000
100,0001 cycles
Retention CC C Minimum data retention at 85 °C
average ambient temperature2
1
Unit
Min
cycles
Blocks with 0–1,000 P/E
cycles
20
—
years
Blocks with 10,000 P/E
cycles
10
—
years
Blocks with 100,000 P/E
cycles
5
—
years
To be confirmed
Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units
will experience single bit corrections throughout the life of the product with no impact to product reliability.
Table 24. Flash read access timing
Symbol
fREAD
CC
C
Parameter
P
Maximum
frequency for
Flash reading
C
C
1
Conditions1
Max
Unit
2 wait states
64
MHz
1 wait state
40
0 wait states
20
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
3.10.2
Flash power supply DC characteristics
Table 25 shows the power supply DC characteristics on external supply.
MPC5607B Microcontroller Data Sheet, Rev. 3
38
Freescale Semiconductor
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Value
Symbol
Electrical characteristics
Table 25. Flash power supply DC electrical characteristics
Parameter
Value2
Conditions1
Unit
Min
ICFREAD3
CC
IDFREAD3
ICFMOD3
CC
IDFMOD3
ICFLPW3
CC
IDFLPW3
ICFPWD3
IDFPWD
CC
3
Typ
Max
Code Flash
33
Data Flash
33
Code Flash
52
Data Flash
33
Sum of the
current
consumptio
n on VDDHV
and VDDBV
during
Flash low
power
mode
Code Flash
1.1
mA
Data Flash
900
µA
Sum of the
current
consumptio
n on VDDHV
and VDDBV
during
Flash
power
down mode
Code Flash
150
µA
Data Flash
150
Sum of the
current
consumptio
n on VDDHV
and VDDBV
on read
access
Flash
module
read
fCPU = 64
MHz4
Sum of the
current
consumptio
n on VDDHV
and VDDBV
on matrix
modificatio
n
(program/er
ase)
Program/
Erase
on-going
while
reading
Flash
registers
fCPU = 64
MHz4
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Symbol
mA
mA
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 / 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 Data based on characterization results, not tested in production
4
fCPU 64 MHz can be achieved only at up to 105 °C
2
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
39
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.10.3
Start-up/Switch-off timings
Symbol
TFLARSTEXI CC
C
Value
Parameter Conditions1
Unit
Min
Typ
Max
T
Delay for
Flash
module to
exit reset
mode
—
—
—
125
TFLALPEXIT CC
T
Delay for
Flash
module to
exit
low-power
mode
—
—
—
0.5
TFLAPDEXIT CC
T
Delay for
Flash
module to
exit
power-dow
n mode
—
—
—
30
TFLALPENTR CC
T
Delay for
Flash
module to
enter
low-power
mode
—
—
—
0.5
T
Delay for
Flash module to enter
power-dow
n mode
—
—
—
1.5
T
Y
TFLAPDENT CC
RY
1
µs
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
3.11
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
3.11.1
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified
MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in
particular.
Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC
level requested for the application.
•
Software recommendations − The software flowchart must include the management of runaway conditions such as:
— Corrupted program counter
MPC5607B Microcontroller Data Sheet, Rev. 3
40
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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Table 26. Start-up time/Switch-off time
— Unexpected reset
— Critical data corruption (control registers...)
Prequalification trials − Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the
software can be hardened to prevent unrecoverable errors occurring.
•
3.11.2
Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC61967-1
standard, which specifies the general conditions for EMI measurements.
Table 27. EMI radiated emission measurement1,2
Symbol
C
Paramete
r
Value
Conditions
Unit
Min
—
SR
—
Scan
range
—
0.150
fCPU
SR
—
Operating
frequency
—
—
VDD_LV
SR
—
LV
operating
voltages
—
SEMI
CC
T
Peak level VDD =
5 V,
TA = 25 °
C,
LQFP144
package
Test
conformin
g to IEC
61967-2,
fOSC = 8
MHz/fCPU
= 64 MHz
Typ
Max
1000
MHz
64
—
MHz
—
1.28
—
V
No PLL
frequency
modulatio
n
—
—
18
dBµV
± 2% PLL
frequency
modulatio
n
—
—
143
dBµV
1
EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your
local marketing representative.
3
All values need to be confirmed during device validation
2
3.11.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine
its performance in terms of electrical sensitivity.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
41
Preliminary—Subject to Change Without Notice
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Electrical characteristics
Electrical characteristics
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts×(n+1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
Table 28. ESD absolute maximum ratings1,2
Conditions
Class
Max value3
Unit
VESD(HBM) Electrostatic discharge voltage
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C
2000
V
VESD(MM) Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
VESD(CDM) Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
Symbol
Ratings
750 (corners)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
3
Data based on characterization results, not tested in production
3.11.3.2
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 29. Latch-up results
Symbol
LU
3.12
Parameter
Static latch-up class
Conditions
TA = 125 °C
conforming to JESD 78
Class
II level A
Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure describes a simple model of the internal oscillator driver and provides
an example of a connection for an oscillator or a resonator.
Table 30 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.
MPC5607B Microcontroller Data Sheet, Rev. 3
42
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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3.11.3.1
Electrical characteristics
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not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
EXTAL
C1
Crystal
EXTAL
RP
XTAL
C2
DEVICE
VDD
I
R
EXTAL
XTAL
Resonator
DEVICE
XTAL
DEVICE
Figure 10. Crystal oscillator and resonator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
Table 30. Crystal description
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
xtalin/xtalout
C1 = C2
(pF)1
Shunt
capacitance
between
xtalout
and xtalin
C02 (pF)
Nominal
frequency
(MHz)
NDK crystal
reference
Crystal
equivalent
series
resistance
ESR Ω
4
NX8045GB
300
2.68
591.0
21
2.93
8
NX5032GA
300
2.46
160.7
17
3.01
10
150
2.93
86.6
15
2.91
12
120
3.11
56.5
15
2.93
16
120
3.90
25.3
10
3.00
1
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing
includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2 The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,
package, etc.).
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
43
Preliminary—Subject to Change Without Notice
Electrical characteristics
S_MTRANS bit (ME_GS register)
0
VXTAL
1/fMXOSC
VMXOSC
90%
VMXOSCOP
10%
TMXOSCSU
valid internal clock
Figure 11. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Table 31. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Symbol
C
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
fFXOSC
SR — Fast external crystal
oscillator frequency
—
4.0
—
16.0
MHz
gmFXOSC
CC C Fast external crystal
oscillator
transconductance
VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 0
2.2
—
8.2
mA/V
CC P
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 0
2.0
—
7.4
CC C
VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 1
2.7
—
9.7
CC C
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 1
2.5
—
9.2
CC T Oscillation amplitude at
EXTAL
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
1.3
—
—
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
1.3
—
—
—
—
0.95
—
—
2
VFXOSC
VFXOSCOP CC P Oscillation operating point
IFXOSC,3
CC T Fast external crystal
oscillator consumption
V
V
3
mA
MPC5607B Microcontroller Data Sheet, Rev. 3
44
Freescale Semiconductor
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1
Electrical characteristics
Table 31. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued)
TFXOSCSU
C
Parameter
CC T Fast external crystal
oscillator start-up time
Conditions
Unit
Min
Typ
Max
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
—
—
6
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
—
—
1.8
ms
VIH
SR P Input high level CMOS
(Schmitt Trigger)
Oscillator bypass mode
0.65VDD
—
VDD+0.4
V
VIL
SR P Input low level CMOS
(Schmitt Trigger)
Oscillator bypass mode
−0.4
—
0.35VDD
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 Stated values take into account only analog module consumption but not the digital contributor (clock tree and
enabled peripherals)
1
2
3.13
Slow external crystal oscillator (32 kHz) electrical characteristics
The device provides a low power oscillator/resonator driver.
OSC32K_EXTAL
OSC32K_EXTAL
Resonator
Crystal
C1
RP
OSC32K_XTAL
DEVICE
OSC32K_XTAL
C2
DEVICE
Figure 12. Crystal oscillator and resonator connection scheme
NOTE
OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
45
Preliminary—Subject to Change Without Notice
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Symbol
Value2
1
Electrical characteristics
l
C1
Crystal
Cm
C2
Rm
Lm
C1
C2
Figure 13. Equivalent circuit of a quartz crystal
Table 32. Crystal motional characteristics1
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
Lm
Motional inductance
—
—
11.796
—
KH
Cm
Motional capacitance
—
—
2
—
fF
—
18
—
28
pF
kW
C1/C2 Load capacitance at OSC32K_XTAL and
OSC32K_EXTAL with respect to ground2
Rm3
Motional resistance
AC coupled @ C0 = 2.85 pF4
—
—
65
AC coupled @ C0 = 4.9
pF4
—
—
50
AC coupled @ C0 = 7.0
pF4
—
—
35
AC coupled @ C0 = 9.0 pF4
—
—
30
1
The crystal used is Epson Toyocom MC306.
This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to
ground. It includes all the parasitics due to board traces, crystal and package.
3 Maximum ESR (R ) of the crystal is 50 kΩ
m
4
C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins
2
MPC5607B Microcontroller Data Sheet, Rev. 3
46
Freescale Semiconductor
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C0
Electrical characteristics
OSCON bit (OSC_CTL register)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
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1
0
VOSC32K_XTAL
1/fLPXOSC32K
VLPXOSC32K
90%
10%
TLPXOSC32KSU
valid internal clock
Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics
Table 33. Slow external crystal oscillator (32 kHz) electrical characteristics
Symbol
C
Parameter
fSXOSC
SR — Slow external crystal oscillator
frequency
gmSXOSC
CC — Slow external crystal oscillator
transconductance
VSXOSC
CC T Oscillation amplitude
ISXOSCBIAS CC T Oscillation bias current
Value2
Conditions1
—
Unit
Min
Typ
Max
32
32.768
40
VDD = 3.3 V ± 10%,
PAD3V5V = 1
TBD
VDD = 5.0 V ± 10%
PAD3V5V = 0
TBD
VDD = 3.3 V ± 10%,
PAD3V5V = 1
TBD
VDD = 5.0 V ± 10%,
PAD3V5V = 0
TBD
—
—
—
2.1
kHz
mA/V
—
TBD
V
µA
ISXOSC
CC T Slow external crystal oscillator
consumption
—
—
—
8
µA
TSXOSCSU
CC T Slow external crystal oscillator
start-up time
—
—
—
23
s
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal
1
2
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
47
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.14
FMPLL electrical characteristics
Table 34. FMPLL electrical characteristics
Symbol
C
Value2
1
Parameter
Conditions
Unit
Min
Typ
Max
fPLLIN
SR — FMPLL reference clock3
—
4
—
64
MHz
ΔPLLIN
SR — FMPLL reference clock duty
cycle3
—
40
—
60
%
—
16
—
64
MHz
fPLLOUT CC P FMPLL output clock frequency
fCPU
SR — System clock frequency
—
—
—
644
MHz
fFREE
CC P Free-running frequency
—
20
—
150
MHz
tLOCK
CC P FMPLL lock time
40
100
µs
ΔtLTJIT CC — FMPLL long term jitter
IPLL
CC C FMPLL consumption
Stable oscillator (fPLLIN = 16 MHz)
fPLLIN = 16 MHz (resonator),
fPLLCLK @ 64 MHz, 4000 cycles
—
—
10
ns
TA = 25 °C
—
—
4
mA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
All values need to be confirmed during device validation.
3 PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN.
4 f
CPU 64 MHz can be achieved only at up to 105 °C
1
2
3.15
Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz main internal RC oscillator. This is used as the default clock at the power-up of the device.
Table 35. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol
Parameter
CC P Fast internal RC oscillator high TA = 25 °C, trimmed
frequency
SR —
—
fFIRC
IFIRCRUN
C
3,
IFIRCPWD
Value2
Conditions1
Unit
Min
Typ
Max
—
16
—
12
MHz
20
CC T Fast internal RC oscillator high TA = 25 °C, trimmed
frequency current in running
mode
—
—
200
µA
CC D Fast internal RC oscillator high TA = 25 °C
frequency current in power
—
TA = 55 °C
down mode
—
TBD
10
µA
—
TBD
TBD
MPC5607B Microcontroller Data Sheet, Rev. 3
48
Freescale Semiconductor
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The device provides a frequency modulated phase locked loop (FMPLL) module to generate a fast system clock from the main
oscillator driver.
Electrical characteristics
Table 35. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
C
Parameter
Conditions
Typ
Max
sysclk = off
—
500
—
sysclk = 2 MHz
—
600
—
sysclk = 4 MHz
—
700
—
sysclk = 8 MHz
—
900
—
sysclk = 16 MHz
—
1250
—
VDD = 5.0 V ± 10%
—
1.1
2.0
VDD = 3.3 V ± 10%
—
1.2
TBD
—
TA = 125 °C VDD = 5.0 V ± 10%
—
—
2.0
—
VDD = 3.3 V ± 10%
—
—
TBD
+1
IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 °C
frequency and system clock
current in stop mode
TFIRCSU
Unit
Min
CC C Fast internal RC oscillator
start-up time
—
TA = 55 °C
CC C Fast internal RC oscillator
precision after software
trimming of fFIRC
TA = 25 °C
−1
—
ΔFIRCTRIM CC C Fast internal RC oscillator
trimming step
TA = 25 °C
—
1.6
−5
—
ΔFIRCPRE
ΔFIRCVAR
CC C Fast internal RC oscillator
variation over temperature and
supply with respect to fFIRC at
TA = 25 °C in high-frequency
configuration
—
µA
µs
%
%
+5
%
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
All values need to be confirmed during device validation.
3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
1
2
3.16
Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz low power internal RC oscillator. This can be used as the reference clock for the RTC module.
Table 36. Slow internal RC oscillator (128 kHz) electrical characteristics
Symbol
fSIRC
ISIRC3,
C
Parameter
Value2
Conditions1
CC P Slow internal RC oscillator low
frequency
SR —
TA = 25 °C, trimmed
CC C Slow internal RC oscillator low
frequency current
TA = 25 °C, trimmed
—
Unit
Min
Typ
Max
—
128
—
100
—
150
—
—
5
kHz
µA
MPC5607B Microcontroller Data Sheet, Rev. 3
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Symbol
Value2
1
Electrical characteristics
Table 36. Slow internal RC oscillator (128 kHz) electrical characteristics (continued)
C
Parameter
Conditions
Unit
Min
Typ
Max
TSIRCSU
CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ± 10%
time
—
8
12
µs
ΔSIRCPRE
CC C Slow internal RC oscillator precision TA = 25 °C
after software trimming of fSIRC
−2
—
+2
%
ΔSIRCTRIM
CC C Slow internal RC oscillator trimming
step
—
2.7
—
ΔSIRCVAR
CC C Slow internal RC oscillator variation High frequency configuration
in temperature and supply with
respect to fSIRC at TA = 55 °C in high
frequency configuration
−10
—
+10
—
%
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
All values need to be confirmed during device validation.
3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
1
2
3.17
3.17.1
ADC electrical characteristics
Introduction
The device provides two Successive Approximation Register (SAR) analog-to-digital converters (10-bit and 12-bit).
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Symbol
Value2
1
Electrical characteristics
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
5
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error OSE
Figure 15. ADC0 characteristic and error definitions
3.17.2
Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources
charge during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
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Offset Error OSE
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 kΩ is obtained (REQ
= 1 / (fc*CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage
partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit
must be designed to respect the Equation 4:
Eqn. 4
R S + R F + R L + R SW + R AD
1
V A • --------------------------------------------------------------------------- < --- LSB
R EQ
2
Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW
and RAD) can be neglected with respect to external resistances.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
VA
Filter
RF
Current Limiter
RL
CF
Channel
Selection
Sampling
RSW1
RAD
CP1
CP2
CS
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
Current Limiter Resistance
RL
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
Figure 16. Input equivalent circuit (precise channels)
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Electrical characteristics
Electrical characteristics
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
Filter
RF
VA
Current Limiter
RL
CF
RS
RF
CF
RL
RSW
RAD
CP
CS
CP1
Channel
Selection
Extended
Switch
Sampling
RSW1
RSW2
RAD
CP3
CP2
CS
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance (two contributions RSW1 and RSW2)
Sampling Switch Impedance
Pin Capacitance (three contributions, CP1, CP2 and CP3)
Sampling Capacitance
Figure 17. Input equivalent circuit (extended channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are
initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 16): A charge sharing phenomenon
is installed when the sampling phase is started (A/D switch close).
Voltage Transient on CS
VCS
VA
VA2
ΔV < 0.5 LSB
1
2
τ1 < (RSW + RAD) CS << TS
τ2 = RL (CS + CP1 + CP2)
VA1
TS
t
Figure 18. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
1.
A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series,
and the time constant is
MPC5607B Microcontroller Data Sheet, Rev. 3
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EXTERNAL CIRCUIT
Electrical characteristics
Eqn. 5
Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS
is always much longer than the internal time constant:
Eqn. 6
τ 1 < ( R SW + R AD ) • C S « T S
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance
according to Equation 7:
Eqn. 7
V A1 • ( C S + C P1 + C P2 ) = V A • ( C P1 + C P2 )
2.
A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance
RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality
would be faster), the time constant is:
Eqn. 8
τ 2 < R L • ( C S + C P1 + C P2 )
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time TS, a constraints on RL sizing is obtained:
Eqn. 9
10 • τ 2 = 10 • R L • ( C S + C P1 + C P2 ) < TS
Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source
impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2
(at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge
balance assuming now CS already charged at VA1):
Eqn. 10
VA2 • ( C S + C P1 + C P2 + C F ) = V A • C F + V A1 • ( C P1 + C P2 + C S )
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to
provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of
the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
MPC5607B Microcontroller Data Sheet, Rev. 3
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CP • CS
τ 1 = ( R SW + R AD ) • --------------------CP + CS
Electrical characteristics
Analog source bandwidth (VA)
Noise
fF = f0 (Anti-aliasing filtering condition)
2 f0 < fC (Nyquist)
f0
f
Anti-aliasing filter (fF = RC filter pole)
fF
f
Sampled signal spectrum (fC = Conversion rate)
f0
fC
f
Figure 19. Spectral representation of input signal
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF),
according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater
than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS,
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the
sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
voltage on CS:
Eqn. 11
VA
C P1 + C P2 + C F
----------- = ------------------------------------------------------V A2
C P1 + C P2 + C F + C S
From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of
half a count, a constraint is evident on CF value:
ADC0 (10-bit)
Eqn. 12
C F > 2048 • C S
ADC1 (12-bit)
Eqn. 13
C F > 8192 • C S
MPC5607B Microcontroller Data Sheet, Rev. 3
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TC < 2 RFCF (Conversion rate vs. filter pole)
Electrical characteristics
3.17.3
ADC electrical characteristics
Value
Symbol C
Parameter
Conditions
Unit
Min
Typ
Max
—
1
—
ILKG CC C Input leakage current TA = −40 °C No current injection on adjacent pin
nA
C
TA = 25 °C
—
1
—
C
TA = 105 °C
—
8
200
P
TA = 125 °C
—
45
400
Table 38. ADC conversion characteristics (10-bit ADC0)
Symbol
C
Paramete
r
Conditions1
Value
Unit
Min
Typ
Max
VSS_ADC0
SR
—
Voltage on
VSS_HV_
ADC0
(ADC0
reference)
pin with
respect to
ground
(VSS)2
—
−0.1
—
0.1
V
VDD_ADC0
SR
—
Voltage on
VDD_HV_
ADC pin
(ADC
reference)
with
respect to
ground
(VSS)
—
VDD−0.1
—
VDD+0.1
V
VAINx
SR
—
Analog
input
voltage3
—
VSS_ADC0
−0.1
—
VDD_ADC0
+0.1
V
fADC0
SR
—
ADC0
analog
frequency
—
6
—
32 + 4%
MHz
ΔADC0_SY
SR
—
ADC0
ADCLKSEL = 14
digital
clock duty
cycle
(ipg_clk)
45
—
55
%
SR
—
ADC0
power up
delay
—
—
1.5
µs
S
tADC0_PU
—
MPC5607B Microcontroller Data Sheet, Rev. 3
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Table 37. ADC input leakage current
Electrical characteristics
Table 38. ADC conversion characteristics (continued)(10-bit ADC0)
tADC0_S
C
CC
T
Paramete
r
Sample
time5
Value
Conditions1
fADC = 32 MHz,
ADC0_conf_sample_i
nput = 17
Unit
Min
Typ
0.5
—
fADC = 6 MHz,
INPSAMP = 255
tADC0_C
CC
P
Conversio fADC = 32 MHz,
n time6
ADC_conf_comp = 2
CS
CC
D
ADC0
input
sampling
capacitan
ce
CP1
CC
D
CP2
CC
CP3
—
Max
µs
42
0.625
—
—
—
—
3
pF
ADC0
input pin
capacitan
ce 1
—
—
—
3
pF
D
ADC0
input pin
capacitan
ce 2
—
—
—
1
pF
CC
D
ADC0
input pin
capacitan
ce 3
—
—
—
1
pF
RSW1
CC
D
Internal
resistance
of analog
source
—
—
—
3
kΩ
RSW2
CC
D
Internal
resistance
of analog
source
—
—
—
2
kΩ
RAD
CC
D
Internal
resistance
of analog
source
—
—
—
2
kΩ
IINJ
SR
—
Input
current
Injection
VDD =
3.3 V ±
10%
−5
—
5
mA
VDD =
5.0 V ±
10%
−5
—
5
Current
injection
on one
ADC0
input,
different
from the
converted
one
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Symbol
µs
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
57
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 38. ADC conversion characteristics (continued)(10-bit ADC0)
C
4
5
6
7
Typ
Max
T
Absolute No overload
value for
integral
non-linear
ity
—
0.5
1.5
LSB
| DNL |
CC
T
Absolute No overload
differential
non-linear
ity
—
0.5
1.0
LSB
| OFS |
CC
T
Absolute
offset
error
—
—
0.5
—
LSB
| GNE |
CC
T
Absolute
gain error
—
—
0.6
—
LSB
TUEP
CC
P
Total
Without current
unadjuste injection
d error7 for
With current injection
precise
channels,
input only
pins
−2
0.6
2
LSB
Total
Without current
unadjuste injection
d error7 for
With current injection
extended
channel
−3
CC
T
T
3
Unit
Min
CC
TUEX
2
Value
Conditions1
| INL |
T
1
Paramete
r
−3
−4
3
1
3
LSB
4
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured
by internal divider by 2.
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the
end of the sample time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC0_S depend on programming.
This parameter does not include the sample time tADC0_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
MPC5607B Microcontroller Data Sheet, Rev. 3
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Symbol
Electrical characteristics
Offset Error OSE
Gain Error GE
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4095
4094
4093
4092
4091
1 LSB ideal = AVDD / 4096
4090
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
5
(5)
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)
Offset Error OSE
Figure 20. ADC1 characteristic and error definitions
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
59
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 39. Conversion characteristics (12-bit ADC1)
Parameter
Value
Conditions1
Unit
Min
Typ
Max
VSS_ADC1
SR
Voltage on
VSS_HV_A
DC1 (ADC1
reference)
pin with
respect to
ground
(VSS)2
—
-0.1
0.1
V
VDD_ADC1
SR
Voltage on
VDD_HV_
ADC1 pin
(ADC1
reference)
with
respect to
ground
(VSS)
—
VDD-0.1
VDD+0.1
V
VAINx
SR
Analog
input
voltage3
—
VSS_ADC1-0
.1
VDD_ADC1+
0.1
V
fADC1
SR
ADC1
analog
frequency
—
32 + 3%
tADC1_PU
SR
ADC1
power up
delay
—
tADC1_S
CC
fADC1= 32 MHz,
Sample
time4
ADC1_conf_sample_inp
VDD=3.3 V ut = 20
600
Sample
time4
VDD =5.0 V
fADC1= 32 MHz,
ADC1_conf_sample_inp
ut = 17
500
Sample
time4
VDD=3.3 V
fADC1= 3.33 MHz,
ADC1_conf_sample_inp
ut = 255
76.2
fADC1= 3.33 MHz,
Sample
time4
ADC1_conf_sample_inp
VDD =5.0 V ut = 255
76.2
32 + 4%
MHz
1.5
µs
ns
µs
MPC5607B Microcontroller Data Sheet, Rev. 3
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Symbol
Electrical characteristics
Table 39. Conversion characteristics (12-bit ADC1) (continued)
Parameter
Value
Conditions1
Unit
Min
tADC1_C
CC
Typ
Max
Conversion fADC1 = 20MHz,
time5
ADC1_conf_comp = 0
VDD=3.3 V
2.4
µs
Conversion fADC 1= 13.33 MHz,
time5
ADC1_conf_comp = 0
VDD =5.0 V
1.5
µs
Conversion fADC 1= 13.33 MHz,
time5
ADC1_conf_comp = 0
VDD=3.3 V
3.6
µs
Conversion fADC1 = 32 MHz,
time5
ADC1_conf_comp = 0
VDD =5.0 V
3.6
µs
ΔADC0_SYS
SR
ADC1
ADCLKSEL = 16
digital clock
duty cycle
(ipg_clk)
CS
CC
ADC1 input
sampling
capacitanc
e
—
5
pF
CP1
CC
ADC1 input
pin
capacitanc
e1
—
3
pF
CP2
CC
ADC1 input
pin
capacitanc
e2
—
1
pF
CP3
CC
ADC1 input
pin
capacitanc
e3
—
1.5
pF
RSW1
CC
Internal
resistance
of analog
source
—
1
kΩ
RSW2
CC
Internal
resistance
of analog
source
—
2
kΩ
RAD
CC
Internal
resistance
of analog
source
—
0.3
kΩ
45
—
55
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Symbol
%
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
61
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 39. Conversion characteristics (12-bit ADC1) (continued)
IINJ
Parameter
SR
Input
current
Injection
Value
Conditions1
Current
injection on
one ADC1
input,
different
from the
converted
one
Unit
Min
Typ
Max
VDD = 3.3 V
± 10%
-5
—
5
VDD = 5.0 V
± 10%
-5
—
5
mA
INLP
CC
Absolute
No overload
Integral
non-linearit
y-Precise
channels
1
3
LSB
INLX
CC
Absolute
No overload
Integral
non-linearit
y-Extended
channels
1.5
5
LSB
DNL
CC
Absolute
No overload
Differential
non-linearit
y
0.5
1
LSB
OFS
CC
Absolute
Offset error
—
2
LSB
GNE
CC
Absolute
Gain error
—
2
LSB
TUEP7
CC
Total
Unadjusted
Without current injection
Error for
precise
With current injection
channels,
input only
pins
TUEX7
CC
Total
Unadjusted
Without current injection
Error for
extended
With current injection
channel
-6
6
-8
8
-10
10
LSB
-12
12
LSB
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 / 125 °C, unless otherwise specified.
Analog and digital VSS must be common (to be tied together externally).
3 V
AINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
4 During the sample time the input capacitance C can be charged/discharged by the external source. The internal
S
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the
end of the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC1_S depend on programming.
2
MPC5607B Microcontroller Data Sheet, Rev. 3
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Symbol
Electrical characteristics
5
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This parameter does not include the sample time tADC1_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
6
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured
by internal divider by 2.
7
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
63
Preliminary—Subject to Change Without Notice
Electrical characteristics
On-chip peripherals
3.18.1
Current consumption
Table 40. On-chip peripherals current consumption1
Value
Symbol
C
Parameter
Conditions
Unit
Min
IDD_BV(CAN
CC
T
)
IDD_BV(eMI
CC
T
OS)
500 Kbps
CAN
(FlexCAN)
125 Kbps
supply
current on
VDD_BV
Total (static
+ dynamic)
consumpti
on:
• FlexCAN
in
loop-ba
ck mode
• XTAL@8
MHz
used as
CAN
engine
clock
source
• Message
sending
period is
580 µs
Typ
Max
7.652 * fperiph + 84.73
µA
8.0743 * fperiph + 26.757
eMIOS
Static consumption:
supply
• eMIOS channel OFF
current on • Global prescaler
VDD_BV
enabled
28.7 * fperiph
Dynamic consumption:
• It does not change
varying the
frequency (0.003
mA)
3
IDD_BV(SCI)
CC
T
SCI
Total (static + dynamic)
(LINFlex) consumption:
supply
• LIN mode
current on • Baudrate: 20 Kbps
VDD_BV
4.7804 * fperiph + 30.946
IDD_BV(SPI)
CC
T
SPI (DSPI) Ballast static
consumption (only
supply
current on clocked)
VDD_BV
Ballast dynamic
consumption
(continuus
communication):
• Baudrate: 2 Mbit
• Trasmission every 8
µs
• Frame: 16 bits
1
16.3 * fperiph
MPC5607B Microcontroller Data Sheet, Rev. 3
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3.18
Electrical characteristics
Table 40. On-chip peripherals current consumption1 (continued)
Value
C
Parameter
Conditions
Unit
Min
IDD_BV(ADC
CC
T
)
IDD_HV_AD
CC
T
C(ADC)
IDD_HV(FLA
CC
T
SH)
Typ
Max
VDD = 5.5
V
Ballast
static
consumpti
on (no
conversion
)
0.0409 * fperiph
VDD = 5.5
V
Ballast
dynamic
consumpti
on
(continuus
conversion
)
0.0049 * fperiph
VDD = 5.5
ADC
Analog
supply
V
static
consumpti
current on
on (no
VDD_HV_AD
conversion
C
)
0.0017 * fperiph
VDD = 5.5
V
Analog
dynamic
consumpti
on
(continuus
conversion
)
0.075 * fperiph + 0.032
-
13.25
-
0.0031 * fperiph
ADC
supply
current on
VDD_BV
CFlash +
VDD = 5.5
DFlash
V
supply
current on
VDD_HV_AD
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Symbol
mA
C
IDD_HV(PLL)
1
CC
T
PLL supply VDD = 5.5
current on
V
VDD_HV
Operating conditions: TA = 25 °C, fperiph = 8 MHz to 64 MHz
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
65
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.18.2
DSPI characteristics
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tSCK
SR
D
SCK cycle time
64
—
—
ns
—
fDSPI
SR
D
DSPI digital controller
frequency
—
—
fCPU
MHz
—
ΔtCSC
CC
D
Internal delay
between pad
associated to SCK
and pad associated to
CSn in master mode
—
—
1201
ns
2
tCSCext2
CC
D
CS to
Master
SCK delay mode
SR
D
CC
D
SR
D
CC
D
SR
D
3
4
tASCext3
tSDC
Slave
mode
After SCK Master
delay
mode
Slave
mode
SCK duty Master
cycle
mode
Slave
mode
tCSCext = tCSC + ΔtCSC
32
—
ns
—
tASCext = tASC + ΔtCSC
ns
1/fDSPI + 5
ns
—
—
ns
—
tSCK/2
—
ns
tSCK/2
—
—
5
tA
SR
D
Slave
access
time
—
27
—
—
ns
6
tDI
SR
D
Slave
SOUT
disable
time
—
0
—
—
ns
7
tSUI
SR
D
Data
Master
setup time (MTFE =
for inputs 0)
35
—
—
ns
Slave
5
—
—
Master
(MTFE =
1)
35
—
—
Data hold Master
time for
(MTFE =
inputs
0)
0
—
—
Slave
24
—
—
Master
(MTFE =
1)
0
—
—
8
tHI
SR
D
ns
MPC5607B Microcontroller Data Sheet, Rev. 3
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Table 41. DSPI characteristics
Electrical characteristics
Table 41. DSPI characteristics (continued)
Value
9
10
Symbol
tSUO5
tHO5
C
CC
CC
D
D
Parameter
Unit
Min
Typ
Max
—
—
32
Slave
—
—
34
Master
(MTFE =
1)
—
—
32
Data hold Master
time for
(MTFE =
outputs
0)
2
—
—
5.5
—
—
2
—
—
Data valid Master
after SCK (MTFE =
edge
0)
Slave
Master
(MTFE =
1)
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No.
ns
ns
1
Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad.
The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields
in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than ΔtCSC to ensure
positive tCSCext.
3 The t
ASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in
DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than ΔtASC to ensure positive
tASCext.
4 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.
5 SCK and SOUT configured as MEDIUM pad
2
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
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Preliminary—Subject to Change Without Notice
Electrical characteristics
Figure 21. DSPI classic SPI timing - master, CPHA = 0
2
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3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
SIN
First Data
Last Data
Data
12
SOUT
First Data
11
Data
Last Data
Note: Numbers shown reference Table 41.
Figure 22. DSPI classic SPI timing - master, CPHA = 1
PCSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
SIN
Data
First Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Note: Numbers shown reference Table 41.
MPC5607B Microcontroller Data Sheet, Rev. 3
68
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Preliminary—Subject to Change Without Notice
Electrical characteristics
Figure 23. DSPI classic SPI timing - slave, CPHA = 0
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3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
First Data
SOUT
9
6
Data
Last Data
Data
Last Data
10
First Data
SIN
11
12
Note: Numbers shown reference Table 41.
Figure 24. DSPI classic SPI timing - slave, CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 41.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
69
Preliminary—Subject to Change Without Notice
Electrical characteristics
Figure 25. DSPI modified transfer format timing - master, CPHA = 0
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
SIN
10
First Data
Last Data
Data
12
SOUT
11
First Data
Last Data
Data
Note: Numbers shown reference Table 41.
Figure 26. DSPI modified transfer format timing - master, CPHA = 1
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
First Data
Data
12
SOUT
First Data
Data
Last Data
11
Last Data
Note: Numbers shown reference Table 41.
MPC5607B Microcontroller Data Sheet, Rev. 3
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3
PCSx
Electrical characteristics
Figure 27. DSPI modified transfer format timing - slave, CPHA = 0
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3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
First Data
SOUT
Data
6
Last Data
10
9
Data
First Data
SIN
12
11
5
Last Data
Note: Numbers shown reference Table 41.
Figure 28. DSPI modified transfer format timing - slave, CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
12
First Data
SOUT
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 41.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
71
Preliminary—Subject to Change Without Notice
7
PCSS
PCSx
Note: Numbers shown reference Table 41.
MPC5607B Microcontroller Data Sheet, Rev. 3
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Electrical characteristics
Figure 29. DSPI PCS strobe (PCSS) timing
8
Freescale Semiconductor
Electrical characteristics
3.18.3
Nexus characteristics
Table 42. Nexus characteristics
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tTCYC
CC D TCK cycle time
64
—
—
ns
2
tMCYC
CC D MCKO cycle time
32
—
—
ns
3
tMDOV
CC D MCKO low to MDO data valid
—
—
8
ns
4
tMSEOV
CC D MCKO low to MSEO_b data valid
—
—
8
ns
5
tEVTOV
CC D MCKO low to EVTO data valid
—
—
8
ns
6
tNTDIS
CC D TDI data setup time
15
—
—
ns
tNTMSS
CC D TMS data setup time
15
—
—
ns
tNTDIH
CC D TDI data hold time
5
—
—
ns
tNTMSH
CC D TMS data hold time
5
—
—
ns
7
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Value
No.
8
tTDOV
CC D TCK low to TDO data valid
35
—
—
ns
9
tTDOI
CC D TCK low to TDO data invalid
6
—
—
ns
Figure 30. Nexus TDI, TMS, TDO timing
TCK
10
11
TMS, TDI
12
TDO
Note: Numbers shown reference Table 42.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
73
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.18.4
JTAG characteristics
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tJCYC
CC
D TCK cycle time
64
—
—
ns
2
tTDIS
CC
D TDI setup time
15
—
—
ns
3
tTDIH
CC
D TDI hold time
5
—
—
ns
4
tTMSS
CC
D TMS setup time
15
—
—
ns
5
tTMSH
CC
D TMS hold time
5
—
—
ns
6
tTDOV
CC
D TCK low to TDO valid
—
33
ns
7
tTDOI
CC
D TCK low to TDO invalid
—
—
ns
6
Figure 31. Timing diagram - JTAG boundary scan
TCK
2/4
DATA INPUTS
3/5
INPUT DATA VALID
6
DATA OUTPUTS
OUTPUT DATA VALID
7
DATA OUTPUTS
Note: Numbers shown reference Table 43.
MPC5607B Microcontroller Data Sheet, Rev. 3
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Table 43. JTAG characteristics
4
Package characteristics
4.1
Package mechanical data
4.1.1
176 LQFP
Figure 32. 176 LQFP package mechanical drawing (Part 1 of 3)
MPC5607B Microcontroller Data Sheet, Rev. 3
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Package characteristics
75
Figure 33. 176 LQFP package mechanical drawing (Part 2 of 3)
MPC5607B Microcontroller Data Sheet, Rev. 3
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Package characteristics
Freescale Semiconductor
Figure 34. 176 LQFP package mechanical drawing (Part 3 of 3)
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
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Package characteristics
77
Package characteristics
Table 44. LQFP176 mechanical data1
inches2
mm
Min
Typ
Max
Min
Typ
Max
A
1.400
1.600
A1
0.050
0.150
0.002
A2
1.350
1.450
0.053
0.057
b
0.170
0.270
0.007
0.011
C
0.090
0.200
0.004
0.008
D
23.900
24.100
0.941
0.949
E
23.900
24.100
0.941
0.949
e
0.063
0.500
0.020
HD
25.900
26.100
1.020
1.028
HE
25.900
26.100
1.020
1.028
0.450
0.750
0.018
0.030
3
L
L1
1.000
0.039
ZD
1.250
0.049
ZE
1.250
0.049
q
0°
7°
0°
7°
Tolerance
mm
inches
ccc
0.080
0.0031
1
Controlling dimension: millimeter
Values in inches are converted from mm and rounded to 4 decimal digits.
3
L dimension is measured at gauge plane at 0.25 mm above the seating plane
2
MPC5607B Microcontroller Data Sheet, Rev. 3
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Symbol
4.1.2
Figure 35. 144 LQFP package mechanical drawing (Part 1 of 2)
MPC5607B Microcontroller Data Sheet, Rev. 3
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Package characteristics
144 LQFP
79
Figure 36. 144 LQFP package mechanical drawing (Part 2 of 2)
MPC5607B Microcontroller Data Sheet, Rev. 3
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Package characteristics
Freescale Semiconductor
Package characteristics
Table 45. LQFP144 mechanical data
inches1
mm
Min
Typ
A
Min
Typ
1.600
A1
0.050
A2
1.350
b
0.170
c
0.090
D
21.800
D1
19.800
D3
Max
0.0630
0.150
0.0020
1.400
1.450
0.0531
0.0551
0.0571
0.220
0.270
0.0067
0.0087
0.0106
0.200
0.0035
22.000
22.200
0.8583
0.8661
0.8740
20.000
20.200
0.7795
0.7874
0.7953
17.500
0.0059
0.0079
0.6890
E
21.800
22.000
22.200
0.8583
0.8661
0.8740
E1
19.800
20.000
20.200
0.7795
0.7874
0.7953
E3
17.500
0.6890
e
0.500
0.0197
L
0.450
L1
k
1
Max
0.600
0.750
0.0177
1.000
0.0 °
3.5 °
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Symbol
0.0236
0.0295
0.0394
7.0°
3.5 °
0.0 °
Tolerance
mm
inches
ccc
0.080
0.0031
7.0 °
Values in inches are converted from mm and rounded to 4 decimal digits.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
81
Preliminary—Subject to Change Without Notice
4.1.3
Figure 37. 100 LQFP package mechanical drawing (Part 1 of 3)
MPC5607B Microcontroller Data Sheet, Rev. 3
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Package characteristics
100 LQFP
Freescale Semiconductor
Figure 38. 100 LQFP package mechanical drawing (Part 2 of 3)
MPC5607B Microcontroller Data Sheet, Rev. 3
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Package characteristics
83
Figure 39. 100 LQFP package mechanical drawing (Part 3 of 3)
MPC5607B Microcontroller Data Sheet, Rev. 3
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Package characteristics
Freescale Semiconductor
Package characteristics
Table 46. LQFP100 mechanical data
inches1
mm
Symbol
Typ
A
Min
Typ
1.600
A1
0.050
A2
1.350
b
0.170
c
0.090
D
15.800
D1
13.800
D3
Max
0.0630
0.150
0.0020
1.400
1.450
0.0531
0.0551
0.0571
0.220
0.270
0.0067
0.0087
0.0106
0.200
0.0035
16.000
16.200
0.6220
0.6299
0.6378
14.000
14.200
0.5433
0.5512
0.5591
12.000
0.0059
0.0079
0.4724
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
12.000
0.4724
e
0.500
0.0197
L
0.450
L1
k
1
Max
0.600
0.750
0.0177
1.000
0.0 °
3.5 °
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Min
0.0236
0.0295
0.0394
7.0 °
0.0 °
3.5 °
Tolerance
mm
inches
ccc
0.080
0.0031
7.0 °
Values in inches are converted from mm and rounded to 4 decimal digits.
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
85
Preliminary—Subject to Change Without Notice
4.1.4
Figure 40. 208 MAPBGA package mechanical drawing (Part 1 of 2)
MPC5607B Microcontroller Data Sheet, Rev. 3
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Package characteristics
208MAPBGA
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Package characteristics
Figure 41. 208 MAPBGA package mechanical drawing (Part 2 of 2)
Table 47. LBGA208 mechanical data
inches1
mm
Symbol
Notes
Min
Typ
A
A1
Max
Min
Typ
1.70
0.30
0.0669
1.085
0.0427
A3
0.30
0.0118
A4
0.80
0.50
2
0.0118
A2
b
Max
0.60
0.70
0.0315
0.0197
0.0236
0.0276
3
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
87
Preliminary—Subject to Change Without Notice
Package characteristics
Table 47. LBGA208 mechanical data (continued)
inches1
mm
D
Notes
Min
Typ
Max
Min
Typ
Max
16.80
17.00
17.20
0.6614
0.6693
0.6772
D1
E
15.00
16.80
17.00
0.5906
17.20
0.6614
0.6693
E1
15.00
0.5906
e
1.00
0.0394
F
1.00
0.0394
0.6772
ddd
0.20
0.0079
eee
0.25
0.0098
4
fff
0.10
0.0039
5
1
Values in inches are converted from mm and rounded to 4 decimal digits.
LBGA stands for Low profile Ball Grid Array.
- Low profile: The total profile height (Dim A) is measured from the seating plane to the top of the component
- The maximum total package height is calculated by the following methodology:
A2 Typ+A1 Typ +√ (A12+A32+A42 tolerance values)
- Low profile: 1.20mm < A < 1.70mm
3 The typical ball diameter before mounting is 0.60mm.
4 The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with
respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this
tolerance zone.
5 The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as
defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones.
2
MPC5607B Microcontroller Data Sheet, Rev. 3
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Symbol
Ordering information
5
Ordering information
Example code:
M
PC
56
0
7
B
E
M
LL
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Figure 42. Commercial product code structure
R
Qualification Status
PowerPC Core
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Optional fields
Temperature spec.
Package Code
R = Tape & Reel (blank if Tray)
Qualification Status
Flash Size (z0 core)
Temperature spec.
M = MC status
S = Auto qualified
P = PC status
5 = 768 KB
6 = 1024 KB
7 = 1.5 MB
C = –40° C to 85°C
V = –40° C to 105°C
M = –40° C to 125°C
Automotive Platform
Product
Package Code
56 = PPC in 90nm
57 = PPC in 65nm
B = Body
C = Gateway
LL = 100 LQFP
LQ = 144 LQFP
LU= 176 LQFP
1
208 MAPBGA available only as development package for Nexus2+
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
89
Preliminary—Subject to Change Without Notice
Revision history
6
Revision history
Table 48. Revision history
Revision
Date
Substantive changes
1
12-Jan-2009 Initial release
2
09 Nov-2009 Updated Features
-Replaced 27 IRQs in place of 23
-ADC features
-External Ballast resistor support conditions
-updated device summary-added 208 BGA details
-updated block diagram to include WKUP
-updated block diagram to include 5 ch ADC 12 -bit
-updated Block summary table
-updated LQFP 144, 176 and 100 pinouts. Applied new naming convention for ADC
signals as ADCx_P[x] and ADCx_S[x]
Section 1, “General description
-updated Bolero 1.5M device comparison table
-updated block diagram-aligned with 512k
-updated block summary-aligned with 512k
Section 2, “Package pinouts
-updated 100,144,176,208 packages according to cut2.0 changes
Added Section 3.5.1, “External ballast resistor recommendations
Added NVUSRO [WATCHDOG_EN] field description
updated Absolute maximum ratings
updated LQFP thermal characteristics
updated I/O supply segments
updated Voltage regulator capacitance connection
updated Low voltage monitor electrical characteristics
updated Low voltage power domain electrical characteristics
updated DC electrical characteristics
updated Program/Erase specifications
updated Conversion characteristics (10 bit ADC)
updated FMPLL electrical characteristics
updated Fast RC oscillator electrical characteristics-aligned with Bolero 512K
updated On-chip peripherals current consumption
updated ADC characteristics and error definitions diagram
updated ADC conversion characteristics (10 bit and 12 bit)
Added ADC characteristics and error definitions diagram for 12 bit ADC
3
25 Jan-2010 Updated Features
Updated block diagram to connect peripherals to pad I/O
Updated block summary to include ADC 12-bit
Updated 144, 176 and 100 pinouts to adjust format issues
Table 26 Flash module life-retention value changed from 1-5 to 5 yrs
Minor editing changes
MPC5607B Microcontroller Data Sheet, Rev. 3
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not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Table 48 summarizes revisions to this document.
Abbreviations
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Appendix A
Abbreviations
Table 49 lists abbreviations used but not defined elsewhere in this document.
Table 49. Abbreviations
Abbreviation
Meaning
CMOS
Complementary metal–oxide–semiconductor
CPHA
Clock phase
CPOL
Clock polarity
CS
EVTO
Peripheral chip select
Event out
LED
Light emitting diode
MCKO
Message clock out
MDO
Message data out
MSEO
Message start/end out
MTFE
Modified timing format enable
SCK
Serial communications clock
SOUT
Serial data out
TBD
To be defined
TCK
Test clock input
TDI
Test data input
TDO
Test data output
TMS
Test mode select
MPC5607B Microcontroller Data Sheet, Rev. 3
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MPC5607B
Rev. 3
01/2010
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
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