Freescale MPC8555PXAKF Powerquiccâ ¢ iii integrated communications processor hardware specification Datasheet

Freescale Semiconductor
MPC8555EEC
Rev. 4, 12/2006
Technical Data
MPC8555E PowerQUICC™ III
Integrated Communications Processor
Hardware Specifications
The MPC8555E integrates a PowerPC™ processor core
built on Power Architecture™ technology with system logic
required for networking, telecommunications, and wireless
infrastructure applications. The MPC8555E is a member of
the PowerQUICC™ III family of devices that combine
system-level support for industry-standard interfaces with
processors that implement the embedded category of the
Power Architecture technology. For functional
characteristics of the processor, refer to the MPC8555E
PowerQUICC™ III Integrated Communications Processor
Reference Manual.
To locate any published errata or updates for this document
refer to http://www.freescale.com or contact your Freescale
sales office.
© Freescale Semiconductor, Inc., 2004, 2004, 2006. All rights reserved.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ethernet: Three-Speed, MII Management . . . . . . . . . . 22
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . . 55
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
System Design Information . . . . . . . . . . . . . . . . . . . . . 77
Document Revision History . . . . . . . . . . . . . . . . . . . . 84
Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . 84
Overview
1
Overview
The following section provides a high-level overview of the MPC8555E features. Figure 1 shows the
major functional units within the MPC8555E.
DDR
SDRAM
DDR SDRAM Controller
I2C Controller
DUART
GPIO
32b
Local Bus Controller
IRQs
Programmable
Interrupt Controller
MIIs/RMIIs
TDMs
I/Os
Serial Interfaces
MPHY
UTOPIA
Time-Slot Assigner
CPM
FCC
FCC
SCC
SCC/USB
SCC
SMC
SMC
SPI
I2C
Security
Engine
e500
Coherency
Module
Serial
DMA
256 Kbyte
L2 Cache/
SRAM
Core Complex
Bus
e500 Core
32-Kbyte L1
I Cache
32-Kbyte L1
D Cache
64/32b PCI Controller
OCeaN
ROM
0/32b PCI Controller
I-Memory
DMA Controller
DPRAM
RISC
Engine
10/100/1000 MAC
Parallel I/O
Baud Rate
Generators
10/100/1000 MAC
MII, GMII, TBI,
RTBI, RGMIIs
Timers
CPM
Interrupt
Controller
Figure 1. MPC8555E Block Diagram
1.1
Key Features
The following lists an overview of the MPC8555E feature set.
• Embedded e500 Book E-compatible core
— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
— Dual-issue superscalar, 7-stage pipeline design
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
— Lockable L1 caches—entire cache or on a per-line basis
— Separate locking for instructions and data
— Single-precision floating-point operations
— Memory management unit especially designed for embedded applications
— Enhanced hardware and software debug support
— Dynamic power management
— Performance monitor facility
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Overview
•
•
Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
802.11i, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels, a Controller,
and a set of crypto Execution Units (EUs). The Execution Units are:
— Public Key Execution Unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048-bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511-bits
— Data Encryption Standard Execution Unit (DEU)
– DES, 3DES
– Two key (K1, K2) or Three Key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced Encryption Standard Unit (AESU)
– Implements the Rinjdael symmetric key cipher
– Key lengths of 128, 192, and 256 bits.Two key
– ECB, CBC, CCM, and Counter modes
— ARC Four execution unit (AFEU)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message Digest Execution Unit (MDEU)
– SHA with 160-bit or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Random Number Generator (RNG)
— 4 Crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes
High-performance RISC CPM operating at up to 333 MHz
— CPM software compatibility with previous PowerQUICC families
— One instruction per clock
— Executes code from internal ROM or instruction RAM
— 32-bit RISC architecture
— Tuned for communication environments: instruction set supports CRC computation and bit
manipulation.
— Internal timer
— Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and
virtual DMA channels for each peripheral controller
— Handles serial protocols and virtual DMA
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Overview
•
— Two full-duplex fast communications controllers (FCCs) that support the following protocols:
– ATM protocol through two UTOPIA level 2 interfaces
– IEEE802.3/Fast Ethernet (10/100)
– HDLC
– Totally transparent operation
— Three full-duplex serial communications controllers (SCCs) support the following protocols:
– High level/synchronous data link control (HDLC/SDLC)
– LocalTalk (HDLC-based local area network protocol)
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART (1x clock mode)
– Binary synchronous communication (BISYNC)
– Totally transparent operation
– QMC support, providing 64 channels per SCC using only one physical TDM interface
— Universal serial bus (USB) controller that is full/low-speed compliant (multiplexed on an SCC)
– USB host mode
– Supports USB slave mode
— Serial peripheral interface (SPI) support for master or slave
— I2C bus controller
— Two serial management controllers (SMCs) supporting:
– UART
– Transparent
– General-circuit interfaces (GCI)
— Time-slot assigner supports multiplexing of data from any of the SCCs and FCCs onto eight
time-division multiplexed (TDM) interfaces. The time-slot assigner supports the following
TDM formats:
– T1/CEPT lines
– T3/E3
– Pulse code modulation (PCM) highway interface
– ISDN primary rate
– Freescale interchip digital link (IDL)
– General circuit interface (GCI)
— User-defined interfaces
— Eight independent baud rate generators (BRGs)
— Four general-purpose 16-bit timers or two 32-bit timers
— General-purpose parallel ports—16 parallel I/O lines with interrupt capability
256 Kbytes of on-chip memory
— Can act as a 256-Kbyte level-2 cache
— Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Overview
—
—
—
—
—
•
•
•
Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM
Full ECC support on 64-bit boundary in both cache and SRAM modes
SRAM operation supports relocation and is byte-accessible
Cache mode supports instruction caching, data caching, or both
External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing)
— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
— Supports locking the entire cache or selected lines
– Individual line locks set and cleared through Book E instructions or by externally mastered
transactions
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately
— Read and write buffering for internal bus accesses
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 32-bit address space
— Inbound and outbound ATMUs map to larger external address spaces
– Three inbound windows plus a configuration window on PCI
– Four inbound windows
– Four outbound windows plus default translation for PCI
DDR memory controller
— Programmable timing supporting first generation DDR SDRAM
— 64-bit data interface, up to MHz data rate
— Four banks of memory supported, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
— Contiguous or discontiguous memory mapping
— Sleep mode support for self refresh DDR SDRAM
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL2 compatible I/O
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Overview
•
•
•
•
•
— Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
— Four global high resolution timers/counters that can generate interrupts
— Supports additional internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs
— Interrupt summary registers allow fast identification of interrupt source
Two I2C controllers (one is contained within the CPM, the other is a stand-alone controller which
is not part of the CPM)
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
— Optionally loads configuration data from serial ROM at reset via the stand-alone I2C interface
— Can be used to initialize configuration registers and/or memory
— Supports extended I2C addressing mode
— Data integrity checked with preamble signature and CRC
DUART
— Two 4-wire interfaces (RXD, TXD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 166 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Two Three-speed (10/100/1000)Ethernet controllers (TSECs)
— Dual IEEE 802.3, 802.3u, 802.3x, 802.3z AC compliant controllers
— Support for Ethernet physical interfaces:
– 10/100/1000 Mbps IEEE 802.3 GMII
– 10/100 Mbps IEEE 802.3 MII
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Overview
•
•
– 10 Mbps IEEE 802.3 MII
– 1000 Mbps IEEE 802.3z TBI
– 10/100/1000 Mbps RGMII/RTBI
— Full- and half-duplex support
— Buffer descriptors are backwards compatible with MPC8260 and MPC860T 10/100
programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— 2-Kbyte internal transmit and receive FIFOs
— MII management interface for control and status
— Programmable CRC generation and checking
OCeaN switch fabric
— Three-port crossbar packet switch
— Reorders packets from a source based on priorities
— Reorders packets to bypass blocked packets
— Implements starvation avoidance algorithms
— Supports packets with payloads of up to 256 bytes
Integrated DMA controller
— Four-channel controller
— All channels accessible by both local and remote masters
— Extended DMA functions (advanced chaining and striding capability)
•
— Support for scatter and gather transfers
— Misaligned transfer capability
— Interrupt on completed segment, link, list, and error
— Supports transfers to or from any local memory or I/O port
— Selectable hardware-enforced coherency (snoop/no-snoop)
— Ability to start and flow control each DMA channel from external 3-pin interface
— Ability to launch DMA from single write transaction
PCI Controllers
— PCI 2.2 compatible
— One 64-bit or two 32-bit PCI ports supported at 16 to 66 MHz
— Host and agent mode support, 64-bit PCI port can be host or agent, if two 32-bit ports, only one
can be an agent
— 64-bit dual address cycle (DAC) support
— Supports PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses
— Supports posting of processor-to-PCI and PCI-to-memory writes
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Electrical Characteristics
•
•
— PCI 3.3-V compatible
— Selectable hardware-enforced coherency
— Selectable clock source (SYSCLK or independent PCI_CLK)
Power management
— Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O
— Supports power save modes: doze, nap, and sleep
— Employs dynamic power management
— Selectable clock source (sysclk or independent PCI_CLK)
System performance monitor
— Supports eight 32-bit counters that count the occurrence of selected events
— Ability to count up to 512 counter specific events
— Supports 64 reference events that can be counted on any of the 8 counters
— Supports duration and quantity threshold counting
•
•
•
2
— Burstiness feature that permits counting of burst events with a programmable time between
bursts
— Triggering and chaining capability
— Ability to generate an interrupt on overflow
System access port
— Uses JTAG interface and a TAP controller to access entire system memory map
— Supports 32-bit accesses to configuration registers
— Supports cache-line burst accesses to main memory
— Supports large block (4-Kbyte) uploads and downloads
— Supports continuous bit streaming of entire block for fast upload and download
IEEE 1149.1-compliant, JTAG boundary scan
783 FC-PBGA package
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8555E. The MPC8555E is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Electrical Characteristics
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings 1
Characteristic
Symbol
Max Value
Unit
Core supply voltage
VDD
–0.3 to 1.32
0.3 to 1.43 (for 1 GHz only)
V
PLL supply voltage
AVDD
–0.3 to 1.32
0.3 to 1.43 (for 1 GHz only)
V
DDR DRAM I/O voltage
GVDD
–0.3 to 3.63
V
Three-speed Ethernet I/O, MII management voltage
LVDD
–0.3 to 3.63
–0.3 to 2.75
V
CPM, PCI, local bus, DUART, system control and power
management, I2C, and JTAG I/O voltage
OVDD
–0.3 to 3.63
V
3
Input voltage
MVIN
–0.3 to (GVDD + 0.3)
V
2, 5
MVREF
–0.3 to (GVDD + 0.3)
V
2, 5
Three-speed Ethernet signals
LVIN
–0.3 to (LVDD + 0.3)
V
4, 5
CPM, Local bus, DUART,
SYSCLK, system control and
power management, I2C, and
JTAG signals
OVIN
–0.3 to (OVDD + 0.3)1
V
5
PCI
OVIN
–0.3 to (OVDD + 0.3)
V
6
TSTG
–55 to 150
•C
DDR DRAM signals
DDR DRAM reference
Storage temperature range
Notes
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 3.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Electrical Characteristics
2.1.2
Power Sequencing
The MPC8555Erequires its power rails to be applied in a specific sequence in order to ensure proper device
operation. These requirements are as follows for power up:
1. VDD, AVDDn
2. GVDD, LVDD, OVDD (I/O supplies)
Items on the same line have no ordering requirement with respect to one another. Items on separate lines
must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value
before the voltage rails on the current step reach ten percent of theirs.
NOTE
If the items on line 2 must precede items on line 1, please ensure that the
delay will not exceed 500 ms and the power sequence is not done greater
than once per day in production environment.
NOTE
From a system standpoint, if the I/O power supplies ramp prior to the VDD
core supply, the I/Os on the MPC8555E may drive a logic one or zero during
power-up.
2.1.3
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8555E. Note that the values in
Table 2 are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
Table 2. Recommended Operating Conditions
Characteristic
Symbol
Recommended Value
Unit
Core supply voltage
VDD
1.2 V ± 60 mV
1.3 V± 50 mV (for 1 GHz only)
V
PLL supply voltage
AVDD
1.2 V ± 60 mV
1.3 V ± 50 mV (for 1 GHz only)
V
DDR DRAM I/O voltage
GVDD
2.5 V ± 125 mV
V
Three-speed Ethernet I/O voltage
LVDD
3.3 V ± 165 mV
2.5 V ± 125 mV
V
PCI, local bus, DUART, system control and power management,
I2C, and JTAG I/O voltage
OVDD
3.3 V ± 165 mV
V
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Electrical Characteristics
Table 2. Recommended Operating Conditions (continued)
Characteristic
Input voltage
Symbol
Recommended Value
Unit
MVIN
GND to GVDD
V
MVREF
GND to GVDD
V
Three-speed Ethernet signals
LVIN
GND to LVDD
V
PCI, local bus, DUART,
SYSCLK, system control and
power management, I2C, and
JTAG signals
OVIN
GND to OVDD
V
Tj
0 to 105
°C
DDR DRAM signals
DDR DRAM reference
Die-junction Temperature
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8555E.
G/L/OVDD + 20%
G/L/OVDD + 5%
VIH
G/L/OVDD
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
of tSYS1
Note:
1. Note that tSYS refers to the clock period associated with the SYSCLK signal.
Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
The MPC8555E core voltage must always be provided at nominal 1.2 V (see Table 2 for actual
recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of
supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with
respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O
circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a
single-ended differential receiver referenced the externally supplied MVREF signal (nominally set to
GVDD/2) as is appropriate for the SSTL2 electrical signaling standard.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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11
Power Characteristics
2.1.4
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 3. Output Drive Capability
Driver Type
Programmable
Output Impedance
(Ω)
Supply
Voltage
Notes
25
OVDD = 3.3 V
1
Local bus interface utilities signals
42 (default)
PCI signals
25
2
42 (default)
DDR signal
20
GVDD = 2.5 V
TSEC/10/100 signals
42
LVDD = 2.5/3.3 V
DUART, system control, I2C, JTAG
42
OVDD = 3.3 V
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.
3
Power Characteristics
The estimated typical power dissipation for this family of PowerQUICC III devices is shown in Table 4.
Table 4. Power Dissipation(1) (2)
Typical Power(3)(4) Maximum Power(5)
(W)
(W)
CCB Frequency
(MHz)
Core Frequency
(MHz)
VDD
200
400
1.2
4.9
6.6
500
1.2
5.2
7.0
600
1.2
5.5
7.3
533
1.2
5.4
7.2
667
1.2
5.9
7.7
800
1.2
6.3
9.1
667
1.2
6.0
7.9
833
1.2
6.5
9.3
1000(6)
1.3
9.6
12.8
267
333
Notes:
1. The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Freescale Semiconductor
Power Characteristics
2. Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power
dissipation of other components on the board, and board thermal resistance. Any customer
design must take these considerations into account to ensure the maximum 105 degrees
junction temperature is not exceeded on this device.
3. Typical power is based on a nominal voltage of VDD = 1.2V, a nominal process, a junction
temperature of Tj = 105° C, and a Dhrystone 2.1 benchmark application.
4. Thermal solutions will likely need to design to a value higher than Typical Power based on
the end application, TA target, and I/O power
5. Maximum power is based on a nominal voltage of VDD = 1.2V, worst case process, a junction
temperature of Tj = 105° C, and an artificial smoke test.
6. The nominal recommended VDD = 1.3V for this speed grade.
Table 5. Typical I/O Power Dissipation
Interface
DDR I/O
PCI I/O
Local Bus I/O
TSEC I/O
Parameters
GVDD
(2.5V)
OVDD
(3.3V)
LVDD
(2.5V)
Unit
Comments
CCB = 200 MHz
0.46
W
—
CCB = 266 Mhz
0.59
W
—
CCB = 300 Mhz
0.66
W
—
CCB = 333 Mhz
0.73
W
—
64b, 66Mhz
0.14
W
—
64b, 33Mhz
0.08
W
—
32b, 66Mhz
0.07
W
Multiply by 2 if using two 32b ports
32b, 33Mhz
0.04
W
32b, 167Mhz
0.30
W
—
32b, 133Mhz
0.24
W
—
32b, 83Mhz
0.16
W
32b, 66Mhz
0.13
W
—
32b, 33Mhz
0.07
W
—
Multiply by number of interfaces
used.
MII
0.01
W
GMII or TBI
0.07
W
RGMII or RTBI
CPM - FCC
LVDD
(3.3V)
0.04
W
MII
0.015
W
—
RMII
0.013
W
—
HDLC 16 Mbps
0.009
W
—
UTOPIA-8 SPHY
0.06
W
—
UTOPIA-8 MPHY
0.1
W
—
UTOPIA-16 SPHY
0.094
W
—
UTOPIA-16 MPHY
0.135
W
—
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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13
Power Characteristics
Table 5. Typical I/O Power Dissipation (continued)
Interface
Parameters
GVDD
(2.5V)
OVDD
(3.3V)
LVDD
(3.3V)
LVDD
(2.5V)
Unit
Comments
CPM - SCC
HDLC 16 Mbps
0.004
W
—
TDMA or TDMB
Nibble Mode
0.01
W
—
TDMA or TDMB
Per Channel
0.005
W
Up to 4 TDM channels, multiply by
number of TDM channels.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
14
Freescale Semiconductor
Clock Timing
4
4.1
Clock Timing
System Clock Timing
Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8555E.
Table 6. SYSCLK AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
SYSCLK frequency
fSYSCLK
—
—
166
MHz
1
SYSCLK cycle time
tSYSCLK
6.0
—
—
ns
—
SYSCLK rise and fall time
tKH, tKL
0.6
1.0
1.2
ns
2
tKHK/tSYSCLK
40
—
60
%
3
—
—
—
+/- 150
ps
4, 5
SYSCLK duty cycle
SYSCLK jitter
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. For spread spectrum clocking, guidelines are +/-1% of the input frequency with a maximum of 60 kHz of modulation
regardless of the input frequency.
4.2
TSEC Gigabit Reference Clock Timing
Table 7 provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the
MPC8555E.
Table 7. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
EC_GTX_CLK125 frequency
fG125
—
125
—
MHz
EC_GTX_CLK125 cycle time
tG125
—
8
—
ns
EC_GTX_CLK125 rise time
tG125R
—
—
1.0
ns
1
EC_GTX_CLK125 fall time
tG125F
—
—
1.0
ns
1
%
1, 2
EC_GTX_CLK125 duty cycle
tG125H/tG125
GMII, TBI
RGMII, RTBI
—
45
47
Notes
55
53
Notes:
1. Timing is guaranteed by design and characterization.
2. EC_GTX_CLK125 is used to generate GTX clock for TSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle
can be loosened from 47/53% as long as PHY device can tolerate the duty cycle generated by GTX_CLK of TSEC.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
15
RESET Initialization
4.3
Real Time Clock Timing
Table 8 provides the real time clock (RTC) AC timing specifications.
Table 8. RTC AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
RTC clock high time
tRTCH
2x
tCCB_CLK
—
—
ns
RTC clock low time
tRTCL
2x
tCCB_CLK
—
—
ns
5
Notes
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8555E. Table 9 provides the RESET initialization AC timing specifications.
Table 9. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET
100
—
μs
Minimum assertion time for SRESET
512
—
SYSCLKs
PLL input setup time with stable SYSCLK before HRESET
negation
100
—
μs
Input setup time for POR configs (other than PLL config) with
respect to negation of HRESET
4
—
SYSCLKs
1
Input hold time for POR configs (including PLL config) with
respect to negation of HRESET
2
—
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR
configs with respect to negation of HRESET
—
5
SYSCLKs
1
1
Notes:
1. SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8555E. See the MPC8555E
PowerQUICC™ III Integrated Communications Processor Reference Manual for more details.
Table 10 provides the PLL and DLL lock times.
Table 10. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
PLL lock times
—
100
μs
DLL lock times
7680
122,880
CCB Clocks
Notes
1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio results in the
minimum and an 8:1 ratio results in the maximum.
2. The CCB clock is determined by the SYSCLK × platform PLL ratio.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
16
Freescale Semiconductor
DDR SDRAM
6
DDR SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8555E.
6.1
DDR SDRAM DC Electrical Characteristics
Table 11 provides the recommended operating conditions for the DDR SDRAM component(s) of the
MPC8555E.
Table 11. DDR SDRAM DC Electrical Characteristics
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
2.375
2.625
V
1
I/O reference voltage
MVREF
0.49 × GVDD
0.51 × GVDD
V
2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.18
GVDD + 0.3
V
Input low voltage
VIL
–0.3
MVREF – 0.18
V
Output leakage current
IOZ
–10
10
μA
Output high current (VOUT = 1.95 V)
IOH
–15.2
—
mA
Output low current (VOUT = 0.35 V)
IOL
15.2
—
mA
IVREF
—
5
μA
MVREF input leakage current
4
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
Table 12 provides the DDR capacitance.
Table 12. DDR SDRAM Capacitance
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, MSYNC_IN
CIO
6
8
pF
1
Delta input/output capacitance: DQ, DQS
CDIO
—
0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak to peak) = 0.2 V.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
17
DDR SDRAM
6.2
DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR SDRAM Input AC Timing Specifications
Table 13 provides the input AC timing specifications for the DDR SDRAM interface.
Table 13. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
Symbol
Min
Max
Unit
AC input low voltage
VIL
—
MVREF – 0.31
V
AC input high voltage
VIH
MVREF + 0.31
GVDD + 0.3
V
tDISKEW
—
MDQS—MDQ/MECC input skew per
byte
For DDR = 333 MHz
For DDR < 266 MHz
ps
Notes
1
750
1125
Note:
1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 <= n <=
7) or ECC (MECC[{0...7}] if n = 8).
6.2.2
DDR SDRAM Output AC Timing Specifications
Table 14 and Table 15 provide the output AC timing specifications and measurement conditions for the
DDR SDRAM interface.
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
Skew between any MCK to ADDR/CMD
Symbol 1
Min
Max
Unit
Notes
tMCK
6
10
ns
2
ps
3
-1000
-1100
-1200
200
300
400
—
ns
4
—
ns
4
—
ns
4
tAOSKEW
333 MHz
266 MHz
200 MHz
ADDR/CMD output setup with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHAS
ADDR/CMD output hold with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHAX
MCS(n) output setup with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHCS
2.8
3.45
4.6
2.0
2.65
3.8
2.8
3.45
4.6
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
18
Freescale Semiconductor
DDR SDRAM
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Symbol 1
Parameter
MCS(n) output hold with respect to MCK
Min
tDDKHCX
333 MHz
266 MHz
200 MHz
MCK to MDQS
Max
Unit
Notes
—
ns
4
ns
5
—
ps
6
—
ps
6
2.0
2.65
3.8
tDDKHMH
-0.9
-1.1
-1.2
333 MHz
266 MHz
200 MHz
0.3
0.5
0.6
MDQ/MECC/MDM output setup with respect to
MDQS
333 MHz
266 MHz
200 MHz
tDDKHDS,
tDDKLDS
MDQ/MECC/MDM output hold with respect to
MDQS
333 MHz
266 MHz
200 MHz
tDDKHDX,
tDDKLDX
MDQS preamble start
tDDKHMP
-0.5 × tMCK – 0.9
-0.5 × tMCK +0.3
ns
7
MDQS epilogue end
tDDKLME
-0.9
0.3
ns
7
900
900
1200
900
900
1200
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until
outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the Clock Control
Register. For the skew measurements referenced for tAOSKEW it is assumed that the clock adjustment is set to align the
address/command valid with the rising edge of MCK.
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks
by 1/2 applied cycle. The MCSx pins are separated from the ADDR/CMD (address and command) bus in the HW spec. This
was separated because the MCSx pins typically have different loadings than the rest of the address and command bus,
even though they have the same timings.
5. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). In the source synchronous mode,
MDQS can launch later than MCK by 0.3 ns at the maximum. However, MCK may launch later than MDQS by as much as
0.9 ns. tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. In source
synchronous mode, this will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing
parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the
MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8555E.
7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8555E. Note that tDDKHMP follows the symbol
conventions described in note 1.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
19
DDR SDRAM
Figure 3 shows the DDR SDRAM output timing for address skew with respect to any MCK.
MCK[n]
MCK[n]
tMCK
tAOSKEWmax)
ADDR/CMD
CMD
NOOP
tAOSKEW(min)
ADDR/CMD
CMD
NOOP
Figure 3. Timing Diagram for tAOSKEW Measurement
Figure 4 shows the DDR SDRAM output timing diagram for the source synchronous mode.
MCK[n]
MCK[n]
tMCK
tDDKHAS ,tDDKHCS
tDDKHAX ,tDDKHCX
ADDR/CMD
Write A0
NOOP
tDDKHMP
tDDKHMH
MDQS[n]
tDDKLME
tDDKHDS
tDDKLDS
MDQ[x]
D0
D1
tDDKLDX
tDDKHDX
Figure 4. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
20
Freescale Semiconductor
DUART
Figure 5 provides the AC test load for the DDR bus.
Z0 = 50 Ω
Output
GVDD/2
RL = 50 Ω
Figure 5. DDR AC Test Load
Table 15. DDR SDRAM Measurement Conditions
Symbol
VTH
DDR
Unit
Notes
MVREF ± 0.31 V
V
1
0.5 × GVDD
V
2
VOUT
Notes:
1. Data input threshold measurement point.
2. Data output measurement point.
7
DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8555E.
7.1
DUART DC Electrical Characteristics
Table 16 provides the DC electrical characteristics for the DUART interface of the MPC8555E.
Table 16. DUART DC Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
VIH
VOUT ≥ VOH (min) or
2
OVDD + 0.3
V
Low-level input voltage
VIL
VOUT ≤ VOL (max)
–0.3
0.8
V
Input current
IIN
VIN 1 = 0 V or VIN = VDD
—
±5
μA
High-level output voltage
VOH
OVDD = min,
IOH = –100 μA
OVDD – 0.2
—
V
Low-level output voltage
VOL
OVDD = min, IOL = 100 μA
—
0.2
V
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
21
Ethernet: Three-Speed, MII Management
7.2
DUART AC Electrical Specifications
Table 17 provides the AC timing parameters for the DUART interface of the MPC8555E.
Table 17. DUART AC Timing Specifications
Parameter
Value
Unit
Notes
Minimum baud rate
fCCB_CLK / 1048576
baud
3
Maximum baud rate
fCCB_CLK / 16
baud
1, 3
16
—
2, 3
Oversample rate
Notes:
1. Actual attainable baud rate will be limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit.
Subsequent bit values are sampled each 16th sample.
3. Guaranteed by design.
8
Ethernet: Three-Speed, MII Management
This section provides the AC and DC electrical characteristics forthree-speed, 10/100/1000, and MII
management.
8.1
Three-Speed Ethernet Controller (TSEC)
(10/100/1000 Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical
Characteristics
The electrical characteristics specified here apply to allGMII (gigabit media independent interface), the
MII (media independent interface), TBI (ten-bit interface), RGMII (reduced gigabit media independent
interface), and RTBI (reduced ten-bit interface) signals except MDIO (management data input/output) and
MDC (management data clock). The RGMII and RTBI interfaces are defined for 2.5 V, while the GMII
and TBI interfaces can be operated at 3.3 or 2.5 V. Whether theGMII, MII, or TBI interface is operated at
3.3 or 2.5 V, the timing is compliant with the IEEE 802.3 standard. The RGMII and RTBI interfaces follow
the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical Layer Device Specification
Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in Section 8.3,
“Ethernet Management Interface Electrical Characteristics.”
8.1.1
TSEC DC Electrical Characteristics
All GMII, MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes
specified in Table 18 and Table 19. The potential applied to the input of a GMII, MII, TBI, RGMII, or
RTBI receiver may exceed the potential of the receiver’s power supply (i.e., a GMII driver powered from
a 3.6-V supply driving VOH into a GMII receiver powered from a 2.5-V supply). Tolerance for dissimilar
GMII driver and receiver supply potentials is implicit in these specifications. The RGMII and RTBI signals
are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
22
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
Table 18. GMII, MII, and TBI DC Electrical Characteristics
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage 3.3 V
LVDD
—
3.13
3.47
V
Output high voltage
VOH
IOH = –4.0 mA
LVDD = Min
2.40
LVDD + 0.3
V
Output low voltage
VOL
IOL = 4.0 mA
LVDD = Min
GND
0.50
V
Input high voltage
VIH
—
—
1.70
LVDD + 0.3
V
Input low voltage
VIL
—
—
–0.3
0.90
V
Input high current
IIH
—
40
μA
–600
—
μA
Input low current
VIN 1 = LVDD
1
IIL
VIN = GND
Note:
1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
Table 19. GMII, MII, RGMII RTBI, and TBI DC Electrical Characteristics
Parameters
Symbol
Min
Max
Unit
Supply voltage 2.5 V
LVDD
2.37
2.63
V
Output high voltage
(LVDD = Min, IOH = –1.0 mA)
VOH
2.00
LVDD + 0.3
V
Output low voltage
(LVDD = Min, IOL = 1.0 mA)
VOL
GND – 0.3
0.40
V
Input high voltage
(LVDD = Min)
VIH
1.70
LVDD + 0.3
V
Input low voltage
(LVDD = Min)
VIL
–0.3
0.70
V
Input high current
(VIN 1 = LVDD)
IIH
—
10
μA
Input low current
(VIN 1 = GND)
IIL
–15
—
μA
Note:
1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 1and Table 2.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
23
Ethernet: Three-Speed, MII Management
8.2
GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications
The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.
8.2.1
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
8.2.2
GMII Transmit AC Timing Specifications
Table 20 provides the GMII transmit AC timing specifications.
Table 20. GMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
tGTX
—
8.0
—
ns
tGTXH/tGTX
40
—
60
%
GMII data TXD[7:0], TX_ER, TX_EN setup time
tGTKHDV
2.5
—
—
ns
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
tGTKHDX
0.5
—
5.0
ns
tGTXR3, tGTXR2,4
—
—
1.0
ns
Parameter/Condition
GTX_CLK clock period
GTX_CLK duty cycle
GTX_CLK data clock rise and fall times
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII
transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input
signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect
to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by characterization.
4. Guaranteed by design.
Figure 6 shows the GMII transmit AC timing diagram.
tGTXR
tGTX
GTX_CLK
tGTXH
tGTXF
TXD[7:0]
TX_EN
TX_ER
tGTKHDX
tGTKHDV
Figure 6. GMII Transmit AC Timing Diagram
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
24
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
8.2.2.1
GMII Receive AC Timing Specifications
Table 21 provides the GMII receive AC timing specifications.
Table 21. GMII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
tGRX
—
8.0
—
ns
tGRXH/tGRX
40
—
60
%
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tGRDVKH
2.0
—
—
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tGRDXKH
0.5
—
—
ns
tGRXR, tGRXF 2,3
—
—
1.0
ns
Parameter/Condition
RX_CLK clock period
RX_CLK duty cycle
RX_CLK clock rise and fall time
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH
symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to
the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR)
with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L)
state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing
the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
Figure 7 provides the AC test load for TSEC.
Z0 = 50 Ω
Output
RL = 50 Ω
LVDD/2
Figure 7. TSEC AC Test Load
Figure 8 shows the GMII receive AC timing diagram.
tGRXR
tGRX
RX_CLK
tGRXH
tGRXF
RXD[7:0]
RX_DV
RX_ER
tGRDXKH
tGRDVKH
Figure 8. GMII Receive AC Timing Diagram
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
25
Ethernet: Three-Speed, MII Management
8.2.3
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.3.1
MII Transmit AC Timing Specifications
Table 22 provides the MII transmit AC timing specifications.
Table 22. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
TX_CLK clock period 10 Mbps
tMTX2
—
400
—
ns
TX_CLK clock period 100 Mbps
tMTX
—
40
—
ns
tMTXH/tMTX
35
—
65
%
tMTKHDX
1
5
15
ns
1.0
—
4.0
ns
Parameter/Condition
TX_CLK duty cycle
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
TX_CLK data clock rise and fall time
tMTXR, tMTXF
2,3
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX
symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid
(X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock
of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
Figure 9 shows the MII transmit AC timing diagram.
tMTXR
tMTX
TX_CLK
tMTXH
tMTXF
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 9. MII Transmit AC Timing Diagram
8.2.3.2
MII Receive AC Timing Specifications
Table 23 provides the MII receive AC timing specifications.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
26
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
Table 23. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX2
—
400
—
ns
RX_CLK clock period 100 Mbps
tMRX
—
40
—
ns
tMRXH/tMRX
35
—
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
—
—
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
—
—
ns
tMRXR, tMRXF 2,3
1.0
—
4.0
ns
Parameter/Condition
RX_CLK duty cycle
RX_CLK clock rise and fall time
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference
(K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data
input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
Figure 10 shows the MII receive AC timing diagram.
tMRXR
tMRX
RX_CLK
tMRXH
RXD[3:0]
RX_DV
RX_ER
tMRXF
Valid Data
tMRDVKH
tMRDXKH
Figure 10. MII Receive AC Timing Diagram
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
27
Ethernet: Three-Speed, MII Management
8.2.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.2.4.1
TBI Transmit AC Timing Specifications
Table 24 provides the MII transmit AC timing specifications.
Table 24. TBI Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
tTTX
—
8.0
—
ns
tTTXH/tTTX
40
—
60
%
GMII data TCG[9:0], TX_ER, TX_EN setup time
GTX_CLK going high
tTTKHDV
2.0
—
—
ns
GMII data TCG[9:0], TX_ER, TX_EN hold time from
GTX_CLK going high
tTTKHDX
1.0
—
—
ns
tTTXR, tTTXF 2,3
—
—
1.0
ns
Parameter/Condition
GTX_CLK clock period
GTX_CLK duty cycle
GTX_CLK clock rise and fall time
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state
)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV
symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data
signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the
time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
Figure 11 shows the TBI transmit AC timing diagram.
tTTXR
tTTX
GTX_CLK
tTTXH
tTTXF
tTTXF
TCG[9:0]
tTTKHDV
tTTXR
tTTKHDX
Figure 11. TBI Transmit AC Timing Diagram
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
28
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
8.2.4.2
TBI Receive AC Timing Specifications
Table 25 provides the TBI receive AC timing specifications.
Table 25. TBI Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Symbol 1
Parameter/Condition
RX_CLK clock period
Min
Max
16.0
tTRX
RX_CLK skew
Typ
Unit
ns
tSKTRX
7.5
—
8.5
ns
tTRXH/tTRX
40
—
60
%
RCG[9:0] setup time to rising RX_CLK
tTRDVKH
2.5
—
—
ns
RCG[9:0] hold time to rising RX_CLK
tTRDXKH
1.5
—
—
ns
0.7
—
2.4
ns
RX_CLK duty cycle
RX_CLK clock rise time and fall time
tTRXR, tTRXF
2,3
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH
symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the
tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with
respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state.
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is
skew (SK) followed by the clock that is being skewed (TRX).
2. Guaranteed by design.
Figure 12 shows the TBI receive AC timing diagram.
tTRXR
tTRX
RX_CLK1
tTRXH
tTRXF
Valid Data
RXD[9:0]
Valid Data
tTRDVKH
tSKTRX
tTRDXKH
RX_CLK0
tTRDXKH
tTRXH
tTRDVKH
Figure 12. TBI Receive AC Timing Diagram
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
29
Ethernet: Three-Speed, MII Management
8.2.5
RGMII and RTBI AC Timing Specifications
Table 26 presents the RGMII and RTBI AC timing specifications.
Table 26. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKRGT5
–500
0
500
ps
Data to clock input skew (at receiver) 2
tSKRGT
1.0
—
2.8
ns
tRGT6
7.2
8.0
8.8
ns
Duty cycle for 1000Base-T 4
tRGTH/tRGT6
45
50
55
%
Duty cycle for 10BASE-T and 100BASE-TX 3
tRGTH/tRGT6
40
50
60
%
tRGTR6,7, tRGTF6,7
—
—
0.75
ns
Parameter/Condition
Clock cycle duration 3
Rise and fall times
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. The RGMII specification requires that PC board designer add 1.5 ns or greater in trace delay to the RX_CLK in order to meet
this specification. However, as stated above, this device will function with only 1.0 ns of delay.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Guaranteed by characterization.
6. Guaranteed by design.
7. Signal timings are measured at 0.5 V and 2.0 V voltage levels.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
30
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
Figure 13 shows the RBMII and RTBI AC timing and multiplexing diagrams.
tRGT
tRGTH
GTX_CLK
(At Transmitter)
tSKRGT
TXD[8:5][3:0]
TXD[7:4][3:0]
TXD[3:0]
TXD[8:5]
TXD[7:4]
TXD[4]
TXEN
TXD[9]
TXERR
TX_CTL
tSKRGT
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[3:0] RXD[7:4]
tSKRGT
RXD[4]
RXDV
RX_CTL
RXD[9]
RXERR
tSKRGT
RX_CLK
(At PHY)
Figure 13. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.3
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
GMII, RGMII, TBI and RTBI are specified in Section 8.1, “Three-Speed Ethernet Controller (TSEC)
(10/100/1000 Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical Characteristics.”
8.3.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics
for MDIO and MDC are provided in Table 27.
Table 27. MII Management DC Electrical Characteristics
Parameter
Supply voltage (3.3 V)
Symbol
Conditions
Min
Max
Unit
OVDD
—
3.13
3.47
V
Output high voltage
VOH
IOH = –1.0 mA
LVDD = Min
2.10
LVDD + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
LVDD = Min
GND
0.50
V
Input high voltage
VIH
—
1.70
—
V
Input low voltage
VIL
—
—
0.90
V
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
31
Ethernet: Three-Speed, MII Management
Table 27. MII Management DC Electrical Characteristics (continued)
Parameter
Symbol
Conditions
Min
Max
Unit
Input high current
IIH
LVDD = Max
VIN 1 = 2.1 V
—
40
μA
Input low current
IIL
LVDD = Max
VIN = 0.5 V
–600
—
μA
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
8.3.2
MII Management AC Electrical Specifications
Table 28 provides the MII management AC timing specifications.
Table 28. MII Management AC Timing Specifications
At recommended operating conditions with LVDD is 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
Notes
MDC frequency
fMDC
0.893
—
10.4
MHz
2
MDC period
tMDC
96
—
1120
ns
MDC clock pulse width high
tMDCH
32
—
—
ns
2*[1/(fccb_clk/8)]
ns
3
3
Parameter/Condition
MDC to MDIO valid
tMDKHDV
MDC to MDIO delay
tMDKHDX
10
—
2*[1/(fccb_clk/8)]
ns
MDIO to MDC setup time
tMDDVKH
5
—
—
ns
MDIO to MDC hold time
tMDDXKH
0
—
—
ns
MDC rise time
tMDCR
—
—
10
ns
MDC fall time
tMDHF
—
—
10
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX
symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input
signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the system clock speed (that is, for a system clock of 267 MHz, the delay is 70 ns and for
a system clock of 333 MHz, the delay is 58 ns).
3. This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay is 60 ns and for a
CCB clock of 333 MHz, the delay is 48 ns).
4. Guaranteed by design.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
32
Freescale Semiconductor
Local Bus
Figure 14 shows the MII management AC timing diagram.
tMDCR
tMDC
MDC
tMDCF
tMDCH
MDIO
(Input)
tMDDVKH
tMDDXKH
MDIO
(Output)
tMDKHDX
Figure 14. MII Management Interface Timing Diagram
9
Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the
MPC8555E.
9.1
Local Bus DC Electrical Characteristics
Table 29 provides the DC electrical characteristics for the local bus interface.
Table 29. Local Bus DC Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
VIH
VOUT ≥ VOH (min) or
2
OVDD + 0.3
V
Low-level input voltage
VIL
VOUT ≤ VOL (max)
–0.3
0.8
V
IIN
VIN = 0 V or VIN = VDD
—
±5
μA
High-level output voltage
VOH
OVDD = min,
IOH = -2mA
OVDD – 0.2
—
V
Low-level output voltage
VOL
OVDD = min, IOL = 2mA
—
0.2
V
Input current
1
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
33
Local Bus
9.2
Local Bus AC Electrical Specifications
Table 30 describes the general timing parameters of the local bus interface of the MPC8555E with the DLL
enabled.
Table 30. Local Bus General Timing Parameters - DLL Enabled
Symbol 1
Min
Max
Unit
Notes
tLBK
6.0
—
ns
2
LCLK[n] skew to LCLK[m] or LSYNC_OUT
tLBKSKEW
—
150
ps
7, 9
Input setup to local bus clock (except
LUPWAIT)
tLBIVKH1
1.8
—
ns
3, 4, 8
LUPWAIT input setup to local bus clock
tLBIVKH2
1.7
—
ns
3, 4
Input hold from local bus clock (except
LUPWAIT)
tLBIXKH1
0.5
—
ns
3, 4, 8
LUPWAIT input hold from local bus clock
tLBIXKH2
1.0
—
ns
3, 4
LALE output transition to LAD/LDP output
transition (LATCH hold time)
tLBOTOT
1.5
—
ns
6
tLBKHOV1
—
2.3
ns
3, 8
ns
3, 8
ns
3, 8
—
ns
3, 8
—
ns
3, 8
2.8
ns
5, 9
Parameter
Configuration 7
Local bus cycle time
Local bus clock to output valid (except
LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
LWE[0:1] = 00
LWE[0:1] = 11 (default)
LWE[0:1] = 00
3.8
tLBKHOV2
—
LWE[0:1] = 11 (default)
Local bus clock to address valid for LAD
LWE[0:1] = 00
4.0
tLBKHOV3
—
LWE[0:1] = 11 (default)
Output hold from local bus clock (except
LAD/LDP and LALE)
Output hold from local bus clock for
LAD/LDP
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
LWE[0:1] = 00
tLBKHOX1
LWE[0:1] = 11 (default)
0.7
1.6
tLBKHOX2
LWE[0:1] = 11 (default)
LWE[0:1] = 00
2.6
4.1
LWE[0:1] = 11 (default)
LWE[0:1] = 00
2.5
0.7
1.6
tLBKHOZ1
—
4.2
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
34
Freescale Semiconductor
Local Bus
Table 30. Local Bus General Timing Parameters - DLL Enabled (continued)
Parameter
Configuration 7
Symbol 1
Min
Max
Unit
Notes
Local bus clock to output high impedance for
LAD/LDP
LWE[0:1] = 00
tLBKHOZ2
—
2.8
ns
5, 9
LWE[0:1] = 11 (default)
4.2
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes
high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go
high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for DLL enabled mode.
3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN for DLL enabled to 0.4 × OVDD of the signal in
question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. The value of tLBOTOT is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OVDD/2.
8. Guaranteed by characterization.
9. Guaranteed by design.
Table 31 describes the general timing parameters of the local bus interface of the MPC8555E with the DLL
bypassed.
Table 31. Local Bus General Timing Parameters - DLL Bypassed
Symbol 1
Min
Max
Unit
Notes
tLBK
6.0
—
ns
2
tLBKHKT
1.8
3.4
ns
8
LCLK[n] skew to LCLK[m] or LSYNC_OUT
tLBKSKEW
—
150
ps
7, 9
Input setup to local bus clock (except
LUPWAIT)
tLBIVKH1
5.2
—
ns
3, 4
LUPWAIT input setup to local bus clock
tLBIVKH2
5.1
—
ns
3, 4
Input hold from local bus clock (except
LUPWAIT)
tLBIXKH1
-1.3
—
ns
3, 4
LUPWAIT input hold from local bus clock
tLBIXKH2
-0.8
—
ns
3, 4
LALE output transition to LAD/LDP output
transition (LATCH hold time)
tLBOTOT
1.5
—
ns
6
tLBKLOV1
—
0.5
ns
3
ns
3
Parameter
Configuration 7
Local bus cycle time
Internal launch/capture clock to LCLK
delay
Local bus clock to output valid (except
LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
LWE[0:1] = 00
LWE[0:1] = 11 (default)
LWE[0:1] = 00
LWE[0:1] = 11 (default)
2.0
tLBKLOV2
—
0.7
2.2
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
35
Local Bus
Table 31. Local Bus General Timing Parameters - DLL Bypassed (continued)
Parameter
Local bus clock to address valid for LAD
Configuration 7
Symbol 1
Min
Max
Unit
Notes
LWE[0:1] = 00
tLBKLOV3
—
0.8
ns
3
—
ns
3
—
ns
3
1.0
ns
5
ns
5
LWE[0:1] = 11 (default)
Output hold from local bus clock (except
LAD/LDP and LALE)
Output hold from local bus clock for
LAD/LDP
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
Local bus clock to output high impedance
for LAD/LDP
LWE[0:1] = 00
2.3
tLBKLOX1
LWE[0:1] = 11 (default)
LWE[0:1] = 00
-1.8
tLBKLOX2
LWE[0:1] = 11 (default)
LWE[0:1] = 00
-2.7
-2.7
-1.8
tLBKLOZ1
—
LWE[0:1] = 11 (default)
LWE[0:1] = 00
2.4
tLBKLOZ2
—
LWE[0:1] = 11 (default)
1.0
2.4
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the
output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for DLL enabled mode.
3. All signals are measured from OVDD/2 of the rising edge of local bus clock for DLL bypass mode to 0.4 × OVDD of the signal
in question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. The value of tLBOTOT is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OVDD/2.
8. Guaranteed by characterization.
9. Guaranteed by design.
Figure 15 provides the AC test load for the local bus.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 15. Local Bus C Test Load
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
36
Freescale Semiconductor
Local Bus
Figure 16 to Figure 21 show the local bus signals.
LSYNC_IN
tLBIXKH1
tLBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBIXKH1
tLBIVKH1
Input Signal:
LGTA
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
tLBKHOV1
tLBKHOZ1
tLBKHOX1
tLBKHOV2
tLBKHOZ2
tLBKHOX2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKHOV3
tLBKHOZ2
tLBKHOX2
Output (Address) Signal:
LAD[0:31]
tLBOTOT
LALE
Figure 16. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
37
Local Bus
Internal launch/capture clock
tLBKHKT
LCLK[n]
tLBIVKH1
tLBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBIVKH2
Input Signal:
LGTA
tLBIXKH2
tLBKLOV1
tLBKLOX1
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
tLBKLOZ1
tLBKLOZ2
tLBKLOV2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKLOV3
tLBKLOX2
Output (Address) Signal:
LAD[0:31]
tLBOTOT
LALE
Figure 17. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
38
Freescale Semiconductor
Local Bus
LSYNC_IN
T1
T3
tLBKHOV1
tLBKHOZ1
GPCM Mode Output Signals:
LCS[0:7]/LWE
tLBIVKH2
tLBIXKH2
UPM Mode Input Signal:
LUPWAIT
tLBIVKH1
tLBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBKHOV1
tLBKHOZ1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 18. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
39
Local Bus
Internal launch/capture clock
tLBKHKT
T1
T3
LCLK
tLBKLOX1
tLBKLOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
tLBIVKH2
UPM Mode Input Signal:
LUPWAIT
tLBKLOZ1
tLBIXKH2
tLBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
tLBIXKH1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
40
Freescale Semiconductor
Local Bus
LSYNC_IN
T1
T2
T3
T4
tLBKHOV1
tLBKHOZ1
GPCM Mode Output Signals:
LCS[0:7]/LWE
tLBIVKH2
UPM Mode Input Signal:
LUPWAIT
tLBIVKH1
tLBIXKH2
tLBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBKHOV1
tLBKHOZ1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 or 8 (DLL Enabled)
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
41
Local Bus
Internal launch/capture clock
tLBKHKT
T1
T2
T3
T4
LCLK
tLBKLOX1
tLBKLOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
tLBIVKH2
UPM Mode Input Signal:
LUPWAIT
tLBKLOZ1
tLBIXKH2
tLBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
tLBIXKH1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 or 8 (DLL Bypass Mode)
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
42
Freescale Semiconductor
CPM
10 CPM
This section describes the DC and AC electrical specifications for the CPM of the MPC8555E.
10.1
CPM DC Electrical Characteristics
Table 32 provides the DC electrical characteristics for the CPM.
Table 32. CPM DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Notes
Input high voltage
VIH
2.0
3.465
V
1
Input low voltage
VIL
GND
0.8
V
1, 2
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
1
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
1
Output high voltage
VOH
IOH = –2.0 mA
2.4
—
V
1
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
1
Note:
1. This specification applies to the following pins: PA[0–31], PB[4–31], PC[0–31], and PD[4–31].
2. VIL(max) for the IIC interface is 0.8 V rather than the 1.5 V specified in the IIC standard
10.2
CPM AC Timing Specifications
Table 33 and Table 34 provide the CPM input and output AC timing specifications, respectively.
Table 33. CPM Input AC Timing Specifications 1
Symbol 2
Min3
Unit
FCC inputs—internal clock (NMSI) input setup time
tFIIVKH
6
ns
FCC inputs—internal clock (NMSI) hold time
tFIIXKH
0
ns
FCC inputs—external clock (NMSI) input setup time
tFEIVKH
2.5
ns
FCC inputs—external clock (NMSI) hold time
tFEIXKHb
2
ns
SCC/SMC/SPI inputs—internal clock (NMSI) input setup time
tNIIVKH
6
ns
SCC/SMC/SPI inputs—internal clock (NMSI) input hold time
tNIIXKH
0
ns
SCC/SMC/SPI inputs—external clock (NMSI) input setup time
tNEIVKH
4
ns
SCC/SMC/SPI inputs—external clock (NMSI) input hold time
tNEIXKH
2
ns
TDM inputs/SI—input setup time
tTDIVKH
4
ns
TDM inputs/SI—hold time
tTDIXKH
3
ns
PIO inputs—input setup time
tPIIVKH
8
ns
Characteristic
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
43
CPM
Table 33. CPM Input AC Timing Specifications 1 (continued)
Symbol 2
Min3
Unit
PIO inputs—input hold time
tPIIXKH
1
ns
COL width high (FCC)
tFCCH
1.5
CLK
Characteristic
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFIIVKH
symbolizes the FCC inputs internal timing (FI) with respect to the time the input signals (I) reaching the valid state (V)
relative to the reference clock tFCC (K) going to the high (H) state or setup time. And tTDIXKH symbolizes the TDM timing
(TD) with respect to the time the input signals (I) reach the invalid state (X) relative to the reference clock tFCC (K) going to
the high (H) state or hold time.
3. PIO and TIMER inputs and outputs are asynchronous to SYSCLK or any other externally visible clock. PIO/TIMER inputs
are internally synchronized to the CPM internal clock. PIO/TIMER outputs should be treated as asynchronous.
Table 34. CPM Output AC Timing Specifications 1
Symbol 2
Min
Max
Unit
FCC outputs—internal clock (NMSI) delay
tFIKHOX
1
5.5
ns
FCC outputs—external clock (NMSI) delay
tFEKHOX
2
8
ns
SCC/SMC/SPI outputs—internal clock (NMSI) delay
tNIKHOX
0.5
10
ns
SCC/SMC/SPI outputs—external clock (NMSI) delay
tNEKHOX
2
8
ns
TDM outputs/SI delay
tTDKHOX
2.5
11
ns
PIO outputs delay
tPIKHOX
1
11
ns
Characteristic
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFIKHOX symbolizes the FCC
inputs internal timing (FI) for the time tFCC memory clock reference (K) goes from the high state (H) until outputs (O) are
invalid (X).
Figure 22 provides the AC test load for the CPM.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 22. CPM AC Test Load
Figure 23 through Figure 29 represent the AC timing from Table 33 and Table 34. Note that although the
specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when
the falling edge is the active edge.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
44
Freescale Semiconductor
CPM
Figure 23 shows the FCC internal clock.
BRG_OUT
tFIIVKH
tFIIXKH
FCC Input Signals
tFIKHOX
FCC Output Signals
(When GFMR TCI = 0)
tFIKHOX
FCC Output Signals
(When GFMR TCI = 1)
Figure 23. FCC Internal AC Timing Clock Diagram
Figure 24 shows the FCC external clock.
Serial CLKIN
tFEIVKH
tFEIXKH
FCC Input Signals
tFEKHOX
FCC Output Signals
(When GFMR TCI = 0)
tFEKHOX
FCC Output Signals
(When GFMR TCI = 1)
Figure 24. FCC External AC Timing Clock Diagram
Figure 25 shows Ethernet collision timing on FCCs.
COL
(Input)
tFCCH
Figure 25. Ethernet Collision AC Timing Diagram (FCC)
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
45
CPM
Figure 26 shows the SCC/SMC/SPI 1,2external clock.
Serial CLKIN
Input Signals:
SCC/SMC/SPI
(See Note)
tNEIXKH
tNEIVKH
tNEKHOX
Output Signals:
SCC/SMC/SPI
(See Note)
Note: The clock edge is selectable on SCC and SPI.
Figure 26. SCC/SMC/SPI AC Timing External Clock Diagram
Figure 27 shows the SCC/SMC/SPI 1,2 internal clock.
BRG_OUT
Input Signals:
SCC/SMC/SPI
(See Note)
tNIIXKH
tNIIVKH
tNIKHOX
Output Signals:
SCC/SMC/SPI
(See Note)
Note: The clock edge is selectable on SCC and SPI.
Figure 27. SCC/SMC/SPI AC Timing Internal Clock Diagram
Figure 28 shows TDM input and output signals.
Serial CLKIN
tTDIVKH
tTDIXKH
TDM Input Signals
tTDKHOX
TDM Output Signals
Note: There are 4 possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 28. TDM Signal AC Timing Diagram
1
SPI AC timings are internal mode when it is master since SPICLK is an
output, and external mode when it is slave.
2
SPI AC timings refer always to SPICLK.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
46
Freescale Semiconductor
CPM
Sys clk
tPIIVKH
tPIIXKH
PIO inputs
tPIKHOX
PIO outputs
Figure 29. PIO Signal Diagram
10.3
CPM I2C AC Specification
Table 35. I2C Timing
Characteristic
Expression
All Frequencies
Min
Max
Unit
SCL clock frequency (slave)
fSCL
0
FMAX(1)
Hz
SCL clock frequency (master)
fSCL
BRGCLK/16512
BRGCLK/48
Hz
Bus free time between transmissions
tSDHDL
1/(2.2 * fSCL)
-
s
Low period of SCL
tSCLCH
1/(2.2 * fSCL)
-
s
High period of SCL
tSCHCL
1/(2.2 * fSCL)
-
s
Start condition setup time2
tSCHDL
2/(divider * fSCL)
- (2)
s
Start condition hold time2
tSDLCL
3/(divider * fSCL)
-
s
Data hold time 2
tSCLDX
2/(divider * fSCL)
-
s
time2
tSDVCH
3/(divider * fSCL)
-
s
tSRISE
-
1/(10 * fSCL)
s
Data setup
SDA/SCL rise time
SDA/SCL fall time
tSFALL
-
1/(33 * fSCL)
s
Stop condition setup time
tSCHDH
2/(divider * fSCL)
-
s
Notes:
1. FMAX = BRGCLK/(min_divider*prescale. Where prescaler=25-I2MODE[PDIV]; and min_divider=12 if digital filter disabled
and 18 if enabled.
Example #1: if I2MODE[PDIV]=11 (prescaler=4) and I2MODE[FLT]=0 (digital filter disabled) then FMAX=BRGCLK/48
Example #2: if I2MODE[PDIV]=00 (prescaler=32) and I2MODE[FLT]=1 (digital filter enabled) then FMAX=BRGCLK/576
2. divider = fSCL/prescaler.
In master mode: divider=BRGCLK/(fSCL*prescaler)=2*(I2BRG[DIV]+3)
In slave mode: divider=BRGCLK/(fSCL*prescaler)
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
47
CPM
SDA
tSDHDL
tSCLCH
tSCHCL
tSCLDX
tSCHDL
tSDVCH
SCL
tSDLCL
tSRISE
tSFALL
tSCHDH
Figure 30. CPM I2C Bus Timing Diagram
The following two tables are examples of I2C AC parameters at I2C clock value of 100k and 400k
respectively.
Table 36. CPM I2C Timing (fSCL=100KHz)
Frequency = 100KHz
Characteristic
Expression
Unit
Min
Max
SCL clock frequency (slave)
fSCL
100
KHz
SCL clock frequency (master)
fSCL
-
100
KHz
Bus free time between transmissions
tSDHDL
4.7
-
μs
Low period of SCL
tSCLCH
4.7
-
μs
High period of SCL
tSCHCL
4
-
μs
Start condition setup time
tSCHDL
2
-
μs
Start condition hold time
tSDLCL
3
-
μs
Data hold time
tSCLDX
2
-
μs
Data setup time
tSDVCH
3
-
μs
SDA/SCL rise time
tSRISE
-
1
μs
SDA/SCL fall time (master)
tSFALL
-
303
ns
Stop condition setup time
tSCHDH
2
-
μs
Table 37. CPM I2C Timing (fSCL=400KHz)
Frequency = 400KHz
Characteristic
Expression
Unit
Min
Max
SCL clock frequency (slave)
fSCL
400
KHz
SCL clock frequency (master)
fSCL
-
400
KHz
Bus free time between transmissions
tSDHDL
1.2
-
μs
Low period of SCL
tSCLCH
1.2
-
μs
High period of SCL
tSCHCL
1
-
μs
Start condition setup time
tSCHDL
420
-
ns
Start condition hold time
tSDLCL
630
-
ns
Data hold time
tSCLDX
420
-
ns
Data setup time
tSDVCH
630
-
ns
SDA/SCL rise time
tSRISE
-
250
ns
SDA/SCL fall time
tSFALL
-
75
ns
Stop condition setup time
tSCHDH
420
-
ns
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Freescale Semiconductor
JTAG
11 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the
MPC8555E.
Table 38 provides the JTAG AC timing specifications as defined in Figure 32 through Figure 35.
Table 38. JTAG AC Timing Specifications (Independent of SYSCLK) 1
At recommended operating conditions (see Table 2).
Symbol 2
Min
Max
Unit
JTAG external clock frequency of operation
fJTG
0
33.3
MHz
JTAG external clock cycle time
t JTG
30
—
ns
tJTKHKL
15
—
ns
tJTGR & tJTGF
0
2
ns
tTRST
25
—
ns
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
0
—
—
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
20
25
—
—
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
4
4
20
25
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
—
—
—
—
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
3
3
19
9
Parameter
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
Input setup times:
Notes
3
ns
Input hold times:
4
ns
Valid times:
4
ns
Output hold times:
5
ns
5
ns
5, 6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in
question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Figure 31). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the
tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to
the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that,
in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
49
JTAG
Figure 31 provides the AC test load for TDO and the boundary-scan outputs of the MPC8555E.
Z0 = 50 Ω
Output
RL = 50 Ω
OVDD/2
Figure 31. AC Test Load for the JTAG Interface
Figure 32 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
VM
VM
tJTGR
tJTKHKL
tJTGF
tJTG
VM = Midpoint Voltage (OVDD/2)
Figure 32. JTAG Clock Input Timing Diagram
Figure 33 provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OVDD/2)
Figure 33. TRST Timing Diagram
Figure 34 provides the boundary-scan timing diagram.
JTAG
External Clock
VM
VM
tJTDVKH
tJTDXKH
Boundary
Data Inputs
Input
Data Valid
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
tJTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 34. Boundary-Scan Timing Diagram
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
50
Freescale Semiconductor
I2C
Figure 35 provides the test access port timing diagram.
JTAG
External Clock
VM
VM
tJTIVKH
tJTIXKH
Input
Data Valid
TDI, TMS
tJTKLOV
tJTKLOX
TDO
Output Data Valid
tJTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 35. Test Access Port Timing Diagram
12 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8555E.
12.1
I2C DC Electrical Characteristics
Table 39 provides the DC electrical characteristics for the I2C interface of the MPC8555E.
Table 39. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7 × OVDD
OVDD+ 0.3
V
Input low voltage level
VIL
–0.3
0.3 × OVDD
V
Low level output voltage
VOL
0
0.2 × OVDD
V
1
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
tI2KLKV
20 + 0.1 × CB
250
ns
2
Pulse width of spikes which must be suppressed by the
input filter
tI2KHKL
0
50
ns
3
Input current each I/O pin (input voltage is between 0.1 ×
OVDD and 0.9 × OVDD(max)
II
–10
10
μA
4
Capacitance for each I/O pin
CI
—
10
pF
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual for information on the
digital filter used.
4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
51
I2C
12.2
I2C AC Electrical Specifications
Table 40 provides the AC timing parameters for the I2C interface of the MPC8555E.
Table 40. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 39).
Symbol 1
Min
Max
Unit
fI2C
0
400
kHz
Low period of the SCL clock
tI2CL6
1.3
—
μs
High period of the SCL clock
tI2CH6
0.6
—
μs
Setup time for a repeated START condition
tI2SVKH6
0.6
—
μs
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
tI2SXKL6
0.6
—
μs
Data setup time
tI2DVKH6
100
—
ns
—
02
—
0.9 3
Parameter
SCL clock frequency
μs
tI2DXKL
Data hold time:
CBUS compatible masters
I2C bus devices
Rise time of both SDA and SCL signals
tI2CR
20 + 0.1 Cb 4
300
ns
Fall time of both SDA and SCL signals
tI2CF
20 + 0.1 Cb 4
300
ns
Set-up time for STOP condition
tI2PVKH
0.6
—
μs
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL
0.1 × OVDD
—
V
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2 × OVDD
—
V
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start
condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH
symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative
to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
2. MPC8555E provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
5. Guaranteed by design.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
52
Freescale Semiconductor
PCI
Figure 15 provides the AC test load for the I2C.
Z0 = 50 Ω
Output
OVDD/2
RL = 50 Ω
Figure 36. I2C AC Test Load
Figure 37 shows the AC timing diagram for the I2C bus.
SDA
tI2CF
tI2DVKH
tI2KHKL
tI2CL
tI2CF
tI2SXKL
tI2CR
SCL
tI2SXKL
S
tI2CH
tI2DXKL
tI2SVKH
tI2PVKH
Sr
P
S
Figure 37. I2C Bus AC Timing Diagram
13 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8555E.
13.1
PCI DC Electrical Characteristics
Table 41 provides the DC electrical characteristics for the PCI interface of the MPC8555E.
Table 41. PCI DC Electrical Characteristics 1
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
VIH
VOUT ≥ VOH (min) or
2
OVDD + 0.3
V
Low-level input voltage
VIL
VOUT ≤ VOL (max)
–0.3
0.8
V
IIN
VIN = 0 V or VIN = VDD
—
±5
μA
High-level output voltage
VOH
OVDD = min,
IOH = –100 μA
OVDD – 0.2
—
V
Low-level output voltage
VOL
OVDD = min,
IOL = 100 μA
—
0.2
V
Input current
2
Notes:
1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications.
2. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
53
PCI
13.2
PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the MPC8555E. Note that the
SYSCLK signal is used as the PCI input clock. Table 42 provides the PCI AC timing specifications at 66
MHz.
NOTE
PCI Clock can be PCI1_CLK or SYSCLK based on POR config input.
NOTE
The input setup time does not meet the PCI specification.
Table 42. PCI AC Timing Specifications at 66 MHz
Symbol 1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—
6.0
ns
2, 3
Output hold from Clock
tPCKHOX
2.0
—
ns
2, 9
Clock to output high impedance
tPCKHOZ
—
14
ns
2, 3, 10
Input setup to Clock
tPCIVKH
3.3
—
ns
2, 4, 9
Input hold from Clock
tPCIXKH
0
—
ns
2, 4, 9
REQ64 to HRESET 9 setup time
tPCRVRH
10 × tSYS
—
clocks
5, 6, 10
HRESET to REQ64 hold time
tPCRHRX
0
50
ns
6, 10
HRESET high to first FRAME assertion
tPCRHFV
10
—
clocks
7, 10
Parameter
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK
clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to
the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
system clock period must be kept within the minimum and maximum defined ranges. For values see Section 15, “Clocking.”
6. The setup and hold time is with respect to the rising edge of HRESET.
7. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus
Specifications.
8. The reset assertion timing requirement for HRESET is 100 μs.
9. Guaranteed by characterization.
10.Guaranteed by design.
Figure 15 provides the AC test load for PCI.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 38. PCI AC Test Load
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
54
Freescale Semiconductor
Package and Pin Listings
Figure 39 shows the PCI input AC timing conditions.
CLK
tPCIVKH
tPCIXKH
Input
Figure 39. PCI Input AC Timing Measurement Conditions
Figure 40 shows the PCI output AC timing conditions.
CLK
tPCKHOV
Output Delay
tPCKHOZ
High-Impedance
Output
Figure 40. PCI Output AC Timing Measurement Condition
14 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions.
14.1
Package Parameters for the MPC8555E FC-PBGA
The package parameters are as provided in the following list. The package type is 29 mm × 29 mm, 783
flip chip plastic ball grid array (FC-PBGA).
Die size
8.7 mm × 9.3 mm × 0.75 mm
Package outline
29 mm × 29 mm
Interconnects
783
Pitch
1 mm
Minimum module height
Maximum module height
Solder Balls
Ball diameter (typical)
3.07 mm
3.75 mm
62 Sn/36 Pb/2 Ag
0.5 mm
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
55
Package and Pin Listings
14.2
Mechanical Dimensions of the FC-PBGA
Figure 41 the mechanical dimensions and bottom surface nomenclature of the MPC8555E 783 FC-PBGA
package.
Figure 41. Mechanical Dimensions and Bottom Surface Nomenclature of the FC-PBGA
NOTES
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
56
Freescale Semiconductor
Package and Pin Listings
3.
4.
5.
6.
7.
Maximum solder ball diameter measured parallel to datum A.
Datum A, the seating plane, is defined by the spherical crowns of the solder balls.
Capacitors may not be present on all devices.
Caution must be taken not to short capacitors or exposed metal capacitor pads on package top.
The socket lid must always be oriented to A1.
14.3
Pinout Listings
Table 44 provides the pin-out listing for the MPC8555E, 783 FC-PBGA package.
Table 43. MPC8555E Pinout Listing
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
PCI1 and PCI2 (one 64-bit or two 32-bit)
PCI1_AD[63:32],
PCI2_AD[31:0]
AA14, AB14, AC14, AD14, AE14, AF14, AG14, AH14,
V15, W15, Y15, AA15, AB15, AC15, AD15, AG15,
AH15, V16, W16, AB16, AC16, AD16, AE16, AF16,
V17, W17, Y17, AA17, AB17, AE17, AF17, AF18
I/O
OVDD
17
PCI1_AD[31:0]
AH6, AD7, AE7, AH7, AB8, AC8, AF8, AG8, AD9,
AE9, AF9, AG9, AH9, W10, Y10, AA10, AE11, AF11,
AG11, AH11, V12, W12, Y12, AB12, AD12, AE12,
AG12, AH12, V13, Y13, AB13, AC13
I/O
OVDD
17
PCI_C_BE64[7:4]
PCI2_C_BE[3:0]
AG13, AH13, V14, W14
I/O
OVDD
17
PCI_C_BE64[3:0]
PCI1_C_BE[3:0]
AH8, AB10, AD11, AC12
I/O
OVDD
17
PCI1_PAR
AA11
I/O
OVDD
PCI1_PAR64/PCI2_PAR
Y14
I/O
OVDD
PCI1_FRAME
AC10
I/O
OVDD
2
PCI1_TRDY
AG10
I/O
OVDD
2
PCI1_IRDY
AD10
I/O
OVDD
2
PCI1_STOP
V11
I/O
OVDD
2
PCI1_DEVSEL
AH10
I/O
OVDD
2
PCI1_IDSEL
AA9
I
OVDD
PCI1_REQ64/PCI2_FRAME
AE13
I/O
OVDD
5, 10
PCI1_ACK64/PCI2_DEVSEL AD13
I/O
OVDD
2
PCI1_PERR
W11
I/O
OVDD
2
PCI1_SERR
Y11
I/O
OVDD
2, 4
PCI1_REQ[0]
AF5
I/O
OVDD
PCI1_REQ[1:4]
AF3, AE4, AG4, AE5
I
OVDD
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
57
Package and Pin Listings
Table 43. MPC8555E Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
PCI1_GNT[0]
AE6
I/O
OVDD
PCI1_GNT[1:4]
AG5, AH5, AF6, AG6
O
OVDD
PCI1_CLK
AH25
I
OVDD
PCI2_CLK
AH27
I
OVDD
PCI2_GNT[0]
AC18
I/O
OVDD
PCI2_GNT[1:4]
AD18, AE18, AE19, AD19
O
OVDD
PCI2_IDSEL
AC22
I
OVDD
PCI2_IRDY
AD20
I/O
OVDD
2
PCI2_PERR
AC20
I/O
OVDD
2
PCI2_REQ[0]
AD21
I/O
OVDD
PCI2_REQ[1:4]
AE21, AD22, AE22, AC23
I
OVDD
PCI2_SERR
AE20
I/O
OVDD
2,4
PCI2_STOP
AC21
I/O
OVDD
2
PCI2_TRDY
AC19
I/O
OVDD
2
5, 9
5, 9
DDR SDRAM Memory Interface
MDQ[0:63]
M26, L27, L22, K24, M24, M23, K27, K26, K22, J28,
F26, E27, J26, J23, H26, G26, C26, E25, C24, E23,
D26, C25, A24, D23, B23, F22, J21, G21, G22, D22,
H21, E21, N18, J18, D18, L17, M18, L18, C18, A18,
K17, K16, C16, B16, G17, L16, A16, L15, G15, E15,
C14, K13, C15, D15, E14, D14, D13, E13, D12, A11,
F13, H13, A13, B12
I/O
GVDD
MECC[0:7]
N20, M20, L19, E19, C21, A21, G19, A19
I/O
GVDD
MDM[0:8]
L24, H28, F24, L21, E18, E16, G14, B13, M19
O
GVDD
MDQS[0:8]
L26, J25, D25, A22, H18, F16, F14, C13, C20
I/O
GVDD
MBA[0:1]
B18, B19
O
GVDD
MA[0:14]
N19, B21, F21, K21, M21, C23, A23, B24, H23, G24,
K19, B25, D27, J14, J13
O
GVDD
MWE
D17
O
GVDD
MRAS
F17
O
GVDD
MCAS
J16
O
GVDD
MCS[0:3]
H16, G16, J15, H15
O
GVDD
MCKE[0:1]
E26, E28
O
GVDD
MCK[0:5]
J20, H25, A15, D20, F28, K14
O
GVDD
MCK[0:5]
F20, G27, B15, E20, F27, L14
O
GVDD
11
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Freescale Semiconductor
Package and Pin Listings
Table 43. MPC8555E Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
MSYNC_IN
M28
I
GVDD
22
MSYNC_OUT
N28
O
GVDD
22
Local Bus Controller Interface
LA[27]
U18
O
OVDD
5, 9
LA[28:31]
T18, T19, T20, T21
O
OVDD
5, 7, 9
LAD[0:31]
AD26, AD27, AD28, AC26, AC27, AC28, AA22,
AA23, AA26, Y21, Y22, Y26, W20, W22, W26, V19,
T22, R24, R23, R22, R21, R18, P26, P25, P20, P19,
P18, N22, N23, N24, N25, N26
I/O
OVDD
LALE
V21
O
OVDD
5, 8, 9
LBCTL
V20
O
OVDD
9
LCKE
U23
O
OVDD
LCLK[0:2]
U27, U28, V18
O
OVDD
LCS[0:4]
Y27, Y28, W27, W28, R27
O
OVDD
LCS5/DMA_DREQ2
R28
I/O
OVDD
1
LCS6/DMA_DACK2
P27
O
OVDD
1
LCS7/DMA_DDONE2
P28
O
OVDD
1
LDP[0:3]
AA27, AA28, T26, P21
I/O
OVDD
LGPL0/LSDA10
U19
O
OVDD
5, 9
LGPL1/LSDWE
U22
O
OVDD
5, 9
LGPL2/LOE/LSDRAS
V28
O
OVDD
5, 8, 9
LGPL3/LSDCAS
V27
O
OVDD
5, 9
LGPL4/LGTA/LUPWAIT/
LPBSE
V23
I/O
OVDD
21
LGPL5
V22
O
OVDD
5, 9
LSYNC_IN
T27
I
OVDD
LSYNC_OUT
T28
O
OVDD
LWE[0:1]/LSDDQM[0:1]/
LBS[0:1]
AB28, AB27
O
OVDD
1, 5, 9
LWE[2:3]/LSDDQM[2:3]/
LBS[2:3]
T23, P24
O
OVDD
1, 5, 9
DMA
DMA_DREQ[0:1]
H5, G4
I
OVDD
DMA_DACK[0:1]
H6, G5
O
OVDD
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
59
Package and Pin Listings
Table 43. MPC8555E Pinout Listing (continued)
Signal
DMA_DDONE[0:1]
Package Pin Number
Pin Type
Power
Supply
O
OVDD
H7, G6
Notes
Programmable Interrupt Controller
MCP
AG17
I
OVDD
UDE
AG16
I
OVDD
IRQ[0:7]
AA18, Y18, AB18, AG24, AA21, Y19, AA19, AG25
I
OVDD
IRQ8
AB20
I
OVDD
9
IRQ9/DMA_DREQ3
Y20
I
OVDD
1
IRQ10/DMA_DACK3
AF26
I/O
OVDD
1
IRQ11/DMA_DDONE3
AH24
I/O
OVDD
1
IRQ_OUT
AB21
O
OVDD
2, 4
5, 9
Ethernet Management Interface
EC_MDC
F1
O
OVDD
EC_MDIO
E1
I/O
OVDD
I
LVDD
Gigabit Reference Clock
EC_GTX_CLK125
E2
Three-Speed Ethernet Controller (Gigabit Ethernet 1)
TSEC1_TXD[7:4]
A6, F7, D7, C7
O
LVDD
TSEC1_TXD[3:0]
B7, A7, G8, E8
O
LVDD
9, 18
TSEC1_TX_EN
C8
O
LVDD
11
TSEC1_TX_ER
B8
O
LVDD
TSEC1_TX_CLK
C6
I
LVDD
TSEC1_GTX_CLK
B6
O
LVDD
TSEC1_CRS
C3
I
LVDD
TSEC1_COL
G7
I
LVDD
TSEC1_RXD[7:0]
D4, B4, D3, D5, B5, A5, F6, E6
I
LVDD
TSEC1_RX_DV
D2
I
LVDD
TSEC1_RX_ER
E5
I
LVDD
TSEC1_RX_CLK
D6
I
LVDD
Three-Speed Ethernet Controller (Gigabit Ethernet 2)
TSEC2_TXD[7:4]
B10, A10, J10, K11
O
LVDD
TSEC2_TXD[3:0]
J11, H11, G11, E11
O
LVDD
5, 9, 18
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Freescale Semiconductor
Package and Pin Listings
Table 43. MPC8555E Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
11
TSEC2_TX_EN
B11
O
LVDD
TSEC2_TX_ER
D11
O
LVDD
TSEC2_TX_CLK
D10
I
LVDD
TSEC2_GTX_CLK
C10
O
LVDD
TSEC2_CRS
D9
I
LVDD
TSEC2_COL
F8
I
LVDD
TSEC2_RXD[7:0]
F9, E9, C9, B9, A9, H9, G10, F10
I
LVDD
TSEC2_RX_DV
H8
I
LVDD
TSEC2_RX_ER
A8
I
LVDD
TSEC2_RX_CLK
E10
I
LVDD
DUART
UART_CTS[0,1]
Y2, Y3
I
OVDD
UART_RTS[0,1]
Y1, AD1
O
OVDD
UART_SIN[0,1]
P11, AD5
I
OVDD
UART_SOUT[0,1]
N6, AD2
O
OVDD
I2C interface
IIC_SDA
AH22
I/O
OVDD
4, 19
IIC_SCL
AH23
I/O
OVDD
4, 19
System Control
HRESET
AH16
I
OVDD
HRESET_REQ
AG20
O
OVDD
SRESET
AF20
I
OVDD
CKSTP_IN
M11
I
OVDD
CKSTP_OUT
G1
O
OVDD
18
2, 4
Debug
TRIG_IN
N12
I
OVDD
TRIG_OUT/READY
G2
O
OVDD
6, 9, 18
MSRCID[0:1]
J9, G3
O
OVDD
5, 6, 9
MSRCID[2:3]
F3, F5
O
OVDD
6
MSRCID4
F2
O
OVDD
6
MDVAL
F4
O
OVDD
6
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
61
Package and Pin Listings
Table 43. MPC8555E Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
Clock
SYSCLK
AH21
I
OVDD
RTC
AB23
I
OVDD
CLK_OUT
AF22
O
OVDD
JTAG
TCK
AF21
I
OVDD
TDI
AG21
I
OVDD
12
TDO
AF19
O
OVDD
11
TMS
AF23
I
OVDD
12
TRST
AG23
I
OVDD
12
DFT
LSSD_MODE
AG19
I
OVDD
20
L1_TSTCLK
AB22
I
OVDD
20
L2_TSTCLK
AG22
I
OVDD
20
TEST_SEL0
AH20
I
OVDD
3
TEST_SEL1
AG26
I
OVDD
3
Thermal Management
THERM0
AG2
—
—
14
THERM1
AH3
—
—
14
Power Management
ASLEEP
AG18
9, 18
Power and Ground Signals
AVDD1
AH19
Power for e500
PLL (1.2 V)
AVDD1
AVDD2
AH18
Power for CCB
PLL (1.2 V)
AVDD2
AVDD3
AH17
Power for CPM
PLL (1.2 V)
AVDD3
AVDD4
AF28
Power for PCI1
PLL (1.2 V)
AVDD4
AVDD5
AE28
Power for PCI2
PLL (1.2 V)
AVDD5
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
62
Freescale Semiconductor
Package and Pin Listings
Table 43. MPC8555E Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
GND
A12, A17, B3, B14, B20, B26, B27, C2, C4, C11,C17,
C19, C22, C27, D8, E3, E12, E24, F11, F18, F23, G9,
G12, G25, H4, H12, H14, H17, H20, H22, H27, J19,
J24, K5, K9, K18, K23, K28, L6, L20, L25, M4, M12,
M14, M16, M22, M27, N2, N13, N15, N17, P12, P14,
P16, P23, R13, R15, R17, R20, R26, T3, T8, T10,
T12, T14, T16, U6, U13, U15, U16, U17, U21, V7,
V10, V26, W5, W18, W23, Y8, Y16, AA6, AA13, AB4,
AB11, AB19, AC6, AC9, AD3, AD8, AD17, AF2, AF4,
AF10, AF13, AF15, AF27, AG3, AG7
—
—
GVDD
A14, A20, A25, A26, A27, A28, B17, B22, B28, C12, Power for DDR
C28, D16, D19, D21, D24, D28, E17, E22, F12, F15,
DRAM I/O
F19, F25, G13, G18, G20, G23, G28, H19, H24, J12,
Voltage
J17, J22, J27, K15, K20, K25, L13, L23, L28, M25,
(2.5 V)
N21
GVDD
LVDD
A4, C5, E7, H10
Reference
Voltage;
Three-Speed
Ethernet I/O
(2.5 V, 3.3 V)
LVDD
MVREF
N27
Reference
Voltage Signal;
DDR
MVREF
No Connects
AA24, AA25, AA3, AA4, AA7 AA8, AB24, AB25,
AC24, AC25, AD23, AD24, AD25, AE23, AE24,
AE25, AE26, AE27, AF24, AF25, H1, H2, J1, J2, J3,
J4, J5, J6, M1, N1, N10, N11, N4, N5, N7, N8, N9,
P10, P8, P9, R10, R11, T24, T25, U24, U25, V24,
V25, W24, W25, W9, Y24, Y25, Y5, Y6, Y9, AH26,
AH28, AG28, AH1, AG1, AH2, B1, B2, A2, A3
—
—
OVDD
D1, E4, H3, K4, K10, L7, M5, N3, P22, R19, R25, T2,
PCI, 10/100
T7, U5, U20, U26, V8, W4, W13, W19, W21, Y7, Y23, Ethernet, and
AA5, AA12, AA16, AA20, AB7, AB9, AB26, AC5,
other Standard
AC11, AC17, AD4, AE1, AE8, AE10, AE15, AF7,
(3.3 V)
AF12, AG27, AH4
RESERVED
C1, T11, U11, AF1
SENSEVDD
Signal
Notes
16
OVDD
—
—
15
L12
Power for Core
(1.2 V)
VDD
13
SENSEVSS
K12
—
—
13
VDD
M13, M15, M17, N14, N16, P13, P15, P17, R12, R14, Power for Core
R16, T13, T15, T17, U12, U14
(1.2 V)
VDD
CPM
PA[8:31]
J7, J8, K8, K7, K6, K3, K2, K1, L1, L2, L3, L4, L5, L8,
L9, L10, L11, M10, M9, M8, M7, M6, M3, M2
I/0
OVDD
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
63
Package and Pin Listings
Table 43. MPC8555E Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
PB[18:31]
P7, P6, P5, P4, P3, P2, P1, R1, R2, R3, R4, R5, R6,
R7
I/0
OVDD
PC[0, 1, 4-29]
R8, R9, T9, T6, T5, T4, T1, U1, U2, U3, U4, U7, U8,
U9, U10, V9, V6, V5, V4, V3, V2, V1, W1, W2, W3,
W6, W7, W8
I/0
OVDD
PD[7, 14-25, 29-31]
Y4, AA2, AA1, AB1, AB2, AB3, AB5, AB6, AC7, AC4,
AC3, AC2, AC1, AD6, AE3, AE2
I/0
OVDD
Signal
Notes
Notes:
1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as
DMA_REQ2.
2. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OVDD.
3. TEST_SEL0 must be pulled-high, TEST_SEL1 must be tied to ground.
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the MPC8555E is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. If an external
device connected to this pin might pull it down during reset, then a pull-up or active driver is needed if the signal is intended
to be high during reset.
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down
resistors. See Section 15.2, “Platform/System PLL Ratio.”
8. The value of LALE and LGPL2 at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ pull-up or
pull-down resistors. See the Section 15.3, “e500 Core PLL Ratio.”
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.
10.This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI
operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit
PCI device. Refer to the PCI Specification.
11.This output is actively driven during reset rather than being three-stated during reset.
12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13.These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking
and regulation.
14.Internal thermally sensitive resistor.
15.No connections should be made to these pins.
16.These pins are not connected for any functional use.
17.PCI specifications recommend that a weak pull-up resistor (2–10 kΩ) be placed on the higher order pins to OVDD when
using 64-bit buffer mode (pins PCI_AD[63:32] and PCI2_C_BE[7:4]).
18. If this pin is connected to a device that pulls down during reset, an external pull-up is required to that is strong enough to pull
this signal to a logic 1 during reset.
19. Recommend a pull-up resistor (~1 kΩ) be placed on this pin to OVDD.
20. These are test signals for factory use only and must be pulled up (100Ω το 1kΩ) to OVDD for normal machine operation.
21. If this signal is used as both an input and an output, a weak pull-up (~10kΩ) is required on this pin.
22. MSYNC_IN and MSYNC_OUT should be connected together for proper operation.
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Clocking
15 Clocking
This section describes the PLL configuration of the MPC8555E. Note that the platform clock is identical
to the CCB clock.
15.1
Clock Ranges
Table 44 provides the clocking specifications for the processor core and Table 45 provides the clocking
specifications for the memory bus.
Table 44. Processor Core Clocking Specifications
Maximum Processor Core Frequency
Characteristic
e500 core
processor
frequency
533 MHz
600 MHz
667 MHz
833 MHz
1000 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
400
533
400
600
400
667
400
833
400
1000
Unit Notes
MHz 1, 2, 3
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to Section 15.2, “Platform/System PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings.
2.)The minimum e500 core frequency is based on the minimum platform frequency of 200 MHz.
3. 1000 MHz frequency supports only a 1.3 V core.
Table 45. Memory Bus Clocking Specifications
Maximum Processor Core
Frequency
Characteristic
Memory bus frequency
533, 600, 667, 883, 1000 MHz
Min
Max
100
166
Unit
Notes
MHz
1, 2, 3
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that
the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to Section 15.2, “Platform/System PLL
Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings.
2. The memory bus speed is half of the DDR data rate, hence, half of the platform clock frequency.
3. 1000 MHz frequency supports only a 1.3 V core.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Clocking
15.2
Platform/System PLL Ratio
The platform clock is the clock that drives the L2 cache, the DDR SDRAM data rate, and the e500 core
complex bus (CCB), and is also called the CCB clock. The values are determined by the binary value on
LA[28:31] at power up, as shown in Table 46.
There is no default for this PLL ratio; these signals must be pulled to the desired values.
For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.
Table 46. CCB Clock Ratio
Binary Value of
LA[28:31] Signals
Ratio Description
0000
16:1 ratio CCB clock: SYSCLK (PCI bus)
0001
Reserved
0010
2:1 ratio CCB clock: SYSCLK (PCI bus)
0011
3:1 ratio CCB clock: SYSCLK (PCI bus)
0100
4:1 ratio CCB clock: SYSCLK (PCI bus)
0101
5:1 ratio CCB clock: SYSCLK (PCI bus)
0110
6:1 ratio CCB clock: SYSCLK (PCI bus)
0111
Reserved
1000
8:1 ratio CCB clock: SYSCLK (PCI bus)
1001
9:1 ratio CCB clock: SYSCLK (PCI bus)
1010
10:1 ratio CCB clock: SYSCLK (PCI bus)
1011
Reserved
1100
12:1 ratio CCB clock: SYSCLK (PCI bus)
1101
Reserved
1110
Reserved
1111
Reserved
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Clocking
15.3
e500 Core PLL Ratio
Table 47 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This
ratio is determined by the binary value of LALE and LGPL2 at power up, as shown in Table 47.
Table 47. e500 Core to CCB Ratio
Binary Value of
LALE, LGPL2 Signals
15.4
Ratio Description
00
2:1 e500 core:CCB
01
5:2 e500 core:CCB
10
3:1 e500 core:CCB
11
7:2 e500 core:CCB
Frequency Options
Table 48 shows the expected frequency values for the platform frequency when using a CCB to SYSCLK
ratio in comparison to the memory bus speed.
Table 48. Frequency Options with Respect to Memory Bus Speeds
CCB to SYSCLK
Ratio
SYSCLK (MHz)
17
25
33
42
67
83
100
111
133
200
222
267
300
333
Platform/CCB Frequency (MHz)
2
3
200
250
4
267
333
5
208
6
200
250
333
8
200
267
9
225
300
10
250
333
12
200
16
267
333
300
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67
Thermal
16 Thermal
This section describes the thermal specifications of the MPC8555E.
16.1
Thermal Characteristics
Table 49 provides the package thermal characteristics for the MPC8555E.
Table 49. Package Thermal Characteristics
Characteristic
Symbol
Value
Unit
Notes
Junction-to-ambient Natural Convection on four layer board (2s2p)
RθJMA
17
°C/W
1, 2
Junction-to-ambient (@200 ft/min or 1.0 m/s) on four layer board (2s2p)
RθJMA
14
°C/W
1, 2
Junction-to-ambient (@400 ft/min or 2.0 m/s) on four layer board (2s2p)
RθJMA
13
•C/W
1, 2
Junction-to-board thermal
RθJB
10
•C/W
3
Junction-to-case thermal
RθJC
0.96
•C/W
4
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance
2. Per JEDEC JESD51-6 with the board horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1). Cold plate temperature is used for case temperature; measured value includes the thermal resistance of the
interface layer.
16.2
Thermal Management Information
This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA)
package for air-cooled applications. Proper thermal control design is primarily dependent on the
system-level design—the heat sink, airflow, and thermal interface material. The recommended attachment
method to the heat sink is illustrated in Figure 42. The heat sink should be attached to the printed-circuit
board with the spring force centered over the die. This spring force should not exceed 10 pounds force.
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Thermal
FC-PBGA Package
Heat Sink
Heat Sink
Clip
Thermal Interface Material
Lid
Die
Printed-Circuit Board
Figure 42. Package Exploded Cross-Sectional View with Several Heat Sink Options
The system board designer can choose between several types of heat sinks to place on the MPC8555E.
There are several commercially-available heat sinks from the following vendors:
Aavid Thermalloy
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
603-224-9988
Alpha Novatech
473 Sapena Ct. #15
Santa Clara, CA 95054
Internet: www.alphanovatech.com
408-749-7601
International Electronic Research Corporation (IERC)
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
818-842-7277
Millennium Electronics (MEI)
Loroco Sites
671 East Brokaw Road
San Jose, CA 95112
Internet: www.mei-millennium.com
408-436-8770
Tyco Electronics
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
800-522-6752
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
603-635-5102
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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69
Thermal
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Several
heat sinks offered by Aavid Thermalloy, Alpha Novatech, IERC, Chip Coolers, Millennium Electronics,
and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, that will allow the
MPC8555E to function in various environments.
16.2.1
Recommended Thermal Model
For system thermal modeling, the MPC8555E thermal model is shown in Figure 52. Five cuboids are used
to represent this device. To simplify the model, the solder balls and substrate are modeled as a single block
29x29x1.6 mm with the conductivity adjusted accordingly. The die is modeled as 8.7 x 9.3 mm at a
thickness of 0.75 mm. The bump/underfill layer is modeled as a collapsed resistance between the die and
substrate assuming a conductivity of 4.4 W/m•K in the thickness dimension of 0.07 mm. The lid attach
adhesive is also modeled as a collapsed resistance with dimensions of 8.7 x 9.3 x 0.05 mm and the
conductivity of 1.07 W/m•K. The nickel plated copper lid is modeled as 11 x 11 x 1 mm.
Conductivity
Value
Unit
Lid
(11 × 11 × 1 mm)
kx
360
ky
360
kz
360
W/(m × K)
Bump/underfill
Die
z
Substrate and solder balls
Lid Adhesive—Collapsed resistance
(8.7 × 9.3 × 0.05 mm)
kz
Adhesive
Lid
Side View of Model (Not to Scale)
1.07
Die
(8.7 × 9.3 × 0.75 mm)
x
Bump/Underfill—Collapsed resistance
(8.7 × 9.3 × 0.07 mm)
kz
Substrate
4.4
Substrate and Solder Balls
(25 × 25 × 1.6 mm)
kx
14.2
ky
14.2
kz
1.2
Heat Source
y
Top View of Model (Not to Scale)
Figure 43. MPC8555E Thermal Model
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Thermal
16.2.2
Internal Package Conduction Resistance
For the packaging technology, shown in Table 49, the intrinsic internal conduction thermal resistance paths
are as follows:
• The die junction-to-case thermal resistance
• The die junction-to-board thermal resistance
Figure 44 depicts the primary heat transfer path for a package with an attached heat sink mounted to a
printed-circuit board.
External Resistance
Radiation
Convection
Heat Sink
Thermal Interface Material
Die/Package
Die Junction
Package/Leads
Internal Resistance
Printed-Circuit Board
External Resistance
Radiation
Convection
(Note the internal versus external package resistance)
Figure 44. Package with Heat Sink Mounted to a Printed-Circuit Board
The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is
conducted through the silicon and through the lid, then through the heat sink attach material (or thermal
interface material), and finally to the heat sink. The junction-to-case thermal resistance is low enough that
the heat sink attach material and heat sink thermal resistance are the dominant terms.
16.2.3
Thermal Interface Materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal
contact resistance. For those applications where the heat sink is attached by spring clip mechanism,
Figure 45 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,
graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.
As shown, the performance of these thermal interface materials improves with increasing contact pressure.
The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a
thermal resistance approximately six times greater than the thermal grease joint.
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see
Figure 41). Therefore, the synthetic grease offers the best thermal performance, especially at the low
interface pressure.
When removing the heat sink for re-work, it is preferable to slide the heat sink off slowly until the thermal
interface material loses its grip. If the support fixture around the package prevents sliding off the heat sink,
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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71
Thermal
the heat sink should be slowly removed. Heating the heat sink to 40-50•C with an air gun can soften the
interface material and make the removal easier. The use of an adhesive for heat sink attach is not
recommended.
Silicone Sheet (0.006 in.)
Bare Joint
Floroether Oil Sheet (0.007 in.)
Graphite/Oil Sheet (0.005 in.)
Synthetic Grease
Specific Thermal Resistance (K-in.2/W)
2
1.5
1
0.5
0
0
10
20
30
40
50
60
70
80
Contact Pressure (psi)
Figure 45. Thermal Performance of Select Thermal Interface Materials
The system board designer can choose between several types of thermal interface. There are several
commercially-available thermal interfaces provided by the following vendors:
Chomerics, Inc.
77 Dragon Ct.
Woburn, MA 01888-4014
Internet: www.chomerics.com
781-935-4850
Dow-Corning Corporation
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
Midland, MI 48686-0997
Internet: www.dowcorning.com
800-248-2481
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com
888-642-7674
The Bergquist Company
18930 West 78th St.
800-347-4572
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Thermal
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
Thermagon Inc.
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
16.2.4
888-246-9050
Heat Sink Selection Examples
The following section provides a heat sink selection example using one of the commercially available heat
sinks.
16.2.4.1
Case 1
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
TJ = TI + TR + (θJC + θINT + θSA) × PD
where
TJ is the die-junction temperature
TI is the inlet cabinet ambient temperature
TR is the air temperature rise within the computer cabinet
θJC is the junction-to-case thermal resistance
θINT is the adhesive or interface material thermal resistance
θSA is the heat sink base-to-ambient thermal resistance
PD is the power dissipated by the device. See Table 4 and Table 5.
During operation the die-junction temperatures (TJ) should be maintained within the range specified in
Table 2. The temperature of air cooling the component greatly depends on the ambient inlet air temperature
and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (TA)
may range from 30° to 40°C. The air temperature rise within a cabinet (TR) may be in the range of 5° to
10°C. The thermal resistance of some thermal interface material (θINT) may be about 1°C/W. For the
purposes of this example, the θJC value given in Table 49 that includes the thermal grease interface and is
documented in note 4 is used. If a thermal pad is used, θINT must be added.
Assuming a TI of 30 C, a TR of 5 C, a FC-PBGA package θJC = 0.96, and a power consumption (PD) of
8.0 W, the following expression for TJ is obtained:
Die-junction temperature: TJ = 30°C + 5°C + (0.96°C/W + θSA) × 8.0 W
The heat sink-to-ambient thermal resistance (θSA) versus airflow velocity for a Thermalloy heat sink
#2328B is shown in Figure 46.
Assuming an air velocity of 2 m/s, we have an effective θSA+ of about 3.3 C/W, thus
TJ = 30 C + 5 C + (0.96 C/W + 3.3 C/W) × 8.0 W,
resulting in a die-junction temperature of approximately 69 C which is well within the maximum
operating temperature of the component.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Thermal
8
Thermalloy #2328B Pin-fin Heat Sink
(25 × 28 × 15 mm)
Heat Sink Thermal Resistance (°C/W)
7
6
5
4
3
2
1
0
0.5
1
1.5
2
2.5
3
3.5
Approach Air Velocity (m/s)
Figure 46. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity
16.2.4.2
Case 2
Every system application has different conditions that the thermal management solution must solve. As an
alternate example, assume that the air reaching the component is 85 C with an approach velocity of 1
m/sec. For a maximum junction temperature of 105 C at 8 W, the total thermal resistance of junction to
case thermal resistance plus thermal interface material plus heat sink thermal resistance must be less than
2.5 C/W. The value of the junction to case thermal resistance in Table 49 includes the thermal interface
resistance of a thin layer of thermal grease as documented in footnote 4 of the table. Assuming that the
heat sink is flat enough to allow a thin layer of grease or phase change material, then the heat sink must be
less than 1.5 C/W.
Millennium Electronics (MEI) has tooled a heat sink MTHERM-1051 for this requirement assuming a
compactPCI environment at 1 m/sec and a heat sink height of 12 mm. The MEI solution is illustrated in
Figure 47 and Figure 48. This design has several significant advantages:
• The heat sink is clipped to a plastic frame attached to the application board with screws or plastic
inserts at the corners away from the primary signal routing areas.
• The heat sink clip is designed to apply the force holding the heat sink in place directly above the
die at a maximum force of less than 10 lbs.
• For applications with significant vibration requirements, silicone damping material can be applied
between the heat sink and plastic frame.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Freescale Semiconductor
Thermal
The spring mounting should be designed to apply the force only directly above the die. By localizing the
force, rocking of the heat sink is minimized. One suggested mounting method attaches a plastic fence to
the board to provide the structure on which the heat sink spring clips. The plastic fence also provides the
opportunity to minimize the holes in the printed-circuit board and to locate them at the corners of the
package. Figure 47 and provide exploded views of the plastic fence, heat sink, and spring clip.
Figure 47. Exploded Views (1) of a Heat Sink Attachment using a Plastic Fence
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
75
Thermal
Figure 48. Exploded Views (2) of a Heat Sink Attachment using a Plastic Force
The die junction-to-ambient and the heat sink-to-ambient thermal resistances are common figure-of-merits
used for comparing the thermal performance of various microelectronic packaging technologies, one
should exercise caution when only using this metric in determining thermal management because no single
parameter can adequately describe three-dimensional heat flow. The final die-junction operating
temperature is not only a function of the component-level thermal resistance, but the system level design
and its operating conditions. In addition to the component’s power consumption, a number of factors affect
the final operating die-junction temperature: airflow, board population (local heat flux of adjacent
components), system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today’s
microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation convection
and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models
for the boards, as well as, system-level designs.
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System Design Information
17 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8555E.
17.1
System Clocking
The MPC8555E includes five PLLs.
1. The platform PLL (AVDD1) generates the platform clock from the externally supplied SYSCLK
input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL
ratio configuration bits as described in Section 15.2, “Platform/System PLL Ratio.”
2. The e500 Core PLL (AVDD2) generates the core clock as a slave to the platform clock. The
frequency ratio between the e500 core clock and the platform clock is selected using the e500
PLL ratio configuration bits as described in Section 15.3, “e500 Core PLL Ratio.”
3. The CPM PLL (AVDD3) is slaved to the platform clock and is used to generate clocks used
internally by the CPM block. The ratio between the CPM PLL and the platform clock is fixed and
not under user control.
4. The PCI1 PLL (AVDD4) generates the clocking for the first PCI bus.
5. The PCI2 PLL (AVDD5) generates the clock for the second PCI bus.
17.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,
AVDD2, AVDD3, AVDD4, and AVDD5 respectively). The AVDD level should always be equivalent to VDD,
and preferably these voltages will be derived directly from VDD through a low frequency filter scheme
such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 49, one to each of the five AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of the 783 FC-PBGA footprint, without the inductance of vias.
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System Design Information
Figure 49 shows the PLL power supply filter circuit.
10 Ω
VDD
AVDD (or L2AVDD)
2.2 µF
2.2 µF
GND
Low ESL Surface Mount Capacitors
Figure 49. PLL Power Supply Filter Circuit
17.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the MPC8555E can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8555E system, and the
MPC8555E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that
the system designer place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins
of the MPC8555E. These decoupling capacitors should receive their power from separate VDD, OVDD,
GVDD, LVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance.
Capacitors may be placed directly under the device using a standard escape pattern. Others may surround
the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
17.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high
inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of
the MPC8555E.
17.5
Output Buffer DC Impedance
The MPC8555E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 50). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
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System Design Information
When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals
OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN)/2.
OVDD
RN
SW2
Pad
Data
SW1
RP
OGND
Figure 50. Driver Impedance Measurement
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured
while driving logic 1 with an external precision differential termination resistor of value Rterm. The
measured voltage is V2 = 1/(1/R1 + 1/R2)) × Isource. Solving for the output impedance gives Rsource = Rterm
× (V1/V2 – 1). The drive current is then Isource = V1/Rsource.
Table 50 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,
nominal OVDD, 105°C.
Table 50. Impedance Characteristics
Impedance
Local Bus, Ethernet,
DUART, Control,
Configuration, Power
Management
PCI
DDR DRAM
Symbol
Unit
RN
43 Target
25 Target
20 Target
Z0
Ω
RP
43 Target
25 Target
20 Target
Z0
Ω
Differential
NA
NA
NA
ZDIFF
Ω
Note: Nominal supply voltages. See Table 1, Tj = 105°C.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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79
System Design Information
17.6
Configuration Pin Multiplexing
The MPC8555E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip gated resistor of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to pull
the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and
for platform/system clocks after HRESET deassertion to ensure capture of the reset value). When the input
receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with
minimal signal quality or delay disruption. The default value for all configuration bits treated this way has
been encoded such that a high voltage level puts the device into the default state and external resistors are
needed only when non-default settings are required by the user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value
of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus
configured.
The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up
devices.
17.7
Pull-Up Resistor Requirements
The MPC8555E requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type
pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 52. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
TSEC1_TXD[3:0] must not be pulled low during reset. Some PHY chips have internal pulldowns that
could cause this to happen. If such PHY chips are used, then a pullup must be placed on these signals strong
enough to restore these signals to a logical 1 during reset.
Refer to the PCI 2.2 specification for all pull-ups required for PCI.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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System Design Information
17.8 JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE Std 1149.1 specification, but is provided on all processors that implement the Power Architecture.
The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does
not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state
using only the TCK and TMS signals, generally systems will assert TRST during the power-on reset flow.
Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the
common on-chip processor (COP) function.
The COP function of these processors allow a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
to fully control the processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be
merged into these signals with logic.
The arrangement shown in Figure 51 allows the COP port to independently assert HRESET or TRST,
while ensuring that the target can drive HRESET as well.
The COP interface has a standard header, shown in Figure 51, for connection to the target system, and is
based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The
connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features. An inexpensive option can be to leave
the COP header unpopulated until needed.
There is no standardized way to number the COP header; consequently, many different pin numbers have
been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others
use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as
with an IC). Regardless of the numbering, the signal placement recommended in Figure 51 is common to
all known emulators.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
81
System Design Information
COP_TDO
1
2
NC
COP_TDI
3
4
COP_TRST
NC
5
6
COP_VDD_SENSE
COP_TCK
7
8
COP_CHKSTP_IN
COP_TMS
9
10
NC
COP_SRESET
11
12
NC
COP_HRESET
13
KEY
No pin
COP_CHKSTP_OUT
15
16
GND
Figure 51. COP Connector Physical Pinout
17.8.1 Termination of Unused Signals
If the JTAG interface and COP header will not be used, Freescale recommends the following connections:
• TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
the power-on reset flow. Freescale recommends that the COP header be designed into the system
as shown in Figure 52. If this is not possible, the isolation resistor will allow future access to TRST
in case a JTAG interface may need to be wired onto the system in future debug situations.
• Tie TCK to OVDD through a 10 kΩ resistor. This will prevent TCK from changing state and
reading incorrect data into the device.
• No connection is required for TDI, TMS, or TDO.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Freescale Semiconductor
System Design Information
OVDD
SRESET
From Target
Board Sources
(if any)
HRESET
13
11
10 kΩ
SRESET 6
10 kΩ
HRESET1
COP_HRESET
10 kΩ
COP_SRESET
10 kΩ
5
10 kΩ
10 kΩ
2
3
4
5
6
7
8
9
10
11
12
KEY
13 No
pin
15
6
5
COP Header
1
4
15
COP_TRST
COP_VDD_SENSE2
10 Ω
NC
COP_CHKSTP_OUT
CKSTP_OUT
10 kΩ
14 3
10 kΩ
COP_CHKSTP_IN
CKSTP_IN
8
COP_TMS
16
9
COP Connector
Physical Pinout
TRST1
1
3
TMS
COP_TDO
TDO
COP_TDI
TDI
COP_TCK
7
TCK
2
NC
10
NC
12
4
10 kΩ
16
Notes:
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
in order to fully control the processor as shown here.
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for
improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid
accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.
6. Asserting SRESET causes a machine check interrupt to the e500 core.
Figure 52. JTAG Interface Connection
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
83
Document Revision History
18 Document Revision History
Table 58 provides a revision history for this hardware specification.
Table 51. Document Revision History
Rev. No.
Date
Substantive Change(s)
4
12/2006
Updated Section 2.1.2, “Power Sequencing.”
Updated back page information.
3.2
11/2006
Updated Section 2.1.2, “Power Sequencing.”
Replaced Section 17.8, “JTAG Configuration Signals.”
3.1
10/2005
Table 4: Added footnote 2 about junction temperature.
Table 4: Added max. power values for 1000 MHz core frequency.
Removed Figure 3, “Maximum AC Waveforms on PCI Interface for 3.3-V Signaling.”
Table 30: Modified note to tLBKSKEW from 8 to 9
Table 30: Changed tLBKHOZ1 and tLBKHOV2 values.
Table 30: Added note 3 to tLBKHOV1.
Table 30 and Table 31: Modified note 3.
Table 31: Added note 3 to tLBKLOV1.
Table 31: Modified values for tLBKHKT, tLBKLOV1, tLBKLOV2, tLBKLOV3, tLBKLOZ1, and tLBKLOZ2.
Figure 20: Changed Input Signals: LAD[0:31]/LDP[0:3].
Table 43: Modified note for signal CLK_OUT.
Table 43: PCI1_CLK and PCI2_CLK changed from I/O to I.
Table 52: Added column for Encryption Acceleration.
3
8/29/2005
2
8/2005
Previous revision’s history listed incorrect cross references. Table 2 is now correctly listed as
Table 27 and Table 38 is now listed as Table 31.
Table 7: Added note 2.
Table 14: Modified min and max values for tDDKHMP
1
6/2005
Table 27: Changed LVdd to OVdd for the supply voltage Ethernet management interface.
Table 4: Modified footnote 4 and changed typical power for the 1000MHz core frequency.
Table 31: Corrected symbols for body rows 9–15, effectively changing them from a high state to a
low state.
0
6/2005
Initial Release.
Table 4: Modified max. power values.
Table 43: Modified notes for signals TSEC1_TXD[3:0], TSEC2_TXD[3:0], TRIG_OUT/READY,
MSRCID4, CLK_OUT, and MDVAL.
19 Device Nomenclature
Ordering information for the parts fully covered by this specification document is provided in
Section 19.1, “Nomenclature of Parts Fully Addressed by this Document.”
19.1
Nomenclature of Parts Fully Addressed by this Document
Table 52 provides the Freescale part numbering nomenclature for the MPC8555E. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact your
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
84
Freescale Semiconductor
Device Nomenclature
local Freescale sales office. In addition to the processor frequency, the part numbering scheme also
includes an application modifier which may specify special application conditions. Each part number also
contains a revision code which refers to the die mask revision number.
Table 52. Part Numbering Nomenclature
MPC nnnn
Product
Part
Encryption
Code Identifier Acceleration
MPC
8555
Blank = not
included
E = included
t
pp
aa
a
r
Temperature
Range1
Package 2
Processor
Frequency 3
Platform
Frequency
Revision
Level4
AJ = 533 MHz
AK = 600 MHz
AL = 667 MHz
AP = 833 MHz
AQ = 1000 MHZ
D = 266 MHz
E = 300 MHz
F = 333 MHz
Blank = 0 to 105°C PX = FC-PBGA
C = –40 to 105°C
VT = FC-PBGA
(lead free)
Notes:
1. For Temperature Range=C, Processor Frequency is limited to 667 MHz with a Platform Frequency selector of 333 MHz,
Processor Frequency is limited to 533 MHz with a Platform Frequency selector of 266 MHz.
2. See Section 14, “Package and Pin Listings,” for more information on available package types.
3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other
maximum core frequencies.
4. Contact you local Freescale field applications engineer (FAE).
19.2
Part Marking
Parts are marked as the example shown in Figure 53.
MPCnnnn
MPC85nn
xPXxxxn
tppaaar
MMMMM
ATWLYYWWA
CCCCC
85xx
FC-PBGA
Notes:
MMMMM is the 5-digit mask number.
ATWLYYWWA is the traceability code.
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 53. Part Marking for FC-PBGA Device
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Device Nomenclature
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87
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Document Number: MPC8555EEC
Rev. 4
12/2006
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