E2L0067-18-Z2 ¡ Semiconductor MSM518222A ¡ Semiconductor This version: Dec. 1998 MSM518222A 262,214-Word ¥ 8-Bit Field Memory DESCRIPTION The OKI MSM518222A is a high performance 2-Mbit, 256K ¥ 8-bit, Field Memory. It is designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity TVs and VTRs, exclusively. The MSM518222A is not designed for the other use or high end use in medical systems, professional graphics systems which require long term picture, and data storage systems and others. The 2-Mbit capacity fits one field of a conventional NTSC TV screen. Two cascaded MSM518222As make one frame of the screen: two or more MSM518222As can be cascaded directly without any delay devices between them. (Cascading provides larger storage depth or a longer delay). Each of the 8-bit planes has separate serial write and read ports. These employ independent control clocks to support asynchronous read and write operations. Different clock rates are also supported, which allow alternate data rates between write and read data streams. The MSM518222Aprovides high speed FIFO, First-In First-Out, operation without external refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MSM518222A's function is simple, and similar to a digital delay device whose delay-bit-length is easily set by reset timing. The delay length, and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additional SRAM serial registers, or line buffers for the initial access of 256 ¥ 8-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings. The MSM518222A is similar in operation and functionality to OKI 1-Mbit Field Memory MSM514221B, with the addition of cascade capability. (As for MSM514221B operation compatible 2-Mbit Field Memory, OKI has the MSM518221A which is a sister device of MSM518222A). Additionally, the MSM518222A has a write mask function or input enable function (IE), and readdata skipping function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address increments, but IE and OE cannot stop the increment, when write/ read clocking is continuously applied to MSM518222A. The input enable (IE) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. This facilitates data processing to display a "picture in picture" on a TV screen. 1/16 ¡ Semiconductor MSM518222A FEATURES • Single power supply : 5 V ±10% • 512 Rows ¥ 512 Columns ¥ 8 bits • Fast FIFO (First-In First-Out) operation • High speed asynchronous serial access Read/write cycle time 25 ns/30 ns/40 ns Access time 25 ns/25 ns/30 ns • Direct cascading capability • Write mask function (Input enable control) • Data skipping function (Output enable control) • Self refresh (No refresh control is required) • Package options : 28-pin 400 mil plastic ZIP (ZIP28-P-400-1.27) 28-pin 400 mil plastic SOJ (SOJ28-P-400-1.27) 28-pin 430 mil plastic SOP (SOP28-P-430-1.27-K) (Product : MSM518222A-xxZS) (Product : MSM518222A-xxJS) (Product : MSM518222A-xxGS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) Cycle Time (Min.) MSM518222A-25ZS 25 ns 25 ns MSM518222A-30ZS 25 ns 30 ns MSM518222A-40ZS 30 ns 40 ns MSM518222A-25JS 25 ns 25 ns MSM518222A-30JS 25 ns 30 ns MSM518222A-40JS 30 ns 40 ns MSM518222A-30GS-K 25 ns 30 ns MSM518222A-40GS-K 30 ns 40 ns Package 400 mil 28-pin ZIP 400 mil 28-pin SOJ 430 mil 28-pin SOP 2/16 ¡ Semiconductor MSM518222A PIN CONFIGURATION (TOP VIEW) WE 1 DIN0 3 DIN2 5 VCC 7 DIN5 9 DIN7 11 SWCK 13 NC 15 OE 17 DOUT6 19 DOUT4 21 DOUT3 23 DOUT1 25 RSTR 27 2 IE 4 DIN1 6 DIN3 8 DIN4 10 DIN6 12 RSTW 14 NC 16 RE 18 DOUT7 20 DOUT5 22 VSS DIN4 1 28 VCC DIN4 1 28 VCC DIN5 2 27 DIN3 DIN5 2 27 DIN3 DIN6 3 26 DIN2 DIN6 3 26 DIN2 DIN7 4 25 DIN1 DIN7 4 25 DIN1 RSTW 5 24 DIN0 RSTW 5 24 DIN0 SWCK 6 23 IE SWCK 6 23 IE NC 7 22 WE NC 7 RE 8 21 NC RE 8 21 NC OE 9 20 SRCK OE 9 20 SRCK DOUT7 10 19 RSTR DOUT7 10 19 RSTR DOUT6 11 18 DOUT0 DOUT6 11 18 DOUT0 DOUT5 12 17 DOUT1 DOUT5 12 17 DOUT1 DOUT4 13 16 DOUT2 DOUT4 13 16 DOUT2 VSS 14 15 DOUT3 VSS 14 15 DOUT3 22 WE 24 DOUT2 28-Pin Plastic SOJ 26 DOUT0 28-Pin Plastic SOP 28 SRCK 28-Pin Plastic ZIP Pin Name SWCK SRCK WE RE IE OE RSTW RSTR DIN0 - 7 DOUT0 - 7 VCC VSS NC Function Serial Write Clock Serial Read Clock Write Enable Read Enable Input Enable Output Enable Write Reset Clock Read Reset Clock Data Input Data Output Power Supply (5 V) Ground (0 V) No Connection 3/16 RE Serial Read RSTR SRCK Controller 512-Word Serial Read Register (¥ 8) Read Line Buffer Low-Half (¥ 8) ¡ Semiconductor Data-out Buffer (¥ 8) OE BLOCK DIAGRAM DOUT (¥ 8) Read Line Buffer High-Half (¥ 8) 256 (¥ 8) 256 (¥ 8) 71-Word Sub-Register (¥ 8) X Decoder 256K (¥ 8) Memory Array Read/Write and Refresh Controller 71-Word Sub-Register (¥ 8) 256 (¥ 8) Write Line Buffer Low-Half (¥ 8) 256 (¥ 8) Clock Oscillator Write Line Buffer High-Half (¥ 8) 512-Word Serial Write Register (¥ 8) 4/16 Data-in Buffer (¥ 8) Serial Write DIN (¥ 8) IE WE Controller RSTW SWCK MSM518222A VBB Generator ¡ Semiconductor MSM518222A OPERATION Write Operation The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW. Each write operation, which begins after RSTW, must contain at least 80 active write cycles, i.e. SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time is stored in the serial data registers attached to the DRAM array, an RSTW operation is required after the last SWCK cycle. Note that every write timing of MSM518222A is delayed by one clock compared with read timings for easy cascading without any interface delay devices. Write Reset : RSTW The first positive transition of SWCK after RSTW becomes high resets the write address counters to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely controlled by the SWCK rising edge after the high level of RSTW, the states of WE and IE are ignored in the write reset cycle. Before RSTW may be brought high again for a further reset operation, it must be low for at least two SWCK cycles. Data Inputs : DIN0 - 7 Write Clock : SWCK The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK. Write Enable : WE WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high) restrictions, because the MSM518222A is in fully static operation as long as the power is on. Note that WE setup and hold times are referenced to the rising edge of SWCK. Input Enable : IE IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are referenced to the rising edge of SWCK. 5/16 ¡ Semiconductor MSM518222A Read Operation The read operation is controlled by three clocks, SRCK, RSTR, and RE. Read operation is accomplished by cycling SRCK, and holding RE high after the read address pointer reset operation or RSTR. Each read operation, which begins after RSTR, must contain at least 80 active read cycles, i.e. SRCK cycles while RE is high. Read Reset : RSTR The first positive transition of SRCK after RSTR becomes high resets the read address counters to zero. RSTR setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled by the SRCK rising edge after the high level of RSTR, the states of RE and OE are ignored in the read reset cycle. Before RSTR may be brought high again for a further reset operation, it must be low for at least *two SRCK cycles. Data Out : DOUT0 - 7 Read Clock : SRCK Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read operation. The SRCK input increments the internal read address pointer when RE is high. The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of SRCK. *There are no output valid time restrictions on MSM518222A. Read Enable : RE The function of RE is to gate the SRCK clock for incrementing the read pointer. When RE is high before the rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock. Output Enable : OE OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE level. Note that OE setup and hold times are referenced to the rising edge of SRCK. 6/16 ¡ Semiconductor MSM518222A Power-up and Initialization On power-up, the device is designed to begin proper operation after at least 100 ms after VCC has stabilized to a value within the range of recommended operating conditions. After this 100 ms stabilization interval, the following initialization sequence must be performed. Because the read and write address counters are not valid after power-up, a minimum of 80 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW operation and an RSTR operation, to properly initialize the write and the read address pointer. Dummy write cycles/RSTW and dummy read cycles/RSTR may occur simultaneously. If these dummy read and write operations start while VCC and/or the substrate voltage has not stabilized, it is necessary to perform an RSTR operation plus a minimum of 80 SRCK cycles plus another RSTR operation, and an RSTW operation plus a minimum of 80 SRCK cycles plus another RSTW operation to properly initialize read and write address pointers. Old/New Data Access There must be a minimum delay of 600 SWCK cycles between writing into memory and reading out from memory. If reading from the first field starts with an RSTR operation, before the start of writing the second field (before the next RSTW operation), then the data just written will be read out. The start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 70 SWCK cycles. If the RSTR operation for the first field read-out occurs less than 70 SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. The first field of data that is read out while the second field of data is written is called "old data". In order to read out "new data", i.e., the second field written in, the delay between an RSTW operation and an RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW and RSTR operations is more than 71 but less than 600 cycles, then the data read out will be undetermined. It may be "old data" or "new" data, or a combination of old and new data. Such a timing should be avoided. Cascade Operation The MSM518222A is designed to allow easy cascading of multiple memory devices. This provides higher storage depth, or a longer delay than can be achieved with only one memory device. 7/16 ¡ Semiconductor MSM518222A ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Symbol Condition Rating Unit Input Output Voltage Parameter VT at Ta = 25°C, VSS –1.0 to 7.0 V Output Current IOS Ta = 25°C 50 mA Power Dissipation PD Ta = 25°C 1 W Operating Temperature Topr — 0 to 70 °C Storage Temperature Tstg — –55 to 150 °C Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage VCC 4.5 5.0 5.5 V Power Supply Voltage VSS 0 0 0 V Input High Voltage VIH 2.4 VCC VCC + 1 V Input Low Voltage VIL –1.0 0 0.8 V DC Characteristics Parameter Symbol Condition Min. Max. Unit Input Leakage Current ILI 0 < VI < VCC + 1, Other Pins Tested at V = 0 V –10 10 mA Output Leakage Current ILO 0 < VO < VCC –10 10 mA Output "H" Level Voltage VOH IOH = –1 mA 2.4 — V Output "L" Level Voltage VOL IOL = 2 mA — 0.4 V -25 — 60 Operating Current ICC1 Minimum Cycle Time, Output Open -30 — 50 -40 — 40 Standby Current ICC2 Input Pin = VIH / VIL — 5 Capacitance mA mA (Ta = 25°C, f = 1 MHz) Parameter Symbol Max. Unit Input Capacitance (DIN, SWCK, SRCK, RSTW, RSTR, WE, RE, IE, OE) CI 7 pF Output Capacitance (DOUT) CO 7 pF 8/16 ¡ Semiconductor MSM518222A AC Characteristics (VCC = 5 V ±10%, Ta = 0°C to 70°C) MSM518222A-25 MSM518222A-30 MSM518222A-40 Parameter Symbol Unit Min. Max. Min. Max. Min. Max. tAC — 25 — 25 — 30 ns DOUT Hold Time from SRCK tDDCK 6 — 6 — 6 — ns DOUT Enable Time from SRCK tDECK 6 25 6 25 6 25 ns SWCK "H" Pulse Width tWSWH 9 — 12 — 17 — ns SWCK "L" Pulse Width tWSWL 9 — 12 — 17 — ns Input Data Setup Time tDS 5 — 5 — 5 — ns Input Data Hold Time tDH 6 — 6 — 6 — ns WE Enable Setup Time tWENS 0 — 0 — 0 — ns WE Enable Hold Time tWENH 5 — 5 — 5 — ns WE Disable Setup Time tWDSS 0 — 0 — 0 — ns WE Disable Hold Time tWDSH 5 — 5 — 5 — ns IE Enable Setup Time tIENS 0 — 0 — 0 — ns IE Enable Hold Time tIENH 5 — 5 — 5 — ns IE Disable Setup Time tIDSS 0 — 0 — 0 — ns IE Disable Hold Time tIDSH 5 — 5 — 5 — ns WE "H" Pulse Width WE "L" Pulse Width tWWEH tWWEL 5 5 — — 10 — 10 — ns 10 — 10 — ns IE "H" Pulse Width tWIEH 5 — 10 — 10 — ns IE "L" Pulse Width tWIEL 5 — 10 — 10 — ns RSTW Setup Time tRSTWS 0 — 0 — 0 — ns RSTW Hold Time tRSTWH 10 — 10 — 10 — ns SRCK "H" Pulse Width tWSRH 9 — 12 — 17 — ns SRCK "L" Pulse Width tWSRL 9 — 12 — 17 — ns RE Enable Setup Time tRENS 0 — 0 — 0 — ns RE Enable Hold Time tRENH 5 — 5 — 5 — ns RE Disable Setup Time RE Disable Hold Time tRDSS tRDSH 0 5 — — 0 5 — — 0 5 — — ns ns OE Enable Setup Time tOENS 0 — 0 — 0 — ns OE Enable Hold Time OE Disable Setup Time tOENH tODSS 5 0 — — 5 0 — — 5 0 — — ns ns OE Disable Hold Time RE "H" Pulse Width tODSH tWREH 5 5 — — 5 10 — — 5 10 — — ns ns RE "L" Pulse Width tWREL 5 — 10 — 10 — ns OE "H" Pulse Width tWOEH 5 — 10 — 10 — ns OE "L" Pulse Width tWOEL 5 — 10 — 10 — ns RSTR Setup Time tRSTRS 0 — 0 — 0 — ns RSTR Hold Time tRSTRH 10 — 10 — 10 — ns SWCK Cycle Time tSWC 25 — 30 — 40 — ns SRCK Cycle Time tSRC 25 — 30 — 40 — ns tT 3 30 3 30 3 30 ns Access Time from SRCK Transition Time (Rise and Fall) 9/16 ¡ Semiconductor MSM518222A Notes: 1. Input signal reference levels for the parameter measurement are VIH = 3.0 V and VIL = 0 V. The transition time tT is defined to be a transition time that signal transfers between VIH = 3.0 V and VIL = 0 V. 2. AC measurements assume tT = 3 ns. 3. Read address must have more than a 600 address delay than write address in every cycle when asynchronous read/write is performed. 4. Read must have more than a 600 address delay than write in order to read the data written in a current series of write cycles which has been started at last write reset cycle: this is called "new data read". When read has less than a 70 address delay than write, the read data are the data written in a previous series of write cycles which had been written before the last write reset cycle: this is called "old data read". 5. When the read address delay is between more than 71 and less than 599, read data will be undetermined. However, normal write is achieved in this address condition. 6. Outputs are measured with a load equivalent to 1 TTL load and 30 pF. Output reference levels are VOH = 2.4 V and VOL = 0.8 V. 10/16 ¡ Semiconductor MSM518222A TIMING WAVEFORM Write Cycle Timing (Write Reset) n cycle 0 cycle 1 cycle 2 cycle VIH VIL SWCK tRSTWH tRSTWS tT tWSWH tWSWL tSWC VIH VIL RSTW tDH , tDS DIN n-1 n 0 1 2 VIH VIL WE VIH VIL IE VIH VIL Write Cycle Timing (Write Enable) n cycle Disable cycle Disable cycle n+1 cycle VIH VIL SWCK tWENH tWDSH tWDSS tWENS VIH VIL WE tWWEH tWWEL DIN IE RSTW n-1 n n+1 VIH VIL VIH VIL VIH VIL 11/16 , ¡ Semiconductor MSM518222A Write Cycle Timing (Input Enable) n cycle n+1 cycle n+2 cycle n+3 cycle VIH VIL SWCK tIDSH tIENH tIDSS tIENS VIH VIL IE tWIEH tWIEL n-1 DIN n n+3 VIH VIL VIH VIL WE VIH VIL RSTW Read Cycle Timing (Read Reset) n cycle 0 cycle 1 cycle 2 cycle VIH VIL SRCK tT tWSRH tRSTRH tRSTRS tWSRL tSRC VIH VIL RSTR tDDCK tAC DOUT n-1 n 0 1 2 VOH VOL RE VIH VIL OE VIH VIL 12/16 , , ¡ Semiconductor MSM518222A Read Cycle Timing (Read Enable) n cycle Disable cycle Disable cycle n+1 cycle VIH VIL SRCK tRDSH tRENH tRDSS tRENS VIH VIL RE tWREL DOUT tWREH n-1 n n+1 VOH VOL VIH VIL OE VIH VIL RSTR Read Cycle Timing (Output Enable) n cycle n+1 cycle n+2 cycle n+3 cycle VIH VIL SRCK tODSH tOENH tODSS tOENS VIH VIL OE tWOEN DOUT RE RSTR n-1 n tWOEH tDECK Hi-Z n+3 VOH VOL VIH VIL VIH VIL 13/16 ¡ Semiconductor MSM518222A PACKAGE DIMENSIONS (Unit : mm) ZIP28-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.85 TYP. 14/16 ¡ Semiconductor MSM518222A (Unit : mm) SOJ28-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.30 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/16 ¡ Semiconductor MSM518222A (Unit : mm) SOP28-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.75 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/16 E2Y0002-28-41 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1998 Oki Electric Industry Co., Ltd. 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