OKI MSM6652A Internal mask rom voice synthesis ic, internal one-time-programmable otp rom voice synthesis ic, external rom drive voice synthesis ic Datasheet

FEDL6650-03
¡ Semiconductor
This version: Jul. 2000
Previous version: Sep. 1999
MSM6652/53/54/55/56-xxx, MSM6652A/53A/
54A/55A/56A/58A-xxx, MSM66P54-xx,
MSM66P56-xx, MSM6650
Internal Mask ROM Voice Synthesis IC, Internal One-Time-Programmable (OTP) ROM
Voice Synthesis IC, External ROM Drive Voice Synthesis IC
This document contains minimum specifications. For full specifications, please contact your
nearest Oki office or representative.
GENERAL DESCRIPTION
The MSM6650 family is the successor to OKI's MSM6375 family. To ensure high-quality voice
synthesis, the MSM6650 family members offer adaptive differential pulse-code modulation (ADPCM)
playback, pulse-code modulation (PCM) playback, 12-bit D/A conversion, and on-chip –40 dB/
octave low-pass filter (LPF).
The conventional "beep" tones and 2-channel playback are now easier to use. OKI has added
additional functions such as melody play, fade-out, and random playback. OKI has improved
external control by adding an Edit ROM. The Edit ROM can be used to form sentences by linking
phrases.
The MSM6650 family members can support a variety of applications as it can function in either
Standalone Mode or Microcontroller Interface Mode. In Microcontroller Interface Mode, serial input
control is available. Serial input control minimizes the number of microcontroller port pins required
for voice synthesis control. The MSM6650 family includes an internal mask ROM version, internal
one-time-programmable (OTP) ROM version, and external ROM version. The features of the
MSM6650 family devices are as follows.
• MSM6652/53/54/55/56-xxx
These devices are single-chip voice synthesizers with an on-chip mask ROM using the CMOS
technology.
Standalone Mode or Microcontroller Interface Mode can be selected by mask option.
• MSM6652A/53A/54A/55A/56A/58A-xxx
The trial production period for these devices is shorter than those described above. These devices
are suitable for developing prototype models and concept demonstration of new products.
• MSM66P54-xx, MSM66P56-xx
The device is a single-chip CMOS voice synthesizer with one-time-programmable (OTP) ROM.
Standalone and Microcontroller Interface Modes are selected by using a code (01-04).
The user can easily write voice data using the development tool AR761 or AR762, or P54 adapter.
Unlike the mask ROM version, the OTP version is suited to applications which requires a small lot
production of different type devices or short delivery time.
• MSM6650
The MSM6650 device can directly connect external ROM or EPROM of up to 64 Mbits, which
stores voice data.
This device is ideally suited to an evaluation IC for the MSM6650 family because its circuit
configuration is identical to those of the mask ROM-based and OTP version devices.
1/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
• Option Table
Pin Name
MSM6652/53/54/55/56
MSM6652A/53A/54A/55A/56A/58A
MSM66P54/P56
MSM6650
Microcontroller Interface Mode
Serial Input
Standalone Mode
Parallel Input With Standby
No Standby
Mask Option
—
*1
—
–01
–02
–03
–04
CPU
"H"
"H"
"L"
"L"
SERIAL
"H"
"L"
"L"
"L"
STBY
—
—
"L"
"H"
*2
*1. The options for the mask ROM-based devices are mask options. The user should send OKI an
option list before starting development. A sample of option list is shown below.
*2. A code of OTP version device corresponds to one of the options. The user should specify either
MSM66P54-03 or MSM66P54-04 or MSM66P56-03 or MSM66P56-04. (In this case, no option list
is required.)
Oki Electric Industry Co., Ltd.
Date:
Option List
You are requested to develop MSM665X-XXX on the following conditions.
1. Options
There are four options for the MSM6650 family.
Choose and circle the desired option.
Option
Interface mode
Input
Standby
conversion
Option A
Microcontroller
Serial
—
Option B
Microcontroller
Parallel
—
Option C
Standalone
—
Yes
Option D
Standalone
—
No
2. Package and quantity
Item
Package
(circle the desired one)
Quantity
Note
Ceramic
sample
18-pin DIP
(ceramic)
24-pin SOP
(ceramic)
chip
pcs
Up to 10 samples.
Operating temp. :
10 to 30°C
Mold
sample
18-pin DIP
(plastic)
24-pin SOP
(plastic)
chip
pcs
Up to 50 samples
Mass
production
18-pin DIP
(plastic)
24-pin SOP
(plastic)
chip
pcs per lot
monthly
Signed by
Title :
Company name :
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FEDL6650-03
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MSM6650 Family
STANDALONE MODE
FEATURES
Device name
ROM size
Maximum playback time (sec)
fSAM=4.0 kHz fSAM=6.4 kHz
fSAM=8.0 kHz
fSAM=16 kHz
MSM6652, 6652A
288 Kbits
16.9
10.5
8.4
4.2
MSM6653, 6653A
544 Kbits
31.2
19.5
15.6
7.8
MSM6654, 6654A
1 Mbit
63.8
39.9
31.9
15.9
MSM6655, 6655A
1.5 Mbits
96.5
60.3
48.2
24.1
MSM6656, 6656A
2 Mbits
129.1
80.7
64.5
32.2
MSM6658A
4 Mbits
259.7
162.9
129.8
64.9
MSM66P54
1 Mbit
63.8
39.9
31.9
15.9
MSM66P56
2 Mbit
129.1
80.7
64.5
32.2
MSM6650
64 Mbits (Max)
4194.3
2620.5
2096.4
1048.2
Note: Actual voice ROM area is smaller by 22 Kbits.
• 4-bit ADPCM or 8-bit PCM sound generation
• Melody function
• Edit ROM function
• Two-channel mixing function
• Built-in random playback function
• Fade-out function via four-step sound volume attenuation
• Built-in beep tone of 0.5 kHz, 1.0 kHz, 1.3 kHz, or 2.0 kHz selectable with a specific code
• Sampling frequency of 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.6 kHz, 12.8 kHz, 16.0 kHz, or 32.0 kHz
(32 kHz sampling is not possible when using RC oscillation)
• Up to 120 phrases
• Built-in 12-bit D/A converter
• Built-in –40 dB/octave low-pass filter
• Standby function
• Selectable RC or ceramic oscillation
• Package options:
18-pin plastic DIP (DIP18-P-300-2.54)
(Product name: MSM6652-xxxRS/MSM6653-xxxRS/
MSM6654-xxxRS/MSM6655-xxxRS/
MSM6656-xxxRS/MSM6652A-xxxRS/
MSM6653A-xxxRS/MSM6654A-xxxRS/
MSM6655A-xxxRS/MSM6656A-xxxRS/
MSM6658A-xxxRS)
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM6652-xxxGS-K/MSM6653-xxxGS-K/
MSM6654-xxxGS-K/MSM6655-xxxGS-K/
MSM6656-xxxGS-K/MSM6652A-xxxGS-K/
MSM6653A-xxxGS-K/MSM6654A-xxxGS-K/
MSM6655A-xxxGS-K/MSM6656A-xxxGS-K/
MSM6658A-xxxGS-K/MSM66P54-03GS-K/
MSM66P54-04GS-K/MSM66P56-03GS-K/
MSM66P56-04GS-K)
20-pin plastic DIP (DIP20-P-300-2.54-W1) (Product name: MSM66P54-03RS/MSM66P54-04RS/
MSM66P56-03RS/MSM66P56-04RS)
64-pin plastic QFP (QFP64-P-1420-1.00-BK) (Product name: MSM6650GS-BK)
64-pin plastic SDIP (SDIP64-P-750-1.778) (Product name: MSM6650SS)
3/45
8
TEST
RND
BUSY
OSC1
OSC2
I/O
Interface
OSC
Ceramic/
Crystal/RC
Timing Controller
RESET
VDD
GND
DATA
Controller
PCM
Synthesizer
12
Melody
Generator
12-Bit
DAC
BEEP Tone
Generator
LPF
AOUT
FEDL6650-03
4/45
XT/CR
16-Bit (MSM6652/52A)
17-Bit (MSM6653/53A)
17-Bit (MSM6654/54A)
18-Bit (MSM6655/55A)
18-Bit (MSM6656/56A)
19-Bit (MSM6658A)
Address Counter
MSM6650 Family
OSC3
Random
Circuit
ADPCM
Synthesizer
¡ Semiconductor
7
16-Bit (MSM6652/52A)
17-Bit (MSM6653/53A)
17-Bit (MSM6654/54A)
18-Bit (MSM6655/55A)
18-Bit (MSM6656/56A)
19-Bit (MSM6658A)
Multiplexer
BLOCK DIAGRAMS
Address &
Switching
Controller
(MSM6652/52A)
(MSM6653/53A)
(MSM6654/54A)
(MSM6655/55A)
(MSM6656/56A)
(MSM6658A)
ROM
(Containing 22-Kbit Phrase Control
Table & Phrase Address Table)
MSM6652/53/54/55/56-xxx
MSM6652A/53A/54A/55A/56A/58A-xxx
A2
A1
A0
SW3
SW2
SW1
SW0
288-Kbit
544-Kbit
1-Mbit
1.5-Mbit
2-Mbit
4-Mbit
Program Circuit
A2
A1
A0
SW3
SW2
SW1
SW0
Address &
Switching
Controller
7
1-Mbit OTP ROM (MSM66P54-xx)
2-Mbit OTP ROM (MSM66P56-xx)
17-Bit (MSM66P54-xx)
18-Bit (MSM66P56-xx)
Multiplexer
(Containing 22-Kbit Phrase Control
Table & Phrase Address Table)
¡ Semiconductor
MSM66P54/P56-xx
PGM
VPP
8
TEST
ADPCM
Synthesizer
RND
BUSY
Random
Circuit
DATA
Controller
17-Bit (MSM66P54-xx)
18-Bit (MSM66P56-xx)
Address Counter
PCM
Synthesizer
I/O
Interface
12
Melody
Generator
12-Bit
DAC
OSC1
5/45
XT/CR
Timing Controller
BEEP Tone
Generator
RESET
VDD
GND
LPF
AOUT
FEDL6650-03
OSC3
OSC
(Ceramic/
Crystal/RC)
MSM6650 Family
OSC2
D7
D0
8-Bit LATCH
Address &
Switching
Controller
7
23-Bit Multiplexer
¡ Semiconductor
A2
A1
A0
SW3
SW2
SW1
SW0
RA0
MSM6650
RA22
8
TEST1, 3
RND
Random
Circuit
DATA
Controller
23-Bit Address
Counter
CE
RCS
BUSY
NAR
IBUSY
STANDBY
XT/OSC1
XT/OSC2
PCM
Synthesizer
12
I/O
Interface
OSC
(Ceramic/
Crystal/RC)
RESET CPU STBY TEST2 DVDD DGND
12-Bit
DAC
BEEP Tone
Generator
LPF
AGND AVDD AOUT
FEDL6650-03
6/45
XT/CR
Timing Controller
Melody
Generator
MSM6650 Family
OSC3
ADPCM
Synthesizer
FEDL6650-03
¡ Semiconductor
MSM6650 Family
PIN CONFIGURATION (TOP VIEW)
The MSM66P54-xx and MSM66P56-xx has two more pins than the MSM6652-6658A while their pin
configurations are identical.
The additional two pins (VPP, PGM) of the MSM66P54-xx/P56-xx may be open at playback after
completion of writing.
MSM6652-6658A (Mask ROM)
MSM66P54/P56 (OTP)
A0
1
18 SW3
VPP
1
20 PGM
A1
2
17 SW2
A0
2
19 SW3
A2
3
16 SW1
A1
3
18 SW2
TEST
4
15 SW0
A2
4
17 SW1
TEST
5
16 SW0
13 OSC3
RESET
6
15 RND
7
12 OSC2
BUSY
7
14 OSC3
AOUT
8
11 OSC1
XT/CR
8
13 OSC2
GND
9
10 VDD
AOUT
9
12 OSC1
RESET
5
14 RND
BUSY
6
XT/CR
GND 10
18-Pin Plastic DIP
11 VDD
20-Pin Plastic DIP
MSM6652-xxxRS, MSM6653-xxxRS, MSM6654-xxxRS,
MSM66P54-03/-04RS
MSM6655-xxxRS, MSM6656-xxxRS, MSM6652A-xxxRS,
MSM66P56-03/-04RS
MSM6653A-xxxRS, MSM6654A-xxxRS, MSM6655A-xxxRS,
MSM6656A-xxxRS, MSM6658A-xxxRS
MSM6652-6658A (Mask ROM)
MSM66P54/P56 (OTP)
VDD
1
24
GND
VDD
1
24
GND
OSC1
2
23
AOUT
OSC1
2
23
AOUT
OSC2
3
22
XT/CR
OSC2
3
22
XT/CR
NC
4
21
NC
NC
4
21
NC
OSC3
5
20
BUSY
OSC3
5
20
BUSY
NC
6
19
NC
NC
6
19
NC
NC
7
18
NC
PGM
7
18
VPP
RND
8
17
RESET
RND
8
17
RESET
SW0
9
16
TEST
SW0
9
16
TEST
SW1
10
15
A2
SW1
10
15
A2
SW2
11
14
A1
SW2
11
14
A1
SW3
12
13
A0
SW3
12
13
A0
24-Pin Plastic SOP
MSM6652-xxxGS-K, MSM6653-xxxGS-K,
MSM6654-xxxGS-K, MSM6655-xxxGS-K,
MSM6656-xxxGS-K, MSM6652A-xxxGS-K,
MSM6653A-xxxGS-K, MSM6654A-xxxGS-K,
MSM6655A-xxxGS-K, MSM6656A-xxxGS-K,
MSM6658A-xxxGS-K
24-Pin Plastic SOP
MSM66P54-03/-04GS-K
MSM66P56-03/-04GS-K
7/45
¡ Semiconductor
MSM6650
,
FEDL6650-03
MSM6650 Family
14
15
16
17
18
19
52
53
54
56
57
58
59
60
61
62
63
55
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RA10
RA9
RA8
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
D7
D6
D5
D4
D3
D2
D1
NC
32
13
49
31
12
50
30
11
51
29
9
10
28
8
27
7
26
6
25
5
24
4
23
3
22
2
21
OSC3
TEST1
RND
XT/CR
CPU
TEST2
IBUSY
NC
1
STANDBY
SW0
SW1
SW2
SW3
A0
A1
A2
TEST3
RESET
CE
RCS
D0
NC
NC
BUSY
NAR
AOUT
AGND
DGND
AVDD
DVDD
XT/OSC1
XT/OSC2
20
64
STBY
RA22
RA21
RA20
RA19
RA18
RA17
RA16
RA15
RA14
RA13
RA12
RA11
Product name: MSM6650GS-BK
NC : No connection
64-Pin Plastic QFP
8/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
Product name: MSM6650SS
XT/OSC2
1
64
XT/OSC1
OSC3
2
63
DVDD
TEST1
3
62
AVDD
RND
4
61
DGND
XT/CR
5
60
AGND
CPU
6
59
AOUT
TEST2
7
58
NAR
IBUSY
8
57
BUSY
NC
9
56
NC
STANDBY
SW0
10
11
55
54
STBY
RA22
SW1
12
53
RA21
SW2
13
52
RA20
SW3
14
51
RA19
A0
15
50
RA18
A1
16
49
RA17
A2
48
47
RA16
TEST3
17
18
RESET
19
46
RA14
RA15
CE
20
45
RA13
RCS
21
44
RA12
D0
22
43
RA11
NC
23
42
RA10
D1
24
41
NC
D2
D3
25
26
40
39
RA9
RA8
D4
27
38
RA7
D5
28
37
RA6
D6
29
36
RA5
D7
30
35
RA4
RA0
RA1
31
34
32
33
RA3
RA2
NC : No connection
64-Pin Plastic SDIP
9/45
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¡ Semiconductor
MSM6650 Family
PIN DESCRIPTIONS
1. MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx
18-Pin plastic DIP
Pin
Symbol Type
Description
Reset. Setting this pin to "L" puts the LSI in standby status. At this time,
oscillation stops, AOUT is pulled to GND, and the deveice is initialized.
This pin has an internal pull-up resistor.
5
RESET
I
6
BUSY
O
7
XT/CR
I
8
AOUT
O
Sound Output. This is the synthesized output pin of the internal low-pass filter.
11
OSC1
I
Oscillator 1. This pin is a ceramic oscillator connection pin when using ceramic
oscillation. This pin is an RC connection pin when using RC oscillation.
When using an external clock, use this pin as the clock input.
12
OSC2
O
Oscillator 2. This pin is a ceramic oscillator connection pin when using a
ceramic oscillator. This is an RC connection pin when using RC oscillation.
Leave open if using an external clock. OSC2 outputs a "L" level in standby status.
13
OSC3
O
Oscillator 3. Leave open if using a ceramic oscillator. This pin is the RC
connection pin when using RC oscillation. When RC oscillation is selected, OSC3
outputs a "H" level in standby status.
I
Random Playback. Random playback starts when the RND pin is set to a "L"
level. At the fall of RND, addresses from the random address playback circuit
inside the IC are fetched. Set to a "H" level if random playback is not used.
This pin has an internal pull-up resistor.
Phrase Inputs. These pins are phrase input pins corresponding to playback.
If the input changes, SW0 to SW3 pins capture address data after 16 ms and
speech playback commences. These pins have internal pull-down resistors.
14
RND
Busy. This pin outputs a "L" level during playback. At power-on, this pin is at "H"
level.
XT/CR selectable pin. Set to "H" level when using ceramic oscillation. Set to
"L" level when using RC oscillation.
15-18
SW0-SW3
I
1-3
A0-A2
I
9
GND
—
Ground.
10
VDD
—
Power supply. Insert a 0.1mF or more bypass capacitor between this pin and GND.
4
TEST
I
Phrase Inputs. Phrase input pins correspoding to playback. The A0 input
becomes invalid when the random playback function is used.
Test Mode. Set to "H" level. This pin has an internal pull-up resistor.
10/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
2.MSM66P54-xx, MSM66P56-xx
20-Pin plastic DIP
Pin
Symbol Type
Description
Reset. Setting this pin to "L" puts the LSI in standby status. At this time,
oscillation stops, AOUT is pulled to GND, and the deveice is initialized.
This pin has an internal pull-up resistor.
6
RESET
I
7
BUSY
O
8
XT/CR
I
9
AOUT
O
Sound Output. This is the synthesized output pin of the internal low-pass filter.
12
OSC1
I
Oscillator 1. This pin is a ceramic oscillator connection pin when using ceramic
oscillation. This pin is an RC connection pin when using RC oscillation.
When using an external clock, use this pin as the clock input.
13
OSC2
O
Oscillator 2. This pin is a ceramic oscillator connection pin when using a
ceramic oscillator. This is an RC connection pin when using RC oscillation.
Leave open if using an external clock. OSC2 outputs a "L" level in standby status.
14
OSC3
O
Oscillator 3. Leave open if using a ceramic oscillator. This pin is the RC
connection pin when using RC oscillation. When RC oscillation is selected, OSC3
outputs a "H" level in standby status.
Busy. This pin outputs a "L" level during playback. At power-on, this pin is at "H"
level.
XT/CR selectable pin. Set to "H" level when using ceramic oscillation. Set to
"L" level when using RC oscillation.
15
RND
I
Random Playback. Random playback starts when the RND pin is set to a "L"
level. At the fall of RND, addresses from the random address playback circuit
inside the IC are fetched. Set to a "H" level if random playback is not used.
This pin has an internal pull-up resistor.
16-19
SW0-SW3
I
Phrase Inputs. These pins are phrase input pins corresponding to playback.
If the input changes, SW0 to SW3 pins capture address data after 16 ms and
speech playback commences. These pins have internal pull-down resistors.
2-4
A0-A2
I
10
GND
—
Ground.
11
VDD
—
Power supply. Insert a 0.1mF or more bypass capacitor between this pin and GND.
5
TEST
I
1
VPP
—
Test Mode. Set to "H" level. This pin has an internal pull-up resistor.
Power supply used when writing data to internal OTP ROM. Leave open or set to
20
PGM
I
Phrase Inputs. Phrase input pins correspoding to playback. The A0 input
becomes invalid when the random playback function is used.
"H" level during playback.
Interface with voice analysis edit tool AR203 or AR204. Set to "L" level or leave
open during playback.
11/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
3.MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx, MSM66P54-xx,
MSM66P56-xx
24-Pin plastic SOP
Pin
Symbol Type
Description
Reset. Setting this pin to "L" puts the LSI in standby status. At this time,
oscillation stops, AOUT is pulled to GND, and the deveice is initialized.
This pin has an internal pull-up resistor.
17
RESET
I
20
BUSY
O
22
XT/CR
I
23
AOUT
O
Sound Output. This is the synthesized output pin of the internal low-pass filter.
2
OSC1
I
Oscillator 1. This pin is a ceramic oscillator connection pin when using ceramic
oscillation. This pin is an RC connection pin when using RC oscillation.
When using an external clock, use this pin as the clock input.
3
OSC2
O
Oscillator 2. This pin is a ceramic oscillator connection pin when using a
ceramic oscillator. This is an RC connection pin when using RC oscillation.
Leave open if using an external clock. OSC2 outputs a "L" level in standby status.
5
OSC3
O
Oscillator 3. Leave open if using a ceramic oscillator. This pin is the RC
connection pin when using RC oscillation. When RC oscillation is selected, OSC3
outputs a "H" level in standby status.
8
RND
I
Random Playback. Random playback starts when the RND pin is set to a "L"
level. At the fall of RND, addresses from the random address playback circuit
inside the IC are fetched. Set to a "H" level if random playback is not used.
This pin has an internal pull-up resistor.
9-12
SW0-SW3
I
Phrase Inputs. These pins are phrase input pins corresponding to playback.
If the input changes, SW0 to SW3 pins capture address data after 16 ms and
speech playback commences. These pins have internal pull-down resistors.
13-15
A0-A2
I
24
GND
—
Ground.
1
VDD
—
Power supply. Insert a 0.1mF or more bypass capacitor between this pin and GND.
16
TEST
I
18
VPP*
—
Test Mode. Set to "H" level. This pin has an internal pull-up resistor.
Power supply used when writing data to internal OTP ROM. Leave open or set to
7
PGM*
I
Busy. This pin outputs a "L" level during playback. At power-on, this pin is at "H"
level.
XT/CR selectable pin. Set to "H" level when using ceramic oscillation. Set to
"L" level when using RC oscillation.
Phrase Inputs. Phrase input pins correspoding to playback. The A0 input
becomes invalid when the random playback function is used.
"H" level during playback.
Interface with voice analysis edit tool AR203 or AR204. Set to "L" level or leave
open during playback.
* Pins for MSM66P54/56-xx only
12/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
4.MSM6650
64-Pin plastic QFP (64-Pin plastic SDIP)
Pin
Symbol Type
Description
Reset. Setting this pin to "L" puts the LSI in standby status. At this time,
oscillation stops, AOUT is pulled to GND, and the deveice is initialized.
This pin has an internal pull-up resistor.
29(19)
RESET
I
3(57)
BUSY
O
15(5)
XT/CR
I
5 (59)
AOUT
O
Sound Output. This is the synthesized output pin of the internal low-pass filter.
10(64)
XT/OSC1
I
Oscillator 1. This pin is a ceramic oscillator connection pin when using ceramic
oscillation. This pin is an RC connection pin when using RC oscillation.
When using an external clock, use this pin as the clock input.
11(1)
XT/OSC2
O
Oscillator 2. This pin is a ceramic oscillator connection pin when using a
ceramic oscillator. This is an RC connection pin when using RC oscillation.
Leave open if using an external clock. OSC2 outputs a "L" level in standby status.
12(2)
OSC3
O
Oscillator 3. Leave open if using a ceramic oscillator. This pin is the RC
connection pin when using RC oscillation. When RC oscillation is selected, OSC3
outputs a "H" level in standby status.
RND
I
Random Playback. Random playback starts when the RND pin is set to a "L"
level. At the fall of RND, addresses from the random address playback circuit
inside the IC are fetched. Set to a "H" level if random playback is not used.
This pin has an internal pull-up resistor.
SW0-SW3
I
Phrase Inputs. These pins are phrase input pins corresponding to playback.
If the input changes, SW0 to SW3 pins capture address data after 16 ms and
speech playback commences. These pins have internal pull-down resistors.
A0-A2
I
14(4)
21-24
(11-14)
25-27
(15-17)
Busy. This pin outputs a "L" level during playback. At power-on, this pin is at "H"
level.
XT/CR selectable pin. Set to "H" level when using ceramic oscillation. Set to
"L" level when using RC oscillation.
Phrase Inputs. Phrase input pins correspoding to playback. The A0 input
becomes invalid when the random playback function is used.
13/45
FEDL6650-03
¡ Semiconductor
Pin
MSM6650 Family
Description
Symbol Type
6 (60)
AGND
—
Analog ground pin.
7 (61)
DGND
—
Digital ground pin.
8 (62)
AVDD
—
Analog power pin. Insert a 0.1 mF or more bypass capacitor in between this pin and AGND.
9 (63)
DVDD
—
16 (6)
CPU
I
13, 28 (3, 18)
TEST1, 3
I
17 (7)
TEST2
I
18 (8)
IBUSY
O
20 (10)
STANDBY
O
Digiral power pin. Insert a 0.1 mF or more bypass capacitor in between this pin and DGND.
CPU Mode. Set to "L" level to select Standalone Mode. Set to "H" level to select
Microcontroller Interface Mode.
Test. Set these pins to "H" level. The TEST1 and TEST3 pins have internal pull-up
resistor.
Test. Set this pin to "L" level.
I Busy. Outputs a "L" level during voice playback (except during standby
conversion time), or when the AOUT pin is at half VDD level.
Standby Indicator. This output pin remains at "L" level during oscillation.
Chip Enable. CE is a timing output pin to control read of external memory.
30 (20)
CE
O
This pin outputs when RCS is at the "L" level. This pin goes high impedance
when RCS is at the "H" level.
Read Chip Select. The data bits D0-D7 are internally pulled down when RCS
31 (21)
RCS
I
is high. Addresses and CE are output when RCS is at "L" level. The RA22-RA0
address pins and CE pin become high impedance.
32, 34-40
(22, 24-30)
41-63
(31-40, 42-54)
D0-D7
I
RA0-RA22
O
External Memory Data Bus. Data is input when RCS is low. When RCS is
high, these pins become low due to internal pull-down resistors.
External Memory Address. These are address pins for an external memory
output when RCS is low. These pins become high impedance status if RCS is in
"H" level.
Standby Contorl. If set to "L" level, the MSM6650 enters standby mode 0.2
64 (55)
STBY
I
seconds after voice ends. If set to "H" level, the MSM6650 AOUT output maintains
half VDD after voice ends.
14/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
ABSOLUTE MAXIMUM RATINGS
(GND=0 V)
Parameter
Symbol
Condition
Power supply voltage
VDD
Ta = 25°C
Input voltage
VIN
Storage temperature
TSTG
Rating
Unit
–0.3 to +7.0
V
–0.3 to VDD+0.3
V
–55 to +150
°C
—
RECOMMENDED OPERATING CONDITIONS
(GND=0 V)
Parameter
Power supply voltage
Symbol
VDD
Condition
MSM6652-56, MSM6650,
MSM6652A-56A
Range
Unit
2.4 to 5.5
V
VDD
MSM6658A, MSM66P54/P56
3.5 to 5.5
V
Top
—
–40 to +85
°C
Master clock frequency 1
fOSC1
When crystal selected
Master clock frequency 2
fOSC2
When RC selected (*)
Operating temperature
*
Min.
Typ.
Max.
3.5
4.096
4.5
200
256
300
MHz
kHz
If RC oscillation is selected, 32kHz sampling frequency cannot be selected.
15/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
"H" input voltage
Symbol
VIH
(VDD=4.5 to 5.5 V, GND=0 V, Ta=–40 to +85°C)
Condition
Min.
Typ.
Max. Unit
0.84¥VDD —
—
—
V
"L" input voltage
VIL
—
—
—
0.17¥VDD
V
"H" output voltage
VOH
IOH=–1 mA
4.6
—
—
V
"L" output voltage
VOL
IOL=2 mA
—
—
0.4
V
"H" input current 1
IIH1
VIH=VDD
—
—
10
mA
"H" input current 2
IIH2
90
200
mA
IIL1
Internal pull-down resistance
VIL=GND
30
"L" input current 1
–10
—
—
mA
IIL2
Internal pull-up resistance
–200
–90
–30
mA
IDD
fOSC=4.096 MHz, No load
—
6
10
mA
Ta=–40°C to +50°C
—
—
10
mA
Ta=–40°C to +85°C
—
—
30
mA
"L" input current 2
(note)
Operating power consumption
Standby power consumption
IDS
DC Characteristics
(VDD=2.4 to 3.6 V, GND=0 V, Ta=–40 to +85°C)
Parameter
"H" input voltage
VIH
Condition
—
Max.
—
Unit
"L" input voltage
VIL
—
—
—
0.17¥VDD
"H" output voltage
VOH
IOH=–1 mA
V
2.6
—
—
"L" output voltage
V
VOL
IOL=2 mA
—
—
0.4
"H" input current 1
V
IIH1
VIH=VDD
—
—
10
mA
"H" input current 2
IIH2
10
30
100
mA
"L" input current 1
IIL1
Internal pull-down resistance
VIL=GND
–10
—
—
mA
"L" input current 2
IIL2
Internal pull-up resistance
–100
–30
–10
mA
Operating power consumiption
IDD
fOSC=4.096 MHz, No load
—
4
7
mA
Ta=–40°C to +50°C
—
—
5
mA
Ta=–40°C to +85°C
—
—
20
mA
Standby power consumption
Symbol
IDS
Min.
Typ.
0.84¥VDD —
V
LPF driving resistance
RAOUT
When LPF output is selected
50
—
—
kW
LPF output impedance
RLPF
IF=100 mA
—
1
3
kW
16/45
¡ Semiconductor
APPLICATION CIRCUITS
SW2
SW3
XT/CR
RND
A0
FEDL6650-03
MSM6650 Family
OSC1
A2
OSC3
OSC2
A1
MSM6652/53/54/55/56
MSM6652A/53A/54A/55A/56A/58A
MSM66P54/P56
TEST
AOUT
SW0
SW1
GND
17/45
Application Circuit in Standalone Mode Supporting 15 Switch-Selected Phrases
VDD
(MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx, MSM66P54/P56-xx)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FEDL6650-03
¡ Semiconductor
MSM6650 Family
(MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx, MSM66P54/P56-xx)
VDD
S3
S2
S1
SW0
MSM6652/53/54/55/56
MSM6652A/53A/54A/55A/56A/58A
MSM66P54/P56
S4
VDD
SW1
SW2
SW3
TEST
RND
XT/CR
A0
A1
AOUT
OSC3
OSC2
OSC1
A2
GND
Application Circuit in Standalone Mode Supporting Four Switch-Selected Words
Switches and Playback Addresses
A2
A1
A0
SW3
SW2
SW1
SW0
ADR
S1
0
0
0
0
0
0
1
01
S2
0
0
0
0
0
1
0
02
S3
0
0
0
0
1
0
0
04
S4
0
0
0
1
0
0
0
08
18/45
SW1
RA15
A15
RA0
A0
D7
O7
SW3
SW2
FEDL6650-03
DGND AGND
CE
GND
MSM6650 Family
OSC1
A2
OSC3
OSC2
A1
O0
OE
XT/CR
D0
TEST1,3
RND
CE
A0
MSM27C512
AOUT
MSM6650
VPP
¡ Semiconductor
SW0
AVDD
VCC
DVDD
19/45
Application Circuit in Standalone Mode Supporting 15 Switch-Selected Phrases
(MSM6650)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CE
AOUT
RA18
SW0 RA17
SW1
RA16
SW2
SW3
VPP
OE
A16
VDD
VDD
A0
O7
O7
O7
O7
O0
O0
O0
O0
CE
GND
CE
GND
CE
GND
20/45
FEDL6650-03
GND
MSM6650 Family
CE
VDD
MSM27C101
A0
VPP
OE
A16
MSM27C101
A0
VPP
OE
A16
MSM27C101
DGND AGND
A0
VPP
OE
A16
MSM27C101
RA0
TEST1
TEST3
D7
RND
TEST2
STBY
D0
XT/CR
CPU OSC3
A0
OSC2
A1
OSC1
A2
VDD
¡ Semiconductor
AVDD
(MSM6650)
DVDD
74HC139
MSM6650
Application Circuit in Standalone Mode Supporting Four 1-Mbit EPROMs
2G
1B 1Y3
1Y2
1Y1
1A 1Y0
1G
FEDL6650-03
¡ Semiconductor
MSM6650 Family
MICROCONTROLLER INTERFACE MODE
FEATURES
Device name
Maximum playback time (sec)
Data ROM
size
fSAM=4.0 kHz fSAM=6.4 kHz fSAM=8.0 kHz fSAM=16 kHz fSAM=32 kHz
MSM6652, 6652A
288 Kbits
16.9
10.5
8.4
4.2
2.1
MSM6653, 6653A
544 Kbits
31.2
19.5
15.6
7.8
3.9
MSM6654, 6654A
1 Mbit
63.8
39.9
31.9
15.9
7.9
MSM6655, 6655A
1.5 Mbits
96.5
60.3
48.2
24.1
12.0
MSM6656, 6656A
2 Mbits
129.1
80.7
64.5
32.2
16.1
MSM6658A
4 Mbits
259.7
162.9
129.8
64.9
32.4
MSM66P54
1 Mbit
63.8
39.9
31.9
15.9
7.9
MSM66P56
2 Mbit
129.1
80.7
64.5
32.2
16.1
MSM6650
64 Mbits (Max)
4194.3
2620.5
2096.4
1048.2
524.1
Note: Actual voice ROM area is smaller by 22 Kbits.
• 4-bit ADPCM or 8-bit PCM sound generation
• Melody function
• Edit ROM function
• Two-channel mixing function
• Fade-out function via four-step sound volume attenuation
• Serial input or parallel input selectable
• Built-in beep tone of 0.5 kHz, 1.0 kHz, 1.3 kHz, or 2.0 kHz selectable with a specific code
• Sampling frequency of 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.6 kHz, 12.8 kHz, 16.0 kHz, or 32.0 kHz
(32 kHz sampling is not possible when using RC oscillation)
• Up to 127 phrases
• Built-in 12-bit D/A converter
• Built-in –40 dB/octave low-pass filter
• Standby function
• Package options:
18-pin plastic DIP (DIP18-P-300-2.54)
(Product name: MSM6652-xxxRS/MSM6653-xxxRS/
MSM6654-xxxRS/MSM6655-xxxRS/
MSM6656-xxxRS/MSM6652A-xxxRS/
MSM6653A-xxxRS/MSM6654A-xxxRS/
MSM6655A-xxxRS/MSM6656A-xxxRS/
MSM6658A-xxxRS)
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name:MSM6652-xxxGS-K/MSM6653-xxxGS-K/
MSM6654-xxxGS-K/MSM6655-xxxGS-K/
MSM6656-xxxGS-K/MSM6652A-xxxGS-K/
MSM6653A-xxxGS-K/MSM6654A-xxxGS-K/
MSM6655A-xxxGS-K/MSM6656A-xxxGS-K/
MSM6658A-xxxGS-K/MSM66P54-01GS-K/
MSM66P54-02GS-K/MSM66P56-01GS-K/
MSM66P56-02GS-K)
20-pin plastic DIP (DIP20-P-300-2.54-W1) (Product name: MSM66P54-01RS/MSM66P54-02RS/
MSM66P56-01RS/MSM66P56-02RS)
64-pin plastic QFP (QFP64-P-1420-1.00-BK)(Product name: MSM6650GS-BK)
64-pin plastic SDIP (SDIP64-P-750-1.778) (Product name: MSM6650SS)
21/45
ST
CMD
I/O
Interface
BUSY
NAR
16-Bit (MSM6652/52A)
17-Bit (MSM6653/53A)
17-Bit (MSM6654/54A)
18-Bit (MSM6655/55A)
18-Bit (MSM6656/56A)
19-Bit (MSM6658A)
Address Counter
DATA
Controller
8
ADPCM
Synthesizer
¡ Semiconductor
CH
7
16-Bit (MSM6652/52A)
17-Bit (MSM6653/53A)
17-Bit (MSM6654/54A)
18-Bit (MSM6655/55A)
18-Bit (MSM6656/56A)
19-Bit (MSM6658A)
Multiplexer
BLOCK DIAGRAMS
Address &
Command
Controller
(MSM6652/52A)
(MSM6653/53A)
(MSM6654/54A)
(MSM6655/55A)
(MSM6656/56A)
(MSM6658A)
ROM
(Containing 22-Kbit Phrase Control
Table & Phrase Address Table)
MSM6652/53/54/55/56-xxx
MSM6652A/53A/54A/55A/56A/58A-xxx
I6/SD
I5/SI
I4
I3/PORT1
I2/PORT0
I1
I0
288-Kbit
544-Kbit
1-Mbit
1.5-Mbit
2-Mbit
4-Mbit
PCM
Synthesizer
12
Melody
Generator
12-Bit
DAC
BEEP Tone
Generator
LPF
XT
OSC
Timing Controller
VDD
GND
AOUT
FEDL6650-03
22/45
RESET
MSM6650 Family
XT
Program Circuit
I6/SD
I5/SI
I4
I3/PORT1
I2/PORT0
I1
I0
Address &
Command
Controller
7
1-Mbit OTP ROM (MSM66P54-xx)
2-Mbit OTP ROM (MSM66P56-xx)
17-Bit (MSM66P54-xx)
18-Bit (MSM66P56-xx)
Multiplexer
(Containing 22-Kbit Phrase Control
Table & Phrase Address Table)
¡ Semiconductor
MSM66P54/P56-xx
PGM
VPP
8
ADPCM
Synthesizer
CH
ST
CMD
I/O
Interface
DATA
Controller
17-Bit (MSM66P54-xx)
18-Bit (MSM66P56-xx)
Address Counter
PCM
Synthesizer
BUSY
NAR
12
Melody
Generator
12-Bit
DAC
XT
Timing Controller
OSC
23/45
RESET
VDD
GND
LPF
AOUT
FEDL6650-03
BEEP Tone
Generator
MSM6650 Family
XT
CH
ST
CMD
CE
RCS
BUSY
NAR
IBUSY
STANDBY
D7
D0
8-Bit LATCH
Address &
Switching
Controller
7
23-Bit Multiplexer
¡ Semiconductor
I6/SD
I5/SI
I4
I3/PORT1
I2/PORT0
I1
I0
RA0
MSM6650
RA22
8
DATA
Controller
23-Bit Address
Counter
ADPCM
Synthesizer
PCM
Synthesizer
I/O
Interface
12
Melody
Generator
12-Bit
DAC
BEEP Tone
Generator
LPF
XT
XT
OSC
Timing Controller
RESET CPU TEST2 SERIAL DVDD DGND
AGND AVDD AOUT
FEDL6650-03
24/45
TEST1
MSM6650 Family
MCK
FEDL6650-03
¡ Semiconductor
MSM6650 Family
PIN CONFIGURATION (TOP VIEW)
The MSM66P54/P56-xx has two more pins than the MSM6652-6658A while their pin configurations
are identical.
The additional two pins (VPP, PGM) of the MSM66P54/P56-xx may be open at playback after
completion of writing.
MSM6652-6658A (Mask ROM)
MSM66P54/P56 (OTP)
I4
1
18 I3/PORT1
VPP
1
20 PGM
I5/SI
2
17 I2/PORT0
I4
2
19 I3/PORT1
I6/SD
3
16 I1
I5/SI
3
18 I2/PORT0
CH
4
15 I0
I6/SD
4
17 I1
CH
5
16 I0
RESET
6
15 ST
12 XT
BUSY
7
14 CMD
8
11 XT
NAR
8
13 XT
9
10 VDD
AOUT
9
12 XT
RESET
5
14 ST
BUSY
6
13 CMD
NAR
7
AOUT
GND
GND 10
18-Pin Plastic DIP
11 VDD
20-Pin Plastic DIP
MSM6652-xxxRS, MSM6653-xxxRS, MSM6654-xxxRS,
MSM6655-xxxRS, MSM6656-xxxRS, MSM6652A-xxxRS,
MSM6653A-xxxRS, MSM6654A-xxxRS, MSM6655A-xxxRS,
MSM6656A-xxxRS, MSM6658A-xxxRS
MSM66P54-01/-02RS
MSM66P56-01/-02RS
MSM6652-6658A (Mask ROM)
MSM66P54/P56 (OTP)
VDD
1
24
GND
VDD
1
24
GND
XT
2
23
AOUT
XT
2
23
AOUT
XT
3
22
NAR
XT
3
22
NAR
NC
4
21
NC
NC
4
21
NC
CMD
5
20
BUSY
CMD
5
20
BUSY
NC
6
19
NC
NC
6
19
NC
NC
7
18
NC
PGM
7
18
VPP
ST
8
17
RESET
ST
8
17
RESET
I0
9
16
CH
I0
9
16
CH
I1
10
15
I6/SD
I1
10
15
I6/SD
I2/PORT0
11
14
I5/SI
I2/PORT0
11
14
I5/SI
I3/PORT1
12
13
I4
I3/PORT1
12
13
I4
24-Pin Plastic SOP
MSM6652-xxxGS-K, MSM6653-xxxGS-K,
MSM6654-xxxGS-K, MSM6655-xxxGS-K,
MSM6656-xxxGS-K, MSM6652A-xxxGS-K,
MSM6653A-xxxGS-K, MSM6654A-xxxGS-K,
MSM6655A-xxxGS-K, MSM6656A-xxxGS-K,
MSM6658A-xxxGS-K
24-Pin Plastic SOP
MSM66P54-01/-02GS-K
MSM66P56-01/-02GS-K
25/45
¡ Semiconductor
MSM6650
,
FEDL6650-03
MSM6650 Family
13
14
15
16
17
18
19
52
53
54
56
57
58
59
60
61
62
63
55
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RA10
RA9
RA8
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
D7
D6
D5
D4
D3
D2
D1
NC
32
12
49
31
11
50
30
10
51
29
9
28
8
27
7
26
6
25
5
24
4
23
3
22
2
21
1
STANDBY
I0
I1
I2/PORT0
I3/PORT1
I4
I5/SI
I6/SD
CH
RESET
CE
RCS
D0
NC
NC
BUSY
NAR
AOUT
AGND
DGND
AVDD
DVDD
XT
XT
MCK
CMD
ST
TEST1
CPU
SERIAL
IBUSY
NC
20
64
TEST2
RA22
RA21
RA20
RA19
RA18
RA17
RA16
RA15
RA14
RA13
RA12
RA11
Product name: MSM6650GS-BK
NC : No connection
64-Pin Plastic QFP
26/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
Product name: MSM6650SS
XT
1
64
XT
MCK
2
63
DVDD
CMD
3
62
AVDD
ST
4
61
DGND
TEST1
5
60
AGND
CPU
6
59
AOUT
SERIAL
7
58
NAR
IBUSY
8
57
BUSY
NC
9
56
NC
STANDBY
10
TEST2
I0
11
55
54
I1
12
53
RA21
I2/PORT0
13
52
RA20
I3/PORT1
14
51
RA19
RA22
I4
15
50
RA18
I5/SI
16
49
RA17
I6/SD
CH
17
18
48
47
RA16
RA15
RESET
19
46
RA14
CE
20
45
RA13
RCS
21
44
RA12
D0
22
43
RA11
NC
23
42
RA10
D1
24
41
NC
D2
25
26
40
39
RA9
D3
D4
27
38
RA7
D5
28
37
RA6
D6
29
36
RA5
D7
30
35
RA4
RA0
RA1
31
34
32
33
RA3
RA2
RA8
NC : No connection
64-Pin Plastic SDIP
27/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
PIN DESCRIPTIONS
1.MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx
18-Pin plastic DIP
Pin
Symbol Type
5
RESET
I
6
BUSY
O
7
NAR
O
Description
Reset. The devices enter stanby status when a low level is input to this pin.
When RESET, oscillation stops. The AOUT output goes to ground and the IC
status is reinitialized.
This pin has an internal pull-up resistor.
Busy. Outputs a "L" level during playback and a "H" level when power is turned ON.
The CMD and ST inputs become effective when high. NAR indicates whether the
address bus (I0 through I6) is ready to accept another address. When high, it is
ready to accept. NAR goes high when power is turned ON.
Analog Speech Output. D/A converter output or LPF output is selected by
8
AOUT
O
11
XT
I
12
XT
O
Ceramic Oscillator Output. If an external clock is used, leave this pin open.
entering the command.
Ceramic Oscillator Input. This pin has an internal 0.5 to 5 MW feedback
resistor between XT and XT. If an external clock is used, this is the clock input pin.
13
CMD
I
Command Input and Option Control. This pin is used as command and
option input when CMD is at the high level with ST low. If this pin is not used or
serial input is optioned, set this pin to "H" level. This pin has an internal pull-up
resistor.
14
ST
I
Start. Speech playback starts at the fall of the ST pulse. The I0 - I6 addresses
are latched at the rise of the ST pulse. Input a ST pulse when NAR goes to the
high level for channels 1 and 2. This pin has an internal pull-up resistor.
4
CH
I
Channel Control. Channel 1 is selected when the input is pulled high. Channel 2
is selected when the input is low. This pin has an internal pull-up resistor.
3
I6/SD
I
This pin is command and user-defined phrase input when parallel input is optioned.
This pin is serial data (command and address) input when serial input is optioned.
2
I5/SI
I
1
I4
I
18
I3/PORT1
I/O
This pin is command and user-defined phrase input when parallel input is optioned.
This pin is used as serial clock input when serial input is optioned.
This pin is command and user-defined phrase input when parallel input is optioned.
When serial input is optioned, set this pin to "L" level. This pin has an internal
pull-down resistor.
This pin is command and user-defined phrase input when parallel input is optioned.
When serial input is optioned, this pin is a port output. The port output is controlled
by entering external silence insertion code.
This pin is command and user-defined phrase input when parallel input is optioned.
17
I2/PORT0
I/O
When serial input is optioned, this pin is a port output. The port output is controlled
by entering external silence insertion code.
This pin is command and user-defined phrase input when parallel input is optioned.
15, 16
I0, I1
I
When serial input is optioned, set this pin to "L" level. This pin has an internal
pull-down resistor.
9
GND
—
Ground pin.
10
VDD
—
Power supply. Insert a 0.1µF ro more bypass capacitor between this pin and GND.
28/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
2.MSM66P54/P56-xx
20-Pin plastic DIP
Pin
Symbol Type
6
RESET
I
7
BUSY
O
Description
Reset. The devices enter stanby status when a low level is input to this pin.
When RESET, oscillation stops. The AOUT output goes to ground and the IC
status is reinitialized.
This pin has an internal pull-up resistor.
Busy. Outputs a "L" level during playback and a "H" level when power is turned ON.
The CMD and ST inputs become effective when high. NAR indicates whether the
8
NAR
O
address bus (I0 through I6) is ready to accept another address. When high, it is
ready to accept. NAR goes high when power is turned ON.
Analog Speech Output. D/A converter output or LPF output is selected by
9
AOUT
O
12
XT
I
13
XT
O
Ceramic Oscillator Output. If an external clock is used, leave this pin open.
entering the command.
Ceramic Oscillator Input. This pin has an internal 0.5 to 5 MW feedback
resistor between XT and XT. If an external clock is used, this is the clock input pin.
14
CMD
I
Command Input and Option Control. This pin is used as command and
option input when CMD is at the high level with ST low. If this pin is not used or
serial input is optioned, set this pin to "H" level. This pin has an internal pull-up
resistor.
15
ST
I
Start. Speech playback starts at the fall of the ST pulse. The I0 - I6 addresses
are latched at the rise of the ST pulse. Input a ST pulse when NAR goes to the
high level for channels 1 and 2. This pin has an internal pull-up resistor.
5
CH
I
Channel Control. Channel 1 is selected when the input is pulled high. Channel 2
is selected when the input is low. This pin has an internal pull-up resistor.
4
I6/SD
I
This pin is command and user-defined phrase input when parallel input is optioned.
This pin is serial data (command and address) input when serial input is optioned.
3
I5/SI
I
2
I4
I
19
I3/PORT1
I/O
This pin is command and user-defined phrase input when parallel input is optioned.
This pin is used as serial clock input when serial input is optioned.
This pin is command and user-defined phrase input when parallel input is optioned.
When serial input is optioned, set this pin to "L" level. This pin has an internal
pull-down resistor.
This pin is command and user-defined phrase input when parallel input is optioned.
When serial input is optioned, this pin is a port output. The port output is controlled
by entering external silence insertion code.
This pin is command and user-defined phrase input when parallel input is optioned.
18
I2/PORT0
I/O
When serial input is optioned, this pin is a port output. The port output is controlled
by entering external silence insertion code.
This pin is command and user-defined phrase input when parallel input is optioned.
When serial input is optioned, set this pin to "L" level. This pin has an internal
16, 17
I0, I1
I
10
GND
—
Ground pin.
11
VDD
—
Power supply. Insert a 0.1µF ro more bypass capacitor between this pin and GND.
1
VPP
—
Supply voltage for writing data to internal OTP ROM.
20
PGM
I
pull-down resistor.
Interface with voice analysis edit tools AR203 and AR204. Set to "L" level or leave
open during playback. This pin has an internal pull-down resistor.
29/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
3.MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx, MSM66P54/P56-xx
24-Pin plastic SOP
Pin
Symbol Type
17
RESET
I
20
BUSY
O
22
NAR
O
Description
Reset. The devices enter stanby status when a low level is input to this pin.
When RESET, oscillation stops. The AOUT output goes to ground and the IC
status is reinitialized.
This pin has an internal pull-up resistor.
Busy. Outputs a "L" level during playback and a "H" level when power is turned ON.
The CMD and ST inputs become effective when high. NAR indicates whether the
address bus (I0 through I6) is ready to accept another address. When high, it is
ready to accept. NAR goes high when power is turned ON.
Analog Speech Output. D/A converter output or LPF output is selected by
23
AOUT
O
2
XT
I
3
XT
O
Ceramic Oscillator Output. If an external clock is used, leave this pin open.
entering the command.
Ceramic Oscillator Input. This pin has an internal 0.5 to 5 MW feedback
resistor between XT and XT. If an external clock is used, this is the clock input pin.
5
CMD
I
Command Input and Option Control. This pin is used as command and
option input when CMD is at the high level with ST low. If this pin is not used or
serial input is optioned, set this pin to "H" level. This pin has an internal pull-up
resistor.
8
ST
I
Start. Speech playback starts at the fall of the ST pulse. The I0 - I6 addresses
are latched at the rise of the ST pulse. Input a ST pulse when NAR goes to the
high level for channels 1 and 2. This pin has an internal pull-up resistor.
16
CH
I
Channel Control. Channel 1 is selected when the input is pulled high. Channel 2
is selected when the input is low. This pin has an internal pull-up resistor.
15
I6/SD
I
This pin is command and user-defined phrase input when parallel input is optioned.
This pin is serial data (command and address) input when serial input is optioned.
14
I5/SI
I
13
I4
I
I3/PORT1
I/O
This pin is command and user-defined phrase input when parallel input is optioned.
This pin is used as serial clock input when serial input is optioned.
This pin is command and user-defined phrase input when parallel input is optioned.
When serial input is optioned, set this pin to "L" level. This pin has an internal
pull-down resistor.
This pin is command and user-defined phrase input when parallel input is optioned.
12
When serial input is optioned, this pin is a port output. The port output is controlled
by entering external silence insertion code.
This pin is command and user-defined phrase input when parallel input is optioned.
11
I2/PORT0
I/O
When serial input is optioned, this pin is a port output. The port output is controlled
by entering external silence insertion code.
30/45
FEDL6650-03
¡ Semiconductor
Pin
MSM6650 Family
Symbol Type
Description
This pin is command and user-defined phrase input when parallel input is optioned.
When serial input is optioned, set this pin to "L" level. This pin has an internal
9, 10
I0, I1
I
24
GND
—
Ground pin.
1
VDD
—
Power supply. Insert a 0.1µF ro more bypass capacitor between this pin and GND.
18
VPP *
—
Supply voltage for writing data to internal OTP ROM.
7
PGM *
I
pull-down resistor.
*
Interface with voice analysis edit tools AR761 and AR762. Set to "L" level or leave
open during playback. This pin has an internal pull-down resistor.
Pins for MSM66P54/56-xx only
31/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
4.MSM6650
64-Pin plastic QFP (64-Pin plastic SDIP)
Pin
Symbol Type
29 (19)
RESET
I
3 (57)
BUSY
O
4 (58)
NAR
O
Description
Reset. The devices enter stanby status when a low level is input to this pin.
When RESET, oscillation stops. The AOUT output goes to ground and the IC
status is reinitalized.
This pin has an internal pull-up resistor.
Busy. Outputs a "L" level during playback and a "H" level when power is turned ON.
The CMD and ST inputs become effective when high. NAR indicates whether the
address bus (I0 through I6) is ready to accept another address. When high, it is
ready to accept. NAR goes high when power is turned ON.
Analog Speech Output. D/A converter output or LPF output is selected by
5 (59)
AOUT
O
10 (64)
XT
I
11 (1)
XT
O
Ceramic Oscillator Output. If an external clock is used, leave this pin open.
entering the command.
Ceramic Oscillator Input. This pin has an internal 0.5 to 5 MW feedback
resistor between XT and XT. If an external clock is used, this is the clock input pin.
13 (3)
CMD
I
Command Input and Option Control. This pin is used as command and
option input when CMD is at the high level with ST low. If this pin is not used or
serial input is optioned, set this pin to "H" level. This pin has an internal pull-up
resistor.
14 (4)
ST
I
Start. Speech playback starts at the fall of the ST pulse. The I0 - I6 addresses
are latched at the rise of the ST pulse. Input a ST pulse when NAR goes to the
high level for channels 1 and 2. This pin has an internal pull-up resistor.
28 (18)
CH
I
Channel Control. Channel 1 is selected when the input is pulled high. Channel 2
is selected when the input is low. This pin has an internal pull-up resistor.
27 (17)
I6/SD
I
This pin is command and user-defined phrase input when parallel input is optioned.
This pin is serial data (command and address) input when serial input is optioned.
26 (16)
I5/SI
I
25 (15)
I4
I
This pin is command and user-defined phrase input when parallel input is optioned.
This pin is used as serial clock input when serial input is optioned.
This pin is command and user-defined phrase input when parallel input is optioned.
When serial input is optioned, set this pin to "L" level. This pin has an internal
pull-down resistor.
This pin is command and user-defined phrase input when parallel input is optioned.
24 (14)
I3/PORT1
I/O
When serial input is optioned, this pin is a port output. The port output is controlled
by entering external silence insertion code.
This pin is command and user-defined phrase input when parallel input is optioned.
23 (13)
I2/PORT0
I/O
When serial input is optioned, this pin is a port output. The port output is controlled
by entering external silence insertion code.
This pin is command and user-defined phrase input when parallel input is optioned.
21, 22 (11, 12)
I0, I1
I
When serial input is optioned, set this pin to "L" level. This pin has an internal
pull-down resistor.
32/45
FEDL6650-03
¡ Semiconductor
Pin
MSM6650 Family
Description
Symbol Type
6 (60)
AGND
—
Analog ground pin.
7 (61)
DGND
—
Digital ground pin.
8 (62)
AVDD
—
Analog power pin. Insert a 0.1mF or more bypass capacitor between this pin and AGND.
9 (63)
DVDD
—
12 (2)
MCK
O
16 (6)
CPU
I
17 (7)
SERIAL
I
Digital power pin. Insert a 0.1mF or more bypass capacitor between this pin and DGND.
Main clock output pin. Use MCK as a connection pin for the MSC1192, etc.
When the IC is in standby status, MCK is held high.
CPU Mode. Set to "H" level to select Microcontroller Interface Mode.
Serial/Parallel Interface Select. This input selects either the parallel or the
serial input interface. The serial input interface is selected with a high level; the
parallel input interface is selected with a low level.
30 (20)
CE
O
31 (21)
RCS
I
D0 - D7
I
32, 34-40
(22, 24-30)
41-63
Chip Enable. CE is a timing output pin to control read of external memory. This pin outputs
when RCS is at the "L" level. This pin goes high impedance when RCS is at the "H" level.
Read Chip Select. The data bits D0-D7 are internally pulled down when RCS is high.
External Memory Data Bus. Data is input when RCS is low. When RCS is high,
these pins become low due to internal pull-down resistors.
External Memory Address. These are address pins for an external memory output
RA0 - RA22
O
TEST1, 2
I
Test. Set these pins to "H" level.
18 (8)
IBUSY
O
Outputs a "L" level during playback or when AOUT is at 1/2 VDD (except standby conversion)
20 (10)
STANDBY
O
Outputs a "L" level during which the device is oscillating.
(31-40, 42-54)
15, 64
(5, 55)
when RCS is low. These pins become high impedance status if RCS is in "H" level.
33/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
ABSOLUTE MAXIMUM RATINGS
(GND=0 V)
Parameter
Power supply voltage
Symbol
VDD
Input voltage
VIN
Storage temperature
TSTG
Condition
Ta = 25°C
—
Rating
Unit
–0.3 to +7.0
V
–0.3 to VDD+0.3
V
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
(GND=0 V)
Parameter
Symbol
Condition
Range
Unit
2.4 to 5.5
V
MSM6658A, MSM66P54/P56
3.5 to 5.5
V
—
–40 to +85
MSM6652-56, MSM6650,
Power supply voltage
VDD
Operating temperature
Top
Master clock frequency
fOSC
MSM6652A-56A
—
°C
Min.
Typ.
Max.
3.5
4.096
4.5
MHz
34/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD=4.5 to 5.5 V, GND=0 V, Ta=–40 to +85°C)
Min.
Typ.
Max. Unit
0.84¥VDD —
—
V
Parameter
High level input voltage
Symbol
VIH
Condition
—
Low level input voltage
VIL
—
—
—
High level output voltage
VOH
IOH=–1 mA
4.6
Low level output voltage
VOL
IOL=2 mA
—
High level input current 1
IIH1
VIH=VDD
—
High level input current 2
IIH2
30
IIL1
Internal pull-down resistor
VIL=GND
–10
IIL2
Internal pull-up resistor
–200
IDD
fOSC=4.096 MHz, No load
—
Ta=–40°C to +50°C
—
Low level input current 1
Low level input current 2
*1
Operating current
Standby current
IDS
0.17¥VDD
V
—
—
V
—
0.4
V
—
10
mA
90
200
mA
—
—
mA
–90
–30
mA
6
10
mA
—
10
mA
Ta=–40°C to +85°C
—
—
30
mA
When D/A output selected
When D/A output selected *2
—
15
—
25
40
35
mV
kW
When D/A output selected *3
15
30
45
kW
RAOUT
When LPF output selected
50
—
—
kW
RLPF
IF=100 mA
—
1
3
kW
D/A output relative accuracy
|VDAE|
D/A output impedance
RDAO
LPF driving resisance
LPF output impedance
*1. Applied to RESET, CMD, ST, CH.
*2. Applied to MSM6652/53/54/55/56, MSM6652A/53A/54A/55A/56A/58A, MSM6650.
*3. Applied to MSM66P54/P56.
DC Characteristics
(VDD=2.4 to 3.6 V, GND=0 V, Ta=–40 to +85°C)
Parameter
High level input voltage
Symbol
VIH
Condition
—
Low level input voltage
VIL
—
—
—
High level output voltage
VOH
IOH=–1 mA
2.6
Low level output voltage
VOL
IOL=2 mA
—
High level input current 1
IIH1
VIH=VDD
—
High level input current 2
IIH2
Low level input current 1
IIL1
Internal pull-down resistor
VIL=GND
10
–10
Low level input current 2 (Note)
IIL2
Internal pull-up resistor
–100
Operating current
IDD
fOSC=4.096 MHz, No load
—
Ta=–40°C to +50°C
—
Standby current
IDS
D/A output relative accuracy
|VDAE|
D/A output impedance
Min.
Typ.
0.84¥VDD —
Max.
—
Unit
0.17¥VDD
V
—
—
V
—
0.4
V
—
10
mA
30
100
mA
—
—
mA
–30
–10
mA
4
7
mA
—
5
mA
V
Ta=–40°C to +85°C
—
—
20
mA
When D/A output selected
—
—
20
mV
RDAO
When D/A output selected
15
25
35
kW
LPF driving resistance
RAOUT
When LPF output selected
50
—
—
kW
LPF output impedance
RLPF
IF=100 mA
—
1
3
kW
Note: Applied to RESET, CMD, ST, CH.
35/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
APPLICATION CIRCUITS
P1.0
I6/SD
P1.1
I5/SI
P1.2
ST
P2.0
RESET
P3.0
NAR
XT
RESET
XT
VDD
MSM6652/53/54/55/56
MSM6652A/53A/54A/55A/56A/58A
MSM66P54/P56
MSM83C154
(MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx, MSM66P54/P56-xx)
GND
CH
CMD
PORT0
PORT1
AOUT
AMP
I4
I1
I0
Application Circuit in Serial Input Interface Mode
36/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
I6
I5
I4
I3
I2
I1
I0
P2.0
CH
P3.1
CMD
P2.2
ST
P2.1
RESET
P3.0
NAR
XT
VDD
MSM6652/53/54/55/56
MSM6652A/53A/54A/55A/56A/58A
MSM66P54/P56
MSM83C154
(MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx, MSM66P54/P56-xx)
AOUT
RESET
XT
AMP
GND
Application circuit in Parallel Input Interface Mode
37/45
74HC139
1Y3
1Y2
1Y1
1Y0
DVDD
VPP
OE
A16
VDD
VPP
OE
RA16
A16
A16
RA0
A0
A0
A0
A0
D7
O7
O7
O7
O7
D0
XT
O0
O0
O0
O0
VDD
MSM27C101
RCS
I4
A16
VDD
MSM27C101
CH
CMD
TEST1
TEST2
CPU
SERIAL
VPP
OE
MSM27C101
ST
NAR
VDD
MSM27C101
RESET
I6/SD
I5/SI
VPP
OE
MSM6650
RESET
P2.0
P1.0
P1.1
P1.2
P3.0
AVDD
CE
RA18
RA17
AOUT
MSM83C154
XT
I1
I0 DGND AGND
CE
GND
CE
GND
CE
GND
CE
GND
FEDL6650-03
38/45
MSM6650 Family
Application Circuit in Microcontroller Interface Mode
Using Four 1-Mbit EPROMs (Serial Input Interface)
1G
¡ Semiconductor
1A
(MSM6650)
1B
2G
1A
74HC139
1Y3
1Y2
1Y1
1Y0
DVDD
VDD
VPP
OE
RA16
A16
RA0
A0
A0
A0
A0
D7
O7
O7
O7
O7
D0
XT
O0
O0
O0
O0
A16
A16
VDD
VPP
OE
A16
MSM27C101
CH
ST
CMD
NAR
VDD
VPP
OE
MSM27C101
P2.1
P2.0
P3.1
P1.0
VDD
VPP
OE
MSM27C101
AOUT
RESET
I6/SD
I5/SI
I4
I3
I2
I1
I0
CE
RA18
RA17
MSM27C101
P2.0
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P3.0
AVDD
MSM6650
MSM83C154
RESET
TEST1
TEST2
CPU
RCS
SERIAL
XT
CE
GND
CE
GND
CE
GND
CE
GND
39/45
FEDL6650-03
DGND AGND
MSM6650 Family
Application Circuit in Microcontroller Interface Mode
Using Four 1-Mbit EPROMs (Parallel Input Interface)
1G
¡ Semiconductor
2G
(MSM6650)
1B
FEDL6650-03
¡ Semiconductor
MSM6650 Family
PACKAGE DIMENSIONS
(Unit : mm)
DIP18-P-300-2.54
Oki Electric Industry Co., Ltd.
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
1.30 TYP.
2/Dec. 11, 1996
40/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Oki Electric Industry Co., Ltd.
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
0.58 TYP.
5/Oct. 13, 1998
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
41/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
(Unit : mm)
DIP20-P-300-2.54-W1
Oki Electric Industry Co., Ltd.
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
1.50 TYP.
2/Dec. 11, 1996
42/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
(Unit : mm)
QFP64-P-1420-1.00-BK
Mirror finish
Oki Electric Industry Co., Ltd.
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
1.25 TYP.
4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
43/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
(Unit : mm)
SDIP64-P-750-1.778
Oki Electric Industry Co., Ltd.
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
Cu alloy
Solder plating (≥5 mm)
8.70 TYP.
2/Dec. 11, 1996
44/45
FEDL6650-03
¡ Semiconductor
MSM6650 Family
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
Copyright 2000 Oki Electric Industry Co., Ltd.
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