OKI MSMQ587 Built-in 16 bit pwm and 8 bit a/d converter, high-speed high-preformance 16 bit microcontroller Datasheet

E2E1033 -27-Y6
Pr
el
im
This
version:
Jan.
1998
MSM66585/586/587/P587/Q587 ina
ry
Previous version: Nov. 1996
¡ Semiconductor
MSM66585/586/587/P587/Q587
¡ Semiconductor
Built-in 16 bit PWM and 8 bit A/D Converter, High-speed High-preformance 16 bit
Microcontroller
GENERAL DESCRIPTION
MSM66585/586/587 are high-performance CMOS 16-bit microcontrollers that integrate a 16bit CPU, ROM, RAM, 8-bit A/D converter, serial port, timers, and PWM. They also allow ROM
and RAM to be expanded externally.
The MSM66P587 is of OTP (One-Time PROM) version and the MSM66Q587 is of Flash EEPROM
version.
FEATURES
• Powerful instruction set
Instruction set superior in orthogonal matrics
8/16-bit arithmetic instructions
Multiply/divide instructions
Bit manipulation instructions
Bit logical operation instructions
ROM table reference instructions
• Abandant addressing modes
Register addressing
Page addressing
Pointer register indirect addressing
Stack addressing
Immediate addressing
• Minimum instruction cycle
100 ns at 20 MHz (4.5V-5.5V)
200 ns at 10 MHz (2.7V-5.5V)
• Program memory (ROM)
Internal: 64 KB (M66587/M66P587/M66Q587), 48 KB (M66585/586)
External: 1 MB, EA pin active
• Data memory (RAM)
Internal: 2 KB
External: 1022 KB
• I/O ports
Analog input-only port: 4 lines (test pins for M66585)
Input/output port:
Maximum 80 lines (40 lines with programmable pull-up)
• Timers
Free-running counter:
16-bit ¥ 1
Realtime output:
16-bit ¥ 2
General autoreload timer: 8-bit ¥ 1
• 16-bit PWM
Input clock divider:
1 divider
• 8-bit serial port
Synchronous with BRG: 1 port
1/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
• A/D converter
8-bit resolution:
4 channels
• Interrupts
Non-maskable:
1 interrupt
Maskable:
9 internal, 4 external (12 vectors)
3-level priority
• ROM window function
• Standby modes
Halt mode
Stop mode
• Package
100-pin TQFP (TQFP100-P-1414-0.50-K) (Product name : MSM66585TS-K)
(Product name : MSM66586TS-K)
(Product name : MSM66587TS-K)
(Product name : MSM66P587TS-K)
(Product name : MSM66Q587TS-K)
2/24
RAM
2 KB
SSP
PSW
LRB
PC
DSR TSR CSR
P6_2/RXD1
P6_3/TXD1
P6_4/RXC1
P6_5/TXC1
P7_4/PWM0
VREF
AGND
AI0
Memory Control
Pointing R
Local R.
*1
ROM
64 KB
Serial Port
Instruction
Decoder
PWM
Port Control
P12
P10
P9
P8
P7
P6
P5
P4
P2
P1
P0
RES
OSC1
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MSM66585/586/587/P587/Q587
System Control
Interrupt
Peripheral
A8/P1_0
A19/P9_3
Event Timer
OSC0
P6_0/INTO
P6_1/INT1
P12_2/INT2
P12_3/INT3
NMI
P7_3/CLKOUT
AD7/P0_7
ALU Control
ACC
AI3
P4_0/ETMCK
AD0/P0_0
A15/P1_7
A16/P9_0
ALU
*2
A to D
Converter
¡ Semiconductor
CPU Core
Control
Registers
BLOCK DIAGRAM
16-bit RTO/PWM
Timer
Bus Port Control
*1. 48KB for M66585 and M66586.
*2. M66585 has no internal A/D converter.
P2_4/RT08
P2_5/RTO9
EA
ALE/P5_5
PSEN/P5_4
RD/P7_1
WR/P7_0
WAIT/P7_2
¡ Semiconductor
MSM66585/586/587/P587/Q587
76 P9_7
77 P2_0
78 P2_1
79 P2_2
80 P2_3
81 P2_4/RT08
82 P2_5/RT09
83 P2_6
84 P2_7
85 P10_0
86 P10_1
87 P10_2
88 P10_3
89 P10_4
90 P10_5
91 P10_6
92 P10_7
93 VDD
94 GND
95 P6_0/INT0
96 P6_1/INT1
97 P6_2/RXD1
98 P6_3/TXD1
12_0
1
75 P9_6
P12_1
2
74 P9_5
INT2/P12_2
3
73 P9_4
INT3/P12_3
4
72 P9_3/A19
P12_4
5
71 P9_2/A18
P12_5
6
70 P9_1/A17
P12_6
7
69 P9_0/A16
P12_7
8
68 GND
VDD
9
*(VDD) VREF 10
67 VDD
66 P1_7/A15
(GND) AGND 11
65 P1_6/A14
(TEST0) AI0 12
64 P1_5/A13
(TEST1) AI1 13
63 P1_4/A12
(TEST2) AI2 14
62 P1_3/A11
(TEST3) AI3 15
61 P1_2/A10
GND 16
60 P1_1/A9
VDD 17
59 P1_0/A8
42
43
44
45
46
47
48
P7_6
P7_5
PWM0/P7_4
CLKOUT/P7_3
WAIT/P7_2
RD/P7_1
WR/P7_0
ALE/P5_5 50
41
P7_7
P5_4PSEN/P5_4 49
40
GND
36
EA
39
35
NMI
OSC1
34
RES
38
33
P8_7
OSC0
32
P8_6
VDD 37
31
P8_5
51 P0_0/AD0
30
52 P0_1/AD1
P4_7 25
P8_4
53 P0_2/AD2
P4_6 24
29
54 P0_3/AD3
P4_5 23
P8_3
55 P0_4/AD4
P4_4 22
28
56 P0_5/AD5
P4_3 21
P8_2
57 P0_6/AD6
P4_2 20
26
58 P0_7/AD7
P4_1 19
P8_1 27
ETMCK/P4_0 18
P8_0
*
99 P6_4/RXC1
100 P6_5/TXC1
PIN CONFIGURATION (TOP VIEW)
For MSM66585, pin name is in parentheses ( ).
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¡ Semiconductor
MSM66585/586/587/P587/Q587
PIN DESCRIPTIONS
Symbol
P0_0-P0_7/
AD0-AD7
P1_0-P1_7/
A8-A15
Type
Description
I/O
Port 0 is 8 input/output pins. Input or output can be specified for each bit with the
Port 0 Mode Register (P0IO). Pull-up resistors can be specified for each bit with the
Port 0 Pull-Up Register (P0PUP).
These pins also function as time-multiplexed address outputs and data input/output
pins (AD0-AD7) when accessing memory that has been expanded externally
(program or data memory).
After reset (by RES signal input, BRK instruction execution, or op code trap), P0 will
be high-impedance inputs.
I/O
Port 1 is 8 input/output pins. Input or output can be specified for each bit with the
Port 1 Mode Register (P1IO). Pull-up resistors can be specified for each bit with the
Port 1 Pull-Up Register (P1PUP).
P1_0-P1_7 also have a secondary function as input/output pins for internal operation.
Their secondary function can be set for each bit with the Port 1 Secondary Function
Control Register (P1SF). The input/output settings by P1IO will be ignored for pins
that have been set to the secondary function by P1SF.
These pins function as output pins for address A8-A15 when accessing program
memory or data memory that has been expanded externally. When the EA pin is low,
A8-A15 will be output regardless of P1SF settings.
After reset (by RES signal input, BRK instruction execution, or op code trap), P1 will
be high-impedance inputs.
I/O
P2_4 and P2_5 also have a secondary function as input/output pins for internal operation.
Their secondary function can be set for each bit with the Port 2 Secondary Function
Control Register (P2SF). The input/output settings of P2IO will be ignored for pins
that have been set to the secondary function by P2SF.
These pins output a previously set level when the value of Timer Registers 8 and 9
match a selected counter value.
After reset (by RES signal input, BRK instruction execution, or op code trap), P2 will
be high-impedance inputs.
I/O
Port 4 is 8 input/output pins. Input or output can be specified for each bit with the
Port 4 Mode Register (P4IO). Pull-up resistors can be specified for each bit with the
Port 4 Pull-Up Register (P4PUP).
P4_0 also has a secondary function as an input pin for internal operation. Its secondary
function can be set for the bit with the Port 4 Secondary Function Control Register (P4SF).
The input/output settings by P4IO will be ignored for pins that have been set to the
secondary function by P4SF.
This is the external clock input pin for the counter of a general 8-bit timer.
After reset (by RES signal input, BRK instruction execution, or op code trap), P4 will
be high-impedance inputs.
I/O
Port 5 is 2 input/output pins. Input or output can be specified for each bit with the
Port 5 Mode Register (P5IO).
P5_4 and P5_5 also have a secondary function as output pins for internal operation.
Their secondary function can be set for each bit with the Port 5 Secondary Function
Control Register (P5SF). The input/output settings of P5IO will be ignored for pins
that have been set to the secondary function by P5SF.
PSEN (P5_4):
This pin outputs the strobe signal for read operations when external program memory
is accessed. Operation will automatically switch to the secondary function when the
EA pin is low. This pin will be pulled up when both the EA pin and RESET pin are low.
ALE (P5_5):
This pin outputs the strobe for externally latching the lower 8 address bits output from
P0 when external memory is accessed. Operation will automatically switch to the
secondary function when the EA pin is low. This pin will be pulled up when both the
EA pin and RESET pin are low.
After reset (by RES signal input, BRK instruction execution, or op code trap), P5 will
be high-impedance inputs.
P2_0-P2_3
P2_4-P2_5/
RT08-RT09
P2_6-P2_7
P4_0/ETMCK
P4_1-P4_7
P5_4/PSEN
P5_5/ALE
5/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
PIN DESCRIPTIONS (Continued)
Symbol
Type
Description
I/O
Port 6 is 6 input/output pins. Input or output can be specified for each bit with the
Port 6 Mode Register (P6IO).
P6_0-P6_5 also have a secondary function as input/output pins for internal operation.
Their secondary function can be set for each bit with the Port 6 Secondary Function
Control Register (P6SF). The input/output settings of P6IO will be ignored for pins
that have been set to the secondary function by P6SF.
INT0 (P5_0), INT1 (P6_1):
These pins input external interrupts 0 and 1.
RXD1 (P6_2):
This pin inputs receive data to the Serial Port 1 receive circuit.
TXD1 (P6_3):
This pin outputs transmit data to the Serial Port 1 transmit circuit.
RXC1 (P6_4):
This pin outputs the shift clock when the Serial Port 1 receive circuit is in master mode.
It inputs the shift clock when the receive circuit is in slave mode.
TXC1 (P6_4):
This pin outputs the shift clock when the Serial Port 1 transmit circuit is in master mode.
It inputs the shift clock when the transmit circuit is in slave mode.
After reset (by RES signal input, BRK instruction execution, or op code trap), P6 will be
high-impedance inputs.
P7_0/WR
P7_1/RD
P7_2/WAIT
P7_3/CLKOUT
P7_4/PWM0
P7_5-P7_7
I/O
Port 7 is 8 input/output pins. Input or output can be specified for each bit with the
Port 7 Mode Register (P7IO).
P7_0-P7_4 also have a secondary function as input/output pins for internal operation.
Their secondary function can be set for each bit with the Port 7 Secondary Function
Control Register (P7SF). The input/output settings of P7IO will be ignored for pins
that have been set to the secondary function by P7SF.
WR (P7_0):
This pin outputs the strobe signal for write operations when external data memory
is accessed.
RD (P7_1):
This pin outputs the strobe signal for read operations when external data memory
is accessed.
WAIT (P7_2):
This pin inputs a wait to the internal CPU when external data memory with a slow
access time is accessed. CPU is driven to "WAIT" state during WAIT pin high.
CLKOUT (P7_3):
This pin outputs the clock pulses set by the Peripheral Control Register (PRPHF).
PWM0 (P7_4):
This pin outputs PWM0.
After reset (by RES signal input, BRK instruction execution, or op code trap), P7 will
be high-impedance inputs.
When P7_0 and P7_1 are used as their secondary functions (WR, RD), they need to
be connected externally to pull-up resistors.
P8_0-P8_7
I/O
Port 8 is 8 input/output pins. Input or output can be specified for each bit with the
Port 8 Mode Register (P8IO).
After reset (by RES signal input, BRK instruction execution, or op code trap), P8 will
be high-impedance inputs.
P6_0/INT0
P6_1/INT1
P6_2/RXD1
P6_3/TXD1
P6_4/RXC1
P6_5/TXC1
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¡ Semiconductor
MSM66585/586/587/P587/Q587
PIN DESCRIPTIONS (Continued)
Symbol
Type
Description
I/O
Port 9 is 8 input/output pins. Input or output can be specified for each bit with the
Port 9 Mode Register (P9IO). Pull-up resistors can be specified for each bit with the
Port 9 Pull-Up Register (P9PUP).
P9_0-P9_3 also have a secondary function as output pins for internal operation.
Their secondary function can be set for each bit with the Port 9 Secondary Function
Control Register (P9SF). The input/output settings of P9IO will be ignored for pins
that have been set to the secondary function by P9SF.
A16-A19 (P9_0-P9_3):
These pins function as output pins for address A16-A19 when accessing program
memory or data memory that has been expanded externally. Note that program
memory address A16-A19 will be output even when accessing data memory that has
been expanded externally. When the EA pin is low and program memory that has
been expanded externally is accessed, A16-A19 will be output regardless of P9SF
settings.
After reset (by RES signal input, BRK instruction execution, or op code trap), P9 will
be high-impedance inputs.
I/O
Port 10 is 8 input/output pins. Input or output can be specified for each bit with the
Port 10 Mode Register (P10IO). Pull-up resistors can be specified for each bit with
the Port 10 Pull-Up Register (P10PUP).
After reset (by RES signal input, BRK instruction execution, or op code trap), P10 will
be high-impedance inputs.
P12_0-P12_1
P12_2-P12_3/
INT2-INT3
P12_4-P12_7
I/O
Port 12 is 8 input/output pins. Input or output can be specified for each bit with the
Port 12 Mode Register (P12IO).
P12_2 and P12_3 also have a secondary function as input pins for internal operation.
Their secondary function can be set for each bit with the Port 12 Secondary Function
Control Register (P12SF). The input/output settings of P12IO will be ignored for pins
that have been set to the secondary function by P12SF.
INT2 (P12_2), INT3 (P12_3):
These pins input external interrupts 2 and 3.
After reset (by RES signal input, BRK instruction execution, or op code trap), P12 will
be high-impedance inputs.
AI0-AI3
I
P9_0P9_3/
A16-A19
P9_4-P9_7
P10_0-P10_7
These are analog input pins for the A/D converter (test pins for MSM66585).
VREF
I
This is the reference voltage pin for the A/D converter (VDD for MSM66585).
AGND
I
This is the ground input pin for the A/D converter (GND for MSM66585).
OSC0
I
OSC1
O
This pins connect to a crystal oscillator, ceramic oscillator, or capacitors for base clock
oscillation. When the base clock is to be supplied externally, it should be input on the
OSC0 pin with the OSC1 pin left open.
NMI
I
This input pin requests a non-maskable interrupt.
RES
I
This is an active-low reset input pin.
EA
I
When this pin is high, program addresses 0H-FFFFH will access internal program
memory and program addresses 10000H-FFFFFH will access external program memory.
To access external program memory, P1, P5, and P9 must be set with their secondary
function control registers.
When this pin is low, all program addresses will access external program memory.
VDD
I
These are voltage pins. All VDD pins (9, 17, 37, 67, 93) should be connected to the
supply voltage (for MSM66585 connect pins 9, 10, 17, 37, 67, 93).
GND
I
These are ground pins. All GND pins (16, 40, 68, 94) should be connected to ground
(for MSM66585 connect pins 11, 16, 40, 68, 94).
7/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
MEMORY MAP
Program Area
Segment 0
Segment 1 to 15
0000H
0000H
Vector table area
74 bytes
0049H
004AH
0069H
006AH
0071H
0072H
VCAL table area
32 bytes
Internal ROM area
External ROM area
Vector table area
8 bytes
0FFFH
1000H
ACAL area
2 KB
0FFFH
1000H
17FFH
1800H
17FFH
1800H
FFFFH
FFFFH
ACAL area
2 KB
* For M66585 and M66586 addresses 0C000H to 0FFFFH of segment 0 are external ROM area.
8/24
FFFFH
7FFFH
8000H
0FFFH
1000H
09FFH
0A00H
00FFH
0100H
01FFH
0200H
02FFH
0300H
0000H
Segment 0
Internal
RAM area
ROM window
setting area
Local register
setting area
External
memory area
FFFFH
ROM window
setting area
FIX area
FIX area
SFR area
Segment 1-15
Expanded SFR area
0FFFH
1000H
0000H
Expanded SFR area
SFR area
7FFFH
3FFFH
1FFFH
03FFH
External
memory area
Common area
BCB Common range
0
0-03FFH
1
0-1FFFH
2
0-3FFFH
3
0-7FFFH
Fixed page
area
0300H
02C0H
0240H
0238H
SBA area
64 bytes
USP
X1
X2
DP
USP
Pointing register
sets
The SBA area that can be
accessed using SB, RB,
JBS, and JBR instruction.
SCB=7
01FFH Expanded SFR area
0200H
X1
X2
DP
SCB=0
USP
X1
0208H
X2
DP
SCB=1
USP
X1
0210H
¡ Semiconductor
MSM66585/586/587/P587/Q587
Data Area
9/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
Area For Setting Local Registers
0000H
Internal RAM
area
0100H
SFR area
Expanded SFR area
0200H
FIX area
0300H
0200H
Area for setting local registers:
Specify 8-byte block with 8-bits of
LRBL
ER0
ER1
ER2
ER3
0A00H
0208H
ER0
R0
R1
R2
R3
R4
R5
R6
R7
R0
R1
LRBL=
00H
LRBL=
01H
External RAM
area
FFFFFH
ER3
0A00H
R6
R7
LRBL=
FFH
10/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Digital power supply voltage
VDD
Input voltage
VI
Output voltage
VO
Analog power supply voltage
AVDD
Analog reference voltage
VREF
Analog input voltage
VAI
Power dissipation
Storage temperature
PD
Conditions
GND=AGND=0V
Ta=25°C
Rating
Units
–0.3 to +7.0
V
–0.3 to VDD+0.3
V
–0.3 to VDD+0.3
V
–0.3 to VDD+0.3
V
–0.3 to AVDD+0.3
V
–0.3 to VREF
V
Per output
650
8
mW
—
–50 to +150
°C
Conditions
Range
Units
fOSC£20MHz
4.5 to 5.5
fOSC£10MHz
2.7 to 5.5
Per package
Ta=70°C
TSTG
mW
RECOMMENDED OPERATING CONDITIONS
Parameter
Digital power supply
voltage
Symbol
VDD
V
Analog reference voltage
VREF
—
AVDD–0.3 to AVDD
V
Analog input voltage
VAI
—
AGND to VREF
V
Memory hold voltage
VDDH
fOSC=0Hz
2.0 to 5.5
V
Operating frequency
fOSC
VDD=5V±10%
VDD=2.7 to 5.5V
2 to 20
MHz
2 to 10
MHz
Temperature range
Ta
—
–30 to +70
°C
MOS loads
20
—
2
—
1
—
Fan-out
N
P0, P5_4, P5_5,
P7_0, P7_1
TTL loads
P1, P2, P4, P6,
P7_2-P7_7,
P8-P10, P12
ALLOWABLE OUTPUT CURRENT
(VDD=2.7 to 5.5V, Ta=–30 to +70°C)
Parameter
Pin
Symbol
Min.
Typ.
Max.
"H" output pin (1 pin)
All output pins
IOH
—
—
–2
"H" output pin (total)
Total of all output pins
SIOH
—
—
–40
"L" output pin (1 pin)
All output pins
IOL
—
—
5
Total of P0, P1, P5 and P7
mA
Total of P2, P9 and P10
"L" output pin (total)
Total of P4 and P8
Units
SIOL
—
—
50
Total of P6 and P12
Total of all output pins
100
Note: Power and ground connections must be made to all external VDD and GND pins.
11/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
ELECTRICAL CHARACTERISTICS
DC Characteristics (VDD=5V±10%)
(Ta=–30 to +70°C)
Parameter
1
Input high voltage
Input high voltage 2, 4, 5, 6, 7
Input low voltage
1
Input low voltage
2, 4, 5, 6, 7
Output high voltage
Output high voltage
Output low voltage
Output low voltage
Symbol
Conditions
VIH
—
VIL
—
1, 4
2
VOH
1, 4
2
VOL
5
Input current
7
Output leakage current 1, 2, 4
2
Pull-up resistor
Input capacitance
Output capacitance
Analog reference power supply
current
Supply current
(stop mode)
IIH/IIL
ILO
Rpull
CI
CO
IREF
IDDS
Supply Current (halt mode)
IDDH
Supply Current
IDD
1.
2.
3.
4.
5.
6.
7.
*
Max
0.44VDD
—
VDD+0.3
0.80VDD
—
VDD+0.3
–0.3
—
0.16VDD
–0.3
—
0.2VDD
IO=–400mA
VDD–0.4
—
—
VDD–0.6
—
—
IO=–200mA
IO=–2.0 mA
VDD–0.4
—
—
VDD–0.6
IO=3.2mA
—
—
—
0.4
IO=5.0mA
—
—
IO=1.6mA
—
—
Units
V
—
0.8
0.4
—
—
0.8
—
—
1/–1
—
—
1/–250
—
—
15/–15
VO=VDD/0V
—
VI=0V
25
—
50
±10
100
—
5
—
—
7
—
A/D conversion operating
—
—
4
mA
A/D conversion stopped
—
—
10
mA
VDD=2V, Ta=25°C*
—
0.2
10
*
—
1
100
fOSC=20MHz,
No Load
—
10
25
—
45
70
3, 6
Input current
Typ
IO=–2.0 mA
IO=5.0mA
Input leakage current
Min
VI=VDD/0V
f=1MHz, Ta=25°C
mA
mA
kW
pF
mA
mA
Applies to P0.
Applies to P1, P2, P4, P6, P7_2-P7_7, P8-P10, P12.
Applies to Ain.
Applies to P5_4, P5_5, P7_0, P7_1.
Applies to RES.
Applies to EA, NMI.
Applies to OSC0.
For input ports, VDD or 0 V. For other cases, unloaded.
12/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
DC Characteristics (2.7V £ VDD £ 5.5V)
(Ta=–30 to +70°C)
Parameter
Symbol
1
Input high voltage
Input high voltage 2, 4, 5, 6, 7
Input low voltage
1
Input low voltage
2, 4, 5, 6, 7
Output high voltage
2
1, 4
Output low voltage
2
VOL
Input leakage current
5
Input current
7
Output leakage current 1, 2, 4
Pull-up resistor
Input capacitance
Output capacitance
Analog reference power
supply current
Typ
Max
—
VDD+0.3
0.80VDD
—
VDD+0.3
–0.3
—
0.16VDD
–0.3
—
0.2VDD
VDD–0.4
—
—
IO=–2.0 mA
IO=–200mA
VDD–0.6
—
—
VDD–0.4
—
—
IO=–2.0 mA
VDD–0.8
—
IO=3.2mA
IO=5.0mA
—
—
—
—
—
IO=1.6mA
—
—
IO=5.0mA
—
—
—
—
1/–1
—
—
1/–250
—
—
15/–15
ILO
VO=VDD/0V
—
—
±10
VI=0V,VDD=5V±10%
25
40
50
100
100
—
5
—
—
7
—
CI
CO
IREF
IDDS
Supply current (halt mode)
IDDH
IDD
VI=0V, VDD=3V±10%
f=1MHz, Ta=25°C
200
A/D conversion
operating
VDD=5.5V
VDD=3.3V
—
—
—
—
4
2
A/D conversion
stopped
VDD=5.5V
—
—
10
VDD=3.3V
—
—
5
VDD=2V, Ta=25°C*
—
0.2
10
*
—
1
100
VDD=5V±10%
—
5
15
VDD=3V±10%
VDD=5V±10%
—
3
10
—
—
30
50
13
25
fOSC=10MHz,
No Load
VDD=3V±10%
V
0.5
1.2
VI=VDD/0V
Rpull
Units
0.5
0.9
IIH/IIL
Supply current (stop mode)
1.
2.
3.
4.
5.
6.
7.
*
Min
0.44VDD
IO=–400mA
3, 6
Input current
Supply current
—
VIL
VOH
Output low voltage
—
VIH
1, 4
Output high voltage
Conditions
mA
mA
kW
pF
mA
mA
mA
mA
Applies to P0.
Applies to P1, P2, P4, P6, P7_2-P7_7, P8-P10, P12.
Applies to Ain.
Applies to P5_4, P5_5, P7_0, P7_1.
Applies to RES.
Applies to EA, NMI.
Applies to OSC0.
For input ports, VDD or 0 V. For other cases, unloaded.
13/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
AC Characteristics (VDD=5V±10%)
• External Program Memory Control
(Ta=–30 to +70°C)
Symbol
Conditions
Min
Max
Clock (OSC) pulse width
Parameter
tfW
—
25
—
ALE pulse width
tAW
2tfW–2
—
PSEN pulse width
tPW
2tfW–5
—
PSEN pulse delay time
tPAD
tfW–3
tfW+3
Low address setup time
tALS
2tfW–3
2tfW+3
Low address hold time
tALH
tfW–3
tfW+3
High address setup time
tAHS
4tfW–3
4tfW+3
High address hold time
tAPH
0
tfW+3
Instruction setup time
tIS
15
—
Instruction hold time
tIH
0
tfW–3
CL=50pF
Units
ns
CLK
tfW
tfW
ALE
tAW
PSEN
tPAD
AD 0-AD7
tPW
PC 0-7
tALS
A 8-A19
INST 0-7
tALH
tIS
tIH
PC 8-19
tAHS
tAPH
14/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
• External Data Memory Control
(Ta=–30 to +70°C)
Parameter
Clock (OSC) pulse width
Symbol
Conditions
Min
Max
tfW
—
25
—
ALE pulse width
tAW
2tfW–2
—
RD pulse width
tRW
2tfW–5
—
WR pulse width
tWW
2tfW–5
—
RD pulse delay time
tRAD
tfW–3
tfW+3
WR pulse delay time
tWAD
tfW–3
tfW+3
2tfW–3
2tfW+3
tfW–3
tfW+3
Low address setup time
tALS
Low address hold time
tALH
CL=50pF
High address setup time
tAHS
3tfW–3
3tfW+3
High address hold time
tAHH
tfW–3
tfW+3
Memory data setup time
tMS
15
—
Memory data hold time
tMH
0
tfW–3
Data delay time
tDD
tALH–0
tALH+5
Data hold time
tDH
tfW–3
tfW+3
Units
ns
CLK
tfW
tfW
ALE
tAW
RD
tRAD
AD 0-AD7
tRW
RAP 0-7
tALS
DIN 0-7
tALH
A 8-A19
tMS
tMH
RAP 8-19
tAHS
tAHH
WR
tWAD
AD 0-AD7
tWW
RAP 0-7
tALS
tALH
tDD
A 8-A19
DOUT 0-7
tDH
RAP 8-19
tAHS
tAHH
15/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
• Serial Port Contorl
Master mode
(Ta=–30 to +70°C)
Parameter
Clock (OSC) pulse width
Symbol
Conditions
Min.
Typ.
Max.
tfW
—
25
—
—
Serial clock cycle time
tSCKC
8tfW
—
—
Output data setup time
tSTMXS
4tfW–5
—
—
Output data hold time
tSTMXH
3tfW–10
—
—
CL=50pF
Input data setup time
tSRMXS
20
—
—
Input data hold time
tSRMXH
0
—
—
Units
ns
SCK
tSCKC
SDOUT
(TXD)
tSTMXH
SDIN
(RXD)
Valid
tSRMXS
tSTMXS
Valid
tSRMXH
16/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
Slave mode
(Ta=–30 to +70°C)
Parameter
Clock (OSC) pulse width
Serial clock cycle time
Symbol
Conditions
tfW
—
tSCKC
Output data setup time
tSTMXS
Output data hold time
tSTMXH
CL=50pF
Min.
Typ.
Max.
25
—
—
8tfW
—
—
2tfW–15
—
—
4tfW–10
—
—
Input data setup time
tSRMXS
20
—
—
Input data hold time
tSRMXH
0
—
—
Units
ns
SCK
tSCKC
SDOUT
(TXD)
tSTMXH
SDIN
(RXD)
Valid
tSRMXS
tSTMXS
Valid
tSRMXH
AC timing mesurement point
VDD
0V
0.8VDD
0.8VDD
0.2VDD
0.2VDD
17/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
AC Characteristics (2.7V £ VDD £ 5.5V)
• External Program Memory Control
(Ta= –30 to +70°C)
Symbol
Conditions
Min
Max
Clock (OSC) pulse width
Parameter
tfW
—
50
—
ALE pulse width
tAW
2tfW–4
—
PSEN pulse width
tPW
2tfW–10
—
PSEN pulse delay time
tPAD
tfW–6
tfW+6
2tfW–6
2tfW+6
tfW–6
tfW+6
Low address setup time
tALS
Low address hold time
tALH
High address setup time
tAHS
4tfW–6
4tfW+6
High address hold time
tAPH
0
tfW+6
Instruction setup time
tIS
30
—
Instruction hold time
tIH
0
tfW–6
CL=50pF
Units
ns
CLK
tfW
tfW
ALE
tAW
PSEN
tPAD
AD 0-AD7
tPW
PC 0-7
tALS
A 8-A19
INST 0-7
tALH
tIS
tIH
PC 8-19
tAHS
tAPH
18/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
• External Data Memory Control
(Ta= –30 to +70°C)
Parameter
Min
Max
50
—
2tfW–4
—
Symbol
Conditions
Clock (OSC) pulse width
tfW
—
ALE pulse width
tAW
RD pulse width
tRW
2tfW–10
—
WR pulse width
tWW
2tfW–10
—
RD pulse delay time
tRAD
tfW–6
tfW+6
WR pulse delay time
tWAD
tfW–6
tfW+6
2tfW–6
2tfW+6
tfW–6
tfW+6
Low address setup time
tALS
Low address hold time
tALH
High address setup time
tAHS
3tfW–6
3tfW+6
CL=50pF
High address hold time
tAHH
tfW–6
tfW+6
Memory data setup time
tMS
30
—
Memory data hold time
tMH
0
tfW–6
Data delay time
tDD
tALH–0
tALH+10
Data hold time
tDH
tfW–6
tfW+6
Units
ns
CLK
tfW
tfW
ALE
tAW
RD
tRAD
AD 0-AD7
tRW
RAP 0-7
tALS
DIN 0-7
tALH
A 8-A19
tMS
tMH
RAP 8-19
tAHS
tAHH
WR
tWAD
AD 0-AD7
tWW
RAP 0-7
tALS
tALH
tDD
A 8-A19
DOUT 0-7
tDH
RAP 8-19
tAHS
tAHH
19/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
• Serial Port Control
Master mode
(Ta=–30 to +70°C)
Parameter
Clock (OSC) pulse width
Symbol
Conditions
Min.
Typ.
Max.
tfW
—
50
—
—
Serial clock cycle time
tSCKC
8tfW
—
—
Output data setup time
tSTMXS
4tfW–10
—
—
Output data hold time
tSTMXH
3tfW–20
—
—
Input data setup time
tSRMXS
30
—
—
Input data hold time
tSRMXH
0
—
—
CL=50pF
Units
ns
SCK
tSCKC
SDOUT
(TXD)
tSTMXH
SDIN
(RXD)
Valid
tSRMXS
tSTMXS
Valid
tSRMXH
20/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
Slave mode
(Ta= –30 to +70°C)
Parameter
Clock (OSC) pulse width
Serial clock cycle time
Symbol
Conditions
tfW
—
tSCKC
Output data setup time
tSTMXS
Output data hold time
tSTMXH
CL=50pF
Min.
Typ.
Max.
50
—
—
8tfW
—
—
2tfW–30
—
—
4tfW–20
—
—
Input data setup time
tSRMXS
30
—
—
Input data hold time
tSRMXH
10
—
—
Units
ns
SCK
tSCKC
SDOUT
(TXD)
tSTMXH
SDIN
(RXD)
Valid
tSRMXS
tSTMXS
Valid
tSRMXH
AC timing mesurement point
VDD
0V
0.8VDD
0.8VDD
0.2VDD
0.2VDD
21/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
A/D Converter Characteristics
(Ta=–30 to +70°C, VDD=VREF=5V±10%, AGND=GND=0V, fOSC=20MHz)
Item
Symbol
Conditions
Min
Typ
Max
Units
n
Refer to the recommended
circuit
Analog input source
impedance
—
8
—
Bit
—
—
±2
—
—
±1
—
—
+2
Resolution
Linearity error
EL
Differential linearity error
ED
Zero scale error
EZS
RI£5kW
Full scale error
EFS
tCONV=19.2msec
—
—
–2
Conversion time
tCONV
by ADTM set data
6.4
—
19.2
LSB
ms/CH
A/D Converter Characteristics
(Ta=–30 to +70°C, VDD=VREF=3V±10%, AGND=GND=0V, fOSC=10MHz)
Item
Symbol
Conditions
Min
Resolution
n
Linearity error
EL
Refer to the recommended
circuit
Analog input source
impedance
Differential linearity error
ED
Zero scale error
EZS
RI£5kW
EFS
tCONV=38.4msec
Full scale error
tCONV ADTM=00b (384CLK selection)
Conversion time
Reference
Voltage
Typ
Max
Units
—
8
—
Bit
—
—
±1
—
—
±0.5
—
—
+1
—
—
–1
—
38.4
—
–
+5V
+
+
0.1
mF
RI
47
mF
AI0~
AI3
+
Analog Voltage
47
mF
ms/CH
VDD
VREF
0.1
mF
LSB
AGND
CI
GND
0V
0.1
mF
RI (analog input source impedance) £ 5kW
Cl = 0.1 mF
Recommended Circuit
22/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
Definition of terms
• Resolution
Resolution is the minimum input analog value that can be resolved. With 8 bits, 28=256 so
resolution can be to (VREF-AGND) ÷ 256.
• Linearity error
Linearity error is the difference between actual conversion characteristics and ideal
conversion characteristics of an 8-bit A/D converter (so this does not include quantization
error).
Ideal conversion characteristics would be to divide the voltage between VREF and AGND
into 256 equal steps.
• Differential linearity error
Differential linearity error indicates slope of conversion characteristics. The change in
analog input voltage value that would change the digital output by one bit is ideally 1 LSB
= (VREF-AGND) ÷ 256, so differential linearity error is the difference between this ideal bit
size and the actual bit size anywhere in the conversion range.
• Zero scale error
Zero scale error is the difference between actual conversion characteristics and ideal
conversion characteristics at the point where digital output switches from 00H to 01H.
• Full scale error
Full scale error is the difference between actual conversion characteristics and ideal
conversion characteristics at the point where digital output switches from FEH to FFH.
23/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.55 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
24/24
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