Micron MT28F008B3WG-9T Flash memory Datasheet

8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
FLASH MEMORY
MT28F008B3
MT28F800B3
3V Only, Dual Supply (Smart 3)
FEATURES
• Eleven erase blocks:
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
Eight main memory blocks
• Smart 3 technology (B3):
3.3V ±0.3V VCC
3.3V ±0.3V VPP application programming
5V ±10% VPP application/production programming1
• Compatible with 0.3µm Smart 3 device
• Advanced 0.18µm CMOS floating-gate process
• Address access time: 90ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• TSOP, SOP and FBGA packaging options
• Byte- or word-wide READ and WRITE
(MT28F800B3):
1 Meg x 8/512K x 16
OPTIONS
44-Pin SOP
MARKING
• Timing
90ns access
-9
• Configurations
1 Meg x 8
512K x 16/1 Meg x 8
GENERAL DESCRIPTION
The MT28F008B3 (x8) and MT28F800B3 (x16/x8) are
low-voltage, nonvolatile, electrically block-erasable (flash),
programmable memory devices containing 8,388,608 bits
organized as 524,288 words (16 bits) or 1,048,576 bytes (8
bits). Writing and erasing the device is done with a VPP
voltage of either 3.3V or 5V, while all operations are
performed with a 3.3V VCC. Due to process technology
advances, 5V VPP is optimal for application and production
programming. These devices are fabricated with Micron’s
advanced 0.18µm CMOS floating-gate process.
The MT28F008B3 and MT28F800B3 are organized
into eleven separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure or
overwrite, the devices feature a hardware-protected
boot block. This block may be used to store code implemented in low-level system recovery. The remaining
blocks vary in density and are written and erased with
no additional security measures.
Refer to Micron’s Web site (www.micron.com/flash)
for the latest data sheet.
MT28F008B3
MT28F800B3
• Boot Block Starting Word Address
Top (7FFFFh)
Bottom (00000h)
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Extended (-40ºC to +85ºC)
• Packages
40-pin TSOP Type I (MT28F008B3)
48-pin TSOP Type I (MT28F800B3)
44-pin SOP (MT28F800B3)
NOTE:
40-Pin TSOP Type I 48-Pin TSOP Type I
T
B
None
ET
VG
WG
SG
1. This generation of devices does not support 12V VPP
production programming; however, 5V VPP application
production programming can be used with no loss of
performance.
Part Number Example:
MT28F800B3WG-9 BET
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
1
©2001, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
PIN ASSIGNMENT (Top View)
48-Pin TSOP Type I
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
VPP
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
44-Pin SOP
A16
BYTE#
VSS
DQ15/(A - 1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
ORDER NUMBER AND PART MARKING
MT28F800B3WG-9 B
MT28F800B3WG-9 T
MT28F800B3WG-9 BET
MT28F800B3WG-9 TET
VPP
1
44
RP#
A18
2
43
WE#
A17
3
42
A8
A7
4
41
A9
A6
5
40
A10
A5
6
39
A11
A4
7
38
A12
A3
8
37
A13
A2
9
36
A14
A1
10
35
A15
A0
11
34
A16
CE#
12
33
BYTE#
VSS
13
32
VSS
OE#
14
31
DQ15/(A - 1)
DQ0
15
30
DQ7
DQ8
16
29
DQ14
DQ1
17
28
DQ6
DQ9
18
27
DQ13
DQ2
19
26
DQ5
DQ10
20
25
DQ12
DQ3
21
24
DQ4
DQ11
22
23
VCC
ORDER NUMBER AND PART MARKING
MT28F800B3SG-9 B
MT28F800B3SG-9 T
MT28F800B3SG-9 BET
MT28F800B3SG-9 TET
40-Pin TSOP Type I
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
VPP
WP#
A18
A7
A6
A5
A4
A3
A2
A1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A17
VSS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
ORDER NUMBER AND PART MARKING
MT28F008B3VG-9 B
MT28F008B3VG-9 T
MT28F008B3VG-9 BET
MT28F008B3VG-9 TET
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
FUNCTIONAL BLOCK DIAGRAM
BYTE# 2
8
Input
Buffer
7
Input
Buffer
I/O
Control
Logic
16KB Boot Block
Addr.
Buffer/
19 (20)
10
X - Decoder/Block Erase Control
A0–A18/(A19)
Latch
A9
9
(10)
Addr.
Power
(Current)
Control
Counter
WP# 1
96KB Main Block
Input
Buffer
128KB Main Block
128KB Main Block
A-1
128KB Main Block
Input Data
Latch/Mux
128KB Main Block
DQ15/(A - 1) 2
128KB Main Block
16
128KB Main Block
DQ8–DQ14 2
128KB Main Block
Command
State
Execution
Machine
Logic
YDecoder
3
RP#
VCC
VPP
8
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
VPP
Switch/
Pump
Output
Buffer
DQ15
Identification
Register
Output
Buffer
7
8
MUX
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
Status
Register
8
NOTE: 1. Does not apply to MT28F800B3SG.
2. Does not apply to MT28F008B3.
DQ0–DQ7
7
Y - Select Gates
Output
Buffer
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
CE#
OE#
WE#
8KB Parameter Block
8KB Parameter Block
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS
44-PIN SOP 40-PIN TSOP 48-PIN TSOP
NUMBERS NUMBERS NUMBERS SYMBOL
TYPE
DESCRIPTION
43
9
11
WE#
Input
Write Enable: Determines if a given cycle is a WRITE cycle. If
WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
–
12
14
WP#
Input
Write Protect: Unlocks the boot block when HIGH if VPP =
VPPH1 (3.3V) or VPPH2 (5V) and RP# = VIH during a WRITE or
ERASE. Does not affect WRITE or ERASE operation on other
blocks.
12
22
26
CE#
Input
Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
44
10
12
RP#
Input
Reset/Power-Down: When LOW, RP# clears the status register,
sets the internal state machine (ISM) to the array read mode
and places the device in deep power-down mode. All inputs,
including CE#, are “Don’t Care,” and all outputs are High-Z.
RP# unlocks the boot block and overrides the condition of
WP# when at VHH (12V), and must be held at VIH during all
other modes of operation.
14
24
28
OE#
Input
Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
33
–
47
BYTE#
Input
Byte Enable: If BYTE# = HIGH, the upper byte is active through
DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are High-Z, and all
data is accessed through DQ0–DQ7. DQ15/(A - 1) becomes the
least significant address input.
11, 10, 9, 8,
7, 6, 5, 4, 42,
41, 40, 39,
38, 37, 36,
35, 34, 3, 2
21, 20, 19, 18,
17, 16, 15, 14,
8, 7, 36, 6, 5,
4, 3, 2, 1, 40,
13, 37
25, 24, 23,
22, 21, 20,
19, 18, 8, 7,
6, 5, 4, 3, 2,
1, 48, 17, 16
A0–A18/
(A19)
Input
Address Inputs: Select a unique 16-bit word or 8-bit byte. The
DQ15/(A - 1) input becomes the lowest order address when
BYTE# = LOW (MT28F800B3) to allow for a selection of an 8bit byte from the 1,048,576 available.
31
–
45
DQ15/
(A - 1)
Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB
Output of address input when BYTE# = LOW during READ or WRITE
operation.
15, 17, 19,
21, 24, 26,
28, 30
25, 26, 27,
28, 32, 33,
34, 35
29, 31, 33,
35, 38, 40,
42, 44
DQ0–
DQ7
Input/ Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE. These pins are used to input
commands to the CEL.
16, 18, 20,
22, 25, 27,
29
–
30, 32, 34,
36, 39, 41,
43
DQ8–
DQ14
Input/ Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE when BYTE# = HIGH. These
pins are High-Z when BYTE# is LOW.
1
11
13
VPP
Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM
until completion of the WRITE or ERASE, VPP must be at VPPH1
(3.3V) or VPPH2 (5V). VPP = “Don’t Care” during all other
operations.
23
30, 31
37
VCC
Supply Power Supply: +3.3V ±0.3V.
13, 32
23, 39
27, 46
VSS
Supply Ground.
–
29, 38
9, 10, 15
NC
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
–
No Connect: These pins may be driven or left unconnected.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
TRUTH TABLE (MT28F800B3)1
RP#
CE#
OE#
A9
VPP
Standby
FUNCTION
H
H
X
WE# WP# BYTE# A0
X
X
X
X
X
X
DQ0–DQ7 DQ8–DQ14 DQ15/A - 1
High-Z
High-Z
High-Z
RESET
L
X
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
READ (word mode)
H
L
L
H
X
H
X
X
X
Data-Out Data-Out Data-Out
READ (byte mode)
H
L
L
H
X
L
X
X
X
Data-Out High-Z
Output Disable
H
L
H
H
X
X
X
X
X
High-Z
High-Z
High-Z
H
L
X
X
X
X
X
20h
X
X
READ
A-1
WRITE/ERASE (EXCEPT BOOT BLOCK)2
ERASE SETUP
ERASE
H
CONFIRM3
H
L
H
L
X
X
X
X
VPPH
D0h
X
X
H
L
H
L
X
X
X
X
X
10h/40h
X
X
H
L
H
L
X
H
X
X
VPPH
Data-In
Data-In
Data-In
H
L
H
L
X
L
X
X
VPPH
Data-In
X
A-1
H
L
H
L
X
X
X
X
X
FFh
X
X
H
L
H
L
X
X
X
X
X
20h
X
X
VHH
L
H
L
X
X
X
X
VPPH
D0h
X
X
H
L
H
L
H
X
X
X
VPPH
D0h
X
X
WRITE SETUP
WRITE (word
WRITE (byte
READ
mode)4
mode)4
ARRAY5
WRITE/ERASE (BOOT
BLOCK)2, 7
ERASE SETUP
ERASE
CONFIRM3
ERASE
CONFIRM3, 6
L
WRITE SETUP
H
L
H
L
X
X
X
X
X
10h/40h
X
X
VHH
L
H
L
X
H
X
X
VPPH
Data-In
Data-In
Data-In
H
L
H
L
H
H
X
X
VPPH
Data-In
Data-In
Data-In
VHH
L
H
L
X
L
X
X
VPPH
Data-In
X
A-1
H
L
H
L
H
L
X
X
VPPH
Data-In
X
A-1
H
L
H
L
X
X
X
X
X
FFh
X
X
Manufacturer Compatibility
(word mode)10
H
L
L
H
X
H
L
VID
X
89h
00h
–
Manufacturer Compatibility
(byte mode)
H
L
L
H
X
L
L
VID
X
89h
High-Z
X
Device (word mode, top boot)10
H
L
L
H
X
H
H
VID
X
9Ch
88h
–
Device (byte mode, top boot)
H
L
L
H
X
L
H
VID
X
9Ch
High-Z
X
Device (word mode, bottom boot)10
H
L
L
H
X
H
H
VID
X
9Dh
88h
–
Device (byte mode, bottom boot)
H
L
L
H
X
L
H
VID
X
9Dh
High-Z
X
WRITE (word mode)4
WRITE (word mode)4, 6
WRITE (byte
mode)4
WRITE (byte
mode)4, 6
READ
ARRAY5
DEVICE IDENTIFICATION8, 9
NOTE: 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).
VPPH = VPPH1 = 3.3V or VPPH2 = 5V.
Operation must be preceded by ERASE SETUP command.
Operation must be preceded by WRITE SETUP command.
The READ ARRAY command must be issued before reading the array after writing or erasing.
When WP# = VIH, RP# may be at VIH or VHH.
VHH = 12V.
VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.
A1–A8, A10–A18 = VIL.
Value reflects DQ8–DQ15.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
TRUTH TABLE (MT28F008B3)1
RP#
CE#
OE#
WE#
WP#
A0
A9
VPP
DQ0–DQ7
Standby
FUNCTION
H
H
X
X
X
X
X
X
High-Z
RESET
L
X
X
X
X
X
X
X
High-Z
READ
H
L
L
H
X
X
X
X
Data-Out
Output Disable
H
L
H
H
X
X
X
X
High-Z
H
L
H
L
X
X
X
X
20h
H
L
H
L
X
X
X
VPPH
D0h
WRITE SETUP
H
L
H
L
X
X
X
X
10h/40h
WRITE4
H
L
H
L
X
X
X
VPPH
Data-In
H
L
H
L
X
X
X
X
FFh
H
L
H
L
X
X
X
X
20h
READ
WRITE/ERASE (EXCEPT BOOT BLOCK)2
ERASE SETUP
ERASE
READ
CONFIRM3
ARRAY5
WRITE/ERASE (BOOT
BLOCK)2, 7
ERASE SETUP
ERASE
CONFIRM3
VHH
L
H
L
X
X
X
VPPH
D0h
ERASE CONFIRM3, 6
H
L
H
L
H
X
X
VPPH
D0h
WRITE SETUP
H
L
H
L
X
X
X
X
10h/40h
WRITE4
VHH
L
H
L
X
X
X
VPPH
Data-In
WRITE4, 6
H
L
H
L
H
X
X
VPPH
Data-In
READ ARRAY5
H
L
H
L
X
X
X
X
FFh
Manufacturer Compatibility
H
L
L
H
X
L
VID
X
89h
Device (top boot)
H
L
L
H
X
H
VID
X
98h
Device (bottom boot)
H
L
L
H
X
H
VID
X
99h
DEVICE
NOTE: 1.
2.
3.
4.
5.
6.
7.
8.
9.
IDENTIFICATION8, 9
L = VIL, H = VIH, X = VIL or VIH.
VPPH = VPPH1 = 3.3V or VPPH2 = 5V.
Operation must be preceded by ERASE SETUP command.
Operation must be preceded by WRITE SETUP command.
The READ ARRAY command must be issued before reading the array after writing or erasing.
When WP# = VIH, RP# may be at VIH or VHH.
VHH = 12V.
VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.
A1–A8, A10–A19 = VIL.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
FUNCTIONAL DESCRIPTION
HARDWARE-PROTECTED BOOT BLOCK
This block of the memory array can be erased or
written only when the RP# pin is taken to VHH or when the
WP# pin is brought HIGH. (The WP# pin does not apply to
the SOP package.) This provides additional security for
the core firmware during in-system firmware updates
should an unintentional power fluctuation or system
reset occur. The MT28F800B3 and MT28F008B3 are available with the boot block starting at the bottom of the
address space (“B” suffix) and the top of the address
space (“T” suffix).
The MT28F800B3 and MT28F008B3 Flash devices incorporate a number of features ideally suited for system
firmware. The memory array is segmented into individual erase blocks. Each block may be erased without
affecting data stored in other blocks. These memory
blocks are read, written and erased with commands to
the command execution logic (CEL). The CEL controls
the operation of the internal state machine (ISM), which
completely controls all WRITE, BLOCK ERASE and VERIFY
operations. The ISM protects each memory location from
over-erasure and optimizes each memory location for
maximum data retention. In addition, the ISM greatly
simplifies the control necessary for writing the device insystem or in an external programmer.
The Functional Description provides detailed information on the operation of the MT28F800B3 and
MT28F008B3 and is organized into these sections:
•
•
•
•
•
•
•
•
•
•
•
SELECTABLE BUS SIZE (MT28F800B3)
The MT28F800B3 allows selection of an 8-bit
(1 Meg x 8) or 16-bit (512K x 16) data bus for reading and
writing the memory. The BYTE# pin is used to select the
bus width. In the x16 configuration, control data is read
or written only on the lower eight bits (DQ0–DQ7).
Data written to the memory array utilizes all active
data pins for the selected configuration. When the x8
configuration is selected, data is written in byte form;
when the x16 configuration is selected, data is written in
word form.
Overview
Memory Architecture
Output (READ) Operations
Input Operations
Command Set
ISM Status Register
Command Execution
Error Handling
WRITE/ERASE Cycle Endurance
Power Usage
Power-Up
INTERNAL STATE MACHINE (ISM)
BLOCK ERASE and BYTE/WORD WRITE timing are
simplified with an ISM that controls all erase and write
algorithms in the memory array. The ISM ensures protection against overerasure and optimizes write margin to
each cell.
During WRITE operations, the ISM automatically increments and monitors WRITE attempts, verifies write
margin on each memory cell and updates the ISM status
register. When BLOCK ERASE is performed, the ISM automatically overwrites the entire addressed block (eliminates overerasure), increments and monitors ERASE attempts, and sets bits in the ISM status register.
OVERVIEW
SMART 3 TECHNOLOGY (B3)
Smart 3 operation allows maximum flexibility for insystem READ, WRITE and ERASE operations. WRITE and
ERASE operations may be executed with a VPP voltage of
3.3V or 5V. Due to process technology advances, 5V V PP is
optimal for application and production programming.
ISM STATUS REGISTER
The ISM status register enables an external processor
to monitor the status of the ISM during WRITE and ERASE
operations. Two bits of the 8-bit status register are set and
cleared entirely by the ISM. These bits indicate whether
the ISM is busy with an ERASE or WRITE task and when an
ERASE has been suspended. Additional error information is set in three other bits: VPP status, write status and
erase status.
ELEVEN INDEPENDENTLY ERASABLE MEMORY
BLOCKS
The MT28F800B3 and MT28F008B3 are organized into
eleven independently erasable memory blocks that allow portions of the memory to be erased without affecting the rest of the memory data. A special boot block is
hardware-protected against inadvertent erasure or writing by requiring either a super-voltage on the RP# pin or
driving the WP# pin HIGH. (The WP# pin does not apply
to the SOP package.) One of these two conditions must
exist along with the VPP voltage (3.3V or 5V) on the VPP pin
before a WRITE or ERASE is performed on the boot
block. The remaining blocks require that only the VPP
voltage be present on the VPP pin before writing or
erasing.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
COMMAND EXECUTION LOGIC (CEL)
The CEL receives and interprets commands to the
device. These commands control the operation of the
ISM and the read path (i.e., memory array, ID register or
status register). Commands may be issued to the CEL
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
while the ISM is active. However, there are restrictions
on what commands are allowed in this condition. See
the Command Execution section for more detail.
tion is block-oriented. All READ and WRITE operations
are done on a random-access basis.
The boot block is protected from unintentional ERASE
or WRITE with a hardware protection circuit which requires that a super-voltage be applied to RP# or that the
WP# pin be driven HIGH before erasure is commenced.
The boot block is intended for the core firmware required
for basic system functionality. The remaining ten blocks
do not require that either of these two conditions be met
before WRITE or ERASE operations.
DEEP POWER-DOWN MODE
To allow for maximum power conservation, the
MT28F800B3 and MT28F008B3 feature a very low current, deep power-down mode. To enter this mode, the
RP# pin is taken to VSS ±0.2V. In this mode, the current
draw is a maximum of 8µA at 3.3V VCC. Entering deep
power-down also clears the status register and sets the
ISM to the read array mode.
BOOT BLOCK
The hardware-protected boot block provides extra
security for the most sensitive portions of the firmware.
This 16KB block may only be erased or written when the
RP# pin is at the specified boot block unlock voltage (VHH)
of 12V or when the WP# pin is HIGH. During a WRITE or
ERASE of the boot block, the RP# pin must be held at VHH
or the WP# pin held HIGH until the WRITE or ERASE is
completed. (The WP# pin does not apply to the SOP
package.) The VPP pin must be at VPPH (3.3V or 5V) when
the boot block is written to or erased.
MEMORY ARCHITECTURE
The MT28F800B3 and MT28F008B3 memory array
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into eleven addressable blocks that vary in size
and are independently erasable. When blocks rather than
the entire array are erased, total device endurance is
enhanced, as is system flexibility. Only the ERASE func-
Figure 1
Memory Address Maps
WORD ADDRESS
BYTE ADDRESS
WORD ADDRESS
7FFFFh
FFFFFh
7FFFFh
FFFFFh
7E000h
7DFFFh
7D000h
7CFFFh
7C000h
7BFFFh
FC000h
FBFFFh
FA000h
F9FFFh
F8000h
F7FFFh
70000h
6FFFFh
E0000h
DFFFFh
60000h
5FFFFh
C0000h
BFFFFh
50000h
4FFFFh
A0000h
9FFFFh
40000h
3FFFFh
80000h
7FFFFh
30000h
2FFFFh
60000h
5FFFFh
20000h
1FFFFh
40000h
3FFFFh
10000h
0FFFFh
20000h
1FFFFh
00000h
00000h
BYTE ADDRESS
16KB Boot Block
128KB Main Block
70000h
6FFFFh
E0000h
DFFFFh
60000h
5FFFFh
C0000h
BFFFFh
50000h
4FFFFh
A0000h
9FFFFh
40000h
3FFFFh
80000h
7FFFFh
30000h
2FFFFh
60000h
5FFFFh
20000h
1FFFFh
40000h
3FFFFh
10000h
0FFFFh
20000h
1FFFFh
04000h
03FFFh
03000h
02FFFh
02000h
01FFFh
08000h
07FFFh
06000h
05FFFh
04000h
03FFFh
00000h
00000h
128KB Main Block
8KB Parameter Block
96KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
8KB Parameter Block
128KB Main Block
8KB Parameter Block
128KB Main Block
16KB Boot Block
Bottom Boot
MT28F008B3/800B3xx-xxB
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
8KB Parameter Block
Top Boot
MT28F008B3/800B3xx-xxT
8
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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
STATUS REGISTER
Performing a READ of the status register requires
the same input sequencing as a READ of the array
except that the address inputs are “Don’t Care.” The
status register contents are always output on DQ0–
DQ7, regardless of the condition of BYTE# on the
MT28F800B3. DQ8–DQ15 are LOW when BYTE# is
HIGH, and DQ8–DQ14 are High-Z when BYTE# is LOW.
Data from the status register is latched on the falling
edge of OE# or CE#, whichever occurs last. If the contents of the status register change during a READ of the
status register, either OE# or CE# may be toggled while
the other is held LOW to update the output.
Following a WRITE or ERASE, the device automatically enters the status register read mode. In addition, a
READ during a WRITE or ERASE produces the status
register contents on DQ0–DQ7. When the device is in the
erase suspend mode, a READ operation produces the
status register contents until another command is issued. In certain other modes, READ STATUS REGISTER
may be given to return to the status register read mode.
All commands and their operations are described in the
Command Set and Command Execution sections.
The MT28F800B3 and MT28F008B3 are available in
two configurations and top or bottom boot block. The top
boot block version supports processors of the x86 variety.
The bottom boot block version is intended for 680X0 and
RISC applications. Figure 1 illustrates the memory address maps associated with these two versions.
PARAMETER BLOCKS
The two 8KB parameter blocks store less sensitive and
more frequently changing system parameters and also
may store configuration or diagnostic coding. These
blocks are enabled for erasure when the VPP pin is at VPPH.
No super-voltage unlock or WP# control is required.
MAIN MEMORY BLOCKS
The eight remaining blocks are general-purpose
memory blocks and do not require a super-voltage on
RP# or WP# control to be erased or written. These blocks
are intended for code storage, ROM-resident applications or operating systems that require in-system update
capability.
OUTPUT (READ) OPERATIONS
The MT28F800B3 and MT28F008B3 feature three different types of READs. Depending on the current mode of
the device, a READ operation produces data from the
memory array, status register or device identification
register. In each of these three cases, the WE#, CE# and
OE# inputs are controlled in a similar manner. Moving
between modes to perform a specific READ is described
in the Command Execution section.
IDENTIFICATION REGISTER
A READ of the two 8-bit device identification registers
requires the same input sequencing as a READ of the
array. WE# must be HIGH, and OE# and CE# must be
LOW. However, ID register data is output only on DQ0–
DQ7, regardless of the condition of BYTE# on the
MT28F800B3. A0 is used to decode between the two bytes
of the device ID register; all other address inputs are
“Don’t Care.” When A0 is LOW, the manufacturer compatibility ID is output, and when A0 is HIGH, the device
ID is output. DQ8–DQ15 are High-Z when BYTE# is LOW.
When BYTE# is HIGH, DQ8–DQ15 are 00h when the
manufacturer compatibility ID is read and 88h when the
device ID is read.
To get to the identification register read mode, READ
IDENTIFICATION may be issued while the device is in
certain other modes. In addition, the identification register read mode can be reached by applying a super-voltage (VID) to the A9 pin. Using this method, the ID register
can be read while the device is in any mode. When A9 is
returned to VIL or VIH, the device returns to the previous
mode.
MEMORY ARRAY
To read the memory array, WE# must be HIGH, and
OE# and CE# must be LOW. Valid data is output on the
DQ pins when these conditions have been met, and a
valid address is given. Valid data remains on the DQ pins
until the address changes, or until OE# or CE# goes HIGH,
whichever occurs first. The DQ pins continue to output
new data after each address transition as long as OE# and
CE# remain LOW.
The MT28F800B3 features selectable bus widths.
When the memory array is accessed as a 512K x 16, BYTE#
is HIGH, and data is output on DQ0–DQ15. To access the
memory array as a 1 Meg x 8, BYTE# must be LOW, DQ8–
DQ14 must be High-Z, and all data must be output on
DQ0–DQ7. The DQ15/(A - 1) pin becomes the lowest
order address input so that 1,048,576 locations can be
read.
After power-up or RESET, the device is automatically
in the array read mode. All commands and their operations are covered in the Command Set and Command
Execution sections.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
INPUT OPERATIONS
The DQ pins are used either to input data to the array
or to input a command to the CEL. A command input
issues an 8-bit command to the CEL to control the mode
of operation of the device. A WRITE is used to input
data to the memory array. The following section de-
9
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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
scribes both types of inputs. More information describing how to use the two types of inputs to write or erase
the device is provided in the Command Execution section.
RP# pin be at VHH or WP# be HIGH. A0–A18 (A19) provide the address to be written, while the data to be
written to the array is input on the DQ pins. The data
and addresses are latched on the rising edge of CE#
(CE#-controlled) or WE# (WE#-controlled), whichever
occurs first. A WRITE must be preceded by a WRITE
SETUP command. Details on how to input data to the
array are described in the Write Sequence section.
Selectable bus sizing applies to WRITEs as it does to
READs on the MT28F800B3. When BYTE# is LOW (byte
mode), data is input on DQ0–DQ7, DQ8–DQ14 are HighZ, and DQ15 becomes the lowest order address input.
When BYTE# is HIGH (word mode), data is input on DQ0–
DQ15.
COMMANDS
To perform a command input, OE# must be HIGH,
and CE# and WE# must be LOW. Addresses are “Don’t
Care” but must be held stable, except during an ERASE
CONFIRM (described in a later section). The 8-bit command is input on DQ0–DQ7, while DQ8–DQ15 are “Don’t
Care” on the MT28F800B3. The command is latched on
the rising edge of CE# (CE#-controlled) or WE# (WE#controlled), whichever occurs first. The condition of
BYTE# on the MT28F800B3 has no effect on a command input.
COMMAND SET
To simplify writing of the memory blocks, the
MT28F800B3 and MT28F008B3 incorporate an ISM that
controls all internal algorithms for writing and erasing
the floating gate memory cells. An 8-bit command set is
used to control the device. Details on how to sequence
commands are provided in the Command Execution
section. Table 1 lists the valid commands.
MEMORY ARRAY
A WRITE to the memory array sets the desired bits to
logic 0s but cannot change a given bit to a logic 1 from a
logic 0. Setting any bits to a logic 1 requires that the entire
block be erased. To perform a WRITE, OE# must be HIGH,
CE# and WE# must be LOW, and VPP must be set to VPPH1
or VPPH2. Writing to the boot block also requires that the
Table 1
Command Set
COMMAND
HEX CODE DESCRIPTION
RESERVED
00h
This command and all unlisted commands are invalid and should not
be called. These commands are reserved to allow for future feature
enhancements.
READ ARRAY
FFh
Must be issued after any other command cycle before the array can be
read. It is not necessary to issue this command after power-up or RESET.
IDENTIFY DEVICE
90h
Allows the device and manufacturer compatibility ID to be read. A0 is
used to decode between the manufacturer compatibility ID (A0 = LOW)
and device ID (A0 = HIGH).
READ STATUS REGISTER
70h
Allows the status register to be read. Please refer to Table 2 for more
information on the status register bits.
CLEAR STATUS REGISTER
50h
Clears status register bits 3-5, which cannot be cleared by the ISM.
ERASE SETUP
20h
The first command given in the two-cycle ERASE sequence. The ERASE is
not completed unless followed by ERASE CONFIRM.
ERASE CONFIRM/RESUME
D0h
The second command given in the two-cycle ERASE sequence. Must follow
an ERASE SETUP command to be valid. Also used during an ERASE
SUSPEND to resume the ERASE.
40h or
10h
The first command given in the two-cycle WRITE sequence. The write
data and address are given in the following cycle to complete the WRITE.
B0h
Requests a halt of the ERASE and puts the device into the erase suspend
mode. When the device is in this mode, only READ STATUS REGISTER,
READ ARRAY and ERASE RESUME commands may be executed.
WRITE SETUP
ERASE SUSPEND
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SMART 3 BOOT BLOCK FLASH MEMORY
ISM STATUS REGISTER
The 8-bit ISM status register (see Table 2) is polled
to check for WRITE or ERASE completion or any related
errors. During or following a WRITE, ERASE or ERASE
SUSPEND, a READ operation outputs the status register
contents on DQ0–DQ7 without prior command. While
the status register contents are read, the outputs are not
be updated if there is a change in the ISM status unless
OE# or CE# is toggled. If the device is not in the write,
erase, erase suspend or status register read mode, READ
STATUS REGISTER (70h) can be issued to view the status
register contents.
All of the defined bits are set by the ISM, but only
the ISM and erase suspend status bits are reset by the
ISM. The erase, write and VPP status bits must be cleared
using CLEAR STATUS REGISTER. If the VPP status bit
(SR3) is set, the CEL does not allow further WRITE or
ERASE operations until the status register is cleared.
This enables the user to choose when to poll and clear
the status register. For example, the host system may
perform multiple BYTE WRITE operations before checking the status register instead of checking after each
individual WRITE. Asserting the RP# signal or powering down the device also clears the status register.
Table 2
Status Register Bit Definitions
STATUS
BIT #
ISMS
ESS
ES
WS
VPPS
R
7
6
5
4
3
2–0
STATUS REGISTER BIT
DESCRIPTION
SR7
ISM STATUS (ISMS)
1 = Ready
0 = Busy
The ISMS bit displays the active status of the state machine during
WRITE or BLOCK ERASE operations. The controlling logic polls this
bit to determine when the erase and write status bits are valid.
SR6
ERASE SUSPEND STATUS (ESS)
1 = ERASE suspended
0 = ERASE in progress/completed
Issuing an ERASE SUSPEND places the ISM in the suspend mode
and sets this and the ISMS bit to “1.” The ESS bit remains “1”
until an ERASE RESUME is issued.
SR5
ERASE STATUS (ES)
1 = BLOCK ERASE error
0 = Successful BLOCK ERASE
ES is set to “1” after the maximum number of ERASE cycles is
executed by the ISM without a successful verify. ES is only cleared
by a CLEAR STATUS REGISTER command or after a RESET.
SR4
WRITE STATUS (WS)
1 = WORD/BYTE WRITE error
0 = Successful WORD/BYTE WRITE
WS is set to “1” after the maximum number of WRITE cycles is
executed by the ISM without a successful verify. WS is only cleared
by a CLEAR STATUS REGISTER command or after a RESET.
SR3
VPP STATUS (VPPS)
1 = No VPP voltage detected
0 = VPP present
VPPS detects the presence of a VPP voltage. It does not monitor VPP
continuously, nor does it indicate a valid VPP voltage. The VPP pin
is sampled for 3.3V or 5V after WRITE or ERASE CONFIRM is given.
VPPS must be cleared by CLEAR STATUS REGISTER or by a RESET.
RESERVED
Reserved for future use.
SR0-2
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
COMMAND EXECUTION
WRITE SEQUENCE
Two consecutive cycles are needed to input data to
the array. WRITE SETUP (40h or 10h) is given in the first
cycle. The next cycle is the WRITE, during which the write
address and data are issued and VPP is brought to VPPH.
Writing to the boot block also requires that the RP# pin be
brought to VHH or the WP# pin be brought HIGH at the
same time VPP is brought to VPPH. The ISM now begins to
write the word or byte. VPP must be held at VPPH until the
WRITE is completed (SR7 = 1).
While the ISM executes the WRITE, the ISM status bit
(SR7) is at 0, and the device does not respond to any
commands. Any READ operation produces the status
register contents on DQ0–DQ7. When the ISM status bit
(SR7) is set to a logic 1, the WRITE has been completed,
and the device goes into the status register read mode
until another command is given.
After the ISM has initiated the WRITE, it cannot be
aborted except by a RESET or by powering down the part.
Doing either during a WRITE corrupts the data being
written. If only the WRITE SETUP command has been
given, the WRITE may be nullified by performing a null
WRITE. To execute a null WRITE, FFh must be written
Commands are issued to bring the device into different operational modes. Each mode allows specific operations to be performed. Several modes require a sequence
of commands to be written before they are reached. The
following section describes the properties of each mode,
and Table 3 lists all command sequences required to
perform the desired operation.
READ ARRAY
The array read mode is the initial state of the device
upon power-up and after a RESET. If the device is in any
other mode, READ ARRAY (FFh) must be given to return
to the array read mode. Unlike the WRITE SETUP command (40h), READ ARRAY does not need to be given
before each individual READ access.
IDENTIFY DEVICE
IDENTIFY DEVICE (90h) may be written to the CEL to
enter the identify device mode. While the device is in this
mode, any READ produces the device identification when
A0 is HIGH and the manufacturer compatibility identification when A0 is LOW. The device remains in this mode
until another command is given.
Table 3
Command Sequences
COMMANDS
BUS
FIRST
SECOND
CYCLES
CYCLE
CYCLE
REQ’D OPERATION ADDRESS DATA OPERATION ADDRESS DATA
NOTES
READ ARRAY
1
WRITE
X
FFh
1
IDENTIFY DEVICE
3
WRITE
X
90h
READ
IA
ID
2, 3
READ STATUS REGISTER
2
WRITE
X
70h
READ
X
SRD
4
CLEAR STATUS REGISTER
1
WRITE
X
50h
5, 6
ERASE SETUP/CONFIRM
2
WRITE
X
20h
WRITE
BA
D0h
ERASE SUSPEND/RESUME
2
WRITE
X
B0h
WRITE
X
D0h
WRITE SETUP/WRITE
2
WRITE
X
40h
WRITE
WA
WD
6, 7
ALTERNATE WORD/BYTE
WRITE
2
WRITE
X
10h
WRITE
WA
WD
6, 7
NOTE: 1.
2.
3.
4.
5.
6.
7.
Must follow WRITE or ERASE CONFIRM commands to the CEL in order to enable Flash array READ cycles.
IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID.
ID = Identify Data.
SRD = Status Register Data.
BA = Block Address (A12–A19).
Addresses are “Don’t Care” in first cycle but must be held stable.
WA = Address to be written; WD = Data to be written to WA.
8Mb Smart 3 Boot Block Flash Memory
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SMART 3 BOOT BLOCK FLASH MEMORY
when BYTE# is LOW, or FFFFh must be written when
BYTE# is HIGH. When the ISM status bit (SR7) has been
set, the device is in the status register read mode until
another command is issued.
that either the RP# pin be set to VHH or the WP# pin be
held HIGH at the same time VPP is set to VPPH.
ERASE SUSPENSION
The only command that may be issued while an
ERASE is in progress is ERASE SUSPEND. This command enables other commands to be executed while
pausing the ERASE in progress. When the device has
reached the erase suspend mode, the erase suspend
status bit (SR6) and ISM status bit (SR7) are set. The
device may now be given a READ ARRAY, ERASE RESUME or READ STATUS REGISTER command. After
READ ARRAY has been issued, any location not within
the block being erased may be read. If ERASE RESUME
is issued before SR6 has been set, the device immediately proceeds with the ERASE in progress.
ERASE SEQUENCE
Executing an ERASE sequence sets all bits within a
block to logic 1. The command sequence necessary to
execute an ERASE is similar to that of a WRITE. To provide added security against accidental block erasure,
two consecutive command cycles are required to initiate
an ERASE of a block. In the first cycle, addresses are
“Don’t Care,” and ERASE SETUP (20h) is given. In the
second cycle, VPP must be brought to VPPH, an address
within the block to be erased must be issued, and ERASE
CONFIRM (D0h) must be given. If a command other than
ERASE CONFIRM is given, the write and erase status bits
(SR4 and SR5) are set, and the device is in the status
register read mode.
After the ERASE CONFIRM (D0h) is issued, the ISM
starts the ERASE of the addressed block. Any READ
operation outputs the status register contents on DQ0–
DQ7. VPP must be held at VPPH until the ERASE is completed (SR7 = 1). When the ERASE is completed, the
device is in the status register read mode until another
command is issued. Erasing the boot block also requires
ERROR HANDLING
After the ISM status bit (SR7) has been set, the VPP
(SR3), write (SR4) and erase (SR5) status bits may be
checked. If one or a combination of these three bits has
been set, an error has occurred. The ISM cannot reset
these three bits. To clear these bits, CLEAR STATUS REGISTER (50h) must be given. If the VPP status bit (SR3) is set,
further WRITE or ERASE operations cannot resume until
the status register is cleared. Table 4 lists the combination of errors.
Table 4
Status Register Error Code Description1
SR5
STATUS BITS
SR4
SR3
ERROR DESCRIPTION
0
0
0
No errors
0
0
1
VPP voltage error
0
1
0
WRITE error
0
1
1
WRITE error, VPP voltage not valid at time of WRITE
1
0
0
ERASE error
1
0
1
ERASE error, VPP voltage not valid at time of ERASE CONFIRM
1
1
0
Command sequencing error or WRITE/ERASE error
1
1
1
Command sequencing error, VPP voltage error, with WRITE and ERASE errors
NOTE: 1. SR3-SR5 must be cleared using CLEAR STATUS REGISTER.
8Mb Smart 3 Boot Block Flash Memory
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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE ENDURANCE
POWER-UP
The MT28F800B3 and MT28F008B3 are designed and
fabricated to meet advanced firmware storage requirements. To ensure this level of reliability, VPP must be at
3.3V ±0.3V or 5V ±10% during WRITE or ERASE cycles.
Due to process technology advances, 5V VPP is optimal
for application and production programming.
The likelihood of unwanted WRITE or ERASE operations is minimized because two consecutive cycles are
required to execute either operation. However, to reset
the ISM and to provide additional protection while VCC is
ramping, one of the following conditions must be met:
• RP# must be held LOW until VCC is at valid
functional level; or
• CE# or WE# may be held HIGH and
RP# must be toggled from VCC-GND-VCC.
After a power-up or RESET, the status register is reset,
and the device enters the array read mode.
POWER USAGE
The MT28F800B3 and MT28F008B3 offer several
power-saving features that may be utilized in the array
read mode to conserve power. Deep power-down mode
is enabled by bringing RP# LOW. Current draw (ICC) in
this mode is a maximum of 8µA at 3.3V VCC. When CE# is
HIGH, the device enters standby mode. In this mode,
maximum ICC current is 100µA at 3.3V VCC. If CE# is
brought HIGH during a WRITE or ERASE, the ISM continues to operate, and the device consumes the respective
active power until the WRITE or ERASE is completed.
Figure 2
Power-Up/Reset Timing Diagram
RP#
Note 1
VCC
(3.3V)
t
AA
Address
VALID
VALID
Data
t
RWH
UNDEFINED
NOTE:
8Mb Smart 3 Boot Block Flash Memory
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1. VCC must be within the valid operating range before RP#
goes HIGH.
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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
SELF-TIMED WRITE SEQUENCE
(WORD OR BYTE WRITE)1
COMPLETE WRITE STATUS-CHECK
SEQUENCE
Start
Start (WRITE completed)
WRITE 40h or 10h
SR3 = 0?
NO
VPP Error 4, 5
NO
BYTE/WORD WRITE Error5
YES
SR4 = 0?
VPP = 3.3V or 5V
YES
WRITE Word or Byte
Address/Data
WRITE Successful
STATUS REGISTER
READ
SR7 = 1?
NO
YES
Complete Status2
Check (optional)
WRITE Complete 3
NOTE: 1. Sequence may be repeated for additional BYTE or WORD WRITEs.
2. Complete status check is not required. However, if SR3 = 1, further WRITEs are inhibited until the status register is
cleared.
3. Device will be in status register read mode. To return to the array read mode, the FFh command must be issued.
4. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE
or ERASE operations are allowed by the CEL.
5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
8Mb Smart 3 Boot Block Flash Memory
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SMART 3 BOOT BLOCK FLASH MEMORY
SELF-TIMED BLOCK ERASE SEQUENCE1
COMPLETE BLOCK ERASE
STATUS-CHECK SEQUENCE
Start
Start (ERASE completed)
WRITE 20h
SR3 = 0?
NO
VPP Error 5, 6
YES
Command Sequence Error6
NO
BLOCK ERASE Error6
YES
VPP = 3.3V or 5V
SR4, 5 = 1?
NO
WRITE D0h,
Block Address
SR5 = 0?
YES
ERASE
Busy
STATUS REGISTER
READ
ERASE Successful
NO
NO
SR7 = 1?
YES
Complete Status 2
Check (optional)
Suspend ERASE?
YES
Suspend 4
Sequence
ERASE Resumed
ERASE Complete 3
NOTE: 1. Sequence may be repeated to erase additional blocks.
2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register is
cleared.
3. To return to the array read mode, the FFh command must be issued.
4. Refer to the ERASE SUSPEND flowchart for more information.
5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE
or ERASE operations are allowed by the CEL.
6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
8Mb Smart 3 Boot Block Flash Memory
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SMART 3 BOOT BLOCK FLASH MEMORY
ERASE SUSPEND/RESUME SEQUENCE
Start (ERASE in progress)
WRITE B0h
(ERASE SUSPEND)
VPP = 3.3V or 5V
STATUS REGISTER
READ
SR7 = 1?
NO
YES
SR6 = 1?
NO
YES
ERASE Completed
WRITE FFh
(READ ARRAY)
Done
Reading?
NO
YES
WRITE D0h
(ERASE RESUME)
Resume ERASE
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
**VCC, input and I/O pins may transition to -2V for <20ns
and VCC + 2V for <20ns.
†Voltage may pulse to -2V for <20ns and 7V for <20ns.
††Voltage may pulse to -2V for <20ns and 14V for <20ns.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply
Relative to VSS ..................................... -0.5V to +4V**
Input Voltage Relative to VSS .................... -0.5V to +4V**
VPP Voltage Relative to VSS ........................ -0.5V to +5.5V†
RP# or A9 Pin Voltage
Relative to VSS ................................ -0.5V to +12.6V††
Temperature Under Bias .......................... -10ºC to +80ºC
Storage Temperature (plastic) ............... -55ºC to +125ºC
Power Dissipation ......................................................... 1W
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC READ
OPERATING CONDITIONS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
3.3V Supply Voltage
VCC
3
3.6
V
1
Input High (Logic 1) Voltage, all inputs
VIH
2.4
VCC + 0.5
V
1
Input Low (Logic 0) Voltage, all inputs
VIL
-0.5
0.8
V
1
Device Identification Voltage, A9
VID
10
12.6
V
1
VPP Supply Voltage
VPP
-0.5
5.5
V
1
NOTES
DC OPERATING CHARACTERISTICS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
VOH
VCC - 0.2
–
V
VOL
–
0.45
V
IL
-1
1
µA
INPUT LEAKAGE CURRENT: A9 INPUT
(10V ≤ A9 ≤ 12V = VID)
IID
–
500
µA
INPUT LEAKAGE CURRENT: RP# INPUT
(10V ≤ RP# ≤ 12V = VHH)
IHH
–
500
µA
OUTPUT LEAKAGE CURRENT
(DOUT is disabled; 0V ≤ VOUT ≤ VCC)
IOZ
-10
10
µA
OUTPUT VOLTAGE LEVELS
Output High Voltage (IOH = -100µA)
Output Low Voltage (IOL = 2mA)
1
INPUT LEAKAGE CURRENT
Any input (0V ≤ VIN ≤ VCC);
All other pins not under test = 0V
NOTE: 1. All voltages referenced to VSS.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
CAPACITANCE
(TA = 25ºC; f = 1 MHz)
PARAMETER/CONDITION
SYMBOL
MAX
UNITS
Input Capacitance
CI
9
pF
Output Capacitance
CO
12
pF
NOTES
READ AND STANDBY CURRENT DRAIN1
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC)
PARAMETER/CONDITION
SYMBOL
MAX
READ CURRENT: WORD-WIDE
(CE# ≤ 0.2V; OE# ž VCC - 0.2V; f = 5 MHz;
Other inputs ≤ 0.2V or ž VCC - 0.2V; RP# ž VCC - 0.2V)
UNITS NOTES
ICC1
15
mA
2, 3
READ CURRENT: BYTE-WIDE
(CE# ≤ 0.2V; OE# ž VCC - 0.2V; f = 5 MHz;
Other inputs ≤ 0.2V or ž VCC - 0.2V; RP# = VCC - 0.2V)
ICC2
15
mA
2, 3
STANDBY CURRENT: TTL INPUT LEVELS
VCC power supply standby current
(CE# = RP# = VIH; Other inputs = VIL or VIH)
ICC3
2
mA
STANDBY CURRENT: CMOS INPUT LEVELS
VCC power supply standby current
(CE# = RP# = VCC - 0.2V)
ICC4
100
µA
DEEP POWER-DOWN CURRENT: VCC SUPPLY
(RP# = VSS ±0.2V)
ICC6
8
µA
STANDBY OR READ CURRENT: VPP SUPPLY
(VPP ≤ 5.5V)
IPP1
±15
µA
DEEP POWER-DOWN CURRENT: VPP SUPPLY
(RP# = VSS ±0.2V)
IPP2
5
µA
NOTE: 1. VCC = MAX VCC during ICC tests.
2. ICC is dependent on cycle rates.
3. ICC is dependent on output loading. Specified values are obtained with the outputs open.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
READ TIMING PARAMETERS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS1
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +3.3V ±0.3V
AC CHARACTERISTICS
PARAMETER
READ cycle time
Access time from CE#
Access time from OE#
Access time from address
RP# HIGH to output valid delay
OE# or CE# HIGH to output in High-Z
Output hold time from OE#, CE# or address change
RP# LOW pulse width
SYMBOL
tRC
tACE
tAOE
tAA
tRWH
tOD
tOH
tRP
-9/-9 ET
MIN
MAX
90
90
40
90
1,000
25
0
150
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
2
2
NOTE: 1. Measurements tested under AC Test Conditions.
2. OE# may be delayed by tACE minus tAOE after CE# falls before tACE is affected.
AC TEST CONDITIONS
Input pulse levels ...................................................... 0V to 3V
Input rise and fall times ................................................ <10ns
Input timing reference level ........................................... 1.5V
Output timing reference level ........................................ 1.5V
Output load ................................... 1 TTL gate and CL = 50pF
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
WORD-WIDE READ CYCLE1
VIH
A0–A18/(A19)
VALID ADDRESS
VIL
tRC
tAA
VIH
CE#
VIL
tACE
VIH
OE#
VIL
VIH
WE#
VIL
tOD
tAOE
tOH
VIH
DQ0–DQ15
VALID DATA
VIL
tRWH
VIH
RP#
VIL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
Extended Temperature (-40ºC ≤ TA ≤ +85ºC)
SYMBOL
tRC
-9/-9 ET
MIN
MAX
90
UNITS
ns
SYMBOL
tRWH
tACE
90
ns
tOD
tAOE
40
90
ns
ns
tOH
tAA
-9/-9 ET
MIN
MAX
1,000
25
0
UNITS
ns
ns
ns
NOTE: 1. BYTE# = HIGH (MT28F800B3 only).
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
BYTE-WIDE READ CYCLE1
VIH
A0–A18/(A19)
VALID ADDRESS
VIL
tRC
tAA
VIH
CE#
VIL
tACE
VIH
OE#
VIL
VIH
WE#
VIL
tOD
tAOE
tOH
VIH
DQ0–DQ7
VALID DATA
VIL
VIH
DQ8–DQ14
VIL
HIGH-Z
tRWH
VIH
RP#
VIL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
Extended Temperature (-40ºC ≤ TA ≤ +85ºC)
-9/-9 ET
SYMBOL
tRC
tACE
MIN
90
tAOE
tAA
MAX
-9/-9 ET
90
UNITS
ns
ns
40
90
ns
ns
SYMBOL
tRWH
tOD
tOH
MIN
0
MAX
1,000
25
UNITS
ns
ns
ns
NOTE: 1. BYTE# = LOW (MT28F800B3 only).
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
RECOMMENDED DC WRITE/ERASE CONDITIONS1
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +3.3V ±0.3V
PARAMETER/CONDITION
SYMBOL
MIN
VPP WRITE/ERASE lockout voltage
VPPLK
–
MAX UNITS NOTES
1.5
V
2
VPP voltage during WRITE/ERASE operation
VPPH1
3.0
3.6
V
3
VPP voltage during WRITE/ERASE operation
VPPH2
4.5
5.5
V
Boot block unlock voltage
VHH
10
12.6
V
VCC WRITE/ERASE lockout voltage
VLKO
2
–
V
WRITE/ERASE CURRENT DRAIN4
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC - TA - +85ºC); VCC = +3.3V ±0.3V
3.3V VPP 5V VPP
PARAMETER/CONDITION
SYMBOL
MAX
MAX
WORD WRITE CURRENT: VCC SUPPLY
ICC7
20
20
mA
5
WORD WRITE CURRENT: VPP SUPPLY
IPP3
20
20
mA
5
BYTE WRITE CURRENT: VCC SUPPLY
ICC8
20
20
mA
6
BYTE WRITE CURRENT: VPP SUPPLY
IPP4
20
20
mA
6
ERASE CURRENT: VCC SUPPLY
ICC9
25
25
mA
ERASE CURRENT: VPP SUPPLY
IPP5
25
30
mA
ERASE SUSPEND CURRENT: VCC SUPPLY
(ERASE suspended)
ICC10
8
10
mA
ERASE SUSPEND CURRENT: VPP SUPPLY
(ERASE suspended)
IPP6
200
200
µA
NOTE: 1.
2.
3.
4.
5.
6.
7.
UNITS NOTES
7
WRITE operations are tested at VPP voltages equal to or less than the previous ERASE.
Absolute WRITE/ERASE protection when VPP ≤ VPPLK.
When 3.3V VCC and VPP are used, VCC cannot exceed VPP by more than 500mV during WRITE and ERASE operations.
All currents are in RMS unless otherwise noted.
Applies to MT28F800B3 only.
Applies to MT28F008B3 and MT28F800B3 with BYTE# = LOW.
Parameter is specified when device is not accessed. Actual current draw will be I CC10 plus read current if a READ is
executed while the device is in erase suspend mode.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS:
WE# (CE#)-CONTROLLED WRITES
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +3.3V ±0.3V
AC CHARACTERISTICS
PARAMETER
WRITE cycle time
WE# (CE#) HIGH pulse width
WE# (CE#) pulse width
Address setup time to WE# (CE#) HIGH
Address hold time from WE# (CE#) HIGH
Data setup time to WE# (CE#) HIGH
Data hold time from WE# (CE#) HIGH
CE# (WE#) setup time to WE# (CE#) LOW
CE# (WE#) hold time from WE# (CE#) HIGH
VPP setup time to WE# (CE#) HIGH
VPP setup time to WE# (CE#) HIGH
RP# HIGH to WE# (CE#) LOW delay
RP# at VHH or WP# HIGH setup time to WE# (CE#) HIGH
WRITE duration (WORD or BYTE WRITE)
Boot BLOCK ERASE duration
Parameter BLOCK ERASE duration
Main BLOCK ERASE duration
WE# (CE#) HIGH to busy status (SR7 = 0)
VPP hold time from status data valid
RP# at VHH or WP# HIGH hold time from status data valid
Boot block relock delay time
SYMBOL
tWC
tWPH (tCPH)
tWP (tCP)
tAS
tAH
tDS
tDH
tCS (tWS)
tCH (tWH)
tVPS1
tVPS2
tRS
tRHS
tWED1
tWED2
tWED3
tWED4
tWB
tVPH
tRHH
tREL
-9/-9 ET
MIN
MAX
90
20
50
50
0
50
0
0
0
200
100
1,000
100
2
100
100
500
200
0
0
100
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ms
ms
ns
ns
ns
ns
NOTES
1
2
3
5
5
5
5
4
5
3
6
WORD/BYTE WRITE AND ERASE DURATION CHARACTERISTICS
3.3V VPP
5V VPP
PARAMETER
TYP MAX TYP MAX UNITS NOTES
Boot/parameter BLOCK ERASE time
0.5
7
0.4
7
Main BLOCK ERASE time
2.8
14
1.5
14
s
7
Main BLOCK WRITE time (byte mode)
1.5
–
1
–
s
7, 8, 9
Main BLOCK WRITE time (word mode)
1.5
–
1
–
s
7, 8, 9
NOTE: 1.
2.
3.
4.
5.
6.
7.
8.
9.
s
7
Measured with VPP = VPPH1 = 3.3V.
Measured with VPP = VPPH2 = 5V.
RP# should be held at VHH or WP# held HIGH until boot block WRITE or ERASE is complete.
Polling status register before tWB is met may falsely indicate WRITE or ERASE completion.
WRITE/ERASE times are measured to valid status register data (SR7 = 1).
tREL is required to relock boot block after WRITE or ERASE to boot block.
Typical values measured at TA = +25ºC.
Assumes no system overhead.
Typical WRITE times use checkerboard data pattern.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE
WE#-CONTROLLED WRITE/ERASE
VIH
A0–A18/(A19)
Note 1
VIL
tAS
AIN
tAS
tAH
tAH
VIH
CE#
VIL
tCS
tCH
VIH
OE#
VIL
tWC
tWP
tWED1/2/3/4
tWPH
VIH
WE#
DQ0–DQ7/
DQ0–DQ15 2
tWB
VIL
VIH
tDS
CMD
in
VIL
VHH
tDH
tDH
tDS
Status
(SR7=0)
CMD/
Data-in
tRS
tRHS
Status
(SR7=1)
tRHH
CMD
in
[Unlock boot block]
VIH
RP# 3
VIL
[Unlock boot block]
VIH
WP# 3
VIL
tVPS1
tVPS2
VPPH2
VPP
tVPH
[5V VPP]
[3.3V VPP]
VPPH1
VIL
WRITE or ERASE (block)
address asserted, and
WRITE data or ERASE
CONFIRM issued
WRITE SETUP or
ERASE SETUP input
WRITE or ERASE
executed, status register
checked for completion
Command for next
operation issued
DON’T CARE
TIMING PARAMETERS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
Extended Temperature (-40ºC ≤ TA ≤ +85ºC)
SYMBOL
tWC
tWPH
tWP
tAS
tAH
tDS
tDH
tCS
tCH
tVPS1
-9/-9 ET
MIN
MAX
90
UNITS
ns
SYMBOL
tVPS2
20
50
ns
ns
tRS
50
0
50
ns
ns
ns
tWED1
0
0
ns
ns
tWED4
0
200
ns
ns
tVPH
tRHS
tWED2
tWED3
tWB
-9/-9 ET
MIN
MAX
UNITS
100
ns
1,000
100
2
ns
ns
µs
100
100
ms
ms
500
200
ms
ns
0
0
ns
ns
tRHH
NOTE: 1. Address inputs are “Don’t Care” but must be held stable.
2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit.
3. Either RP# at VHH or WP# HIGH unlocks the boot block.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE
CE#-CONTROLLED WRITE/ERASE
VIH
A0–A18/(A19)
Note 1
VIL
tAS
AIN
tAS
tAH
tAH
VIH
WE#
VIL
tWS
tWH
VIH
OE#
VIL
tWC
tCP
tWED1/2/3/4
tCPH
VIH
CE#
DQ0–DQ7/
DQ0–DQ15 2
VIL
VIH
VIL
VHH
tWB
tDH
tDS
tDH
tDS
CMD
in
Status
(SR7=0)
CMD/
Data-in
tRS
tRHS
Status
(SR7=1)
tRHH
CMD
in
[Unlock boot block]
VIH
RP# 3
VIL
[Unlock boot block]
VIH
WP#
3
VIL
tVPS1
tVPS2
VPPH2
VPP
tVPH
[5V VPP]
[3.3V VPP]
VPPH1
VIL
WRITE or ERASE (block)
address asserted, and
WRITE data or ERASE
CONFIRM issued
WRITE SETUP or
ERASE SETUP input
WRITE or ERASE
executed, status register
checked for completion
Command for next
operation issued
DON’T CARE
TIMING PARAMETERS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
Extended Temperature (-40ºC ≤ TA ≤ +85ºC)
SYMBOL
tWC
tCPH
tCP
tAS
tAH
tDS
tDH
tWS
tWH
tVPS1
-9/-9 ET
MIN
MAX
90
UNITS
ns
SYMBOL
tVPS2
20
50
ns
ns
tRS
50
0
50
ns
ns
ns
tWED1
0
0
ns
ns
tWED4
0
200
ns
ns
tVPH
tRHS
tWED2
tWED3
tWB
-9/-9 ET
MIN
MAX
UNITS
100
ns
1,000
100
2
ns
ns
µs
100
100
ms
ms
500
200
ms
ns
0
0
ns
ns
tRHH
NOTE: 1. Address inputs are “Don’t Care” but must be held stable.
2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit.
3. Either RP# at VHH or WP# HIGH unlocks the boot block.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
40-PIN PLASTIC TSOP I
(10mm x 20mm)
.795 (20.20)
.780 (19.80)
.727 (18.47)
.0197 (0.50)
TYP
.010 (0.25)
.721 (18.31)
1
40
PIN #1 INDEX
.397 (10.08)
.391 (9.93)
.010 (0.25)
.006 (0.15)
20
21
.010 (0.25)
.004 (0.10)
.007 (0.18)
.005 (0.13)
GAGE
PLANE
.047 (1.20)
MAX
SEE DETAIL A
.008 (0.20)
.002 (0.05)
.024 (0.60)
.016 (0.40)
DETAIL A
.0315 (0.80)
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
48-PIN PLASTIC TSOP I
(12mm x 20mm)
.795 (20.20)
.780 (19.80)
.727 (18.47)
.0197 (0.50)
TYP
.010 (0.25)
.721 (18.31)
1
48
PIN #1 INDEX
.475 (12.07)
.469 (11.91)
.010 (0.25)
.006 (0.15)
25
24
.010 (0.25)
.004 (0.10)
.007 (0.18)
.005 (0.12)
SEE DETAIL A
GAGE
PLANE
.047 (1.20) MAX
.008 (0.20)
.002 (0.05)
.024 (0.60)
.016 (0.40)
DETAIL A
.0315 (0.80)
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
44-PIN PLASTIC SOP1
(600 mil)
1.113 (28.27)
1.107 (28.12)
.050 (1.27)
TYP
.007 (0.18)
.020 (0.50)
.015 (0.38)
.005 (0.13)
.643 (16.34)
.620 (15.74)
.499 (12.68)
.493 (12.52)
PIN #1 INDEX
.030 (0.76)
SEE DETAIL A
.004 (0.10)
.016 (0.40)
.010 (0.25)
.106 (2.70) MAX
GAGE PLANE
.010 (0.25)
DETAIL A
.0315 (0.80)
(ROTATED 90 CW)
.066 (1.72)
NOTE: 1. Not recommended for new designs.
2. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
3. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
The Micron logo and the M logo are trademarks of Micron Technology, Inc.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
REVISION HISTORY
Rev. 3, Pub. 10/01 ................................................................................................................................................... 10/01
• Updated input capacitance spec
• Changed access time to 90ns
Rev. 2 ......................................................................................................................................................................................... 3/01
• Changed to 0.18µm process
• 12V VPP no longer supported
• 10V ≤ VHH ≤ 12V
• VOH ≤ VCC - 0.2V
• tRWH changed to 1µs from 800ns
• tAH changed to 10ns from 0ns
• AC test output load CL changed to 50pF
• Typical main BLOCK ERASE time changed to 1.5s from 1s
• Typical main BLOCK WRITE time (byte mode) changed to 1s from 0.5s
• Typical main BLOCK WRITE time (word mode) changed to 1s from 0.5s
• MT28F800B3 only available in WG and SG packages
• MT28F008B3 only available in VG package
• Added 80ns access time for commercial and extended temperature ranges
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
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