SRAM MT5C1005 Austin Semiconductor, Inc. 256K x 4 SRAM PIN ASSIGNMENT (Top View) SRAM MEMORY ARRAY AVAILABLE AS MILITARY SPECIFICATIONS 32-Pin LCC (EC) 32-Pin SOJ (DCJ) 28-Pin DIP (C) (400 MIL) •MIL-STD-883 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 CE\ OE\ Vss FEATURES • • • • High Speed: 20, 25, 35, and 45 Battery Backup: 2V data retention Low power standby High-performance, low-power CMOS double-metal process • Single +5V (+10%) Power Supply • Easy memory expansion with CE\ and OE\ options. • All inputs and outputs are TTL compatible OPTIONS -20 -25 -35 -45 -55* -70* • Package(s) Ceramic DIP (400 mil) C Ceramic Quad LCC (contact factory) ECW Ceramic LCC EC Ceramic Flatpack F Ceramic SOJ DCJ A7 A8 A9 A12 A10 A11 A13 NC A14 A15 A16 A17 NC CE\ OE\ Vss Vcc A6 A5 A4 A3 A2 A1 A0 NC DQ4 DQ3 DQ2 DQ1 WE\ 32-Pin Flat Pack (F) No. 109 No. 206 No. 207 No. 303 No. 501 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A6 A5 A2 A4 A3 A1 NC NC A0 NC DQ4 DQ3 DQ2 DQ1 WE\ 32-Pin LCC (ECW) Vcc A6 A5 A2 A4 A3 A1 NC NC A0 NC DQ4 DQ3 DQ2 DQ1 WE\ A9 A8 A7 NC Vcc A6 A5 A7 A8 A9 A12 A10 A11 A13 NC A14 A15 A16 A17 NC CE\ OE\ Vss 4 3 2 1 31 32 30 A10 A11 A12 A13 A14 A15 A16 A17 CE\ 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 A2 A4 A3 A1 A0 NC NC NC DQ4 14 15 16 17 18 19 20 GENERAL DESCRIPTION The Austin Semiconductor SRAM family employs high-speed, low power CMOS designs fabricated using doublelayer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, ASI offers chip enable (CE\) and output enable (OE\) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH while CE\ and OE\ go LOW. The devices offer a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. All devices operation from a single +5V power supply and all inputs and outputs are fully TTL compatible. • Operating Temperature Ranges IT Industrial (-40oC to +85oC) Military (-55oC to +125oC) XT • 2V data retention/low power 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DQ3 DQ2 DQ1 WE\ Vss OE\ NC • Timing 20ns access 25ns access 35ns access 45ns access 55ns access 70ns access MARKING 1 2 3 4 5 6 7 8 9 10 11 12 13 14 L *Electrical characteristics identical to those provided for the 45ns access devices. For more products and information please visit our web site at www.austinsemiconductor.com MT5C1005 Rev. 3.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM MT5C1005 Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM VCC A GND A ROW DECODER A A A A DQ4 I/O CONTROL A 262,144 x 4-BIT MEMORY ARRAY A DQ1 A A CE\ COLUMN DECODER OE\ WE\ A A A A A A A A POWER DOWN TRUTH TABLE MODE STANDBY READ READ WRITE MT5C1005 Rev. 3.2 06/05 OE\ X L H X CE\ H L L L WE\ X H H L DQ HIGH-Z Q HIGH-Z D POWER STANDBY ACTIVE ACTIVE ACTIVE Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM MT5C1005 Austin Semiconductor, Inc. *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS* Supply Voltage Range (Vcc)................................-.5V to +7.0V Storage Temperature......................................-65°C to +150°C Voltage on any Pin Relative to Vss................-.5V to Vcc+.5V Max Junction Temperature............................................+175°C Lead Temperature (soldering 10 seconds)..................+260oC Power Dissipation ...............................................................1 W ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TC < 125oC; VCC = 5V +10%) DESCRIPTION Input High (Logic 1) Voltage CONDITIONS SYM MIN MAX UNITS NOTES VIH 2.2 VCC+0.5 V 1 VIL -0.5 0.8 V 1 Input Low (Logic 0) Voltage Input Leakage Current 0V<VIN<VCC ILI -10 10 µA Output Leakage Current Output(s) disabled 0V<VOUT<VCC ILO -10 10 µA Output High Voltage IOH = -4.0mA VOH 2.4 Output Low Voltage IOL = 8.0mA VOL 0.4 V 1 V 1 CONDITIONS SYM -20 MAX -25 -35 -45 Power Supply Current: Operating WE\, CE\ < VIL; VCC = MAX Output Open Icc 180 180 180 180 mA Power Supply Current: Standby CE\ > VIH; All Other Inputs ISBT2 25 25 25 25 mA ISBC 16 16 16 16 mA PARAMETER < VIL or > VIH, VCC = MAX CE\ > VCC -0.2V; VCC = MAX VIL < VSS +0.2V VIH > VCC -0.2V; f = 0 Hz* UNITS NOTES 3 * “L” version only. CAPACITANCE PARAMETER Input Capacitance CONDITIONS SYM MAX UNITS NOTES VIN = 0V, CI 12 pF 4 CO 14 pF 4 TA = 25°C, f = 1MHz Output Capacitance (DQ1-DQ4) MT5C1005 Rev. 3.2 06/05 VCC = 5V Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SRAM MT5C1005 Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (-55oC < TC < 125oC; VCC = 5V +10%) DESCRIPTION READ CYCLE READ cycle time Address access time Chip Enable access time Output hold from address change Chip Enable to output in Low-Z Chip disable to output in High-Z Chip Enable to power-up time Chip disable to power-down time Output Enable access time Output Enable to output in Low-Z Output disable to output in High-Z WRITE CYCLE WRITE cycle time Chip Enable to end of write Address valid to end of write Address setup time Address hold from end of write WRITE pulse width Data setup time Data hold time Write disable to output in Low-Z Write Enable to output in High-Z MT5C1005 Rev. 3.2 06/05 -20 -25 -35 -45 SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES tRC tAA tACE tOH tLZCE tHZCE tPU tPD tAOE tLZOE tHZOE 20 tWC tCW tAW tAS tAH tWP tDS tDH 20 15 15 0 0 15 12 0 3 0 tLZWE tHZWE 25 20 20 3 3 35 25 25 3 3 10 0 3 3 12 0 20 8 0 0 8 20 25 20 20 0 0 20 15 0 3 0 0 10 20 ns ns ns ns ns ns ns ns ns ns 4, 6, 7 4, 6, 7 45 25 0 20 35 30 30 0 0 30 20 0 3 0 25 4, 6, 7 4, 6, 7 25 0 35 20 10 ns ns ns ns ns ns ns ns ns ns ns 45 45 3 3 0 25 10 8 45 35 35 15 45 35 35 0 0 35 25 0 3 0 4, 6, 7 4, 6, 7 4 4 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SRAM MT5C1005 Austin Semiconductor, Inc. AC TEST CONDITIONS Input pulse levels ................................... Vss to 3.0V Input rise and fall times ....................................... 5ns Input timing reference levels ............................. 1.5V Output reference levels ..................................... 1.5V Output load .............................. See Figures 1 and 2 167Ω Q 30pF 167Ω VTH = 1.73V Q Fig. 1 Output Load Equivalent 5pF VTH = 1.73V Fig. 2 Output Load Equivalent 7. At any given temperature and voltage condition, t HZCE is less than tLZCE, and tHZWE is less than t LZWE and tHZOE is less than tLZOE. 8. WE\ is HIGH for READ cycle. 9. Device is continuously selected. Chip enables and output enables are held in their active state. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip enable (CE\) and write enable (WE\) can initiate and terminate a WRITE cycle. NOTES 1. 2. 3. All voltages referenced to VSS (GND). -3V for pulse width < 20ns ICC is dependent on output loading and cycle rates. The specified value applies with the outputs unloaded, and f = 1 Hz. t RC (MIN) 4. This parameter is guaranteed but not tested. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. Minimum of 5pF for tEHQZ, tOHQZ, tELQX, tOLQX, and tWHQX. DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) CONDITIONS DESCRIPTION SYM VCC for Retention Data VDR CE\ > (VCC-0.2V) and VIN > (VCC-0.2V) or < 0.2V Data Retention Current VCC = 2V Chip Deselect to Data Retention Time Operation Recovery Time MIN 2 MAX ICCDR tCDR 0 tR tRC UNITS NOTES V 5 mA -- ns 4 ns 4, 11 LOW Vcc DATA RETENTION WAVEFORM DATA RETENTION MODE VCC 4.5V VDR > 2V t t CDR CE\ VIH VIL 1234 123456789 123 123456789 123 1234 123456789 123 1234 123456789 123 1234 4.5V R V DR 12345678 1234 123 12345678 1234 123 12345678 1234 123 12345678 1234 123 123 123 123 123 DON’T CARE 1234 1234 1234 1234UNDEFINED MT5C1005 Rev. 3.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 SRAM MT5C1005 Austin Semiconductor, Inc. READ CYCLE NO. 1 8, 9 ttRC RC ADDRESS VALID ttAA AA ttOH OH DQ PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 2 7, 8, 10 ttRC RC CE\ ttAOE AOE t HZOE tHZOE tLZOE tLZOE OE\ ttLZCE LZCE tACE tACE tHZCE tHZCE DQ DATA VALID ttPU PU ttPD PD Icc 1234 1234 1234DON’T CARE 1234 1234 1234 1234 UNDEFINED MT5C1005 Rev. 3.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 SRAM MT5C1005 Austin Semiconductor, Inc. WRITE CYCLE NO. 1 12 (Chip Enabled Controlled) t WC tWC ADDRESS tAW tAW ttAS AS t AH tAH tCW tCW CE\ 1234567890123456789012 1 1 WE\ 1234567890123456789012 t WP tWP1 1123456789012345678901234567890121234567890 1123456789012345678901234567890121234567890 t DH tDH ttDS DS D DATA VAILD Q HIGH Z WRITE CYCLE NO. 2 7, 12 (Write Enabled Controlled) tWC tWC ADDRESS tAW tAW ttAH AH tCW tCW 12345678901234567 121 12345678901234567 12 12345678901234567 121 CE\ tAS t AS 12345678901234567890123 1 1212345678901234567890123 112345678901234567890123 t WP tWP1 WE\ tDS D t DH tDH DATA VALID Q HIGH-Z 1234 1234 1234DON’T CARE 1234 12345 12345 12345 12345UNDEFINED NOTE: Output enable (OE\) is inactive (HIGH). MT5C1005 Rev. 3.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 SRAM MT5C1005 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #109 (Package Designator C) D A Q Pin 1 L e b b1 E c E1 SYMBOL A b b1 c D E E1 e L Q ASI PACKAGE SPECIFICATIONS MIN MAX 0.090 0.110 0.016 0.020 0.040 0.060 0.008 0.012 1.386 1.414 0.385 0.405 0.390 0.410 0.090 0.110 0.125 0.175 0.040 0.060 *All measurements are in inches. MT5C1005 Rev. 3.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 SRAM MT5C1005 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #206 (Package Designator ECW) E1 A L1 e D D1 b2 b E SYMBOL A b b1 b2 D D1 E E1 e L L1 b1 L ASI PACKAGE SPECIFICATIONS MIN MAX 0.077 0.093 0.022 0.028 0.004 0.014 0.054 0.066 0.742 0.758 0.395 0.405 0.442 0.458 0.295 0.305 0.045 0.055 0.045 0.055 0.077 0.093 *All measurements are in inches. MT5C1005 Rev. 3.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 SRAM Austin Semiconductor, Inc. MT5C1005 MECHANICAL DEFINITIONS* ASI Case #207 (Package Designator EC) A L1 D L e b b1 E b2 SYMBOL A b b1 b2 D E e L L1 ASI PACKAGE SPECIFICATIONS MIN MAX 0.080 0.100 0.022 0.028 0.004 0.014 0.054 0.066 0.815 0.835 0.392 0.408 0.045 0.055 0.070 0.080 0.090 0.110 *All measurements are in inches. MT5C1005 Rev. 3.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 SRAM MT5C1005 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #303 (Package Designator F) E L Pin 1 Index e 32 1 17 16 D b D1 Bottom View Top View A c Q E2 SYMBOL A b c D D1 E E2 e L Q ASI PACKAGE SPECIFICATIONS MIN MAX --0.125 0.015 0.019 0.004 0.006 0.812 0.828 0.745 0.755 0.405 0.415 0.324 0.336 0.045 0.055 0.290 0.310 0.027 0.033 *All measurements are in inches. MT5C1005 Rev. 3.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 SRAM Austin Semiconductor, Inc. MT5C1005 MECHANICAL DEFINITIONS* ASI Case #501 (Package Designator DCJ) A D e D1 R E2 b E1 E A2 SYMBOL A A2 b D D1 E e E1 E2 R ASI PACKAGE SPECIFICATIONS MIN MAX 0.135 0.153 0.026 0.036 0.015 0.019 0.812 0.828 0.740 0.755 0.405 0.415 0.045 0.055 0.435 0.445 0.360 0.380 0.030 0.040 *All measurements are in inches. MT5C1005 Rev. 3.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 SRAM Austin Semiconductor, Inc. MT5C1005 ORDERING INFORMATION EXAMPLE: MT5C1005EC-45/XT EXAMPLE: MT5C1005C-20L/IT Device Number Package Speed Options** Process Type ns Device Number MT5C1005 C -20 L /* MT5C1005 MT5C1005 C -25 L /* MT5C1005 MT5C1005 C -35 L /* MT5C1005 MT5C1005 C -40 L /* MT5C1005 MT5C1005 C -55 L /* MT5C1005 MT5C1005 C -70 L /* MT5C1005 Package Speed Options** Process Type ns EC -20 L /* ECW EC -25 L /* ECW EC -35 L /* ECW EC -40 L /* ECW EC -55 L /* ECW EC -70 L /* ECW EXAMPLE: MT5C1005F-25L/883C EXAMPLE: MT5C1005DCJ-70/XT Device Package Speed Options** Process ns Number Type MT5C1005 F -20 L /* MT5C1005 F -25 L /* MT5C1005 F -35 L /* MT5C1005 F -40 L /* MT5C1005 F -55 L /* MT5C1005 F -70 L /* Device Package Speed Options** Process Number Type ns MT5C1005 DCJ -20 L /* MT5C1005 DCJ -25 L /* MT5C1005 DCJ -35 L /* MT5C1005 DCJ -40 L /* MT5C1005 DCJ -55 L /* MT5C1005 DCJ -70 L /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing -40oC to +85oC -55oC to +125oC -55oC to +125oC ** OPTIONS L = 2V Data Retention/Low Power MT5C1005 Rev. 3.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13