Zarlink MT88E39ASR Calling number identification circuit Datasheet

MT88E39
Calling Number Identification Circuit
(CNIC1.1)
Data Sheet
Features
November 2004
•
1200 baud Bell 202 and CCITT V.23 Frequency
Shift Keying (FSK) demodulation
•
Compatible with Bellcore GR-30-CORE, SR-TSV002476, TIA/EIA-716 and ETSI 300 778-1
•
High input sensitivity
•
Dual mode 3-wire data interface (Serial FSK data
stream or MT88E43 compatible 1 byte buffer)
•
Internal gain adjustable amplifier
•
Carrier detect status output
•
Uses 3.579545 MHz crystal or ceramic resonator
•
3 to 5 V ±10% supply voltage
•
Low power CMOS with power down mode
•
Direct pin to pin replacement of MT8841 and
MT88E41
Ordering Information
MT88E39AS
MT88E39ASR
MT88E39AS1
MT88E39ASR1
Pin
Pin
Pin
Pin
SOIC
SOIC
SOIC*
SOIC*
Tubes
Tape & Reel
Tubes
Tape & Reel
*Pb Free Matte Tin
-40°C to +85°C
Description
The MT88E39 Calling Number Identification Circuit
(CNIC1.1) is a CMOS integrated circuit which provides
an interface to calling line information delivery services
that utilize 1200 baud Bell 202 or CCITT V.23 FSK data
transmission schemes. The MT88E39 receives and
demodulates the FSK signal and outputs the data into
a simple dual mode 3-wire serial interface which
eliminates the need for an UART.
Applications
•
16
16
16
16
Global (North America, Japan, Europe) FSK
based CID (Calling Identity Delivery) / CLIP
(Calling Line Identity Presentation)
•
Feature phones, adjunct boxes
•
FAX machines
•
Telephone answering machines
•
Computer Telephony Integration (CTI)
•
Battery powered applications
The MT88E39 is Bellcore, ETSI and NTT compatible
and can operate in 3 V and 5 V applications. It is a pin
to pin replacement of the MT8841 and MT88E41 by
operating in the MT88E41 FSK interface mode (mode
0) when placed in a MT88E41 socket. New designs
may also choose the MT88E43 compatible interface
(mode 1) where the microcontroller reads the FSK byte
from a 1 byte buffer.
GS
DATA
IN-
-
IN+
+
Receive
Bandpass
Filter
Data and Timing
Recovery
FSK
Demodulator
DR
DCLK
CAP
VRef
Bias
Generator
Carrier
Detector
to other
circuits
Clock
Generator
PWDN
CD
OSC1 OSC2
MODE
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1998 - 2004, Zarlink Semiconductor Inc. All Rights Reserved.
IC
MT88E39
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN+
INGS
VRef
CAP
OSC1
OSC2
VSS
Data Sheet
VDD
IC**
MODE*
PWDN
CD
DR
DATA
DCLK
16 PIN SOIC
* Was IC1 in MT88E41
** Was IC2 in MT88E41
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
IN+
Non-inverting Op-Amp (Input).
2
IN-
Inverting Op-Amp (Input).
3
GS
Gain Select (Output). Gives access to op-amp output for connection of feedback resistor.
4
VRef
Voltage Reference (Output). Nominally VDD/2. This is used to bias the op-amp inputs.
5
CAP
Capacitor. Connect a 0.1 µF capacitor to VSS.
6
OSC1 Oscillator (Input). Crystal connection. This pin can be driven directly from an external clocking
source.
7
OSC2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external clock, this pin
should be left open.
8
VSS
Power supply ground.
9
DCLK 3-wire FSK Interface: Data Clock (CMOS Output/Schmitt Input). In mode 0 (MT88E41
compatible mode - when the MODE pin is logic low) this is a CMOS output which denotes the
nominal mid-point of a FSK data bit.
In mode 1 (when the MODE pin is logic high) this is a Schmitt trigger input used to shift the
FSK data byte out to the DATA pin.
10
DATA 3-wire FSK Interface: Data (CMOS Output). In mode 0 (MT88E41 compatible mode - when
the MODE pin is logic low) the FSK serial bit stream is output to DATA as demodulated. Mark
frequency corresponds to logical 1. Space frequency corresponds to logical 0.
In mode 1 (when the MODE pin is logic high) the start and stop bits are stripped off and only
the data byte is stored in a 1 byte buffer. At the end of each word signalled by the DR pin, the
microcontroller should shift the byte out to DATA pin by applying 8 read pulses at the DCLK
pin.
11
DR
3-wire FSK Interface: Data Ready (Open Drain/CMOS Output). Active low. In mode 0
(MT88E41 compatible mode - when the MODE pin is logic low) this is an open drain output. In
mode 1 (when the MODE pin is logic high) this is a CMOS output.
This pin denotes the end of a word. Typically, DR is used to interrupt the microcontroller. It is
normally hi-Z or high (modes 0 and 1 respectively) and goes low for half a bit time at the end of
a word. But in mode 1 if DCLK begins during DR low, the first rising edge of the DCLK input
will return DR to high. This feature allows an interrupt requested by DR to be cleared upon
reading the first DATA bit.
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Zarlink Semiconductor Inc.
MT88E39
Data Sheet
Pin Description
Pin #
Name
12
CD
Description
Carrier Detect (Open Drain/CMOS Output). Active low. In mode 0 (MT88E41 compatible
mode - when the MODE pin is logic low) this is an open drain output. In mode 1 (when the
MODE pin is logic high) this is a CMOS output.
A logic low indicates that a carrier has been present for a specified time on the line. A time
hysteresis is provided to allow for momentary discontinuity of carrier. The demodulated FSK
data is inhibited until the carrier has been detected.
13
PWDN Power Down (Schmitt Input). Active high. Powers down the device including the input opamp and the oscillator. Must be low for operation.
14
MODE Mode select (Input). This pin selects the 3-wire FSK interface mode. To select mode 0
(MT88E41 compatible mode) this pin should be logic low. To select mode 1 this pin should be
logic high.
Because this pin is already connected to Vss in ’E41 applications, the MT88E39 can replace
the ’E41 without any circuit or software change.
15
IC
16
VDD
Internal Connection. Internal connection. Leave open circuit. In MT88E41, this was IC2
which was also left open in the application circuit.
Positive power supply voltage.
Functional Description
The MT88E39 is a FSK demodulator compatible with FSK based Caller ID services around the world, such as in
North America, France, Germany, and Japan. Caller ID is the generic term for a group of services offered by
telephone operating companies whereby information about the calling party is delivered to the subscriber. In the
FSK based methods, the information is modulated in either Bell 202 (in North America) or CCITT V.23 (in Europe)
FSK format and transmitted at 1200 baud from the serving end office to the subscriber’s terminal.
In North America, Caller ID uses the voiceband data transmission interface defined in the Bellcore document GR30-CORE. The terminal or CPE (Customer Premises Equipment) requirements are defined in Bellcore document
SR-TSV-002476. Typical services are CND (Calling Number Delivery), CNAM (Calling Name Delivery), VMWI
(Visual Message Waiting Indicator) and CIDCW (Calling Identity Delivery on Call Waiting).
In on-hook Caller ID, such as CND and CNAM, the information is typically transmitted from the end office before the
subscriber picks up the phone. There are various methods such as between the first and second rings (North
America), between an abbreviated ring and the first true ring (Japan, France and Germany). On-hook Caller ID can
also occur without ringing for services such as VMWI. The MT88E39 is suitable for these forms of alerting.
In off-hook Caller ID, such as CIDCW, information about a new calling party is sent to the subscriber who is already
engaged in a call. Bellcore’s method uses a special dual tone known as CAS (CPE Alerting Signal) which should be
detected by the CPE. After the CPE has acknowledged with a DTMF digit, the end office will send the FSK data.
The MT88E39 is suitable for receiving the FSK data but a separate CAS detector is required.
The MT88E39 provides an interface to the Caller ID physical layer. It bandpass filters and demodulates the 1200
baud FSK signal. It also provides a convenient interface to extract the demodulated FSK data. Although the main
application of the MT88E39 is Caller ID, it can also be used wherever 1200 baud Bell 202 and/or CCITT V.23 FSK
reception is required.
3 to 5V operation
The MT88E39 can operate from 5.5 V down to 2.7 V, but the FSK reject level will change with Vdd. In a battery
powered CPE, the FSK accept level will become lower as the batteries are run down. If the CPE is designed for
4.5 V, the accept level will be lowered when the batteries drain to 3 V. In North America there is a requirement for
rejecting FSK signals which are below 3 mVrms when data is not preceded by ringing, such as VMWI (Visual
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Zarlink Semiconductor Inc.
MT88E39
Data Sheet
Message Waiting Indicator) applications. When the batteries are drained, the CPE will not meet the reject level. For
on-hook Caller ID, there is no reject level and the CPE will meet all requirements.
Input Configuration
The input arrangement of the MT88E39 provides an operational amplifier, as well as a bias source (VRef) which is
used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the op-amp output (GS)
for adjustment of gain.
Figure 3 shows the necessary connections for a differential input configuration. In a single-ended configuration, the
input pins are connected as shown in Figure 4.
C1
R1
IN+
IN-
C2
R4
R5
GS
R2
R3
VRef
DIFFERENTIAL INPUT AMPLIFIER
MT88E39
C1 = C2
R1 = R4
R3 = (R2 x R5) / (R2 + R5)
For unity gain, R5 = R1
INPUT IMPEDANCE
VOLTAGE GAIN
(AVdiff) = R5/R1
(ZINdiff) = 2 R12 + (1/ωC)2
Figure 3 - Differential Input Configuration
IN+
C
IN-
RIN
RF
GS
VRef
VOLTAGE GAIN
(AV) = RF / RIN
MT88E39
Figure 4 - Single-Ended Input Configuration
3-wire FSK Data Interface
The MT88E39 provides a powerful dual mode 3-wire interface so that the 8-bit data words in the demodulated FSK
bit stream can be extracted without the need either for an external UART or for the microcontroller to perform the
UART function in software. The interface is specifically designed for the 1200 baud rate and is comprised of the
DATA, DCLK (data clock) and DR (data ready) pins. Two modes (0 and 1) are selectable via control of the device’s
MODE pin. In mode 0 the FSK bit stream is output as demodulated. In mode 1 the FSK data byte is store in a 1 byte
buffer. Note that in mode 0 DR and CD are open drain outputs; in mode 1 they are CMOS outputs. DCLK is an
output in mode 0, an input in mode 1.
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Zarlink Semiconductor Inc.
MT88E39
Data Sheet
Mode 0
This mode is selected when the MODE pin is low. It is the MT88E41 compatible mode where the FSK data stream
is output as demodulated. Since the MODE pin was IC1 in MT88E41 and connected to Vss, the MT88E39 will work
in mode 0 when placed in a MT88E41 socket.
In this mode, the MT88E39 receives the FSK signal, demodulates it, and outputs the data directly to the DATA pin
(see Figure 11). For each received stop and start bit sequence, the MT88E39 outputs a fixed frequency clock string
of 8 pulses at the DCLK pin. Each DCLK rising edge occurs in the nominal centre of a data bit. DCLK is not
generated for the stop and start bits. Consequently, DCLK will clock only valid data into a peripheral device such as
a serial to parallel shift register or a microcontroller. The MT88E39 also outputs an end of word pulse (Data Ready)
on the DR pin, which indicates the reception of every 10-bit word (counting the start and stop bits) sent from the end
office. DR can be used to interrupt a microcontroller or cause a serial to parallel converter to parallel load its data
into a microcontroller. The mode 0 DATA pin can also be connected to a personal computer’s serial communication
port after converting from CMOS to RS-232 voltage levels.
Mode 1
This mode is selected when the MODE pin is high. In this mode, the microcontroller supplies read pulses at the
DCLK pin (which is now an input) to shift the 8-bit data words out of the MT88E39, onto the DATA pin. The
MT88E39 asserts DR to denote the word boundary and indicate to the microprocessor that a new word has
become available (see Figure 12).
Internal to the MT88E39, the demodulated data bits are sampled and stored. The start and stop bits are stripped
off. After the 8th bit, the data byte is parallel loaded into an 8 bit shift register and DR goes low. The shift register’s
contents are shifted out to the DATA pin on the supplied DCLK’s rising edge in the order they were received.
If DCLK begins while DR is low, DR will return to high upon the first DCLK. This feature allows the associated
interrupt to be cleared by the first read pulse. Otherwise DR is low for half a nominal bit time (1/2400 sec). After the
last bit has been read, additional DCLKs are ignored.
Note that in both modes, the 3-pin interface may also output data generated by speech or other voiceband signals.
The user may choose to ignore these outputs when FSK data is not expected, or force the MT88E39 into its power
down mode.
Power Down Mode
For applications requiring reduced power consumption, the MT88E39 can be forced into power down when it is not
needed. This is done by pulling the PWDN pin high. In power down mode, the oscillator, op-amp and internal
circuitry are all disabled and the MT88E39 will not react to the input signal. DR and CD are at high impedance or at
logic high (modes 0 and 1 respectively). In mode 0, DATA and DCLK are at logic high. The MT88E39 can be
awakened for reception of the FSK signal by pulling the PWDN pin low.
Carrier Detect
The carrier detector provides an indication of the presence of a signal in the FSK frequency band. It detects the
presence of a signal of sufficient amplitude at the output of the FSK bandpass filter. The signal is qualified by a
digital algorithm before the CD output is set low to indicate carrier detection. A 10ms hysteresis is provided to allow
for momentary signal drop out once CD has been activated. CD is released when there is no activity at the FSK
bandpass filter output for 10 ms.
When CD is inactive (high), the raw output of the demodulator is ignored by the data timing recovery circuit (see
Figure 1). In mode 0, the DATA pin is forced high. No DCLK or DR signal is generated. In mode 1, the internal shift
register is not updated and no DR is generated. If DCLK is clocked (in mode 1), DATA is undefined.
Note that signals such as CAS, speech and DTMF tones also lie in the FSK frequency band and the carrier detector
may be activated by these signals. They will be demodulated and presented as data. To avoid false data, the
PWDN pin should be used to disable the FSK demodulator when no FSK signal is expected.
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Zarlink Semiconductor Inc.
MT88E39
Data Sheet
Ringing, on the other hand, does not pose a problem as it is ignored by the carrier detector.
Crystal Oscillator
The MT88E39 uses either a 3.579545 MHz ceramic resonator or crystal oscillator as the master timing source.
The crystal specification is as follows:
Frequency:
3.579545 MHz
Frequency tolerance:
±0.2%(-40°C+85°C)
Resonance mode:
Parallel
Load capacitance:
18 pF
Maximum series resistance:
150 ohms
Maximum drive level (mW):
2 mW
e.g., CTS MP036S
MT88E39
OSC1
OSC2
MT88E39
OSC1
OSC2
MT88E39
OSC1
OSC2
to the
next MT88E39
3.579545 MHz
(For 5 V application only)
Figure 5 - Common Crystal Connection
For 5 V applications any number of MT88E39 devices can be connected as shown in Figure 5 such that only one
crystal is required. The connection between OSC2 and OSC1 can be DC coupled as shown, or the OSC1 input on
all devices can be driven from a CMOS buffer (dc coupled) with the OSC2 outputs left unconnected.
VRef and CAP Inputs
VRef is the output of a low impedance voltage source equal to VDD/2 and is used to bias the input op-amp. A 0.1 µF
capacitor is required between CAP and VSS to suppress noise on VRef.
Applications
Table 1 shows the Bellcore and ETSI FSK signal characteristics. The application circuit in Figure 6 will meet these
requirements.
For 5 V designs the input op-amp should be set to unity gain to meet the Bellcore requirements and -2.5 dB gain for
ETSI requirements.
As supply voltage (VDD) is decreased, the FSK detect threshold will be lowered. Therefore for designs operating at
other than 5 V nominal voltage, to meet the FSK reject level requirement the gain of the op-amp should be reduced
accordingly.
For 3 V designs the gain settings for Bellcore and ETSI should be -3 dB and -5.5 dB respectively.
For applications requiring detection of lower FSK signal level, the input op-amp may be configured to provide
adequate gain. However, too much gain will cause noise tolerance to fail the TIA requirements because the FSK
signal will be clipped at GS when the single tone noise is added.
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Zarlink Semiconductor Inc.
MT88E39
Data Sheet
Vdd
Vdd
C1
TIP
R1
R2
D1
MT88E39
D2
Vdd
C2
RING
R3
R4
D3
R7
R5
R6
D4
100 nF
20%
100 nF
10%
50 V
Xtal
D5
D7
D6
D8
100 nF
20%
IN+
VDD
IN-
IC
GS
MODE
VRef
PWDN
CAP
CD
OSC1
DR
OSC2
DATA
VSS
DCLK
Vdd
R8*1
R9*1
1N5231B
(FSK interface mode 0 selected)
Vdd
330 nF R10
10%
250 V
Vdd
= To microcontroller
= From microcontroller
200 K
5%
Motorola
4N25
(Ring Detect)
10 nF
464 K
5%
To microcontroller
Note:
*1 R8 and R9 not required when FSK interface mode 1 is selected.
Unless stated otherwise, resistors are 1%, 0.1 Watt; capacitors are 5%, 6.3 V
D1, D2, D3, D4 = diodes, 1N4003 or 1N4148 or equivalent
D5, D6, D7, D8 = bridge rectifier diodes, 1N914
Xtal = 3.579545 MHz, +/-0.2%
R8 = R9 = 100 K, 20%
R10 = 12K1, 1W5, 5%, Fusible resistor
R2 = R4 = 34 K
For 1000 Vrms, 60 Hz isolation from Tip to Earth and Ring to Earth:
R1 = R3 = 430 K, 0.5 W, 5%, 475 V minimum. e.g., IRC Type GS-3
C1 = C2 = 2 n2, 1332 V minimum
If the 1000Vrms is met by other means, then this circuit has to meet FCC part 68 Type B Ringing:
R1 = R3 = 432 K, 0.1 W, 1%, 56 V minimum
C1 = C2 = 2n2, 212V minimum
Example of component values for Vdd = 5 V +/- 10%
For Bellcore applications, set input gain = 0 dB:
For ETSI applications, set input gain = -2.5 dB:
R5 = 53K6
R5 = 53K6
R6 = 60K4
R6 = 63K4
R7 = 464K
R7 = 348K
Example of component values for Vdd = 3 V +/- 10%
For Bellcore applications, set input gain = -3 dB:
For ETSI applications, set input gain = -5.5 dB:
R5 = 44K2
R5 = 44K2
R6 = 51K1
R6 = 53K6
R7 = 332K
R7 = 249K
Figure 6 - Application Circuit
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Zarlink Semiconductor Inc.
MT88E39
Data Sheet
North America: Bellcore *1
Europe: ETSI *2
Mark (logical 1) frequency
1200 Hz +/- 1%
1300 Hz +/- 1.5%
Space (logical 0) frequency
2200 Hz +/- 1%
Parameter
2100 Hz +/- 1.5%
*3
-33.78 to -5.78 dBm
(-36 to -8 dBV *4) *5
Received signal level
-36.20 to -4.23 dBm
(12 to 476 mVrms)
Reject signal level
-48.23 dBm (3 mVrms)
(VMWI only)
-47.78 dBm (-50 dBV)
Transmission rate
1200 baud +/- 1%
1200 baud +/- 1%
-6 to +10 dB
-6 to +6 dB
Twist
Signal to noise ratio
Single tone (f):
-18 dB (f<=60 Hz)
-12 dB (60<f<=120 Hz)
-6 dB (120<f<=200 Hz)
+25 dB (200<f<3200 Hz)
+6 dB (f>=3200 Hz)
MT88E39 FSK input gain
for Vdd = 5 V +/-10%
>= 25 db
(300 to 3400 Hz)
0 dB
-2.5 dB
Table 1 - FSK signal characteristics specified by some standard bodies
Note:
*1:
*2:
*3:
*4:
*5:
Recommended by TIA/EIA-716. Bellcore has agreed to the values and will incorporate them into its future standards.
ETS 300 778-1 (On-hook) Sep 97, ETS 300 778-2 (Off-hook) Jan 97.
dBm = Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms.
dBV = Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms.
On-hook signal range. The Off-hook signal levels are inside this range: -30.78 to -7.78 dBm.
Vdd
Interrupt Source 1
Vdd
Microcontroller
R1
D1
INT1
(open drain)
R1 can be opened and
D1 shorted if the
microcontroller does not
read the INT1 pin.
Interrupt Source 2
INT2
(CMOS)
INT (input)
Vdd
R2 *
MT88E39
DR
(Mode 0: Open Drain)
(Mode 1: CMOS
Input Port Bit
*R2 can be omitted if mode 1 is selected
Figure 7 - Application Circuit (multiple interrupt source)
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Zarlink Semiconductor Inc.
MT88E39
Data Sheet
Absolute Maximum Ratings* - Voltages are with respect to VSS unless otherwise stated.
Parameter
Symbol
Min.
Max.
Units
1
DC Power Supply Voltage VDD to VSS
VDD
-0.3
6
V
2
Voltage on any pin
VP
-0.3
VDD+0.3
V
3
Current at any pin (except VDD and VSS)
I I/O
±10
mA
4
Storage Temperature
TST
+150
°C
5
Package Power Dissipation
PD
500
mW
-65
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
1 DC Power Supply Voltage
VDD
2.7
2 Clock Frequency
fOSC
3 Tolerance on Clock Frequency
∆fc
4 Operating Temperature
Typ.
Max.
Units
5.5
V
3.579545
-40
Test Conditions
MHz
±0.2
%
+85
°C
DC Electrical Characteristics†
1
S
U
P
P
L
Y
2
3
4
DR,
CD,
DATA,
DCLK
5
DR, CD
6
7
8
9
PWDN,
DCLK
(in mode
1)
MODE
PWDN,
DCLK,
MODE
10
11
VRef
Sym.
Standby Supply Current
IDDQ
Operating Supply Current
VDD = 3.0 V, 25oC
VDD = 5.0 V, 25oC
IDD
Sink Current
IOL
2.5
mA
VOL = 0.1 VDD
Source current
DATA
DCLK (in mode 0)
DR, CD (in mode 1)
IOH
0.8
mA
VOH = 0.9 VDD
Output hi-Z current
(in mode 0)
IOZ
10
µA
VOZ=VSS to VDD
Schmitt Input High Threshold
Schmitt Input Low Threshold
VT+
VT-
0.48*VDD
0.28*VDD
0.68*VDD
0.48*VDD
V
V
VHYS
0.2
CMOS Input High Voltage
CMOS Input Low Voltage
VIH
VIL
0.7*VDD
VSS
Input Current
IIN
Schmitt Hysteresis
Min.
Typ.*
Max.
Units
0.1
15
µA
1.2
1.9
2.0
3.0
mA
mA
Test
Conditions
Characteristics
Notes* 1
Notes* 2
Output Voltage
VRef 0.5*VDD - 0.1
Output Resistance
RRef
V
VDD
0.3*VDD
V
10
µA
VSS ≤ VIN ≤ VDD
0.5*VDD + 0.1
V
No Load
2
kΩ
† DC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
* Typical figures are at 25°C and are for design aid only.
Note 1:
PWDN = Vdd. FSK input = 0 mVrms. Digital inputs at either Vdd or Vss. No current drawn from output pins.
Note 2:
PWDN = Vss. FSK input = 0 mVrms. With no current drawn from Vref, OSC2 and all digital pins.
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Zarlink Semiconductor Inc.
MT88E39
Data Sheet
Electrical Characteristics† - Gain Setting Amplifier
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
1
µA
Test Conditions
VSS ≤ VIN ≤ VDD
1
Input Leakage Current
IIN
2
Input Resistance
Rin
3
Input Offset Voltage
VOS
4
Power Supply Rejection Ratio
PSRR
30
dB
1 kHz ripple on VDD
5
Common Mode Rejection
CMRR
30
dB
VCMmin ≤ VIN ≤ VCMmax
6
DC Open Loop Voltage Gain
AVOL
40
dB
7
Unity Gain Bandwidth
fC
0.2
MHz
8
Output Voltage Swing
VO
0.5
9
Capacitive Load (GS)
CL
10 Resistive Load (GS)
11 Common Mode Voltage Range
5
MΩ
25
RL
100
VCM
1.0
mV
VDD-0.7
V
50
pF
Load ≥ 100 kΩ
kΩ
VDD-1.0
V
† Electrical characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FSK
Characteristics
Sym.
1 Input Detection Level
Min.
Typ.‡
-37.78
-40
10
Max.
-1.78
-4
631
Units
dBm 1, 2, 3, 4
dBV
mVrms
2 Input Baud Rate
1188
1200
1212
baud
3 Input Frequency Detection
Bell 202 1 (Mark)
Bell 202 0 (Space)
1188
2178
1200
2200
1212
2222
Hz
Hz
CCITT V.23 1 (Mark)
CCITT V.23 0 (Space)
4 Input Noise Tolerance 20 log
5 Twist=20 log(VMark )
V
1280.5 1300 1319.5
2068.5 2100 2131.5
SNR
20
-6
6
Hz
Hz
dB
10
Notes*
3, 4, 5
dB
Space
† AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Notes*:
1. dBm = Decibels above or below a reference power of 1 mW into 600 Ω. 0 dBm = 0.7746 Vrms.
2. dBV = Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms.
3. Input op-amp configured to 0 dB gain at Vdd = 5 V+/-10%, -3 dB at Vdd = 3 V+/-10%.
4. Mark and Space frequencies have the same amplitude.
5. Band limited random noise (200-3400 Hz). Present when FSK signal present.
6. OSC1 at 3.579545 MHz ±0.2%.
10
Zarlink Semiconductor Inc.
MT88E39
Data Sheet
AC Electrical Characteristics† - Timing
Characteristics
1
2
PWDN
OSC1
3
4
CD
5
Sym.
Power-up time
tPU
Power-down time
tPD
Input FSK to CD low delay
tIAL
Input FSK to CD high delay
tIAH
Min.
Typ.‡
100
Hysteresis
Max.
Units
50
ms
1000
µs
25
ms
10
ms
10
ms
Notes*
1
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only, not guaranteed and not subject to production testing.
Notes*:
1. The device will stop functioning within this time, but more time may be required to reach IDDQ.
AC Electrical Characteristics† - 3-Wire FSK Interface Timing (Mode 0)
Characteristics
1
DATA
Sym.
Rate
Min.
Typ.‡
Max.
Units.
1188
1200
1212
bps
1
5
ms
1, 6
2
Input FSK to DATA delay
3
Rise time
tR
200
ns
3
Fall time
tF
200
ns
3
4
DATA
DCLK
tIDD
Notes*
DATA to DCLK delay
tDCD
6
416
µs
1, 2, 5, 6
6
DCLK to DATA delay
tCDD
6
416
µs
1, 2, 5, 6
7
Frequency
1200.4
1202.8
1205.2
Hz
2
5
8
DCLK
9
10
DCLK
DR
11
12
13
DR
High time
tCH
415
416
417
µs
2
Low time
tCL
415
416
417
µs
2
DCLK to DR delay
tCRD
415
416
417
µs
2
Rise time
tRR
10
µs
4
Fall time
tFF
200
ns
4
Low time
tRL
417
µs
2
415
416
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only, not guaranteed and not subject to production testing.
Notes*:
1. FSK input data at 1200 ±12 baud.
2. OSC1 at 3.579545 MHz ±0.2%.
3. 10 k to V SS, 50pF to V SS.
4. 10 k to V DD, 50pF to V SS.
5. Function of signal condition.
6. For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations.
11
Zarlink Semiconductor Inc.
MT88E39
Data Sheet
AC Electrical Characteristics† - 3-Wire FSK Interface Timing (Mode 1)
Characteristics
Frequency
1
2
DCLK
3
4
5
Sym.
Min.
Typ.‡
fDCLK1
Duty Cycle
30
Rise Time
DCLK
DR
Max.
Units
1
MHz
70
%
100
ns
Notes*
See Fig. 12
DCLK low setup time to DR
tDDS
500
ns
See Fig. 12
DCLK low hold time to DR
tDDH
500
ns
See Fig. 12
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only, not guaranteed and not subject to production testing.
tDCD
tR
tCDD
tF
DATA
DCLK
tCH
tCL
tF
tR
Figure 8 - DATA and DCLK Output Timing (Mode 0)
tFF
tRR
DR
tRL
Figure 9 - DR Output Timing (Mode 0)
12
Zarlink Semiconductor Inc.
MT88E39
channel seizure
2 sec
Data Sheet
checksum
Mark state
TIP/RING
Input FSK
Second
Ring
First Ring
500 ms
(min)
Data
200 ms
(min)
PWDN
tPU
tPD
OSC2
CD *
tIAL
tIAH
DATA
High (Input Idle)
High (Input Idle)
DCLK
(mode 0)
DR *
* with pull-up resistor in mode 0
Figure 10 - Input and Output Timing (Bellcore CND Service)
start
stop
TIP/RING
b7
1
0
start
stop
b0 b1 b2 b3 b4 b5 b6 b7
1
start
stop
b0 b1 b2 b3 b4 b5 b6 b7
0
1
0
b0 b1 b2
tIDD
start
DATA
start
b0 b1 b2 b3 b4 b5 b6 b7
b7
stop
start
b0 b1 b2 b3 b4 b5 b6 b7
stop
DCLK
tCRD
DR *
* with external pull-up resistor
Figure 11 - Serial Data Interface Timing (Mode 0)
13
Zarlink Semiconductor Inc.
b0 b1 b2
stop
MT88E39
Demodulated
Data
(Internal Signal)
word N+1
word N
stop
7
Data Sheet
0
start
2
1
3
4
5
6
7
stop
tRL
DR (Data Ready)
CMOS
tDDS
Output
tDDH
¿
¡
1/fDCLK1
DCLK (Data Clock)*
Schmitt Input
DATA Output
6
7
word N-1
0
1
2
3
4
5
6
0
7
word N
* The DCLK input must be low before and after DR falling edge
¿ DCLK clears DR
¡ DCLK does not clear DR, so DR is low for maximum time (1/2 bit time)
Figure 12 - Serial Data Interface Timing (Mode 1)
14
Zarlink Semiconductor Inc.
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