Zarlink MT89L80AP1 Cmos st-bustm family Datasheet

CMOS ST-BUSTM Family MT89L80
Digital Switch
Data Sheet
Features
Sept. 2006
•
3.3 volt supply
•
5 V tolerant inputs and TTL compatible outputs.
•
256 x 256 channel non-blocking switch
•
Accepts serial streams at 2.048 Mb/s
•
Per-channel three-state control
•
Patented per channel message mode
•
Non-multiplexed microprocessor interface
•
Zarlink ST-BUS compatible
•
Low power consumption: typical 15 mW
Description
•
Pin compatible with the MT8980DP
This VLSI CMOS device is designed for switching
PCM-encoded voice or data, under microprocessor
control, in a modern digital exchange, PBX or Central
Office. It provides simultaneous connections for up to
256 64 kbit/s channels. Each of the eight serial inputs
and outputs consist of 32 64 kbit/s channels
multiplexed to form a 2048 kbit/s ST-BUS stream. In
addition, the MT89L80 provides microprocessor read
and write access to individual ST-BUS channels.
Ordering Information
MT89L80ANR
48 Pin SSOP
MT89L80APR
44 Pin PLCC
MT89L80AP
44 Pin PLCC
MT89L80AN
48 Pin SSOP
MT89L80APR1
44 Pin PLCC*
MT89L80ANR1
48 Pin SSOP*
MT89L80AN1
48 Pin SSOP*
MT89L80AP1
44 Pin PLCC*
*Pb Free Matte Tin
-40°C to +85°C
Applications
•
Key telephone systems
•
PBX systems
•
Small and medium voice switching systems
C4i
**
F0i RESET VDD VSS
Frame
Counter
STi0
STi3
STi4
STi5
Serial
to
Parallel
Converter
Data
Memory
Control Register
STi6
STi7
ODE
Output
MUX
STi1
STi2
Tape & Reel
Tape & Reel
Tubes
Tubes
Tape & Reel
Tubes
Tubes
Tubes
Connection
Memory
STo0
Parallel
to
Serial
Converter
DTA D7/
D0
STo2
STo3
STo4
STo5
STo6
STo7
Control Interface
DS CS R/W A5/
A0
STo1
CSTo
** for 48-pin SSOP only
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
NC
STi2
STi1
STi0
DTA
CSTo
ODE
STo0
STo1
STo2
NC
MT89L80
6
5
4
3
2
1
44
43
42
41
40
VSS
DTA
STi0
STi1
STi2
NC
STi3
STi4
STi5
STi6
STi7
VDD
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
RESET
F0i
C4i
A0
A1
A2
NC
A3
A4
A5
DS
R/W
NC
A3
A4
A5
DS
R/W
CS
D7
D6
D5
NC
18
19
20
21
22
23
24
25
26
27
28
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
Data Sheet
44 PIN PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CSTo
ODE
STo0
STo1
STo2
NC
STo3
STo4
STo5
STo6
STo7
VSS
VDD
D0
D1
D2
D3
D4
NC
D5
D6
D7
CS
VSS
48 PIN SSOP
(JEDEC MO-118, 300mil Wide)
Figure 2 - Pin Connections
Pin Description
Pin #
44
48
PLCC SSOP
Name
2
2
3-5
3-5
STi0-2 ST-BUS Inputs 0 to 2 (5 V-tolerant Inputs). Serial data input streams. These streams
have data rates of 2.048 Mbit/s with 32 channels.
7-11
7-11
STi3-7 ST-BUS Inputs 3 to 7 (5 V-tolerant Inputs). Serial data input streams. These streams
may have data rates of 2.048 Mbit/s with 32channels.
12
12,36
13
13
14
DTA
Description
VDD
Data Acknowledgment (5 V Tolerant Three-state Output). This active low output
indicates that a data bus transfer is complete. A pull-up resistor is required at this
output.
+3.3 Volt Power Supply.
RESET Device Reset (5 V-tolerant input). This pin is only available for the 48-pin SSOP
package.This active low input puts the device in its reset state. It clears the internal
counters and registers. All ST-BUS outputs are set to the high impedance state. In
normal operation. The RESET pin must be held low for a minimum of 100nsec to reset
the device. Internal pull-up.
F0i
Frame Pulse (5 V-tolerant Input). This is the input for the frame synchronization pulse
for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to
reset on the next negative transition of C4i.
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
Pin Description (continued)
Pin #
44
48
PLCC SSOP
Name
Description
14
15
C4i
4.096 MHz Clock (5 V-tolerant Input). ST-BUS bit cell boundaries lie on the alternate
falling edges of this clock.
15-17
16-18
A0-2
Address 0-2 / Input Streams 8-10 (5 V-tolerant Input). These are the inputs for the
address lines on the microprocessor interface.
19-21
20-22
A3-5
Address 3-5 / Input Streams 11-13 (5 V-tolerant Input). These are the inputs for the
address lines on the microprocessor interface.
22
23
DS
Data Strobe (5 V-tolerant Input). This is the input for the active high data strobe on the
microprocessor interface.
23
24
R/W
Read/Write (5 V-tolerant Input). This is the input for the read/write signal on the
microprocessor interface - high for read, low for write.
24
26
CS
Chip Select (5 V-tolerant Input). This is the input for the active low chip select on the
microprocessor interface
25-27
27-29
D7-D5
Data Bus (5 V-tolerant I/O): These are the bidirectional data pins on the
microprocessor interface.
29-33
31-35
D4-D0
Data Bus (5 V-tolerant I/O): These are the bidirectional data pins on the
microprocessor interface.
34
1,
25,37
VSS
35-39
38-42
STo7-3 ST-BUS Outputs 7 to 3 (5 V-Tolerant Three-state Outputs). These are the pins for the
eight 2048 kbit/s ST-BUS output streams.
41-43
44-46
STo2-0 ST-BUS Outputs 2to 0 (5 V-Tolerant Three-state Outputs). These are the pins for the
eight 2048kbit/s ST-BUS output streams.
44
47
ODE
Output Drive Enable (5 V-tolerant Input). If this input is held high, the STo0-STo7
output drivers function normally. If this input is low, the STo0-STo7 output drivers go into
their high impedance state. NB: Even when ODE is high, channels on the STo0-STo7
outputs can go high impedance under software control.
1
48
CSTo
Control ST-BUS Output (5 V-Tolerant Output). Each frame of 256 bits on this ST-BUS
output contains the values of bit 1 in the 256 locations of the Connection Memory High.
6, 18, 6, 19,
28, 40 30, 43
NC
Ground.
No Connection.
Functional Description
In recent years, there has been a trend in telephony towards digital switching, particularly in association with
software control. Simultaneously, there has been a trend in system architectures towards distributed processing or
multi-processor systems.
In accordance with these trends, Zarlink has devised the ST-BUS (Serial Telecom Bus). This bus architecture can
be used both in software-controlled digital voice and data switching, and for interprocessor communications. The
uses in switching and in interprocessor communications are completely integrated to allow for a simple general
purpose architecture appropriate for the systems of the future.
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
The serial streams of the ST-BUS operate continuously at 2048 kbit/s and are arranged in 125 µs wide frames
which contain 32 8-bit channels. Zarlink manufactures a number of devices which interface to the ST-BUS; a key
device being the MT89L80 chip.
The MT89L80 can switch data from channels on ST-BUS inputs to channels on ST-BUS outputs, and
simultaneously allows its controlling microprocessor to read channels on ST-BUS inputs or write to channels on STBUS outputs (Message Mode). To the microprocessor, the MT89L80 looks like a memory peripheral. The
microprocessor can write to the MT89L80 to establish switched connections between input ST-BUS channels and
output ST-BUS channels, or to transmit messages on output ST-BUS channels. By reading from the MT89L80, the
microprocessor can receive messages from ST-BUS input channels or check which switched connections have
already been established.
By integrating both switching and interprocessor communications, the MT89L80 allows systems to use distributed
processing and to switch voice or data in an ST-BUS architecture.
Hardware Description
Serial data at 2048 kbit/s is received at the eight ST-BUS inputs (STi0 to STi7), and serial data is transmitted at the
eight ST-BUS outputs (STo0 to STo7). Each serial input accepts 32 channels of digital data, each channel
containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec (e.g.,
Zarlink’s MT8964).
This serial input word is converted into parallel data and stored in the 256 X 8 Data Memory. Locations in the Data
Memory are associated with particular channels on particular ST-BUS input streams. These locations can be read
by the microprocessor which controls the chip.
Locations in the Connection Memory, which is split into high and low parts, are associated with particular ST-BUS
output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either
be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input,
then the contents of the Connection Memory Low location associated with the output channel is used to address
the Data Memory. This Data Memory address corresponds to the channel on the input ST-BUS stream on which the
data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode),
then the contents of the Connection Memory Low location associated with the output channel are output directly,
and this data is output repetitively on the channel once every frame until the microprocessor intervenes.
The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives
address information at A5 to A0 and handles the microprocessor control signals CS, DTA, R/W and DS. There are
two parts to any address in the Data Memory or Connection Memory. The higher order bits come from the Control
Register, which may be written to or read from via the Control Interface. The lower order bits come from the address
lines directly.
The Control Register also allows the chip to broadcast messages on all ST-BUS outputs (i.e., to put every channel
into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the
Connection Memory Low. The Connection Memory High determines whether individual output channels are in
Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of
MT89L80s to be constructed. It also controls the CSTo pin.
All ST-BUS timing is derived from the two signals C4i and F0i.
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
A5
A4
A3
A2
A1
A0
Hex Address
Location
0
1
1
•
•
•
1
0
0
0
•
•
•
1
0
0
0
•
•
•
1
0
0
0
•
•
•
1
0
0
0
•
•
•
1
0
0
1
•
•
•
1
00 - 1F
20
21
•
•
•
3F
Control Register *
Channel 0†
Channel 1†
•
•
•
Channel 31†
* Writing to the Control Register is the only fast transaction.
† Memory and stream are specified by the contents of the Control Register.
Figure 3 - Address Memory Map
Software Control
The address lines on the Control Interface give access to the Control Register directly or, depending on the
contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory.
If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If
A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory
and stream selected in the Control Register.
The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see
Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and
the stream address bits define one of the ST-BUS input or output streams.
Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the
Connection Memory Low.
The other mode control bit, bit 6, puts every output channel on every output stream into active Message Mode; i.e.,
the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the
ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1,
regardless of the actual values.
(unused)
7
Bit
7
6
Stream
Address
Bits
Memory
Select
Bits
Mode
Control
Bits
5
4
3
Name
2
1
0
Description
Split Memory When 1, all subsequent reads are from the Data Memory and writes are to the Connection
Memory Low, except when the Control Register is accessed again. When 0, the Memory
Select bits specify the memory for subsequent operations. In either case, the Stream
Address Bits select the subsection of the memory which is made available.
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
(unused)
7
Bit
Name
6
Message
Mode
5
(unused)
4-3
Memory
Select Bits
2-0
6
Stream
Address
Bits
Memory
Select
Bits
Mode
Control
Bits
5
4
3
2
1
0
Description
When 1, the contents of the Connection Memory Low are output on the Serial Output
streams except when the ODE pin is low. When 0, the Connection Memory bits for each
channel determine what is output.
0-0 - Not to be used
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory Low
1-1 - Connection Memory High
Stream
The number expressed in binary notation on these bits refers to the input or output ST-BUS
Address Bits stream which corresponds to the subsection of memory made accessible for subsequent
operations.
Figure 4 - Control Register Bits
No Corresponding Memory
- These bits give 0s if read.
7
6
5
4
Per Channel
Control Bits
3
2
1
0
Bit
Name
Description
2
Message
Channel
When 1, the contents of the corresponding location in Connection Memory Low are
output on the location’s channel and stream. When 0, the contents of the corresponding
location in Connection Memory Low act as an address for the Data Memory and so
determine the source of the connection to the location’s channel and stream.
1
CSTo Bit
This bit is output on the CSTo pin one channel early. The CSTo bit for stream 0 is output
first.
0
Output
Enable
If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the
output driver for the location’s channel and stream. This allows individual channels on
individual streams to be made high-impedance, allowing switching matrices to be
constructed. A 1 enables the driver and a 0 disables it.
Figure 5 - Connection Memory High Bits
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Zarlink Semiconductor Inc.
MT89L80
Stream
Address
Bits
7
6
Data Sheet
Channel
Address
Bits
5
4
3
2
1
0
Bit
Name
Description
7-5*
Stream
Address
Bits*
The number expressed in binary notation on these 3 bits is the number of the ST-BUS
stream for the source of the connection. Bit 7 is the most significant bit. e.g., if bit 7 is 1,
bit 6 is 0 and bit 5 is 0, then the source of the connection is a channel on STi4.
4-0*
Channel
Address
Bits*
The number expressed in binary notation on these 5 bits is the number of the channel
which is the source of the connection (The ST-BUS stream where the channel lies is
defined by bits 7, 6 and 5.). Bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is 0, bit 2
is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
*If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire
8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated
to define the source of the connection which is output on the channel and stream associated with this location.
Figure 6 - Connection Memory Low Bits
If bit 6 of the Control Register is 0, then bits 2 and 0 of each Connection Memory High location function normally
(see Fig. 5). If bit 2 is 1, the associated ST-BUS output channel is in Message Mode; i.e., the byte in the
corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the
bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low define the STBUS input stream and channel where the byte is to be found (see Fig. 6).
If the ODE pin is low, then all serial outputs are high-impedance. If it is high and bit 6 in the Control Register is 1,
then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the
Connection Memory High location enables the output drivers for the corresponding individual ST-BUS output
stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Fig. 5).
Bit 1 of each Connection Memory High location (see Fig. 5) is output on the CSTo pin once every frame. To allow for
delay in any external control circuitry the bit is output one channel before the corresponding channel on the ST-BUS
streams, and the bit for stream 0 is output first in the channel; e.g., bit 1’s for channel 9 of streams 0-7 are output
synchronously with ST-BUS channel 8 bits 7-0.
Applications
Use in a Simple Digital Switching System
Figs. 7 and 8 show how MT89L80s can be used with MT8964s to form a simple digital switching system. Fig. 7
shows the interface between the MT89L80s and the filter/codecs. Fig. 8 shows the position of these components in
an example architecture.
The MT8964 filter/codec in Fig. 7 receives and transmits digitized voice signals on the ST-BUS input DR, and STBUS output DX, respectively. These signals are routed to the ST-BUS inputs and outputs on the top MT89L80,
which is used as a digital speech switch.
The MT8964 is controlled by the ST-BUS input DC originating from the bottom MT89L80, which generates the
appropriate signals from an output channel in Message Mode. This architecture optimizes the messaging capability
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
of the line circuit by building signalling logic, e.g., for on-off hook detection, which communicates on an ST-BUS
output. This signalling ST-BUS output is monitored by a microprocessor (not shown) through an ST-BUS input on
the bottom MT89L80.
Fig. 8 shows how a simple digital switching system may be designed using the ST-BUS architecture. This is a
private telephone network with 256 extensions which uses a single MT89L80 as a speech switch and a second
MT89L80 for communication with the line interface circuits.
STo0
STi0
89L80 used
as
speech
switch
MT89L80
DX
DR
DC
Signalling
Logic
STo0
STi0
89L80 used
in message
mode for
control and
signalling
MT8964
Filter/Codec
Line Driver
and
2- to 4Wire
Converter
Line Interface Circuit with 8964 Filter/Codec
MT89L80
Figure 7 - Example of Typical Interface between 89L80s and 8964s for Simple Digital Switching
System
Line Interface Circuit
with Codec (e.g. 8964)
Line 1
8
Speech
Switch
89L80
STi0-7
8
STo0-7
•
•
•
Repeated for Lines
2 to 255
STo0-7
Controlling
MicroProcessor
8
STi0-7
•
•
•
Repeated for Lines
2 to 255
8
Control &
Signalling
89L80
Line Interface Circuit
with Codec (e.g.8964)
Line 256
Figure 8 - Example Architecture of a Simple Digital Switching System
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
Absolute Maximum Ratings*
Parameter
Symbol
1
Supply Voltage
2
Voltage on any I/O pin (except supply pins)
VO
3
Current at Digital Outputs
IO
4
Storage Temperature
TS
5
Package Power Dissipation
PD
Min.
Max.
Units
-0.3
5.0
V
VSS-0.3
VDD+0.3
V
20
mA
+125
°C
1
W
-55
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
.
Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.
Max.
Units
1
Operating Temperature
TOP
-40
+85
°C
2
Positive Supply
VDD
3.0
3.6
V
3
Input High Voltage
VIH
0.7VDD
VDD
V
4
Input High Voltage on 5 V Tolerant Inputs
VIH
5.5
V
5
Input Low Voltage
VIL
0.3VDD
V
VSS
Test Conditions
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
1
2
3
4
5
6
7
8
9
10
11
I
N
P
U
T
S
O
U
T
P
U
T
S
Sym.
Min.
Typ.‡
Max.
Units
4
7
mA
Supply Current
IDD
Input High Voltage
VIH
Input Low Voltage
VIL
0.3VDD
V
Input Leakage
IIL
5
µA
Input Pin Capacitance
CI
10
pF
0.7VDD
Test Conditions
Outputs unloaded
V
Output High Voltage
VOH
0.8VDD
V
Output High Current
IOH
10
mA
Output Low Voltage
VOL
Output Low Current
IOL
High Impedance Leakage
IOZ
Output Pin Capacitance
CO
0.4
V
5
VI between VSS and VDD
IOH = 10 mA
Sourcing. VOH=2.4V
IOL = 5 mA
mA
Sinking. VOL = 0.4V
5
µA
VO between VSS and VDD
10
pF
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics _Timing Parameter Measurement Voltage Levels
Characteristics
Sym
Level
Units
1
CMOS Threshold Voltage
VTT
0.5VDD
V
2
CMOS Rise/Fall Threshold Voltage high
VHM
0.7VDD
V
3
CMOS Rise/Fall Threshold Voltage low
VLM
0.3VDD
V
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Zarlink Semiconductor Inc.
Test Conditions
MT89L80
Data Sheet
AC Electrical Characteristics† - Clock Timing (Figures 9 and 10)
Sym.
Min.
Typ.‡
Max.
Units
Clock Period*
tCLK
220
244
300
ns
Clock Width High
tCH
85
122
150
ns
Clock Width Low
tCL
85
122
150
ns
Clock Transition Time
tCTT
10
ns
Frame Pulse Setup Time
tFPS
10
190
ns
Frame Pulse Hold Time
tFPH
10
190
ns
Frame Pulse Width
tFPW
Characteristics
1
2
I
N
P
U
T
S
3
4
5
6
7
244
Test Conditions
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.
NB: Frame Pulse is repeated every 512 cycles of C4i.
C4i
F0i
BIT
CELLS
Channel 31
Bit o
Channel 0
Bit 7
Figure 9 - Frame Alignment
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
tCLK
tCL
tCH
tCTT
VHM
C4i
VLM
tCHL
tFPH
tCTT
tFPS
tFPH
tFPS
VHM
F0i
VLM
tFPW
Figure 10 - Clock Timing
AC Electrical Characteristics† - Serial Streams (Figures 11, 12 and 13)
1
2
3
4
5
6
7
Characteristics
Sym.
Min.
O
U
T
P
U
T
S
STo0/7 Delay - Active to High Z
tSAZ
STo0/7 Delay - High Z to Active
I
N
Typ.‡
Max.
Units
Test Conditions
5
55
ns
RL=1 KΩ*, CL=150 pF
tSZA
5
55
ns
CL=150 pF
STo0/7 Delay - Active to Active
tSAA
5
55
ns
CL=150 pF
Output Driver Enable Delay
tOED
50
ns
RL=1 KΩ*, CL=150 pF
External Control Delay
tXCD
55
ns
CL=150 pF
Serial Input Setup Time
tSIS
20
ns
Serial Input Hold Time
tSIH
20
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
Bit Cell Boundary
VHM
C4i
VLM
V
STo0 HM
to
V
STo7 LM
*
tSAZ
STo0 VHM
to
STo7 VLM
*
tSZA
V
STo0 HM
to
V
STo7 LM
tSAA
VHM
CSTo VLM
tXCD
Figure 11 - Serial Outputs and External Control
ODE
VHM
VLM
STo0 VHM
to
STo7 VLM
*
*
tOED
tOED
Figure 12 - Output Driver Enable
12
Zarlink Semiconductor Inc.
MT89L80
Data Sheet
Bit Cell Boundaries
VHM
C4i
VLM
tSIH
STi0 VHM
to
STi7 VLM
tSIS
Figure 13 - Serial Inputs
AC Electrical Characteristics† - Processor Bus (Figures 14)
Characteristics
Sym
Min
Typ‡
Max
Units
1
Chip Select Setup Time
tCSS
0
ns
2
Read/Write Setup Time
tRWS
5
ns
3
Address Setup Time
tADS
5
ns
4
Acknowledgment Delay
Test Conditions
Control Register Read
tAKD
52
120
ns
CL=150 pF
Control Register Write
tAKD
25
65
ns
CL=150 pF
Connection Memory Read
tAKD
62
120
ns
CL=150 pF
Connection Memory Write
tAKD
30
53
ns
CL=150 pF
Data Memory Read
tAKD
560
1220
ns
CL=150 pF
5
Fast Write Data Setup Time
tFWS
6
Slow Write Data Delay
tSWD
7
Read Data Setup Time
tRDS
0
8
Data Hold Time
Read
tDHT
10
Write
tDHT
5
10
50
0
ns
122
90
ns
ns
CL= 150 pF
ns
RL=1 KΩ∗, CL=150 pF
ns
9
Read Data To High Impedance
tRDZ
15
10
Chip Select Hold Time
tCSH
0
ns
11
Read/Write Hold Time
tRWH
0
ns
12
Address Hold Time
tADH
8
ns
13
Acknowledgment Hold Time
tAKH
50
90
80
ns
ns
RL=1 KΩ∗, CL=150 pF
RL=1 KΩ∗, CL=150 pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
13
Zarlink Semiconductor Inc.
MT89L80
DS
VHM
VLM
CS
VHM
VLM
R/W
VHM
VLM
A5
to
A0
VHM
VLM
tCSS
tCSH
tRWS
tRWH
tADS
DTA
VHM
VLM
Data Sheet
tADH
tAKD
tAKH
*
*
tRDS
D7
to
D0
VHM
VLM
tDHT
*
*
tFWS
tSWD
Figure 14 - Processor Bus
14
Zarlink Semiconductor Inc.
tRDZ
Package Code
c Zarlink Semiconductor 2003 All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes
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