MX23L8100 8M-BIT MASK ROM(8/16 BIT OUTPUT) FEATURES ORDER INFORMATION • Bit organization - 1M x 8 (byte mode) - 512K x 16 (word mode) • Fast access time - Random access: 100ns (max.) • Current - Operating: 20mA - Standby: 5uA • Supply voltage - 3.3V±10% • Package - 44 pin SOP (500mil) - 42 pin PDIP (600mil) - 48 pin TSOP (type 1) - 44 pin TSOP (type 2) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 42 PDIP NC NC A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC MX23L8100MC-10 100ns 44 pin SOP MX23L8100MC-12 120ns 44 pin SOP MX23L8100MC-15 150ns 44 pin SOP MX23L8100PC-10 100ns 42 pin PDIP MX23L8100PC-12 120ns 42 pin PDIP MX23L8100PC-15 150ns 42 pin PDIP MX23L8100TC-10 100ns 48 pin TSOP* MX23L8100TC-12 120ns 48 pin TSOP MX23L8100TC-15 150ns 48 pin TSOP MX23L8100RC-10 100ns 48 pin RTSOP* MX23L8100RC-12 120ns 48 pin RTSOP MX23L8100RC-15 150ns 48 pin RTSOP MX23L8100YC-10 100ns 44 pin TSOP MX23L8100YC-12 120ns 44 pin TSOP MX23L8100TI-10 100ns 48 pin TSOP* A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE D0 D8 D1 D9 D2 D10 D3 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 48 TSOP (for word mode only) MX23L8100 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 MX23L8100 NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE D0 D8 D1 D9 D2 D10 D3 D11 Access Time Package Note: 1.48-TSOP and 48-RTSOP support word mode only, not for byte mode. 2.MX23L8100TI-10 is for industrial grade, temperature -40~85°C PIN CONFIGURATION 44 SOP/44TSOP Part No. 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 NC A16 A15 A14 A13 A12 A11 A10 A9 A8 NC VSS NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE NC A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MX23L8100 (Normal Type) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS VSS D15 D7 D14 D6 D13 D5 D12 D4 VCC VCC NC D11 D3 D10 D2 D9 D1 D8 D0 OE VSS VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NC A16 A15 A14 A13 A12 A11 A10 A9 A8 NC VSS NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE 48 Reverse TSOP (for word mode only) VSS VSS D15 D7 D14 D6 D13 D5 D12 D4 VCC VCC NC D11 D3 D10 D2 D9 D1 D8 D0 OE VSS VSS P/N:PM0464 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 MX23L8100 (Reverse Type) REV. 1.7,AUG. 20, 2001 1 MX23L8100 PIN DESCRIPTION Symbol A0~A18 D0~D14 D15/A-1 CE OE Byte VCC VSS NC MODE SELECTION Pin Function Address Inputs Data Outputs D15(Word Mode)/LSB Address (Byte Mode) Chip Enable Input Output Enable Input Word/Byte Mode Selection Power Supply Pin Ground Pin No Connection CE OE Byte D15/A-1 D0~D7 D8~D15 Mode Power H X X X High Z High Z - Stand-by L H X X High Z High Z - Active L L H L L L Output D0~D7 D8~D15 Word Input D0~D7 High Z Byte Active Active BLOCK DIAGRAM A0 Address Buffer Memory Array Page Buffer A18 Word/ Byte Output Buffer D0 D15/(D7) CE BYTE OE ABSOLUTE MAXIMUM RATINGS Item Voltage on any Pin Relative to VSS Ambient Operating Temperature Storage Temperature Symbol VIN Topr Tstg Ratings -1.3V to VCC+2.0V (Note) 0°C to 70°C -65°C to 125°C Note: Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -1.3V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC+0.5V. During voltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns. P/N:PM0464 REV. 1.7, AUG. 20, 2001 2 MX23L8100 DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%) Item Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current (TTL) Standby Current (CMOS) Input Capacitance Output Capacitance Symbol VOH VOL VIH VIL ILI ILO ICC1 ISTB1 ISTB2 CIN COUT MIN. 24V 2.2V -0.3V - MAX. 0.4V VCC+0.3V 0.8V 5uA 5uA 20mA 1mA 5uA 10pF 10pF Conditions IOH = -0.4mA IOL = 1.6mA 0V, VCC 0V, VCC f=10MHz, all output open CE=VIH CE> VCC - 0.2V Ta = 25°C, f = 1MHZ Ta = 25°C, f = 1MHZ AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%) Item Symbol Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Time Output Hold After Address Output High Z Delay tRC tAA tACE tOE tOH tHZ 23L8100-10 MIN. MAX. 100ns 100ns 100ns 50ns 0ns 20ns 23L8100-12 MIN. MAX. 120ns 120ns 120ns 60ns 0ns 20ns 23L8100-15 MIN. MAX. 150ns 150ns 150ns 70ns 0ns 20ns Note:Output high-impedance delay (tHZ) is measured from OE or CE going high, and this parameter guaranteed by design over the full voltage and temperature operating range - not tested. AC Test Conditions Input Pulse Levels Input Rise and Fall Times Input Timing Level Output Timing Level Output Load IOH (load)=-0.4mA 0.4V~2.4V 10ns 1.4V 1.4V See Figure DOUT IOL (load)=1.6mA C<100pF Note:No output loading is present in tester load board. Active loading is used and under software programming control. Output loading capacitance includes load board's and all stray capacitance. P/N:PM0464 REV. 1.7, AUG. 20, 2001 3 MX23L8100 TIMING DIAGRAM RANDOM READ ADD ADD ADD ADD tRC tACE CE tOE OE tOH tAA VALID DATA VALID tHZ VALID Note:CE, OE are enable P/N:PM0464 REV. 1.7, AUG. 20, 2001 4 MX23L8100 PACKAGE INFORMATION 42-PIN PLASTIC DIP(600 mil) P/N:PM0464 REV. 1.7, AUG. 20, 2001 5 MX23L8100 44-PIN PLASTIC SOP P/N:PM0464 REV. 1.7, AUG. 20, 2001 6 MX23L8100 48-PIN PLASTIC TSOP P/N:PM0464 REV. 1.7, AUG. 20, 2001 7 MX23L8100 REVISION HISTORY Revision 1.4 1.5 1.6 1.7 Description Add new 44pin TSOP (type 2) AC CHARACTERISTICS tOH 10ns-->0ns Correct Typing error Modify Package Information Added MX23L8100TI-10 in Order Information P/N:PM0464 Page P3 P1 P5~7 P1 Date Jul/17/1998 FEB/01/1999 JUL/16/2001 AUG/20/2001 REV. 1.7, AUG. 20, 2001 8 MX23L8100 MACRONIX INTERNATIONAL CO., LTD. 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