ETC1 MX26F128J3 Macronix nbit tm memory family 128m [x8/x16] single 3v page mode eliteflash tm memory Datasheet

MX26F128J3
Macronix NBit TM Memory Family
128M [x8/x16] SINGLE 3V PAGE MODE eLiteFlashTM MEMORY
FEATURES
• 3.0V to 3.6V operation voltage
• Block Structure
- 128 x 128Kbyte Erase Blocks
• Fast random / page mode access time
- 120/25 ns Read Access Time
- 150/25 ns Read Access Time
• Page Depth: 4-word
• 128-bit Protection Register
- 64-bit Unique Device Identifier
- 64-bit User Programmable OTP Cells
• 32-Byte Write Buffer
- 6 us/byte Effective Programming Time
• Enhanced Data Protection Features Absolute Protection with VPEN = GND
- Flexible Block Locking
- Block Erase/Program Lockout during Power Transitions
Software Feature
• Support Common Flash Interface (CFI)
- eLiteFlashTM memory device parameters stored on
the device and provide the host system to access.
Hardware Feature
• A0 pin
- Select low byte address when device is in byte mode.
Not used in word mode.
• STS pin
- Indicates the status of the internal state machine.
• VPEN pin
- For Erase /Program/ Block Lock enable.
• VCCQ Pin
- The output buffer power supply, control the device 's
output voltage.
Packaging
Performance
- 56-Lead TSOP
- 64-ball CSP
• Low power dissipation
- typical 15mA active current for page mode read
- 80uA/(max.) standby current
• High Performance
- Block erase time: 2s typ.
- Byte programming time: 210us typ.
- Block programming time: 0.8s typ. (using Write to
Buffer Command)
• Program/Erase Endurance cycles: 100 cycles
Technology
- 0.25u Macronix NBitTM Flash Technology
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MX26F128J3
GENERAL DESCRIPTION
circuit electrical erasure and programming. The device
uses a command register to manage this functionality.
The MXIC's MX26F128J3 series eLiteFlashTM memory
use the most advance 2 bits/cell Nbit technology, double
the storage capacity of memory cell. The device provide
the high density eLiteFlashTM memory solution with reliable performance and most cost-effective.
The MXIC's Nbit technology reliably stores memory contents even after the specific erase and program cycles.
The MXIC cell is designed to optimize the erase and
program mechanisms by utilizing the dielectric's character to trap or release charges from ONO layer.
The device organized as by 8 bits or by 16 bits of output
bus. The device is packaged in 56-Lead TSOP and 64ball CSP. It is designed to be reprogrammed and erased
in system or in standard EPROM programmers.
The device uses a 3.0V to 3.6V VCC supply to perform
the High Reliability Erase and auto Program/Erase algorithms.
The device offers fast access time and allowing operation of high-speed microprocessors without wait states.
To eliminate bus contention, the device has separate chip
enable (CE0, CE1, CE2) and output enable (OE) controls. The device augment EPROM functionality with in-
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
PIN CONFIGURATION
56 TSOP (14mm x 20mm)
A22
CE1
A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RESET
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
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NC
WE
OE
STS
Q15
Q7
Q14
Q6
GND
Q13
Q5
Q12
Q4
VCCQ
GND
Q11
Q3
Q10
Q2
VCC
Q9
Q1
Q8
Q0
A0
BYTE
A23
CE2
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MX26F128J3
64 Ball CSP (10x13x1.2mm, 1.0mm-ball pitch)
1
2
3
4
5
6
7
8
A
A1
A6
A8
VPEN
A13
VCC
A18
A22
B
A2
GND
A9
CE0
A14
DU
A19
CE1
C
A3
A7
A10
A12
A15
DU
A20
A21
D
A4
A5
A11
RESET
DU
DU
A16
A17
E
Q8
Q1
Q9
Q3
Q4
DU
Q15
STS
F
BYTE
Q0
Q10
Q11
Q12
DU
DU
OE
G
A23
A0
Q2
VCCQ
Q5
Q6
Q14
WE
CE2
DU
VCC
GND
Q13
GND
Q7
NC
H
13 mm
10mm
Notes:
1. Don't Use (DU) pins refer to pins that should not be connected.
PIN DESCRIPTION
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A0
Byte Select Address
STS
STATUS Pin
A1~A23
Address Input
BYTE
Byte Mode Enable
Q0~Q15
Data Inputs/Outputs
VPEN
ERASE/PROGRAM/BLOCK Lock
Enable
CE0, CE1, CE2 Chip Enable Input
WE
Write Enable Input
VCCQ
Output Buffer Power Supply
OE
Output Enable Input
VCC
Device Power Supply
RESET
Reset/Power Down mode
GND
Device Ground
NC
Pin Not Connected Internally
DU
Don't Use
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MX26F128J3
BLOCK DIAGRAM
CE0
CE1
CE2
OE
WE
RESET
CONTROL
INPUT
WRITE
STATE
HIGH VOLTAGE
MACHINE
LOGIC
(WSM)
LATCH
BUFFER
Y-DECODER
AND
X-DECODER
ADDRESS
A0-A23
PROGRAM/ERASE
STATE
REGISTER
ARRAY
ARRAY
SOURCE
HV
Y-PASS GATE
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15
I/O BUFFER
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MX26F128J3
Figure 1. Block Architecture
eLiteFlashTM memory reads erases and writes in-system via the local CPU. All bus cycles to or from the eLiteFlashTM
memory conform to standard microprocessor bus cycles.
A[23-0]: 128Mbit
A[23-1]: 128Mbit
7FFFFF
FFFFFF
128-Kbyte Block
FE0000
127
7F0000
.
.
.
64-Kword Block
127
.
.
.
7FFFFF
3FFFFF
63
3F0000
.
.
.
64-Kword Block
63
.
.
.
3FFFFF
128 Mbit
128-Kbyte Block
7E0000
1FFFFF
128-Kbyte Block
3E0000
31
1F0000
.
.
.
64-Kword Block
31
.
.
.
03FFFF
01FFFF
020000
01FFFF
128-Kbyte Block
1
128-Kbyte Block
0
000000
010000
00FFFF
64-Kword Block
1
64-Kword Block
0
000000
Byte Mode (x8)
Word Mode (x16)
Table 1. Chip Enable Truth Table
CE2
CE1
CE0
DEVICE
VIL
VIL
VIL
Enabled
VIL
VIL
VIH
Disabled
VIL
VIH
VIL
Disabled
VIL
VIH
VIH
Disabled
VIH
VIL
VIL
Enabled
VIH
VIL
VIH
Enabled
VIH
VIH
VIL
Enabled
VIH
VIH
VIH
Disabled
NOTE: For Single-chip applications, CE2 and CE1 can
be strapped to GND.
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MX26F128J3
Table 2. Bus Operations
Command
Sequence
Read
Array
Notes
4,5,6
RESET
VIH
Output Standby RESET Read ID Read
Disable
Mode/
Query
Power
Down
Mode
Read
Read
Status
Status
(WSM off) (WSM on)
Write
6,10,11
VIH
VIH
VIH
VIH
VIH
CE0,CE1,CE2(1) Enabled Enabled Disabled X
Enabled
Enabled Enabled
Enabled
Enabled
OE (2)
VIL
VIH
X
X
VIL
VIL
VIL
VIL
VIH
WE (2)
VIH
VIH
X
X
VIH
VIH
VIH
VIH
VIL
Address
X
X
X
X
X
X
See
X
Table 6
X
X
X
X
See
Figure 2
X
VPEN
X
X
X
VPENH
Q (3)
Data out High Z
High Z
High Z Note 8
Note 9
STS
(default mode)
High Z
(7)
X
High Z High Z
(7)
(7)
High Z
(7)
X
VIH
VIL
VIH
Data out
Q7=Data out Data in
Q15-8=High Z
Q6-0=High Z
X
NOTES:
1. See Table 1 on page 7 for valid CE configurations.
2. OE and WE should never be enabled simultaneously.
3. DQ refers to Q0-Q7 if BYTE is low and Q0-Q15 if BYTE is high.
4. Refer to DC Characteristics. When VPEN < VPENLK , memory contents can be read, but not altered.
5. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN . See DC Characteristics for
VPENLK and VPENH voltages.
6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration
algorithms. It is VOH when the WSM is not busy, or in reset/power-down mode.
7. High Z will be VOH with an external pull-up resistor.
8. See Section , "Read Identifier Codes" for read identifier code data.
9. See Section , "Read Query Mode Command" for read query data.
10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN=
VPENH and VCC is within specification.
11.Refer to Table 3 on page 10 for valid DIN during a write operation.
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MX26F128J3
FUNCTION
STANDBY
The device includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block
erase and byte/word/page program operations. Operational modes are selected by the commands written to
the Command User Interface (CUI). The Status Register
indicates the status of the WSM and when the WSM
successfully completes the desired program or block
erase operation.
When CE0, CE1 and CE2 disable the device (see table1)
and place it in standby mode. The power consumption of
this device is reduced. Data input/output are in a highimpedance(High-Z) state. If the memory is deselected
during block erase, program or lock-bit configuration, the
internal control circuits remain active and the device consume normal active power until the operation completes.
POWER-DOWN
READ
When RESET pin is at VIL the device is in the powerdown mode and its power consumption is substantially
low around 25uA. During read modes, the memory is
deselected and the data input/output are in a highimpedance(High-Z) state. To return from power down
mode requires RESET pin at VIH. After return from
powerdown, the CUI is reset to Read Array , and the
Status Register is set to value 80H.
The device has three read modes, which accesses to
the memory array, the Device Identifier or the Status
Register independent of the VPEN voltage. The appropriate read command are required to be written to the
CUI. Upon initial device powerup or after exit from
powerdown, the device automatically resets to read array mode. In the read array mode, low level input to CE0,
CE1, CE2 and OE, high level input to WE and RESET
and address signals to the address inputs (A23-A0) output the data of the addressed location to the data input/
output (Q15~Q0).
During block erase program or lock-bit configuration
modes, RESET pin at VIL will abort either operation.
Memory array data of the block being altered become
invalid.
When reading information in read array mode, the device defaults to asynchronous page mode. In this state,
data is internally read and stored in a high-speed page
buffer. A2:0 addresses data in the page buffer. The page
size is 4 words or 8 bytes. Asynchronous word/byte mode
is supported with no additional commands required.
In default mode, STS transitions low and remains low
for a maximum time of tPLPH+tPHRH until the reset
operation is complete. Memory contents being altered
are no longer valid; the data may be partially corrupted
after a program or partially altered after an erase or lockbit configuration. Time tPHWL is required after RESET
goes to logic-high (VIH) before another command can
be written.
WRITE
Writes to the CUI enables reading of memory array data,
device identifiers and reading and clearing of the Status
Register and when VPEN=VPENH block erasure program and lock-bit configuration. The CUI is written when
the device is enable, WE is active and OE is at high
level. Address and data are latched on the earlier rising
edge of WE and CE. Standard micro-processor write timings are used.
READ QUERY
The read query operation outputs block status information, CFI (Common Flash Interface) ID string, system
interface information, device geometry information and
MXIC extended query information.
OUTPUT DISABLE
When OE is at VIH, output from the devices is disabled.
Data input/output are in a high-impedance(High-Z) state.
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MX26F128J3
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the CUI. Table 3 defines the valid
register command sequences.
When VPEN<VPENLK only read operations from the status register, query, indentifier code or blocks are enabled.
When VPEN=VPENH enables block erase program and lock-bit configuration operations.
Table 3. Command Definitions
Command
Read
Read
Read
Read
Clear
Write to
Word/byte Sector
Sequence
Array
ID
Query
Status
Status
Buffer
Program
Erase
7,8,9
10,11
9,10
Register Register
Notes
5
6
Bus Write Cycles Req'd
1
>2
>2
2
1
>2
2
2
First Bus
Write
Write
Write
Write
Write
Write
Write
Write
X
X
X
X
X
BA
X
BA
FFH
90H
98H
70H
50H
E8H
40H/10H
20H
Second Bus Operation(2)
Read
Read
Read
Write
Write
Write
Read Query
Address(3)
IA
QA
X
BA
PA
BA
Data(4,5)
ID
QD
SRD
N
PD
D0H
Operation(2)
Write Cycles Address(3)
Data(4,5)
Command
Configur-
Set Sector
Clear
Protection
Sequence
ation
Lock-Bit
Sector
Program
Lock-Bit
Notes
12
Bus Write Cycles Req'd
2
2
2
2
First Bus
Write
Write
Write
Write
X
X
X
X
B8H
60H
60H
C0H
Second Bus Operation(2)
Write
Write
Write
Write
Write Cycle
Address(3)
X
BA
X
PA
Data(4,5)
CC
01H
D0H
PD
Operation(2)
Write Cycle Address(3)
Data(4,5)
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MX26F128J3
NOTES:
1. Bus operations are defined in Table 2.
2. X = Any valid address within the device.
BA = Address within the block.
IA = Identifier Code Address: see Figure 2 and Table 14.
QA = Query database Address.
PA = Address of memory location to be programmed.
RCD = Data to be written to the read configuration register. This data is presented to the device on A 16-1 ; all other
address inputs are ignored.
3. ID = Data read from Identifier Codes.
QD = Data read from Query database.
SRD = Data read from status register. See Table 15 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
CC = Configuration Code.
4. The upper byte of the data bus (Q8-Q15) during command writes is a "Don't Care" in x16 operation.
5. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock
codes. See Section 4.3 for read identifier code data.
6. If the WSM is running, only Q7 is valid; Q15-Q8 and Q6-Q0 float, which places them in a high impedance state.
7. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
8. The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument.
Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N =000FH.
The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer.
The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in the
sequence aborts the write to buffer operation. Please see Figure 4. "Write to Buffer Flowchart" for additional
information.
9. The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued.
10.Attempts to issue a block erase or program to a locked block.
11.Either 40H or 10H are recognized by the WSM as the byte/word program setup.
12.The clear block lock-bits operation simultaneously clears all block lock-bits.
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MX26F128J3
Figure 2. Device Identifier Code Memory Map
Word
Address
A[23-1]: 128 Mbit
7FFFFF
Block 127
Reserved for Future
Implementation
7F0003
Block 127 Lock Configuration
7F0002
Reserved for Future
Implementation
7F0000
7EFFFF
(Block 64 through 126)
3FFFFF
Block 63
Reserved for Future
Implementation
3F0003
Block 63 Lock Configuration
3F0002
Reserved for Future
Implementation
3F0000
3EFFFF
(Block 32 through 62)
Reserved for Future
Implementation
1F0003
Block 31 Lock Configuration
128 Mbit
Block 31
1F0002
Reserved for Future
Implementation
1F0000
1EFFFF
(Block 2 through 30)
01FFFF
Block 1
Reserved for Future
Implementation
010003
010002
010000
00FFFF
Block 1 Lock Configuration
Reserved for Future
Implementation
Block 0
Reserved for Future
Implementation
000004
000003
000002
Block 0 Lock Configuration
Device Code
000001
Manufacturer Code
000000
NOTE: A0 is not used in either x8 or x16 mode when obtaining these identifier codes. Data is always given on the low
byte in x16 mode (upper byte contains 00h).
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MX26F128J3
Read Array Command
The device is in Read Array mode on initial device power
up and after exit from power down, or by writing FFH to
the Command User Interface. The read configuration register defaults to asynchronous read page mode. The device remains enabled for reads until another command
is written. The Read Array command functions independently of the VPEN voltage.
Read Query Mode Command
This section defines the data structure or "Database"
returned by the Common Flash Interface (CFI) Query
command. System software should parse this structure
to gain critical information such as block size, density,
x8/x16, and electrical specifications. Once this information has been obtained, the software will know which
command sets to use to enable eLiteFlashTM memory
writes, block erases, and otherwise control the
eLiteFlashTM memory component.
Query Structure Output
The Query Database allows system software to gain information for controlling the eLiteFlashTM memory component. This section describes the device CFI-compliant
interface that allows the host system to access Query
data.
Query data are always presented on the lowest-order
data outputs (DQ 0-7) only. The numerical offset value is
the address relative to the maximum bus width supported
by the device. On this family of devices, the Query table
device starting address is a 10h, which is a word address for x16 devices.
For a word-wide (x16) device, the first two bytes of the
Query structure, "Q" and "R" in ASCII, appear on the
low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the
device outputs ASCII "Q" in the low byte (DQ 0-7 ) and
00h in the high byte (DQ 8-15 ).
At Query addresses containing two or more bytes of information, the least significant data byte is presented at
the lower address, and the most significant data byte is
presented at the higher address.
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MX26F128J3
In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been
dropped. In addition, since the upper byte of word-wide devices is always "00h", the leading "00" has been dropped
from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h
on the upper byte in this mode.
Table 4. Summary of Query Structure Output as a Function of Device and Mode
Device
Type/Mode
x16 device
x16 mode
x16 device
x8 mode
Query start location in
maximum device bus
width addresses
10h
Query data with maximum
device bus width addressing
Hex
Offset
10:
11:
12:
N/A (1)
Hex
Code
0051
0052
0059
N/A (1)
ASCII
Value
"Q"
"R"
"Y"
Query data with byte
addressing
Hex
Offset
20:
21:
22:
Hex
Code
51
00
52
ASCII
Value
"Q"
"Null"
"R"
20:
21:
22:
51
51
52
"Q"
"Q"
"R"
NOTE:
1. The system must drive the lowest order addresses to access all the device's array data when the device is
configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is
"Not Applicable" for x8-configured devices.
Table 5. Example of Query Structure Output of a x16- and x8-Capable Device
Offset
A15-A0
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
...
Word Addressing
Hex Code
Value
D15 - D0
0051
"Q"
0052
"R"
0059
"Y"
P_IDLO
PrVendor
P_IDHI
ID#
PLO
PrVendor
PHI
TblAdr
A_IDLO
AltVendor
A_IDHI
ID#
...
...
Offset
A7-A0
20h
21h
22h
23h
24h
25h
26h
27h
28h
...
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Byte Addressing
Hex Code
Value
D7 - D0
51
"Q"
51
"Q"
52
"R"
52
"R"
59
"Y"
59
"Y"
P_IDLO
PrVendor
P_IDLO
ID#
P_IDHI
ID#
...
...
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MX26F128J3
Query Structure Overview
The Query command causes the eLiteFlashTM memory component to display the Common Flash Interface (CFI)
Query structure or "database". The structure sub-sections and address locations are summarized below.
Table 6. Query Structure (1)
Offset
Sub-Section
Name Description
00h
Manufacturer Code
01h
Device Code
(BA+2)h (2)
Block Status Register
Block-Specific Information
04-0Fh
Reserved
Reserved for Vendor-Specific Information
10h
CFI Query Identification String
Reserved for Vendor-Specific Information
1Bh
System Interface Information
Command Set ID and Vendor Data Offset
27h
Device Geometry Definition
eLiteFlashTM memory Device Layout
P (3)
Primary MXIC-Specific Extended
Vendor-Defined Additional Information Specific to the
Query Table
Primary Vendor Algorithm
NOTES:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a
function of device bus width and mode.
2. BA = Block Address beginning location (i.e., 02000h is block 2s beginning location when the block size is 128
Kbyte).
3. Offset 15 defines "P" which points to the Primary MXIC-Specific Extended Query Table.
Block Status Register
The block status register indicates whether an erase operation completed successfully or whether a given block is
locked or can be accessed for eLiteFlashTM memory program/erase operations.
Table 7. Block Status Register
Offset
(BA+2)h (1)
Length
1
Description
Block Lock Status Register
Address
Value
BA+2:
--00 or --01
BA+2:
(bit 0): 0 or 1
BA+2:
(bit 1-7): 0
BSR.0 Block Lock Status
0 = Unlocked
1 = Locked
BSR 1-7: Reserved for Future Use
NOTE:
1. BA = The beginning location of a Block Address (i.e., 008000h is block 1s (64-KB block) beginning location in word
mode).
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MX26F128J3
CFI Query Identification String
The CFI Query Identification String provides verification that the component supports the Common Flash Interface
specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 8. CFI Identification
Offset
Length
Description
Add.
10
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
10h
3
Query-unique ASCII string "QRY"
13h
2
15h
2
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended Query Table primary algorithm address
17h
2
19h
2
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended Query Table address.
0000h means none exists
Hex
Code
--51
--52
--59
--01
--00
--31
--00
--00
--00
--00
--00
Value
"Q"
"R"
"Y"
System Interface Information
The following device information can optimize system interface software.
Table 9. System Interface Information
Offset Length Description
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
1
1
1
1
1
VCC logic supply minimum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
VCC logic supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
VPP [programming] supply minimum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
VPP [programming] supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
"n" such that typical single word program time-out = 2nus
"n" such that typical max. buffer write time-out = 2nus
"n" such that typical block erase time-out = 2nms
"n" such that typical full chip erase time-out = 2nms
"n" such that maximum word program time-out = 2n times typical
"n" such that maximum buffer write time-out = 2n times typical
"n" such that maximum block erase time-out = 2n times typical
"n" such that maximum chip erase time-out = 2n times typical
P/N:PM0960
Add.
Hex
Code
Value
1B:
--30
3.0V
1C:
--36
3.6 V
1D:
--00
0.0V
1E:
--00
0.0V
1F:
20:
21:
22:
23:
24:
25:
26:
--07
--07
--0A
--00
--04
--04
--04
--00
128us
128us
1s
NA
2ms
2ms
16s
NA
REV. 1.1,OCT. 18, 2004
14
MX26F128J3
Device Geometry Definition
This field provides critical details of the eLiteFlashTM memory device geometry.
Table 10. Device Geometry Definition
Offset Length
Description
27h
28h
1
2
2Ah
2
"n" such that device size = 2n in number of bytes
eLiteFlashTM memory device interface: x8 async(28:00,29:00),
x16 async(28:01,29:00), x8/x16 async(28:02,29:00)
"n" such that maximum number of bytes in write buffer = 2n
2Ch
1
2Dh
4
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in "bulk"
2. x specifies the number of device or partition regions with one or
more contiguous same-size erase blocks
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
Erase Block Region 1 Information
bits 0-15 = y, y+1 = number of identical-size erase blocks
bits 16-31 = z, region erase block(s) size are z x 256 bytes
Code See Table
Below
27:
28:
--02 x8/x16
29:
--00
2A:
--05
32
2B:
--00
2C:
--01
1
2D:
2E:
2F:
30:
Device Geometry Definition
Address
128M
27:
--18
28:
--02
29:
--00
2A:
--05
2B:
--00
2C:
--01
2D:
--7F
2E:
--00
2F:
--00
30:
--02
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15
MX26F128J3
Primary-Vendor Specific Extended Query Table
Certain eLiteFlashTM memory features and commands are optional. The Primary Vendor-Specific Extended Query
table specifies this and other similar information.
Table 11. Primary Vendor-Specific Extended Query
Offset(1) Length
P=31h
(P+0)h
3
(P+1)h
(P+2)h
(P+3)h
1
(P+4)h
1
(P+5)h
(P+6)h
(P+7)h
(P+8)h
4
(P+9)h
(P+A)h
(P+B)h
(P+C)h
(P+D)h
1
2
1
1
Description
Add.
Hex
TM
(Optional eLiteFlash memory Features and Commands)
Code
Primary extended query table
31:
--50
Unique ASCII string "PRI"
32:
--52
33:
--49
Major version number, ASCII
34:
--31
Minor version number, ASCII
35:
--32
Optional feature and command support (1=yes, 0=no)
36:
--C8
bits 9-31 are reserved; undefined bits are "0". If bit 31 is
37:
--00
"1" then another 31 bit field of optional features follows at
38:
--00
the end of the bit-30 field.
39:
--00
bit 0 Chip erase supported
bit 0 = 0
bit 1 Reserved
bit 1 = 0
bit 2 Reserved
bit 2 = 0
bit 3 Legacy lock/unlock supported
bit 3 = 1(1)
bit 4 Queued erase supported
bit 4 = 0
bit 5 Instant Individual block locking supported
bit 5 = 0
bit 6 Protection bits supported
bit 6 = 1
bit 7 Page-mode read supported
bit 7 = 1
bit 8 Synchronous read supported
bit 8 = 0
Value
"P"
"R"
"I"
"1"
"2"
No
Yes(1)
No
No
Yes
Yes
No
Reserved
3A:
--00
Block status register mask
bits 2-15 are Reserved; undefined bits are "0"
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
VCC logic supply highest performance program/erase voltage
bits 0-3 BCD value in 100 mV
bits 4-7 BCD value in volts
VPP optimum program/erase supply voltage
bits 0-3 BCD value in 100 mV
bits 4-7 HEX value in volts
3B:
3C:
--01
--00
bit 0 = 1
bit 1 = 0
Yes
No
3D:
--33
3.3V
3E:
--00
0.0V
NOTE:
1. Future devices may not support the described "Legacy Lock/Unlock" function. Thus bit 3 would have a value of "0".
P/N:PM0960
REV. 1.1,OCT. 18, 2004
16
MX26F128J3
Table 12. Protection Register Information
Offset(1) Length
P=31h
(P+E)h
1
(P+F)h
(P+10)h
(P+11)h
(P+12)h
Description
(Optional eLiteFlashTM memory Features and Commands)
Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available
Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) protection register bytes. Some are pre-programmed
with device-unique serial numbers. Others are user-programmable.
Bits 0-15 point to the protection register lock
byte, the section's first byte. The following bytes are factory
pre-programmed and user-programmable.
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bits 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = "n" such that 2 n = factory pre-programmed bytes
bits 24-31 = "n" such that 2 n = user-programmable bytes
Add.
Value
3F:
Hex
Code
--01
40:
--00
00h
01
NOTE:
1. The variable P is a pointer which is defined at CFI offset 15h.
Table 13. Page Read Information
Offset(1) Length Description
Add.
TM
P=31h
(Optional eLiteFlash memory Features and Commands)
Page Mode Read capability
bits 0-7 = "n" such that 2n HEX value represents the number
(P+13)h
1
of read-page bytes. See offset 28h for device word width to
44:
determine page-mode data output width. 00h indicates no
read page buffer.
(P+14)h
1
Number of synchronous mode read configuration fields that
45:
follow. 00h indicates no burst capability.
(P+15)h
Reserved for future use
46:
Hex
Code
Value
--03
8 byte
--00
0
NOTE:
1. The variable P is a pointer which is defined at CFI offset 15h.
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REV. 1.1,OCT. 18, 2004
17
MX26F128J3
DEVICE OPERATION
SILICON ID READ
The Silicon ID Read mode allows the reading out of a
binary code from the device and will identify its manufacturer and type. This mode is intended for use by
programming equipment for the purpose of automatically
matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.
During the "Silicon ID Read" Mode, manufacturer's code
(MXIC=C2H) can be read out by setting A0=VIL and
device identifier can be read out by setting A0=VIH.
To terminate the operation, it is necessary to write the
read command. The "Silicon ID Read" command functions independently of the VPEN voltage. This command
is valid only when the WSM is off.
To activate this mode, the two cycle "Silicon ID Read"
command is requested. (The command sequence is illustrated in Table 14.
Table 14. MX26F128J3 Silicon ID Codes and Verify Sector Protect Code
Type
Address (1)
Code (HEX)
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Manufacture Code
00000
C2H
1
1
0
0
0
0
1
0
Device Code
00001
(00) 74H
0
1
1
1
0
1
0
0
Block Lock Configuration
X0002 (2)
- Block is Unlocked
DQ0=0
- Block is Locked
DQ0=1
- Reserved for Future Use
DQ1-7
Notes:
1. The lowest order address line is A0.
2. X selects the specific blocks lock configuration code.
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MX26F128J3
Table 15. Status Register Definitions
High Z
Symbol When Status
Busy?
SR.7
No
WRITE STATE MACHINE STATUS
SR.6
Yes
RESERVED
SR.5
Yes
ERASE AND CLEAR LOCK-BITS
STATUS
SR.4
Yes
SR.3
Yes
PROGRAM AND SET LOCK-BIT
STATUS
PROGRAMMING VOLTAGE
STATUS
SR.2
Yes
RESERVED
SR.1
Yes
DEVICE PROTECT STATUS
SR.0
Yes
RESERVED
Definition
Notes
"1"
"0"
Busy
Ready
1
Error in Block Erasure or
Clear Lock-Bits
Successful Block
Erase or Clear
Lock-Bits
Error in Setting Lock-Bit Successful Set Block
Lock Bit
Low Programming Voltage Programming Voltage
Detected, Operation
OK
Aborted
2
Block Lock-Bit Detected,
Operation Abort
4
Unlock
3
5
Notes
1. Check STS or SR.7 to determine block erase, program, or lock-bit configuration completion. SR.6-SR.0 are not
driven while SR.7 = 0
2. If both SR.5 and SR.4 are "1" after a block erase or lock-bit configuration attempt, an improper command sequence was entered.
3. SR.3 does not provide a continuous programming voltage level indication. The WSM interrogates and indicates the
programming voltage level only after Block Erase, Program, Set Block Lock-Bit, or Clear Block Lock-Bits command sequences.
4. SR.1 does not provide a continuous indication of block lock-bit values. The WSM interrogates the block lock-bits
only after Block Erase, Program, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set. Read the block lock configuration codes using the Read
Identifier Codes command to determine block lock-bit status.
5. SR.0 is reserved for future use and should be masked when polling the status register.
Table 16 . Extended Status Register Definitions
High Z
Symbol When Status
Busy?
XSR.7 No
WRITE BUFFER STATUS
XSR.6- Yes
RESERVED
XSR.0
Definition
Notes
"1"
Write buffer available
"0"
Write buffer not available
1
2
Notes:
1. After a Buffer-Write command, XSR.7 = 1 indicates that a Write Buffer is available.
2. XSR.6-XSR.0 are reserved for future use and should be masked when polling the status register.
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19
MX26F128J3
READ STATUS REGISTER COMMAND
WRITE TO BUFFER COMMAND
The Status Register is read after writing the Read Status
Register command of 70H to the Command User Interface. Also, after starting the internal operation the device is set to the Read Status Register mode automatically.
To program the device, a Write to Buffer command is
issue first. A variable number of bytes, up to the buffer
size, can be loaded into the buffer and written to the
eLiteFlashTM memory device. First, the Write to Buffer
Setup command is issued along with the Block Address
(see Figure 4 ,"Write to Buffer Flowchart" on page26).
After the command is issued, the extended Status Register (XSR) can be read when CE is VIL. XSR.7 indicates if the Write Buffer is available.
The contents of Status Register are latched on the later
falling edge of OE or the first edge of CE0, CE1, CE2
that enables the device OE must be toggle to VIH or the
device must be disable before further reads to update
the status register latch. The Read Status Register command functions independently of the VPEN voltage.
If the buffer is available, the number of words/bytes to
be program is written to the device. Next, the start address is given along with the write buffer data. Subsequent writes provide additional device addresses and
data, depending on the count. After the last buffer data
is given, a Write Confirm command must be issued. The
WSM beginning copy the buffer data to the eLiteFlashTM
memory array.
CLEAR STATUS REGISTER COMMAND
The Erase Status, Program Status, Block Status bits
and protect status are set to "1" by the Write State Machine and can only be reset by the Clear Status Register
command of 50H. These bits indicates various failure
conditions.
If an error occurs while writing, the device will stop writing, and status register bit SR.4 will be set to a "1" to
indicate a program failure. The internal WSM verify only
detects errors for "1" that do not successfully program
to "0" . If a program error is detected, the status register
should be cleared. Any time SR.4 and/or SR.5 is set, the
device will not accept any more Write to Buffer commands. Reliable buffered writes can only occur when VCC
is valid and VPEN = VPENH. Also, successful programming requires that the corresponding block lock-bit be
reset.
BLOCK ERASE COMMAND
Automated block erase is initiated by writing the Block
Erase command of 20H followed by the Confirm command of D0H. An address within the block to be erased
is required (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). The CPU
can detect block erase completion by analyzing the output of the STS pin or status register bit SR.7. Toggle OE,
CE0 , CE1 , or CE2 to update the status register. The
CUI remains in read status register mode until a new
command is issued. Also, reliable block erasure can only
occur when VCC is valid and VPEN = VPENH.
BYTE/WORD PROGRAM COMMANDS
Byte/Word program is executed by a two-command sequence. The Byte/Word Program Setup command of 40H
is written to the Command Interface, followed by a second write specifying the address and data to be written.
The WSM controls the program pulse application and
verify operation. The CPU can detect the completion of
the program event by analyzing the STS pin or status
register bit SR.7.
If a byte/word program is attempted while VPEN_V
PENLK, status register bits SR.4 and SR.3 will be set to
"1". Successful byte/word programs require that the corresponding block lock-bit be cleared. If a byte/ word program is attempted when the corresponding block lockbit is set, SR.1 and SR.4 will be set to "1".
P/N:PM0960
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20
MX26F128J3
Read Configuration
The device will support both asynchronous page mode and standard word/byte reads. No configuration is required.
Status register and identifier only support standard word/byte single read operations.
Table 17. Read Configuration Register Definition
RM
16(A16)
R
8
R
15
R
7
R
14
R
6
R
13
R
5
R
R
R
R
12
11
10
9
R
R
R
R
4
3
2
1
Notes
Read mode configuration effects reads from the
eLiteFlashTM memory array.
Status register, query, and identifier reads support
standard word/byte read cycles.
These bits are reserved for future use. Set these
bits to "0".
RCR.16 = READ MODE (RM)
0 = Standard Word/Byte Reads Enabled (Default)
1 = Page-Mode Reads Enabled
RCR.15-1= RESERVED FOR FUTURE
ENHANCEMENTS (R)
Configuration Command
The Status (STS) pin can be configured to different states using the Configuration command. Once the STS pin has
been configured, it remains in that configuration until another configuration command is issued or RP is asserted low.
Initially, the STS pin defaults to RY/BY operation where RY/BY low indicates that the state machine is busy. RY/BY
high indicates that the state machine is ready for a new operation. Table 19, "Configuration Coding Definitions" on
page 28 displays the possible STS configurations.
To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed by the desired
configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described
below. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete
interrupt pulse. Supplying the 00h configuration code with the Configuration command resets the STS pin to the
default RY/BY level mode. The possible configurations and their usage are described in Table 19, "Configuration
Coding Definitions" on page 28. The Configuration command may only be given when the device is not busy. Check
SR.7 for device status. An invalid configuration code will result in both status register bits SR.4 and SR.5 being set
to "1". When configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
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21
MX26F128J3
Table 18. Configuration Coding Definitions
Reserved
Pulse on
Program
Complete (1)
bit 1
bits7-2
Pulse on
Erase
Compete (1)
bit 0
Q7 - Q2 are reserved for future use.
default (Q1-Q 0 = 00) RY/BY, level mode
- used to control HOLD to a memory controller to
prevent accessing a eLiteFlashTM memory subsystem
while any eLiteFlashTM memory device's WSM is busy.
configuration 01 ER INT, pulse mode
- used to generate a system interrupt pulse when any
eLiteFlashTM memory device in an array has completed
a Block Erase.
Helpful for reformatting blocks after file system free
space reclamation or "cleanup"
configuration 10 PR INT, pulse mode
-used to generate a system interrupt pulse when any
eLiteFlashTM memory device in an array has complete
a Program operation. Provides highest performance for
servicing continuous buffer write operations.
configuration 11 ER/PR INT, pulse mode
-used to generate system interrupts to trigger servicing of eLiteFlashTM memory arrays when either erase
or program operations are completed when a common
interrupt service routine is desired.
Q7 - Q2 = Reserved
Q1 - Q0 = STS Pin Configuration Codes
00 = default, level mode RY/BY
(device ready) indication
01 = pulse on Erase complete
10 = pulse on Program complete
11 = pulse on Erase or Program Complete
Configuration Codes 01b, 10b, and 11b are all pulse
mode such that the STS pin pulses low then high when
the operation indicated by the given configuration is
completed.
Configuration Command Sequences for STS pin
configuration (masking bits Q7- Q 2 to 00h) are as
follows:
Default RY/BY level mode: B8h, 00h
ER INT (Erase Interrupt): B8h, 01h
Pulse-on-Erase Complete
PR INT (Program Interrupt): B8h, 02h
Pulse-on-Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase or Program Complete
NOTE: 1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse
width of 250 ns.
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MX26F128J3
tion. To return to read array mode, write the Read Array
command (FFH).
Set Block Lock-Bit Commands
This device provided the block lock-bits, to lock and
unlock the individual block. To set the block lock-bit, the
two cycle Set Block Lock-Bit command is requested.
This command is invalid while the WSM is running. Writing the set block lock-bit command of 60H followed by
confirm command and an appropriate block address.
After the command is written, the device automatically
outputs status register data when read. The CPU can
detect the completion of the set lock-bit event by analyzing the STS pin output or status register bit SR.7.
Also, reliable operations occur only when VCC and VPEN
are valid. With VPEN _VPENLK , lock-bit contents are
protected against alteration.
Programming the Protection Register
The protection register bits are programmed using the
two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide parts
and eight bits at a time for byte-wide parts. First write
the Protection Program Setup command, C0H. The next
write to the device will latch in address and data and
program the specified location.
Any attempt to address Protection Program commands
outside the defined protection register address space will
result in a status register error. Attempting to program a
locked protection register segment will result in a status
register error.
Clear Block Lock-Bits Command
All set block lock-bits can clear by the Clear Block LockBits command. This command is invalid while the WSM
is running. To Clear the block lock-bits, two cycle command is requested . The device automatically outputs
status register data when read. The CPU can detect
completion of the clear block lock-bits event by analyzing the STS pin output or status register bit SR.7. If a
clear block lock-bits operation is aborted due to V PEN
or VCC transiting out of valid range, block lock-bit values
are left in an undetermined state. A repeat of clear block
lock-bits is required to initialize block lock-bit contents to
known values.
Locking the Protection Register
The user-programmable segment of the protection register is lockable by programming Bit 1 of the PR-LOCK
location to 0. Bit 0 of this location is programmed to 0 at
the MXIC factory to protect the unique device number.
Bit 1 is set using the Protection Program command to
program "FFFD" to the PR-LOCK location. After these
bits have been programmed, no further changes can be
made to the values stored in the protection register. Protection Program commands to a locked section will result in a status register error. Protection register lockout
state is not reversible.
Protection Register Program Command
The device offer a 128-bit protection register to increase
the security of a system design. The 128-bits protection
register are divided into two 64-bit segments. One is programmed in the factory with a unique 64-bit number,
which is unchangeable. The other one is left blank for
customer designers to program as desired. Once the
customer segment is programmed, it can be locked to
prevent reprogramming.
VCC TRANSITIONS
Block erase, program, and lock-bit configuration are not
guaranteed if VCC falls outside of the specified operating ranges.
The CUI latches commands issued by system software
and is not altered by CE transitions, or WSM actions. Its
state is read array mode upon power-up, after exit from
power-down mode, or after VCC transitions below VLKO.
Reading the Protection Register
The protection register is read in the identification read
mode. The device is switched to this mode by writing the
Read Identifier command 90H. Once in this mode, read
cycles from addresses retrieve the specified informa-
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23
MX26F128J3
Figure 3. Protection Register Memory Map
Word
Address
A[23 -1]: 128 Mbit
88H
4 Words
User Programmed
85H
84H
4 Words
Factory Programmed
81H
80H
1 Word Lock
NOTE: A 0 is not used in x16 mode when accessing the protection register map (See Table 20 for x16 addressing).
For x8 mode A 0 is used (See Table 21 for x8 addressing).
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MX26F128J3
Table 20. Word-Wide Protection Register Addressing
Word
Use
A8
A7
A6
A5
A4
A3
A2
A1
LOCK
Both
1
0
0
0
0
0
0
0
0
Factory
1
0
0
0
0
0
0
1
1
Factory
1
0
0
0
0
0
1
0
2
Factory
1
0
0
0
0
0
1
1
3
Factory
1
0
0
0
0
1
0
0
4
User
1
0
0
0
0
1
0
1
5
User
1
0
0
0
0
1
1
0
6
User
1
0
0
0
0
1
1
1
7
User
1
0
0
0
1
0
0
0
NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register,
i.e., A23-A9 = 0.
Table 21. Byte-Wide Protection Register Addressing
Word
LOCK
LOCK
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Use
Both
Both
Factory
Factory
Factory
Factory
Factory
Factory
Factory
Factory
User
User
User
User
User
User
User
User
A8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register,
i.e., A23-A9 = 0.
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MX26F128J3
Figure 4. Write to Buffer Flowchart
Start
Command Cycle
- Issue Write-to-Buffer Command
- Address=Any address in block
- Data=0xE8
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal D7
NO
D7=1?
NO
Write to Buffer
Time-Out ?
YES
YES
Write Word Count
- Address=Any address in block
- Data=word count
- Valid range=0x0 thru 0x1F
Write Buffer Data
- Fill write buffer up to word count
- Address=Address(es) within buffer range
- Data=Data to be written
Confirm Cycle
- Issue Confirm Command
- Address=Any address in block
- Data=0xD0
Read Status Register
See Status Register Flowchart
Any Errors?
YES
Error-Handler
User-defined routine
NO
End
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26
MX26F128J3
Figure 5. Status Register Flowchart
Start
Command Cycle
- Issue Status Register Command
- Address = any device address
- Data = 0x70
Data Cycle
- Read Status Register SR[7:0]
SR7 = '1'
No
Y es
- Set/Reset
by WSM
SR6 = '1'
Y es
Erase Suspend
See Suspend/Resume Flowchart
Y es
Program Suspend
See Suspend/Resume Flowchart
No
SR2 = '1'
No
SR5 = '1'
Y es
SR4 = '1'
Y es
Error
Command Sequence
No
No
Error
Erase Failure
Y es
Error
Program Failure
Y es
Error
V PEN < VPENLK
Y es
Error
Block Locked
SR4 = '1'
- Set by WSM
- Reset by user
- See Clear Status
Register
Command
No
SR3 = '1'
No
SR1 = '1'
No
End
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REV. 1.1,OCT. 18, 2004
27
MX26F128J3
Figure 6. Byte/Word Programming Flowchart
Bus
Command
Comments
Operation
Write
Setup Byte/
Data=40H
Word Program Addr=Location to Be
Programmed
Write
Byte/Word
Data=Data to Be
Program
Programmed
Addr=Location to Be
Programmed
Read
Status Register Data
(Note 1)
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
1. Toggling OE (low to high to low) updates the status
register. This can be done in place of issuing the Read
Status Register command. Repeat for subsequent programming operations.
SR full status check can be done after each program
operation, or after a sequence of programming operations.
Write FFH after the last program operation to place
device in read array mode.
Start
Write 40H,
Address
Write Data
and Address
Read
Status Register
SR.7=
0
1
Full Status Check if Desired
Byte/Word Program Complete
FULL STATUS CHECK PROCEDURE
Bus
Command
Operation
Standby
Read Status Register
Data (See Above)
SR.3=
1
Check SR.3
1=Programming to Voltage
Error Detect
Standby
Check SR.1
1=Device Protect Detect
RP=VIH, Block Lock-Bit is
Set Only required for
systems
Standby
Check SR.4
1=Programming Error
Toggling OE (low to high to low) updates the status
register. This can be done in place of issuing the Read
Status Register command. Repeat for subsequent programming operations.
SR.4, SR.3, and SR.1 are only cleared by the Clear
Status Register Command in cases where multiple location are programmed before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
VPP Range Error
0
SR.1=
1
Device Protect Error
1
Programming Error
0
SR.4=
Comments
0
Byte/Word Program Successful
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REV. 1.1,OCT. 18, 2004
28
MX26F128J3
Figure 7. Block Erase Flowchart
Start
Write 20H to Block Address
Write Confirm D0H to Block Address
Read
Status Register
SR.7=1 ?
NO
YES
Full Status Check
If Desired
Erase eLiteFlashTM memory
Block(s) Completed
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REV. 1.1,OCT. 18, 2004
29
MX26F128J3
Figure 8. Set Block Lock-Bit Flowchart
Start
Write 60H, Block Address
Write 01H, Block Address
Read
Status Register
NO
SR.7=1 ?
YES
Full Status Check
If Desired
Set Lock-Bit Completed
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
NO
SR.3=0 ?
Voltage Range Error
YES
YES
SR.4,5=1 ?
Command Sequence Error
NO
NO
SR.4=0 ?
Set Lock-Bit Error
YES
Set Lock-Bit Successful
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30
MX26F128J3
Figure 9. Clear Lock-Bit Flowchart
Start
Write 60H
Write D0H
Read
Status Register
NO
SR.7=1 ?
YES
Full Status Check
If Desired
Set Lock-Bit Completed
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
NO
SR.3=0 ?
Voltage Range Error
YES
YES
SR.4,5=1 ?
Command Sequence Error
NO
NO
SR.5=0 ?
Clear Block Lock-Bits Error
YES
Clear Block Lock-Bit Successful
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31
MX26F128J3
Figure 10. Protection Register Programming Flowchart
Start
Write C0H (Protection Reg.
Program Setup)
Write Protect. Register
Address/Data
Read
Status Register
NO
SR.7=1 ?
YES
Full Status Check
If Desired
Program Completed
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1,1
SR.3, SR.4=
SR.1, SR.4=
SR.1, SR.4=
VPEN Range Error
0,1
Protection Register
Programming Error
1,1
Attempted Program to Locked
Register-Aborted
YES
Program Successful
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32
MX26F128J3
ABSOLUTE MAXIMUM RATINGS
OPERATING RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
OE, and RESET (Note 2) . . . . . . . .-0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Commercial (C) Devices
Ambient Temperature (TA ). . . . . . . . . . . . 0° C to +70° C
VCC Supply Voltages
VCC for full voltage range. . . . . . . . . . . . .+3.0 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See
Figure 6. Maximum DC voltage on input or I/O pins is
VCC +0.5 V. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to
20 ns. See Figure 7.
2. Minimum DC input voltage on pins OE and RESET is
-0.5 V. During voltage transitions OE and RESET may
overshoot VSS to -2.0 V for periods of up to 20 ns.
See Figure 6.
3. No more than one output may be shorted to ground at
a time. Duration of the short circuit should not be
greater than one second.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect
device reliability.
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REV. 1.1,OCT. 18, 2004
33
MX26F128J3
DC Characteristics
Symbol Parameter
ILI
Input and V PEN Load Current
Notes
Typ
1
Max
Unit
±1
uA
Test Conditions
VCC = VCC Max; VCCQ = VCCQ Max
VIN = VCCQ or GND
ILO
Output Leakage Current
±10
1
uA
VCC = VCC Max; VCCQ = VCCQ Max
VIN = VCCQ or GND
CMOS Inputs, VCC = VCC Max,
ICC1
VCC Standby Current
1,2,3
25
80
uA
Device is disabled (see table 2)
RESET=VCCQ±0.2V
0.71
2
mA
TTL Inputs, VCC=VCC max,
Device is disable (see table 2),
RESET=VIH
ICC2
VCC Power-Down Current
25
80
uA
RESET=GND±0.2V
IOUT(STS)=0mA
CMOS Inputs, VCC=VCC Max,
VCCQ=VCCQ Max
15
ICC3
VCC Page Mode Read Current
20
mA
1,3
Device is enabled (see Table 2)
f=5MHz, IOUT=0mA
CMOS Inputs, VCC=VCC Max,
VCCQ=VCCQ Max
24
29
mA
Device is enabled (see Table 2)
f=33MHz, IOUT=0mA
ICC5
VCC Program or Set Lock-Bit
1,4
Current
ICC6
VCC Block Erase or Clear
Block Lock-Bits Current
1,4
35
60
mA
CMOS Inputs, VPEN=VCC
40
70
mA
TTL Inputs, VPEN=VCC
35
70
mA
CMOS Inputs, VPEN=VCC
40
80
mA
TTL Inputs, VPEN=VCC
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REV. 1.1,OCT. 18, 2004
34
MX26F128J3
DC Characteristics, Continued
Symbol Parameter
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
VOH
Output Low Voltage
Output High Voltage
Notes
3
3
Min
-0.5
2.0
1,3
1,3
VPENLK VPEN Lockout during Program, 3,5,6
Erase and Lock-Bit Operations
VPENH VPEN during Block Erase,
5,6
Program, or Lock-Bit Operations
VLKO
VCC Lockout Voltage
7
Max
0.8
VCCQ+0.5
0.4
Unit
V
V
V
0.2
V
0.85 x
VCCQ
VCCQ-0.2
3.0
2.2
V
V
0.5 VCC
V
3.6
V
Test Conditions
VCCQ=VCCQ2/3 Min
IOL=2mA
VCCQ=VCCQ2/3 Min
IOL=100uA
VCCQ=VCCQ Min
IOH=-2.5mA
VCCQ=VCCQ Min
IOH=-100uA
V
NOTES:
1. Includes STS.
2. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH .
3. Sampled, not 100% tested.
4. ICCWS and ICCES are specified with the device de-selected.
5. Block erases, programming, and lock-bit configurations are inhibited when V PEN ˆ V PENLK , and not guaranteed
in the range between VPENLK (max) and VPENH (min), and above VPENH (max).
6. Typically, VPEN is connected to VCC (3.0 V - 3.6 V).
7. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO , and not guaranteed in the
range between VLKO (min) and VCC (min), and above VCC (max).
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REV. 1.1,OCT. 18, 2004
35
MX26F128J3
Figure 11. Transient Input/Output Reference Waveform for VCCQ=3.0V-3.6V
VCCQ
VCCQ/2 Output
TEST POINTS
Input VCCQ/2
0.0
Note:AC test inputs are driven at VCCQ for a Logic "1" and 0.0V for a Logic "0".
Input timing being, and output timing ends, at VCCQ/2V (50% of VCCQ).
Input rise and fall times (10% tp 90%)<5ns.
Figure 12. Transient Equivalent Testing Load Circuit
1.3V
1N914
RL=3.3K ohm
Device
Under Test
Out
CL
NOTE: CL Includes Jig Capacitance
Test Configuration
VCCQ = VCC = 3.0 V-3.6 V
C L (pF)
30
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REV. 1.1,OCT. 18, 2004
36
MX26F128J3
AC Characteristics --Read-Only Operations (1,2)
Versions
(All units in ns unless otherwise noted)
VCC
3.0V-3.6V(3)
VCCQ
3.0V-3.6V(3)
120
Notes
Min
150
Sym
Parameter
Max
tAVAV
Read/Write Cycle Time
tAVQV
Address to Output Delay
120
150
tELQV
CEX to Output Delay
120
150
tGLQV
OE to Non-Array Output Delay
50
50
tPHQV
RESET High to Output Delay
210
210
tELQX
CEX to Output in Low Z
5
0
0
tGLQX
OE to Output in Low Z
5
0
0
tEHQZ
CEX High to Output in High Z
5
35
35
tGHQZ
OE High to Output in High Z
5
15
15
tOH
Output Hold from Address, CEX, or OE
5
120
2, 4
Min
Max
150
0
0
Change, Whichever Occurs First
tELFL/tELFH
CEX Low to BYTE High or Low
5
tFLQV/tFHQV BYTE to Output Delay
tFLQZ
BYTE to Output in High Z
5
tEHEL
CEx High to CEx Low
5
tAPA
Page Address Access Time
tGLQV
OE to Array Output Delay
10
10
1000
1000
1000
1000
0
0
5, 6
25
25
4
25
25
NOTES:CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at
the first edge of CE0, CE1, or CE2 that disables the device (see Table 2).
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
2. OE may be delayed up to t ELQV -t GLQV after the first edge of CE0, CE1, or CE2 that enables the device (see
Table 2) without impact on t ELQV .
3. See Figures 14-16, Transient Input/Output Reference Waveform for VCCQ = 3.0V - 3.6V, Transient Equivalent
Testing Load Circuit for testing characteristics. VCC = 3.0V - 3.6V.
4. When reading the eLiteFlashTM memory array a faster tGLQV (R16) applies. Non-array reads refer to status register
reads, query reads, or device identifier reads.
5. Sampled, not 100% tested.
6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
P/N:PM0960
REV. 1.1,OCT. 18, 2004
37
MX26F128J3
Figure 13. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations
VIH
Address
(A23-A3) VIL
tAVAV
Address VIH
(A2-A0) VIL
Valid Address
Valid Address Valid Address
Valid Address
tEHEL
Disable VIH
CEx[E]
Enable VIL
tEHQZ
tAVQV
VIH
OE [G]
VIL
tGHQZ
tELQV
VIH
WE [W]
tGLQV
VIL
tOH
tAPA
tPHQV
tELQX
DATA[D/Q] VOH
Q0- Q15 VOL
High Z
Valid
Output
Valid
Valid
Output Output
Valid
Output
High Z
tGLQX
VIH
VCC
VIL
VIH
RESET[P]
VIL
tELFL/tELFH
tFLQV/tFHQV
tFLQZ
VIH
BYTE [F]
VIL
NOTE:
1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first
edge of CE0, CE1, or CE2 that disables the device (see Table 2).
2. For standard word/byte read operations, tAPA will equal tAVQV.
3. When reading the eLiteFlashTM memory array a faster tGLQV applies. Non-array reads refer to status register
reads, query reads, or device identifier reads.
P/N:PM0960
REV. 1.1,OCT. 18, 2004
38
MX26F128J3
AC Characteristics--Write Operations (1,2)
Versions
Valid for All
Speeds
Symbol
Parameter
tPHWL (tPHEL )
Unit
Notes
Min
RESET High Recovery to WE(CEX) Going Low
3
210
ns
tELWL (tWLEL )
CEX (WE) Low to WE(CEX) Going Low
4
0
ns
tWP
Write Pulse Width
4
70
ns
tDVWH (tDVEH )
Data Setup to WE(CEX) Going High
5
50
ns
tAVWH (tAVEH )
Address Setup to WE(CEX) Going High
5
55
ns
tWHEH (tEHWH)
CEX (WE) Hold from WE(CEX) High
0
ns
tWHDX (tEHDX)
Data Hold from WE(CEX) High
0
ns
tWHAX (tEHAX)
Address Hold from WE(CEX) High
0
ns
tWPH
Write Pulse Width High
6
30
ns
tVPWH (tVPEH)
VPEN Setup to WE(CEX) Going High
3
0
ns
tWHGL (tEHGL)
Write Recovery before Read
7
35
ns
tWHRL (tEHRL)
WE(CEX) High to STS Going Low
8
tQVVL
VPEN Hold from Valid SRD, STS Going High
tWHQV5 (tEHQV5) Set Lock-Bit Time
tWHQV6 (tEHQV6) Clear Block Lock-Bits Time
Max
500
ns
3,8,9
0
ns
4,9
64
75/85
us
4
0.5
2
sec
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first
edge of CE0, CE1, or CE2 that disables the device (see Table 2).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as
during read-only operations. Refer to AC Characteristics-Read-Only Operations.
2. A write operation can be initiated and terminated with either CE X or WE.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CEX or WE going low (whichever goes low last) to CEX or WE going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
5. Refer to Table 4 for valid A IN and D IN for block erase, program, or lock-bit configuration.
6. Write pulse width high (t WPH) is defined from CEX or WE going high (whichever goes high first) to CEX or WE
going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL .
7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
8. STS timings are based on STS configured in its RY/BY default mode.
9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success
(SR.1/3/4/5=0).
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REV. 1.1,OCT. 18, 2004
39
MX26F128J3
Figure 14. AC Waveform for Write Operations
A
B
C
AIN
AIN
D
E
F
VIH
Address
(A) VIL
tAVWH
(tAVEH)
Disable VIH
tWHAX
(tEHAX)
CEx,(WE)[E(W)]
Enable VIL
tWHGL
(tEHGL)
tWHEH
(tEHWH)
tPHWL
(tPHEL)
VIH
OE
VIL
tELWL
(tWLEL)
tWPH
tWHQZ/tWHRH
Disable VIH
WE,(CEx)[W(E)]
Enable VIL
tWP
tOVWH
(tDVEH)
tWHDX
(tEHDX)
VIH
DATA[D/Q]
VIL
DIN
Valid
SRD
DIN
DIN
tWHRL
(tEHRL)
VOH
STS[R]
VOL
VIH
RESET [P]
VIL
tVPWH
(tVPEH)
tQVVL
VPENH
VPEN[V] VPENLK
VIL
NOTES:
1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first
edge of CE0, CE1, or CE2 that disables the device (see Table 2).
STS is shown in its default mode (RY/BY).
a. VCC power-up and standby.
b. Write block erase, write buffer, or program setup.
c. Write block erase or write buffer confirm, or valid address and data.
d. Automated erase delay.
e. Read status register or query data.
f. Write Read Array command.
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REV. 1.1,OCT. 18, 2004
40
MX26F128J3
Figure 15. AC Waveform for Reset Operation
VIH
STS (R)
VIL
tPHRH
VIH
RESET (P)
VIL
tPLPH
NOTE:
1. STS is shown in its default mode (RY/BY).
Reset Specifications (1)
Sym
tPLPH
tPHRH
Parameter
Notes
RESET Pulse Low Time
2
(If RESET is tied to VCC , this specification is not applicable)
RESET High to Reset during Block Erase, Program, or
3
Lock-Bit Configuration
Min
35
Max
Unit
us
100
ns
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RESET is asserted while a block erase, program, or lock-bit configuration operation is not executing then the
minimum required RESET Pulse Low Time is 100ns.
3. A reset time, tPHQV, is required from the latter of STS (in RY/BY mode) or RESET going high until outputs are
valid.
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41
MX26F128J3
ERASE AND PROGRAMMING PERFORMANCE(1)
LIMITS
PARAMETER
MIN.
TYP.(2)
MAX.
UNITS
Block Erase Time
2.0
15.0
sec
Write Buffer Byte Program Time
218
900
us
Byte Program Time (Using Word/Byte Program Command)
210
900
us
Block Program Time (Using Write to Buffer Command)
0.8
2.4
sec
(Time to Program 32 bytes/16 words)
Block Erase/Program Cycles
Note:
100
Cycles
1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25° C,3.3V. Additionally programming typically assume checkerboard pattern.
LATCH-UP CHARACTERISTICS
MIN.
MAX.
Input Voltage with respect to GND on OE
-1.0V
12.5V
Input Voltage with respect to GND on all power pins, Address pins, CE and WE
-1.0V
2 VCCmax
Input Voltage with respect to GND on all I/O pins
-1.0V
VCC + 1.0V
-100mA
+100mA
Current
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
CAPACITANCE TA=0°° C to 70°° C, VCC=3.0V~3.6V
Parameter Symbol
Parameter Description
Test Set
TYP
MAX
UNIT
CIN
Input Capacitance
VIN=0
6
7.5
pF
COUT
Output Capacitance
VOUT=0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN=0
7.5
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA=25° C, f=1.0MHz
DATA RETENTION
Parameter
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
10
Years
125
20
Years
P/N:PM0960
REV. 1.1,OCT. 18, 2004
42
MX26F128J3
ORDERING INFORMATION
PLASTIC PACKAGE
Part NO.
Access Time
Package type
(ns)
MX26F128J3TC-12
120/25
56-TSOP
MX26F128J3XCC-12
120/25
64-CSP
MX26F128J3TC-15
150/25
56-TSOP
MX26F128J3XCC-15
150/25
64-CSP
P/N:PM0960
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43
MX26F128J3
PACKAGE INFORMATION
P/N:PM0960
REV. 1.1,OCT. 18, 2004
44
MX26F128J3
P/N:PM0960
REV. 1.1,OCT. 18, 2004
45
MX26F128J3
REVISION HISTORY
Revision No. Description
1.0
1. Removed Part No. MX26F640J3
2. To add "eLiteFlashTM" and "NBitTM" trademark
1.1
1. To add 120ns speed grade
P/N:PM0960
Page
All
All
P1,37,43
Date
JUN/30/2004
OCT/18/2004
REV. 1.1,OCT. 18, 2004
46
MX26F128J3
MACRONIX INTERNATIONAL CO., LTD.
Headquarters:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
Europe Office :
TEL:+32-2-456-8020
FAX:+32-2-456-8021
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TEL:+86-755-834-335-79
FAX:+86-755-834-380-78
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TEL:+81-44-246-9100
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FAX:+65-6348-8096
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MACRONIX AMERICA, INC.
TEL:+1-408-262-8887
FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.