N25Q128 128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface Features SPI-compatible serial bus interface 108 MHz (maximum) clock frequency 1.7 V to 2 V single supply voltage VDFPN8 (F8) 8 × 6 mm (MLP8) Supports legacy SPI protocol and new Quad I/O or Dual I/O SPI protocol SO16 (SF) 300 mils width Quad/Dual I/O instructions resulting in an equivalent clock frequency up to 432 MHz: XIP mode for all three protocols – Configurable via volatile or non-volatile registers (enabling the memory to work in XiP mode directly after power on) TBGA24 (12) 6 x 8 mm Program/Erase suspend instructions Continuous read of entire memory via single instruction: – Fast Read – Quad or Dual Output Fast Read – Quad or Dual I/O Fast Read – Additional smart protections available upon customer request Deep Power-down mode: 5 µA (typical) Electronic signature – JEDEC standard two-byte signature (BB18h) – Additional 2 Extended Device ID (EDID) bytes to identify device factory options – Unique ID code (UID) with 14 bytes readonly, available upon customer request Flexible to fit application: – Configurable number of dummy cycles – Output buffer configurable – Fast POR instruction: to speed up power on phase – Reset function available upon customer request 100,000 + program/erase cycles per sector 64-byte user-lockable, one-time programmable (OTP) area Erase capability – Subsector (4-Kbyte) granularity in the 8 boot sectors (bottom or top parts). – Sector (64-Kbyte) granularity More than 20 years data retention Packages – RoHS compliant Write protections – Software write protection applicable to every 64-Kbyte sector (volatile lock bit) – Hardware write protection: protected area size defined by five non-volatile bits (BP0, BP1, BP2, BP3 and TB bit) February 2010 Rev 1.0 1/185 www.numonyx.com 1 Contents N25Q128 - 1.8 V Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 Serial data output (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Serial data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 Hold (HOLD) or Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6 Write protect/enhanced program supply voltage (W/VPP), DQ2 . . . . . . . 18 2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 SPI Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 4.1 Extended SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 Dual I/O SPI (DIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 Quad SPI (QIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 5.2 Extended SPI Protocol Operating features . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.2 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.3 Dual input fast program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.4 Dual Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.5 Quad Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.6 Quad Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.7 Subsector erase, sector erase and bulk erase . . . . . . . . . . . . . . . . . . . 24 5.1.8 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . 24 5.1.9 Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.10 Hold (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Dual SPI (DIO-SPI) Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.1 2/185 Multiple Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 N25Q128 - 1.8 V 5.3 6 Contents 5.2.2 Dual Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.3 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.4 Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 28 5.2.5 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 28 5.2.6 Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.7 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.8 HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Quad SPI (QIO-SPI)Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.1 Multiple Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.2 Quad Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.3 QUAD Command Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.4 Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 30 5.3.5 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 30 5.3.6 Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3.7 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 31 5.3.8 HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3.9 VPP pin Enhanced Supply Voltage feature . . . . . . . . . . . . . . . . . . . . . . 31 Volatile and Non Volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 6.2 6.3 6.4 Legacy SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.3 BP3, BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.4 TB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.5 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Non Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.1 Dummy clock cycle NV configuration bits (NVCR bits from 15 to 12) . . 37 6.2.2 XIP NV configuration bits (NVCR bits from 11 to 9) . . . . . . . . . . . . . . . . 38 6.2.3 Output Driver Strength NV configuration bits (NVCR bits from 8 to 6) . . 38 6.2.4 Fast POR NV configuration bit (NVCR bit 5) . . . . . . . . . . . . . . . . . . . . . 38 6.2.5 Hold (Reset) disable NV configuration bit (NVCR bit 4) . . . . . . . . . . . . 38 6.2.6 Quad Input NV configuration bit (NVCR bit 3) . . . . . . . . . . . . . . . . . . . . 38 6.2.7 Dual Input NV configuration bit (NVCR bit 2) . . . . . . . . . . . . . . . . . . . . . 39 Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3.1 Dummy clock cycle Volatile Configurations bits (VCR bits from 7 to 4) . 40 6.3.2 XIP Volatile Configuration bits (VCR bit 3) . . . . . . . . . . . . . . . . . . . . . . . 41 Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . 41 3/185 Contents N25Q128 - 1.8 V 6.5 7 6.4.1 Quad Input Command VECR<7> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.4.2 Dual Input Command VECR<6> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.4.3 Reset/Hold disable VECR<4> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.4.4 Accelerator pin enable: QIO-SPI protocol / QIFP/QIEFP VECR<3> . . . 43 6.4.5 Output Driver Strength VECR<2:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.5.1 P/E Controller Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.5.2 Erase Suspend Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.5.3 Erase Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.5.4 Program Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.5.5 VPP Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.5.6 Program Suspend Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.5.7 Protection Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.1 SPI Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2 Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . . . 48 8 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.1 4/185 Extended SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.1.1 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.1.2 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.1.3 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . 81 9.1.4 Dual Output Fast Read (DOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.1.5 Dual I/O Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.1.6 Quad Output Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.1.7 Quad I/O Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.1.8 Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.1.9 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.1.10 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.1.11 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9.1.12 Dual Input Fast Program (DIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9.1.13 Dual Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.1.14 Quad Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.1.15 Quad Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 N25Q128 - 1.8 V 9.2 Contents 9.1.16 Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.1.17 Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.1.18 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.1.19 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.1.20 Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.1.21 Program/Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.1.22 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.1.23 Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.1.24 Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.1.25 Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.1.26 Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.1.27 Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.1.28 Read NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.1.29 Write NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.1.30 Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.1.31 Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.1.32 Read Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 110 9.1.33 Write Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 110 9.1.34 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.1.35 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . 112 DIO-SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 9.2.1 Multiple I/O Read Identification protocol . . . . . . . . . . . . . . . . . . . . . . . 115 9.2.2 Dual Command Fast Read (DCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.2.3 Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.2.4 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.2.5 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.2.6 Dual Command Page Program (DCPP) . . . . . . . . . . . . . . . . . . . . . . . 118 9.2.7 Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.2.8 Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.2.9 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.2.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.2.11 Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.2.12 Program/Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.2.13 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.2.14 Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.2.15 Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.2.16 Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5/185 Contents N25Q128 - 1.8 V 9.3 6/185 9.2.17 Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.2.18 Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.2.19 Read NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.2.20 Write NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.2.21 Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.2.22 Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.2.23 Read Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 130 9.2.24 Write Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 130 9.2.25 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.2.26 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . 132 QIO-SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.3.1 Multiple I/O Read Identification (MIORDID) . . . . . . . . . . . . . . . . . . . . . 134 9.3.2 Quad Command Fast Read (QCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.3.3 Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.3.4 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.3.5 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.3.6 Quad Command Page Program (QCPP) . . . . . . . . . . . . . . . . . . . . . . . 139 9.3.7 Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.3.8 Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.3.9 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.3.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.3.11 Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.3.12 Program/Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9.3.13 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 9.3.14 Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.3.15 Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.3.16 Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.3.17 Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.3.18 Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.3.19 Read NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.3.20 Write NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 9.3.21 Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 154 9.3.22 Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 155 9.3.23 Read Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 156 9.3.24 Write Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 157 9.3.25 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9.3.26 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . 160 N25Q128 - 1.8 V 10 11 Contents XIP Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10.1 Enter XIP mode by setting the Non Volatile Configuration Register . . . . 162 10.2 Enter XIP mode by setting the Volatile Configuration Register . . . . . . . 164 10.3 XIP mode hold and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 10.4 XIP Memory reset after a controller reset . . . . . . . . . . . . . . . . . . . . . . . . 166 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.1 Fast POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.2 Rescue sequence in case of power loss during WRNVCR . . . . . . . . . . 169 12 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 13 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 16 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7/185 List of tables N25Q128 - 1.8 V List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. 8/185 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Device Status after Reset Low Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Non-Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Maximum allowed frequency (MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Software protection truth table (Sectors 0 to 255, 64 Kbyte) . . . . . . . . . . . . . . . . . . . . . . . 49 Protected area sizes (TB bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Protected area sizes (TB bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Memory organization (uniform) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Memory organization (bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Memory organization (top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Instruction set: extended SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Read Identification data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Extended Device ID table (first byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Suspend Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Operations Allowed / Disallowed During Device States . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Lock Register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Lock Register in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Instruction set: DIO-SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Instruction set: QIO-SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 NVCR XIP bits setting example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 VCR XIP bits setting example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 VDFPN8 (MLP8) 8-lead very thin dual flat package no lead, 8 × 6 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data . . . . . . 179 TBGA 6x8 mm 24-ball package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Valid Order Information Line Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 N25Q128 - 1.8 V List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 BGA connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Extended SPI protocol example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Non Volatile and Volatile configuration Register Scheme . . . . . . . . . . . . . . . . . . . . . . . . . 33 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Read identification instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Read Data Bytes instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Read Data Bytes at Higher Speed instruction and data-out sequence . . . . . . . . . . . . . . . 82 Dual Output Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Dual I/O Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Quad Input/Output Fast Read instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Quad Input/ Output Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Read OTP instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Write Enable instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Write Disable instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Page Program instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Dual Input Fast Program instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Dual Input Extended Fast Program instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . 93 Quad Input Fast Program instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Quad Input Extended Fast Program instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . 95 Program OTP instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 How to permanently lock the OTP bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Subsector Erase instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Sector Erase instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Bulk Erase instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Read Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Write Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Read Lock Register instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Write to Lock Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Read Flag Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Clear Flag Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Read NV Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Write NV Configuration Register instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Read Volatile Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . 109 Write Volatile Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . 110 Read Volatile Enhanced Configuration Register instruction sequence. . . . . . . . . . . . . . . 110 Write Volatile Enhanced Configuration Register instruction sequence. . . . . . . . . . . . . . . 111 Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Release from Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Multiple I/O Read Identification instruction and data-out sequence DIO-SPI . . . . . . . . . . 115 Dual Command Fast Read instruction and data-out sequence DIO-SPI . . . . . . . . . . . . . 116 Read OTP instruction and data-out sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Write Enable instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Write Disable instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9/185 List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. 10/185 N25Q128 - 1.8 V Dual Command Page Program instruction sequence DSP, 02h . . . . . . . . . . . . . . . . . . . 118 Dual Command Page Program instruction sequence DSP, A2h . . . . . . . . . . . . . . . . . . . 119 Dual Command Page Program instruction sequence DSP, D2h . . . . . . . . . . . . . . . . . . . 119 Program OTP instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Subsector Erase instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Sector Erase instruction sequence DIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Bulk Erase instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Program/Erase Suspend instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . 122 Program/Erase Resume instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Read Status Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Write Status Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Read Lock Register instruction and data-out sequence DIO-SPI. . . . . . . . . . . . . . . . . . . 125 Write to Lock Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Read Flag Status Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . 126 Clear Flag Status Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . 127 Read NV Configuration Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . 127 Write NV Configuration Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . 128 Read Volatile Configuration Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . 129 Write Volatile Configuration Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . 129 Read Volatile Enhanced Configuration Register instruction sequence DIO-SPI . . . . . . . 130 Write Volatile Enhanced Configuration Register instruction sequence DIO-SPI . . . . . . . 131 Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Release from Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Multiple I/O Read Identification instruction and data-out sequence QIO-SPI . . . . . . . . . . 135 Quad Command Fast Read instruction and data-out sequence QSP, 0Bh . . . . . . . . . . . 136 Quad Command Fast Read instruction and data-out sequence QSP, 6Bh . . . . . . . . . . . 136 Quad Command Fast Read instruction and data-out sequence QSP, EBh . . . . . . . . . . . 137 Read OTP instruction and data-out sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Write Enable instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Write Disable instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Quad Command Page Program instruction sequence QIO-SPI, 02h. . . . . . . . . . . . . . . . 140 Quad Command Page Program instruction sequence QIO-SPI, 12h. . . . . . . . . . . . . . . . 140 Quad Command Page Program instruction sequence QIO-SPI, 32h. . . . . . . . . . . . . . . . 141 Program OTP instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Subsector Erase instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Sector Erase instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Bulk Erase instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Program/Erase Suspend instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . 145 Program/Erase Resume instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . 146 Read Status Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Write Status Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Read Lock Register instruction and data-out sequence QIO-SPI . . . . . . . . . . . . . . . . . . 149 Write to Lock Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Read Flag Status Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . 151 Clear Flag Status Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . 152 Read NV Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . 153 Write NV Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . 154 Read Volatile Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . 155 Write Volatile Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . 156 Read Volatile Enhanced Configuration Register instruction sequence QIO-SPI . . . . . . . 157 Write Volatile Enhanced Configuration Register instruction sequence QIO-SPI . . . . . . . 158 Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 N25Q128 - 1.8 V List of figures Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. Figure 110. Figure 111. Figure 112. Figure 113. Figure 114. Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 N25Q128 Read functionality Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 XIP mode directly after power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example) . . . . . . . . . . . . . . . . . . . 165 Power-up timing, Fast POR selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Power-up timing, Fast POR not selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Reset AC waveforms: program or erase cycle is in progress . . . . . . . . . . . . . . . . . . . . . . 174 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Write protect setup and hold timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . 176 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 VPPH timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 VDFPN8 (MLP8) 8-lead very thin dual flat package no lead, 8 × 6 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Figure 115. SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline . . . . . . 179 Figure 116. TBGA - 6 x 8 mm, 24-ball, mechanical package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11/185 Description 1 N25Q128 - 1.8 V Description The N25Q128 is a 128 Mbit (16Mb x 8) serial Flash memory, with advanced write protection mechanisms. It is accessed by a high speed SPI-compatible bus and features the possibility to work in XIP (“eXecute in Place”) mode. The N25Q128 supports innovative, high-performance quad/dual I/O instructions, these new instructions allow to double or quadruple the transfer bandwidth for read and program operations. Furthermore the memory can be operated with 3 different protocols: Standard SPI (Extended SPI protocol) Dual I/O SPI Quad I/O SPI The Standard SPI protocol is enriched by the new quad and dual instructions (Extended SPI protocol). For Dual I/O SPI (DIO-SPI) all the instructions codes, the addresses and the data are always transmitted across two data lines. For Quad I/O SPI (QIO-SPI) the instructions codes, the addresses and the data are always transmitted across four data lines thus enabling a tremendous improvement in both random access time and data throughput. The memory can work in “XIP mode”, that means the device only requires the addresses and not the instructions to output the data. This mode dramatically reduces random access time thus enabling many applications requiring fast code execution without shadowing the memory content on a RAM. The XIP mode can be used with QIO-SPI, DIO-SPI, or Extended SPI protocol, and can be entered and exited using different dedicated instructions to allow maximum flexibility: for applications required to enter in XIP mode right after power up of the device, this can be set as default mode by using dedicated Non Volatile Register (NVR) bits. It is also possible to reduce the power on sequence time with the Fast POR (Power on Reset) feature, enabling a reduction of the latency time before the first read instruction can be performed. Another feature is the ability to pause and resume program and erase cycles by using dedicated Program/Erase Suspend and Resume instructions. The N25Q128 memory offers the following additional Features to be configured by using the Non Volatile Configuration Register (NVCR) for default /Non-Volatile settings or by using the Volatile and Volatile Enhanced Configuration Registers for Volatile settings: the number of dummy cycles for fast read instructions (single, dual and, quad I/O) according to the operating frequency the output buffer impedance the type of SPI protocol (extended SPI, DIO-SPI or QIO-SPI) the required XIP mode Fast or standard POR sequence the Hold (Reset) functionality enabling/disabling The memory is organized as 248 (64-Kbyte) main sectors, in products with Bottom or Top architecture there are 8 64-Kbyte boot sectors, and each boot sector is further divided into 16 4-Kbyte subsectors (128 subsectors in total). The boot sectors can be erased a 4-Kbyte subsector at a time or as a 64-Kbyte sector at a time. The entire memory can be also erased at a time or by sector. 12/185 N25Q128 - 1.8 V Description The memory can be write protected by software using a mix of volatile and non-volatile protection features, depending on the application needs. The protection granularity is of 64Kbyte (sector granularity) for volatile protections. The N25Q128 has 64 one-time-programmable bytes (OTP bytes) that can be read and programmed using two dedicated instructions, Read OTP (ROTP) and Program OTP (POTP), respectively. These 64 bytes can be permanently locked by a particular Program OTP (POTP) sequence. Once they have been locked, they become read-only and this state cannot be reversed. Many different N25Q128 configurations are available, please refer to the ordering scheme page for the possibilities. Additional features are available as security options (The Security features are described in a dedicated Application Note). Please contact your nearest Numonyx Sales office for more information. Figure 1. Logic diagram VCC DQ0 DQ1 C S W/VPP/DQ2 HOLD/DQ3 VSS Logic_Diagram_x25x Note: Reset functionality is available in devices with a dedicated part number. See Section 16: Ordering information. Table 1. Signal names Signal Description I/O C Serial Clock Input DQ0 Serial Data input I/O(1) DQ1 Serial Data output I/O(2) S Chip Select Input W/VPP/DQ2 Write Protect/Enhanced Program supply voltage/additional data I/O I/O(3) HOLD/DQ3(4) Hold (Reset function available upon customer request)/additional data I/O I/O(3) VCC Supply voltage – VSS Ground – 1. Provides dual and quad I/O for Extended SPI protocol instructions, dual I/O for Dual I/O SPI protocol instructions, and quad I/O for Quad I/O SPI protocol instructions. 2. Provides dual and quad instruction input for Extended SPI protocol, dual instruction input for Dual I/O SPI protocol, and quad instruction input for Quad I/O SPI protocol. 3. Provides quad I/O for Extended SPI protocol instructions, and quad I/O for Quad I/O SPI protocol instructions. 4. Reset functionality available with a dedicated part number. See Section 16: Ordering information. 13/185 Description Note: N25Q128 - 1.8 V There is an exposed central pad on the underside of the VDFPN8 package. This is pulled, internally, to VSS, and must not be connected to any other voltage or signal line on the PCB. Figure 2. VDFPN8 connections S DQ1 W/VPP/DQ2 VSS 8 7 6 5 1 2 3 4 VCC HOLD/DQ3 C DQ0 AI13720c 1. Reset functionality available in devices with a dedicated part number. See Section 16: Ordering information. Figure 3. SO16 connections HOLD/DQ3 VCC DU DU DU DU S DQ1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C DQ0 DU DU DU DU VSS W/VPP/DQ2 AI13721c 1. DU = don’t use. 2. See Package mechanical section for package dimensions, and how to identify pin-1. 3. Reset functionality available in devices with a dedicated part number. See Section 16: Ordering information. 14/185 N25Q128 - 1.8 V Figure 4. Description BGA connections 1 A B NC C NC D NC E NC 2 3 4 5 NC NC NC NC C VSS VCC NC S W/VPP/DQ2 NC DQ1 NC NC DQ0 HOLD/DQ3 NC NC NC NC 1. NC = No Connect. 2. See Figure 116.: TBGA - 6 x 8 mm, 24-ball, mechanical package outline. 15/185 Signal descriptions 2 Signal descriptions 2.1 Serial data output (DQ1) N25Q128 - 1.8 V This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). When used as an Input, It is latched on the rising edge of the Serial Clock (C). In the Extended SPI protocol, during the Quad and Dual Input Fast Program (QIFP, DIFP) instructions and during the Quad and Dual Input Extended Fast Program (QIEFP, DIEFP) instructions, pin DQ1 is used also as an input. In the Dual I/O SPI protocol (DIO-SPI) the DQ1 pin always acts as an input/output. In the Quad I/O SPI protocol (QIO-SPI) the DQ1 pin always acts as an input/output, with the exception of the Program or Erase cycle performed with the Enhanced Program Supply Voltage (VPP). In this case the device temporarily goes in Extended SPI protocol. The protocol then becomes QIO-SPI as soon as the VPP pin voltage goes low. 2.2 Serial data input (DQ0) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). Data are shifted out on the falling edge of the Serial Clock (C). In the Extended SPI protocol, during the Quad and Dual Output Fast Read (QOFR, DOFR) and the Quad and Dual Input/Output Fast Read (QIOFR, DIOFR) instructions, pin DQ0 is also used as an input/output. In the DIO-SPI protocol the DQ0 pin always acts as an input/output. In the QIO-SPI protocol, the DQ0 pin always acts as an input/output, with the exception of the Program or Erase cycle performed with the VPP. In this case the device temporarily goes in Extended SPI protocol. Then, the protocol returns to QIO-SPI as soon as the VPP pin voltage goes low. 2.3 Serial Clock (C) This input signal provides the timing for the serial interface. Instructions, addresses, or data present at serial data input (DQ0) are latched on the rising edge of Serial Clock (C). Data are shifted out on the falling edge of the Serial Clock (C). 2.4 Chip Select (S) When this input signal is high, the device is deselected and serial data output (DQ1) is at high impedance. Unless an internal program, erase or write status register cycle is in progress, the device will be in the standby power mode (this is not the deep power-down mode). Driving Chip Select (S) low enables the device, placing it in the active power mode. After power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. 16/185 N25Q128 - 1.8 V 2.5 Signal descriptions Hold (HOLD) or Reset (Reset) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. Reset functionality is present instead of Hold in devices with a dedicated part number. See Section 16: Ordering information. During Hold condition, the Serial Data output (DQ1) is in high impedance, and Serial Data input (DQ0) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. For devices featuring Reset instead of Hold functionality, the Reset (Reset) input provides a hardware reset for the memory. When Reset (Reset) is driven High, the memory is in the normal operating mode. When Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output is high impedance. Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost. In the Extended SPI protocol, during the QOFR, QIOFR, QIFP and the Quad Extended Fast Program (QIEFP) instructions, the Hold (Reset) / DQ3 is used as an input/output (DQ3 functionality). In QIO-SPI, the Hold (Reset) / DQ3 pin acts as an I/O (DQ3 functionality), and the HOLD (Reset) functionality disabled when the device is selected. When the device is deselected (S signal is high), in parts with Reset functionality, it is possible to reset the device unless this functionality is not disabled by mean of dedicated registers bits. The HOLD (Reset) functionality can be disabled using bit 3 of the NVCR or bit 4 of the VECR. 17/185 Signal descriptions 2.6 N25Q128 - 1.8 V Write protect/enhanced program supply voltage (W/VPP), DQ2 W/VPP/DQ2 can be used as: A protection control input. A power supply pin. I/O in Extended SPI protocol quad instructions and in QIO-SPI protocol instructions. When the device is operated in Extended SPI protocol with single or dual instructions, the two functions W or VPP are selected by the voltage range applied to the pin. If the W/VPP input is kept in a low voltage range (0 V to VCC) the pin is seen as a control input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP[0:3] bits of the Status Register. (See Table 3.: Status register format). If VPP is in the range of VPPH, it acts as an additional power supply during the Program or Erase cycles (See Table 29.: Operating conditions). In this case VPP must be stable until the Program or Erase algorithm is completed. During the Extended SPI protocol, the QOFR and QIOFR instructions, and the QIO-SPI protocol instructions, the pin W/VPP/DQ2 is used as an input/output (DQ2 functionality). Using the Extended SPI protocol the QIFP, QIEFP and the QIO-SPI Program/Erase instructions, it is still possible to use the VPP additional power supply to speed up internal operations. However, to enable this possibility it is necessary to set bit 3 of the Volatile Enhanced Configuration Register to 0. In this case the W/VPP/DQ2 pin is used as an I/O pin until the end of the instruction sequence. After the last input data is shifted in, the application should apply VPP voltage to W/VPP/DQ2 within 200 ms to speed up the internal operations. If the VPP voltage is not applied within 200 ms the Program/Erase operations start with standard speed. The default value of the VECR bit 3 is 1, and the VPP functionality for Quad I/O modify instruction is disabled. 2.7 VCC supply voltage VCC is the supply voltage. 2.8 VSS ground VSS is the reference for the VCC supply voltage. 18/185 N25Q128 - 1.8 V 3 SPI Modes SPI Modes These devices can be driven by a micro controller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in standby mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Figure 5. Bus master and memory devices on the SPI bus VSS VCC R SDO SPI interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C SPI Bus Master R CS3 VCC C DQ1DQ0 VSS SPI memory device R VCC C DQ1 DQ0 VSS DQ1DQ0 SPI memory device R SPI memory device VSS CS2 CS1 S W HOLD S W HOLD S W HOLD AI13725b Shown here is an example of three devices working in Extended SPI protocol for simplicity connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the serial data output (DQ1) line at a time; the other devices are high impedance. Resistors R ensures that the N25Q128 is not selected if the bus master leaves the S line in the high impedance state. As the bus master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the bus master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the S line is pulled High while the C line is pulled Low. This ensures that S and C do not become High at the same time, and so that the tSHCH requirement is met. The typical value of R is 100 kΩ, assuming that the time constant R*Cp 19/185 SPI Modes N25Q128 - 1.8 V (Cp = parasitic capacitance of the bus line) is shorter than the time during which the bus master leaves the SPI bus in high impedance. Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the bus master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate. Figure 6. Extended SPI protocol example CPOL CPHA 0 0 C 1 1 C DQ0 DQ1 MSB MSB AI13730 20/185 N25Q128 - 1.8 V 4 SPI Protocols SPI Protocols The N25Q128 memory can work with 3 different Serial protocols: Extended SPI protocol. Dual I/O SPI (DIO-SPI) protocol. Quad I/O SPI (QIO-SPI) protocol. It is possible to choose among the three protocols by means of user volatile or non-volatile configuration bits.It's not possible to mix Extended SPI, DIO-SPI, and QIO-SPI protocols. The device can operate in XIP mode in all 3 protocols. 4.1 Extended SPI protocol This is an extension of the standard (legacy) SPI protocol. Instructions are transmitted on a single data line (DQ0), while addresses and data are transmitted by one, two or four data lines (DQ0, DQ1, W/VPP(DQ2) and HOLD / (DQ3) according to the instruction. When used in the Extended SPI protocol, these devices can be driven by a micro controller in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 Please refer to the SPI modes for a detailed description of these two modes 4.2 Dual I/O SPI (DIO-SPI) protocol Dual I/O SPI (DIO-SPI) protocol: instructions, addresses and I/O data are always transmitted on two data lines (DQ0 and DQ1). Also when in DIO-SPI mode, the device can be driven by a micro controller in either of the two following modes: CPOL= 0, CPHA= 0 CPOL= 1, CPHA= 1 Please refer to the SPI modes for a detailed description of these two modes. Note: Extended SPI protocol Dual I/O instructions allow only address and data to be transmitted over two data lines. However, DIO-SPI allows instructions, addresses, and data to be transmitted on two data lines. This mode can be set using two ways Volatile: by setting bit 6 of the VECR to 0. The device enters DIO-SPI protocol immediately after the Write Enhanced Volatile Configuration Register sequence completes. The device returns to the default working mode (defined by NVCR) on power on. Default/ Non-Volatile: This is default mode on power-up. By setting bit 2 of the NVCR to 0. The device enters DIO-SPI protocol on the subsequent power-on. After all subsequent power-on sequences, the device still starts in DIO-SPI protocol unless bit 2 of NVCR is set to 1 (default value, corresponding to Extended SPI protocol) or bit 3 of NVCR is set to 0 (corresponding to QIO-SPI protocol). 21/185 SPI Protocols 4.3 N25Q128 - 1.8 V Quad SPI (QIO-SPI) protocol Quad SPI (QIO-SPI) protocol: instructions, addresses, and I/O data are always transmitted on four data lines DQ0, DQ1, W/VPP(DQ2), and HOLD / (DQ3). The exception is the Program/Erase cycle performed with the VPP, in which case the device temporarily goes to Extended SPI protocol. Going temporarily into Extended SPI protocol allows the application either to: Note: check the polling bits: WIP bit in the Status Register or Program/Erase Controller bit in the Flag Status Register perform Program/Erase suspend functions. As soon as the VPP pin voltage goes low, the protocol returns to the QIO-SPI protocol. In QIO-SPI protocol the W and HOLD/ (RESET) functionality is disabled when the device is selected (S signal low). When used in the QIO-SPI mode, these devices can be driven by a micro controller in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 Please refer to the SPI modes for a detailed description of the 2 modes. Note: In the Extended SPI protocol only Address and data are allowed to be transmitted on 4 data lines, However in QIO-SPI protocol, the address, data and instructions are transmitted across 4 data lines. This working mode is set in either bit 7 of the Volatile Enhanced Configuration Register (VECR) or in bit 3 of the Non Volatile Configuration Register (NVCR). This mode can be set using two ways 22/185 Volatile: by setting bit 7 of the VECR to 0, the device enters QIO-SPI protocol immediately after the Write Enhanced Volatile Configuration Register sequence completes. The device returns to the default working protocol (defined by the NVCR) on the next power on. Default/ Non- Volatile: This is default protocol on power up. By setting bit 3 of the NVCR to 0, the device enters QIO-SPI protocol on the subsequent power-on. After all subsequent power-on sequences, the device still starts in QIO-SPI protocol unless bit 3 of the NVCR is set to 1 (default value, corresponding to Extended SPI mode). N25Q128 - 1.8 V 5 Operating features 5.1 Extended SPI Protocol Operating features 5.1.1 Read Operations Operating features To read the memory content in Extended SPI protocol different instructions are available: READ, Fast Read, Dual Output Fast Read, Dual Input Output Fast Read, Quad Output Fast Read and Quad Input Output Fast read, allowing the application to choose an instruction to send addresses and receive data by one, two or four data lines. Note: In the Extended SPI protocol the instruction code is always sent on one data line (DQ0): to use two or four data lines the user must use either the DIO-SPI or the QIO-SPI protocol respectively. For fast read instructions the number of dummy clock cycles is configurable by using VCR bits [7:4] or NVCR bits [15:12]. After a successful reading instruction a reduced tSHSL equal to 20 ns is allowed to further improve random access time (in all the other cases tSHSL should be at least 50 ns). See Table 33.: AC Characteristics. 5.1.2 Page programming To program one data byte, two instructions are required: write enable (WREN), which is one byte, and a page program (PP) sequence, which consists of four bytes plus data. This is followed by the internal program cycle (of duration tPP). To spread this overhead, the page program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from ‘1’ to ‘0’), provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the page program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (PP) sequences with each containing only a few bytes (see Section 5.2.3: Page programming and Table 33: AC Characteristics). 5.1.3 Dual input fast program The dual input fast program (DIFP) instruction makes it possible to program up to 256 bytes using two input pins at the same time (by changing bits from ‘1’ to ‘0’). For optimized timings, it is recommended to use the DIFP instruction to program all consecutive targeted bytes in a single sequence rather using several DIFP sequences each containing only a few bytes (see Section 9.1.12: Dual Input Fast Program (DIFP)). 5.1.4 Dual Input Extended Fast Program The Dual Input Extended Fast Program (DIEFP) instruction is an enhanced version of the Dual Input Fast Program instruction, allowing to transmit address across two data lines. For optimized timings, it is recommended to use the DIEFP instruction to program all consecutive targeted bytes in a single sequence rather than using several DIEFP sequences, each containing only a few bytes. 23/185 Operating features 5.1.5 N25Q128 - 1.8 V Quad Input Fast Program The Quad Input Fast Program (QIFP) instruction makes it possible to program up to 256 bytes using 4 input pins at the same time (by changing bits from 1 to 0). For optimized timings, it is recommended to use the QIFP instruction to program all consecutive targeted bytes in a single sequence rather than using several QIFP sequences each containing only a few bytes. 5.1.6 Quad Input Extended Fast Program The Quad Input Extended Fast Program (QIEFP) instruction is an enhanced version of the Quad Input Fast Program instruction, allowing parallel input on the 4 input pins, including the address being sent to the device. For optimized timings, it is recommended to use the QIEFP instruction to program all consecutive targeted bytes in a single sequence rather than using several QIEFP sequences each containing only a few bytes. 5.1.7 Subsector erase, sector erase and bulk erase The page program (PP) instruction allows bits to be reset from ‘1’ to’0’. In order to do this the bytes of memory need to be erased to all 1s (FFh). This can be achieved as follows: a subsector at a time, using the subsector erase (SSE) instruction (only available on the 8 boot sectors at the bottom or top addressable area of a device with a dedicated part number); See Section 16: Ordering information; a sector at a time, using the sector erase (SE) instruction; throughout the entire memory, using the bulk erase (BE) instruction. This starts an internal erase cycle (of duration tSSE, tSE or tBE). The erase instruction must be preceded by a write enable (WREN) instruction. 5.1.8 Polling during a write, program or erase cycle A further improvement in the time to Write Status Register (WRSR), POTP, PP, DIFP,DIEFP,QIFP, QIEFP or Erase (SSE, SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSSE, tSE, or tBE). The application program can monitor if the required internal operation is completed, by polling the dedicated register bits to establish when the previous Write, Program or Erase cycle is complete. The information on the memory being in progress for a Program, Erase, or Write instruction can be checked either on the Write In Progress (WIP) bit of the Status Register or in the Program/Erase Controller bit of the Flag Status Register. Note: The Program/Erase Controller bit is the opposite state of the WIP bit in the Status Register. In the Flag Status Register additional information can be checked, as eventual Program/Erase failures by mean of the Program or erase Error bits. 5.1.9 Active power and standby power modes When Chip Select (S) is Low, the device is selected, and in the active power mode. 24/185 N25Q128 - 1.8 V Operating features When Chip Select (S) is High, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). The device then goes in to the standby power mode. The device consumption drops to ICC1. 5.1.10 Hold (or Reset) condition The Hold (HOLD) signal is used to pause serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any write status register, program or erase cycle that is currently in progress. To enter the hold condition, the device must be selected, with Chip Select (S) Low. The hold condition starts on the falling edge of the Hold (HOLD) signal, provided that the Serial Clock (C) is Low (as shown in Figure 7). The hold condition ends on the rising edge of the Hold (HOLD) signal, provided that the Serial Clock (C) is Low. If the falling edge does not coincide with Serial Clock (C) being Low, the hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the hold condition ends after Serial Clock (C) next goes Low (this is shown in Figure 7). During the hold condition, the serial data output (DQ1) is high impedance, and serial data input (DQ0) and Serial Clock (C) are don’t care. Normally, the device is kept selected, with Chip Select (S) driven Low for the whole duration of the hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the hold condition. If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the hold condition. Figure 7. Hold condition activation C HOLD Hold condition (standard use) Hold condition (non-standard use) AI02029D Reset functionality is available instead of Hold in parts with a dedicated part number. See Section 16: Ordering information. Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost. On Reset going Low, the device enters the reset mode and a time of tRHSL is then required before the device can be reselected by driving Chip Select (S) Low. For the value of tRHSL, see Table 33.: AC Characteristics. All the lock bits are reset to 0 after a Reset Low pulse. 25/185 Operating features Table 2. N25Q128 - 1.8 V Device Status after Reset Low Pulse Conditions: reset pulse occurred Lock bits status Internal logic status Addressed data While decoding an instruction(1): WREN, WRDI, RDID, RDSR, READ, RDLR, Fast_Read, DOFR, DIOFR, QOFR, QIOFR, WRLR, PW, PP, PE, SE, BE, SSE, DP, RDP Reset to 0 Same as POR (2) Not significant Under completion of an Erase or Program cycle of a PW, PP, DIFP, DIEFP, SSE, SE, BE operation Reset to 0 Equivalent to POR (2) Addressed data could be modified Under completion of a WRSR operation Reset to 0 Equivalent to POR (after tW) Write is correctly completed Device deselected (S High) and in standby mode Reset to 0 Same as POR (2) Not significant Note: 1 S remains Low while Reset is Low. 2 See 11: Power-up and power-down The Hold/Reset feature is not available when the Hold (Reset) / DQ3 pin is used as I/O (DQ3 functionality) during Quad Instructions: QOFR, QIOFR,QIFP and QIEFP. The Hold/Reset feature can be disabled by using of the bit 4 of the VECR. 26/185 N25Q128 - 1.8 V 5.2 Operating features Dual SPI (DIO-SPI) Protocol In the Dual SPI (DIO-SPI) protocol all the instructions, addresses and I/O data are transmitted on two data lines. All the functionality available in the Extended SPI protocol is also available in the DIO-SPI protocol. The DIO-SPI instructions are comparable with the Extended SPI instructions; however, in DIO-SPI, the instructions are multiplexed on the two data lines, DQ0 and DQ1. The only exceptions are the READ, Quad Read, and Program instructions, which are not available in DIO-SPI protocol, and the RDID instruction, which is replaced in the DIO-SPI protocol by the Multiple I/O Read Identification (MIORDID) instruction. The Multiple I/O Read Identification Instruction reads just the standard SPI electronic ID (3 bytes), while the Extended SPI protocol RDID instruction allows access to the UID bytes. To help the application code port from Extended SPI to DIO-SPI protocol, the instructions available in the DIO-SPI protocol have the same operation code as the Extended SPI protocol, the only exception being the MIORDID instruction. 5.2.1 Multiple Read Identification The Multiple I/O Read Identification (MIORDID) instruction is available to read the device electronic ID.With respect to the RDID instruction of the Extended SPI protocol, the output data, shifted out on the 2 data lines DQ0 and DQ1. Since the read ID instruction in the DIO-SPI protocol is limited to 3 bytes of the standard electronic ID, the UID bytes are not read with the MIORDID instruction 5.2.2 Dual Command Fast reading Reading the memory data multiplexing the instruction, the addresses and the output data on 2 data lines can be achieved in DIO-SPI protocol by mean of the Dual Command Fast Read instruction, that has 3 instruction codes (BBh, 3Bh and 0Bh) to help the application code porting from Extended SPI protocol to DIO-SPI protocol. Of course quad and single I/O Read instructions are not available in DIO-SPI mode. For Dual Command fast read instructions the number of dummy clock cycles is configurable by using VCR bits [7:4] or NVCR bits [15:12]. After a successful reading instruction, a reduced tSHSL equal to 20ns is allowed to further improve random access time (in all the other cases tSHSL should be at least 50 ns). See Table 33.: AC Characteristics. 5.2.3 Page programming Programming the memory by transmitting the instruction, addresses and the output data on 2 data lines can be achieved in DIO-SPI protocol by using the Dual Command Page Program instruction, that has 3 instruction codes (D2h, A2h and 02h) to help port from Extended SPI protocol to DIO-SPI protocol Quad and single input Program instructions are not available in DIO-SPI mode. 27/185 Operating features N25Q128 - 1.8 V The DIO-SPI protocol is similar to the Extended SPI protocol i.e., to program one data byte two instructions are required: Write Enable (WREN), which is one byte, and a Dual Command Page Program (DCPP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Dual Command Page Program (DCPP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they are consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the DCPP instruction to program all consecutive targeted bytes in a single sequence versus using several DCPP sequences with each containing only a few bytes. See Table 33.: AC Characteristics. 5.2.4 Subsector Erase, Sector Erase and Bulk Erase Similar to the Extended SPI protocol, in the DIO-SPI protocol to erase the memory bytes to all 1s (FFh) the Subsector Erase (SSE), the Sector Erase (SE) and the Bulk Erase (BE) instructions are available. These instructions start an internal Erase cycle (of duration tSSE, tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. Subsector Erase is only available on the 8 Bottom (Top) boot sectors, and is not available in uniform architecture parts 5.2.5 Polling during a Write, Program or Erase cycle Similar to the Extended SPI protocol, in the DIO-SPI protocol it is possible to monitor if the internal write, program or erase operation is completed, by polling the dedicated register bits by using the Read Status Register (RDSR) or Read Flag Status Register (RFSR) instructions, the only obvious difference is that instruction codes, addresses and output data are transmitted across two data lines. 5.2.6 Read and Modify registers Similar to the Extended SPI protocol, the only obvious difference is that instruction codes, addresses and output data are transmitted across two data lines 5.2.7 Active Power and Standby Power modes Similar to the Extended SPI protocol, when Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Cycles). The device then goes in to the Standby Power mode. The device consumption drops to ICC1. 5.2.8 HOLD (or Reset) condition The HOLD (or Reset i.e. for parts having the reset functionality instead of hold pin) signal has exactly the same behavior in DIO-SPI protocol as do in Extended SPI protocol, so please refer to section 5.1.10, Hold (or Reset) condition” in the Extend SPI protocol section for further details. 28/185 N25Q128 - 1.8 V 5.3 Operating features Quad SPI (QIO-SPI)Protocol In the Quad SPI (QIO-SPI) protocol all the Instructions, addresses and I/O data are transmitted on four data lines, with the exception of the polling instructions performed during a Program or Erase cycle performed with VPP, in this case the device temporarily goes in Extended SPI protocol. The protocol again becomes QIO-SPI as soon as the VPP voltage goes low. All the functionality available in the Extended SPI protocol are also available in the QIO-SPI mode, with equivalent instruction transmitted on the 4 data lines DQ0, DQ1, DQ2 and DQ3. The exceptions are the READ, Dual Read and Dual Program instructions, that are not available in QIO-SPI protocol, and the RDID instruction, that is replaced in the QIO-SPI protocol by the Multiple I/O Read Identification (MIORDID) instruction. The Multiple I/O Read Instruction reads just the standard SPI electronic ID (3 bytes), while with the Extended SPI protocol RDID instruction is possible to access also the UID bytes. To help the application code port from Extended SPI to QIO-SPI protocol, the instructions available in the QIO-SPI protocol have the same operation code as in the Extended SPI protocol, the only exception is the MIORDID instruction. 5.3.1 Multiple Read Identification The Multiple I/O Read Identification (MIORDID) instruction is available to read the device electronic ID. With respect to the RDID instruction of the Extended SPI protocol, the output data, shifted out on the 4 data lines DQ0, DQ1, DQ2 and DQ3. Since in the QIO-SPI protocol the Read ID instruction is limited to 3 bytes of the standard electronic ID, the UID bytes are not read with the MIORDID instruction. 5.3.2 Quad Command Fast reading The Array Data can be read by the Quad Command Fast Read instruction using 3 instructions (EBh, 6Bh and 0Bh) to help the application code port from Extended SPI protocol to DIO-SPI protocol. The instruction, address and output data are transmitted across 4 data lines. The Dual and Single I/O Read instructions are not available in QIO-SPI protocol. 5.3.3 QUAD Command Page programming The memory can be programmed in QIO-SPI protocol by the Quad Command Page Program instruction using (02h, 12h and 32h). The instruction, address and input data are transmitted across 4 data lines The Dual and Single I/O Program instructions are not available in QIO-SPI protocol Programming the memory by multiplexing the instruction, the addresses and the output data on 4 wires can be achieved in QIO-SPI protocol by mean of the Quad Command Page Program instruction, that has 3 instruction codes (02h, 12h and 32h) to help the application code porting from Extended SPI protocol to QIO-SPI protocol. Similar to the Extended SPI protocol in the QIO-SPI protocol, to program one data byte two instructions are required: Write Enable (WREN), which is one byte, and Quad Command Page Program (QCPP) sequence, which consists of instruction (one byte), address (3 bytes) and input data. 29/185 Operating features N25Q128 - 1.8 V This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Quad Command Page Program (QCPP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they are in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the QCPP instruction to program all consecutive targeted bytes in a single sequence versus using several QCPP sequences with each containing only a few bytes. See Table 33.: AC Characteristics. The QCPP instruction is transmitted across 4 data lines except when VPP is raised to VPPH. The VPP can be raised to VPPH to decrease programming time (provided that the bit 3 of the VECR has been set to 0 in advance). When bit 3 of VECR is set to 0 after the Quad Command Page Program instruction sequence has been received, the memory temporarily goes in Extended SPI protocol, and is possible to perform polling instructions (checking the WIP bit of the Status Register or the Program/Erase Controller bit of the Flag Status Register) or Program/Erase Suspend instruction even if DQ2 is temporarily used in this VPP functionality. The memory automatically comes back in QIO-SPI protocol as soon as the VPP pin goes Low. 5.3.4 Subsector Erase, Sector Erase and Bulk Erase Similar to the Extended SPI protocol, Subsector Erase (SSE)(1), the Sector Erase (SE) and the Bulk Erase (BE) instructions are used to erase the memory in the QIO-SPI protocol. These instructions start an internal Erase cycle (of duration tSSE, tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. The erase instructions are transmitted across 4 data lines unless the VPP is raised to VPPH. The VPP can be raised to VPPH to decrease erasing time, provided that the bit 3 of the VECR has been set to 0 in advance. In this case, after the erase instruction sequence has been received, the memory temporarily goes in extended SPI protocol, and it is possible to perform polling instructions (checking the WIP bit of the Status Register or the Program/Erase Controller bit of the Flag Status Register) or Program/Erase Suspend instruction even if DQ2 is temporarily used in this VPP functionality. The memory automatically comes back in QIO-SPI protocol as soon as the VPP pin goes Low. Note: Subsector Erase is only available on the 8 Bottom (Top) boot sectors, and is not available in uniform architecture parts 5.3.5 Polling during a Write, Program or Erase cycle It is possible to check if the internal write, program or erase operation is completed, by polling the dedicated register bits of the Read Status Register (RDSR) or Read Flag Status Register (FSR). When the Program or Erase cycle is performed with the VPP, the device temporarily goes in single I/O SPI mode. The protocol became again QIO-SPI as soon as the VPP pin voltage goes low. 30/185 N25Q128 - 1.8 V 5.3.6 Operating features Read and Modify registers The read and modify register instructions are available and behave in QIO-SPI protocol exactly as they do in Extended SPI protocol, the only difference is that instruction codes, addresses and output data are transmitted across 4 data lines. 5.3.7 Active Power and Standby Power modes Exactly as in Extended SPI protocol, when Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal (Program, Erase, Write) Cycles have completed. The device then goes in to the Standby Power mode. The device consumption drops to ICC1. 5.3.8 HOLD (or Reset) condition The HOLD (Hold) feature (or Reset feature, for parts having the reset functionality instead of hold) is disabled in QIO-SPI protocol when the device is selected: the Hold (or Reset)/ DQ3 pin always behaves as an I/O pin (DQ3 function) when the device is deselected. For parts with reset functionality, it is still possible to reset the memory when it is deselected (C signal high). 5.3.9 VPP pin Enhanced Supply Voltage feature It is possible in the QIO-SPI protocol to use the VPP pin as an enhanced supply voltage, but the intention to use VPP as accelerated supply voltage must be declared by setting bit 3 of the VECR to 0. In this case, to accelerate the Program cycle the VPP pin must be raised to VPPH after the device has received the last data to be programmed within 200ms. If the VPP is not raised within 200ms, the program operation starts with the standard internal cycle speed as if the Vpp high voltage were not used, and a flag error appears on Flag Status Register bit 3". 31/185 Volatile and Non Volatile Registers 6 N25Q128 - 1.8 V Volatile and Non Volatile Registers The device features many different registers to store, in volatile or non volatile mode, many parameters and operating configurations: Legacy SPI Status Register 3 configuration registers: – Non Volatile Configuration Register (NVCR), 16 bits – Volatile Configuration Register (VCR), 8 bits – Volatile Enhanced Configuration Register (VECR), 8 bits The Non Volatile Configuration Register (NVCR) affects the memory configuration starting from the successive power-on. It can be used to make the memory start in a determined condition. The VCR and VECR affect the memory configuration after every execution of the related Write Volatile configuration Register (WRVCR) and Write Enhanced Volatile Configuration register (WRVECR) instructions. These instructions overwrite the memory configuration set at POR by NVCR. As described in Figure 8.: Non Volatile and Volatile configuration Register Scheme, the working condition of the memory is set by an internal configuration register, which is not accessible by the user. The working parameters of the internal configuration register are loaded from the NVCR during the boot phase of the device. In this sense the NVCR can be seen as having the default settings of the memory. During the normal life of the application, every time a write volatile or enhanced volatile configuration register instruction is performed, the new configuration parameters set in the volatile registers are also copied in the internal configuration register, thus instantly affecting the memory behavior. Please note that on the next power on the memory will start again in the working protocol set by the Non Volatile Register parameters. 32/185 N25Q128 - 1.8 V Volatile and Non Volatile Registers Figure 8. Non Volatile and Volatile configuration Register Scheme NVCR (Non Volatile Configuratio n Register) Register download executed only during the power on phase VCR (Volatile Co nfiguratio n Register) and VECR (Volatile Enhanced Co nfiguratio n Register) Registers download executed after a WRVCR or WRVECR instructions, it overwrites NVCR configurations on iCR iCR (internal Configuration Register) Device behaviour A Flag Status Register (FSR), 8 bits, is also available to check the status of the device, detecting possible errors or a Program/Erase internal cycle in progress. Each register can be read and modified by means of dedicated instructions in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI). Reading time for all registers is comparable; writing time instead is very different: NVCR bits are set as Flash Cell memory content requiring a longer time to perform internal writing cycles. See Table 33.: AC Characteristics. 33/185 Volatile and Non Volatile Registers 6.1 N25Q128 - 1.8 V Legacy SPI Status Register The Status Register contains a number of status and control bits that can be read or set by specific instructions: Read Status Register (RDSR) and Write Status Register (WRSR). This is available in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI). Table 3. Status register format b7 SRWD b0 BP3 TB BP2 BP1 BP0 WEL WIP Status register write protect Top/bottom bit Block protect bits Write enable latch bit Write in progress bit 6.1.1 WIP bit The Write In Progress (WIP) bit set to 1 indicates that the memory is busy with a Write Status Register, Program or Erase cycle. 0 indicates no cycle is in progress. 6.1.2 WEL bit The Write Enable Latch (WEL) bit set to 1 indicates that the internal Write Enable Latch is set. When set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. 6.1.3 BP3, BP2, BP1, BP0 bits The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP3, BP2, BP1, BP0) bits is set to 1, the relevant memory area, as defined in Table 10.: Protected area sizes (TB bit = 0) and Table 11.: Protected area sizes (TB bit = 1), becomes protected against all program and erase instructions. The Block Protect (BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP3, BP2, BP1, BP0) bits are 0. 6.1.4 TB bit The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Register (WRSR) instruction provided that the Write Enable (WREN) instruction has been issued. 34/185 N25Q128 - 1.8 V Volatile and Non Volatile Registers The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP3, BP2, BP1, BP0) bits to determine if the protected area defined by the Block Protect bits starts from the top or the bottom of the memory array: When TB is reset to '0' (default value), the area protected by the Block Protect bits starts from the top of the memory array. When TB is set to '1', the area protected by the Block Protect bits starts from the bottom of the memory array. The TB bit cannot be written when the SRWD bit is set to '1' and the W pin is driven Low. 6.1.5 SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and the Write Protect (W/VPP) signal allow the device to be put in the hardware protected mode (when the Status Register Write Disable (SRWD) bit is set to '1', and Write Protect ((W/VPP) is driven Low). In this mode, the non-volatile bits of the Status Register (TB, BP3, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. 6.2 Non Volatile Configuration Register The Non Volatile Configuration Register (NVCR) bits affects the default memory configuration after power-on. It can be used to make the memory start in the configuration to fit the application requirements. The device is delivered with Non Volatile Configuration Register (NVCR) bits all erased to 1 (FFFFh). The purpose of the NVCR is to define the default memory settings after the power-on sequence related to many features: The number of dummy clock cycle for fast read instructions, XIP mode configurations, output driver strengths, fast POR sequence, Reset (or Hold) disabling Multiple I/O protocol enabling. The NVCR can be read by the Read Non Volatile Configuration Register (RDNVCR) instruction and written by the Write Non Volatile Configuration Register (WRNVCR) in all the 3 available SPI protocols. See the sections that follow as well as Table 4.: Non-Volatile Configuration Register. 35/185 Volatile and Non Volatile Registers Table 4. Non-Volatile Configuration Register Bit NVCR<15:12> NVCR<11:9> NVCR<8:6> 36/185 N25Q128 - 1.8 V Parameter Value Description 0000 As '1111' 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 Dummy clock 1001 cycle 8 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 Target on maximum allowed frequency fc (108MHz) and to guarantee backward compatibility (default) 000 XIP for SIO Read 001 XIP for DOFR 010 XIP for DIOFR 011 XIP for QOFR 100 XIP for QIOFR 101 reserved 110 reserved 111 XIP disabled (default) 000 reserved 001 90 010 Output Driver 011 Strength 100 60 101 20 110 15 XIP enabling at POR 45 reserved Note To optimize instruction execution (FASTREAD, DOFR,DIOFR,QOFR, QIOFR, ROTP) according to the frequency Impedance at Vcc/2 N25Q128 - 1.8 V Table 4. Bit Volatile and Non Volatile Registers Non-Volatile Configuration Register Parameter Value Description 111 NVCR<5> NVCR<4> NVCR<3> NVCR<2> NVCR<1:0> 6.2.1 Note 30 (default) 0 Enabled POR phase < 100us only read available 1 Disabled (default) POR phase ~ 700us all instructions available Reset/Hold disable 0 disabled 1 enabled (default) Quad Input Command 0 enabled 1 disabled (default) Dual Input Command 0 enabled 1 disabled (default) Reserved xx Don't care Fast POR x READ Disable Pad Hold/Reset functionality Enable command on four input line Enable command on two input line Default value = "11" Dummy clock cycle NV configuration bits (NVCR bits from 15 to 12) The bits from 15 to 12 of the Non Volatile Configuration register store the default settings for the dummy clock cycles number after the fast read instructions (in all the 3 available protocols). The dummy clock cycles number can be set from 1 up to 15 as described here, according to operating frequency (the higher is the operating frequency, the bigger must be the dummy clock cycle number) to optimize the fast read instructions performance. The default values of these bits allow the memory to be safely used with fast read instructions at the maximum frequency (108 MHz). Please note that if the dummy clock number is not sufficient for the operating frequency, the memory reads wrong data. Table 5. Maximum allowed frequency (MHz) Maximum allowed frequency (MHz)(1) Dummy Clock FASTREAD DOFR DIOFR QOFR QIOFR 1 50 50 39 43 20 2 95 85 59 56 39 3 105 95 75 70 49 4 108 105 88 83 59 5 108 108 94 94 69 6 108 108 105 105 78 7 108 108 108 108 86 8 108 108 108 108 95 9 108 108 108 108 105 10 108 108 108 108 108 1. All values are guaranteed by characterization and not 100% tested in production. 37/185 Volatile and Non Volatile Registers 6.2.2 N25Q128 - 1.8 V XIP NV configuration bits (NVCR bits from 11 to 9) The bits from 11 to 9 of the Non Volatile Configuration register store the default settings for the XIP operation, allowing the memory to start working directly on the required XIP mode after successive POR sequence: the device then accepts only address on one, two, or four wires (skipping the instruction) depending on the NVCR XIP bits settings. The default settings for the XIP bits of the NVCR enable the memory to start working in Extended SPI mode after the POR sequence (XIP directly after POR is disabled). 6.2.3 Output Driver Strength NV configuration bits (NVCR bits from 8 to 6) The bits from 8 to 6 of the Non Volatile Configuration register store the default settings for the output driver strength, enabling to optimize the impedance at Vcc/2 output voltage for the specific application. The default values of Output Driver Strength bits of the NVCR set the output impedance at Vcc/2 equal to 30 Ohms. 6.2.4 Fast POR NV configuration bit (NVCR bit 5) The bit 5 of the NVCR enables the FAST POR sequence to speed up the application boot phase before the first READ instruction: if enabled, the FAST POR allows to perform the first read operation after less than 100us. Please note that this timing is valid only for the reading operations: if a modify instruction is then required, after the first WREN instruction the complete POR phase will be performed, resulting in latency time between the WREN and the receiving of the modify instruction (~500us). During this latency time, when the power on second phase is running, no instruction will be accepted except the standard polling instructions either on the Flag Status register or in the Status Register. The default values of Fast POR bit of the NVCR is set to disable the Fast POR feature, in this case the POR sequence requires the standard value of ~500us and after the first WREN instruction no relevant latency time is needed. 6.2.5 Hold (Reset) disable NV configuration bit (NVCR bit 4) The Hold (RESET) disable bit can be used to disable the Hold (Reset) functionality of the Hold (Reset) / DQ3 pin as described in Table 4.: Non-Volatile Configuration Register. This feature can be useful to avoid accidental Hold or Reset condition entries in applications that never require the Hold (Reset) functionality. The default values of Hold (Reset) bit of the NVCR is set to enable the Hold (Reset) functionality. Note: Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16: Ordering information. 6.2.6 Quad Input NV configuration bit (NVCR bit 3) The Quad Input NV configuration bit can be used to make the memory start working in QIOSPI protocol directly after the power on sequence. The products are delivered with this set to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0 the device will enter in QIO-SPI protocol right after the next power on. Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 3 and bit 2 of the Non Volatile Configuration Register set to 0), the memory will work in QIO-SPI. 38/185 N25Q128 - 1.8 V 6.2.7 Volatile and Non Volatile Registers Dual Input NV configuration bit (NVCR bit 2) The Dual Input NV configuration bit can be used to make the memory start working in DIOSPI protocol directly after the power on sequence. The products are delivered with this set to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0 the device will enter in QIO-SPI protocol right after the next power on. Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 3 and bit 2 of the Non Volatile Configuration Register set to 0), the memory will work in QIO-SPI. 6.3 Volatile Configuration Register The Volatile Configuration Register (VCR) affects the memory configuration after every execution of Write Volatile Configuration Register (WRVCR) instruction: this instruction overwrite the memory configuration set at POR by the Non Volatile Configuration Register (NVCR). Its purpose is to define the dummy clock cycles number and to make the device ready to enter in the required XIP mode. 39/185 Volatile and Non Volatile Registers Table 6. Bit VCR<7:4> Volatile Configuration Register Parameter Value As '1111' 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 Dummy clock 1001 cycle 8 10 1011 11 1100 12 1101 13 1110 14 1111 Target on maximum allowed frequency fc (108MHz) and to guarantee backward compatibility (default) XIP 6.3.1 Reserved 9 1010 1 VCR<2:0> Description 0000 0 VCR<3> N25Q128 - 1.8 V xxx Note To optimize instruction execution (FASTREAD, DOFR,DIOFR,QOFR, QIOFR, ROTP) according to the frequency Ready to enter XIP mode To make the data on DQ0 during the first dummy clock NOT “Don’t Care.” For devices with feature set digit equal to 2 or 4 XIP disabled (default) in the part number (Basic XiP), this bit is always Don't Care" reserved Fixed value = 000b Dummy clock cycle Volatile Configurations bits (VCR bits from 7 to 4) The bits from 7 to 4 of the Volatile Configuration Register, as the bits from 15 to 12 of the Volatile Configuration register, set the dummy clock cycles number after the fast read instructions (in all the 3 available protocols). The dummy clock cycles number can be set from 1 up to 15 as described in Table 6.: Volatile Configuration Register, according to operating frequency (the higher is the operating frequency, the bigger must be the dummy clock cycle number, according to Table 5.: Maximum allowed frequency (MHz)) to optimize the fast read instructions performance. Note: 40/185 If the dummy clock number is not sufficient for the operating frequency, the memory reads wrong data. N25Q128 - 1.8 V 6.3.2 Volatile and Non Volatile Registers XIP Volatile Configuration bits (VCR bit 3) The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set to 0 to enable the memory working on XIP mode. For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), this bit is always Don't Care, and it is possible to operate the memory in XIP mode without setting it to 0. See Section 16: Ordering information. 6.4 Volatile Enhanced Configuration Register The Volatile Enhanced Configuration Register (VECR) affects the memory configuration after every execution of Write Volatile Enhanced Configuration Register (WRVECR) instruction: this instruction overwrite the memory configuration set during the POR sequence by the Non Volatile Configuration Register (NVCR). Its purpose is: enabling of QIO-SPI protocol and DIO-SPI protocol Warning: WARNING: in case of both QIO-SPI and DIO-SPI enabled, the memory works in QIO-SPI HOLD (Reset) functionality disabling To enable the VPP functionality in Quad I/O modify operations To define output driver strength (3 bit) 41/185 Volatile and Non Volatile Registers Table 7. Bit VECR<7> VECR<6> Volatile Enhanced Configuration Register Parameter VECR<4> Reset/Hold disable 6.4.1 Description 0 Enabled 1 Disabled (default) 0 Enabled 1 Disabled (default) x Reserved 0 Disabled 1 Enabled (default) Accelerator pin enable in QIO-SPI protocol or in QIFP/QIEFP 0 Enabled 1 Disabled (default) 000 reserved 001 90 010 60 011 45 100 reserved 101 20 110 15 111 30 (default) Note Enable command on four input lines Dual Input Command Reserved VECR<2:0> Value Quad Input Command VECR<5> VECR<3> N25Q128 - 1.8 V Enable command on two input lines Fixed value = 0b Disable Pad Hold/Reset functionality Output Driver Strength The bit must be considered in case of QIFP, QIEFP, or QIO-SPI protocol. It is “Don’t Care” otherwise. Impedance at VCC/2 Quad Input Command VECR<7> The Quad Input Command configuration bit can be used to make the memory start working in QIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register (WRVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI protocol, If this bit is set to 0 the memory works in QIO-SPI protocol. If VECR bit 7 is set back to 1 the memory start working again in Extended SPI protocol, unless the bit 6 is set to 0 (in this case the memory start working in DIO-SPI mode). Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7and bit 6 of the VECR set to 0), the memory will work in QIO-SPI. 6.4.2 Dual Input Command VECR<6> The Dual Input Command configuration bit can be used to make the memory start working in DIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register (WVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI protocol, if this bit is set to 0 the memory works in DIO-SPI protocol (unless the Volatile Enhanced Configuration Register bit 7 is also set to 0). If the Volatile Enhanced Configuration Register bit 6 is set back to 1 the memory start working again in Extended SPI protocol. Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7 and bit 6 of the VECR are set to 0), the memory will work in QIO-SPI. 42/185 N25Q128 - 1.8 V 6.4.3 Volatile and Non Volatile Registers Reset/Hold disable VECR<4> The Hold (RESET) disable bit can be used to disable the Hold (Reset) functionality of the Hold (Reset) / DQ3 pin right after the Write Volatile Enhanced Configuration Register (WVECR) instruction. This feature can be useful to avoid accidental Hold or Reset condition entries in applications that never require the Hold (Reset) functionality. If this bit is set to 0 the Hold (Reset) functionality is disabled, it is possible to enable it back by setting this bit to 1. Please note that after the next power on the Hold (Reset) functionality will be enabled again unless the bit 4 of the Non Volatile Configuration Register is set to 0. Note: Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16: Ordering information. 6.4.4 Accelerator pin enable: QIO-SPI protocol / QIFP/QIEFP VECR<3> The bit 3 of the Volatile Enhanced Configuration Register determines whether it is possible to use the Vpp accelerating voltage to speed up the internal modify operation with the Quad program and erase instructions (both in Extended or QIO-SPI protocols). To use the Vpp voltage with the Quad I/O modify instructions, this bit must be set to 0. The default value is 1, in which case the Vpp pin functionality is disabled in all Quad I/O operations: both in Extended SPI and QIO-SPI protocols. If the Volatile Enhanced Configuration Register bit 3 is set to 0, using the QIO-SPI protocol, after a Quad Command Page Program instruction or an Erase instruction is received (with all input data in the Program case) and the memory is de-selected, the protocol temporarily switches to Extended SPI protocol until Vpp passes from Vpph to normal I/O value (this transition is mandatory to come back to QIO-SPI protocol), to enable the possibility to perform polling instructions (to check if the internal modify cycle is finished by means of the WIP bit of the Status Register or of the Program/Erase controller bit of the Flag Status register) or Program/Erase Suspend instruction even if the DQ2 pin is temporarily used in his Vpp functionality. If the Volatile Enhanced Configuration Register bit 3 is set to 0, after any quad modify instruction (both in Extended SPI protocol and QIO-SPI protocol), there is a maximum allowed time-out of 200 ms after the last instruction input is received and the memory is deselected to raise the Vpp signal to Vpph; otherwise, the modify instruction starts at normal speed, without the Vpph enhancement, and a flag error appears on Flag Status Register bit 3. 6.4.5 Output Driver Strength VECR<2:0> The bits from 2 to 0 of the VECR set the value of the output driver strength, enabling to optimize the impedance at Vcc/2 output voltage for the specific application as described in Table 7.: Volatile Enhanced Configuration Register. The default values of Output Driver Strength is set by the dedicated bits of the Non Volatile Configuration Register (NVCR), the parts are delivered with the output impedance at Vcc/2 equal to 30 Ohms. 43/185 Volatile and Non Volatile Registers 6.5 N25Q128 - 1.8 V Flag Status Register The Flag Status Register is a powerful tool to investigate the status of the device, checking information regarding what is actually doing the memory and detecting possible error conditions. The Flag status register is composed by 8 bit.Three bits (Program/Erase Controller bit, Erase Suspend bit and Program Suspend bit) are a “Status Indicator bit”, they are set and reset automatically by the memory. Four bits (Erase error bit, Program error bit, VPP 1 to 0 error bit and Protection error bit) are “Error Indicators bits”, they are set by the memory when some program or erase operation fails or the user tries to perform a forbidden operation. The user can clear the Error Indicators bits by mean of the Clear Flag Status Register (CLFSR) instruction. All the Flag Status Register bits can be read by mean of the Read Status Register (RFSR) instruction. 44/185 N25Q128 - 1.8 V Table 8. Volatile and Non Volatile Registers Flag Status Register BIT 6.5.1 Description Note 7 P/E Controller (not WIP) Status 6 Erase Suspend Status 5 Erase Error 4 Program Error 3 VPP Error 2 Program Suspend Status 1 Protection Error 0 RESERVED P/E Controller Status bit The bit 7 of the Flag Status register represents the Program/Erase Controller Status bit, It indicates whether there is a Program/Erase internal cycle active. When P/E Controller Status bit is Low (FSR<7>=0) the device is busy; when the bit is High (FSR<7>=1) the device is ready to process a new command. This bit has the same meaning of Write In Progress (WIP) bit of the standard SPI Status Register, but with opposite logic: FSR<7> = not WIP It's possible to make the polling instructions, to check if the internal modify operations are finished, both on the Flag Status register bit 7 or on WIP bit of the Status Register. 6.5.2 Erase Suspend Status bit The bit 6 of the Flag Status register represents the Erase Suspend Status bit, It indicates that an Erase operation has been suspended or is going to be suspended. The bit is set (FSR<6>=1) within the Erase Suspend Latency time, that is as soon as the Program/Erase Suspend command (PES) has been issued, therefore the device may still complete the operation before entering the Suspend Mode. The Erase Suspend Status should be considered valid when the P/E Controller bit is high (FSR<7>=1). When a Program/Erase Resume command (PER) is issued the Erase Suspend Status bit returns Low (FSR<6>=0) 6.5.3 Erase Status bit The bit 5 of the Flag Status Register represents the Erase Status bit. It indicates an erase failure or a protection error when an erase operation is issued. When the Erase Status bit is High (FSR<5>=1) after an Erase failure that means that the P/E Controller has applied the maximum pulses number to the portion to be erased and still failed to verify that it has correctly erased. The Erase Status bit should be read once the P/E Controller Status bit is High. 45/185 Volatile and Non Volatile Registers N25Q128 - 1.8 V The Erase Status bit is related to all possible erase operations: Sector Erase, Sub Sector Erase, and Bulk Erase in all the three available protocols (SPI, DIO-SPI and QIO-SPI). Once the bit 5 is set High, it can only be reset Low (FSR<5>=0) by a Clear Flag Status Register command (CLFSR). If set High it should be reset before a new Erase command is issued; otherwise the new command will appear to fail. 6.5.4 Program Status bit The bit 4 of the Flag Status Register represents the Program Status bit. It indicates: a Program failure an attempt to program a '1' on '0' when VPP=VPPH (only when the pattern is a multiple of 64 bits, otherwise this bit is "Don't care"). a protection error when a program is issued When the Program Status bit is High (FSR<4>=1) after a Program failure that means that the P/E Controller has applied the maximum pulses number to the bytes and it still failed to verify that the required data have been correctly programmed. After an attempt to program '1' on '0', the FSR<4> only goes High (FSR<4>=1) if VPP=VPPH and the data pattern is a multiple of 64 bits: if VPP is not VPPH, FSR<4> remains Low and the attempt is not shown while if VPP is equal to VPPh but the pattern is not a 64 bits multiple the bit 4 is Don't Care. The Program Status bit should be read once the P/E Controller Status bit is High. The Program Status bit is related to all possible program operations in the Extended SPI protocol: Page Program, Dual and Quad Input Fast Program, Dual and Quad Input Extended Fast Program, and OTP Program. The Program Status bit is related to the following program operations in the DIO-SPI and QIO-SPI protocols: Dual and Quad Command Page program and OTP program. Once the bit is set High, it can only be reset Low (FSR<4>=0) by a Clear Flag Status Register command (CLFSR). If set High it should be reset before a new Program command is issued, otherwise the new command will appear to fail. 6.5.5 VPP Status bit The bit 3 of the Flag Status Register represents the VPP Status bit. It indicates an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is sampled at the beginning of a Program or Erase operation. If VPP becomes invalid during an operation, that is the voltage on VPP pin is below the VPPH Voltage (9V), the VPP Status bit goes High (FSR<3>=1) and indeterminate results can occur. Once set High, the VPP Status bit can only be reset Low (FSR<3>=0) by a Clear Flag Status Register command (CLFSR). If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 6.5.6 Program Suspend Status bit The bit 2 of the Flag Status register represents the Program Suspend Status bit, It indicates that an Program operation has been suspended or is going to be suspended. 46/185 N25Q128 - 1.8 V Volatile and Non Volatile Registers The bit is set (FSR<2>=1) within the Erase Suspend Latency time, that is as soon as the Program/Erase Suspend command (PES) has been issued, therefore the device may still complete the operation before entering the Suspend Mode. The Program Suspend Status should be considered valid when the P/E Controller bit is high (FSR<7>=1). When a Program/Erase Resume command (PER) is issued the Program Suspend Status bit returns Low (FSR<2>=0) 6.5.7 Protection Status bit The bit 1 of the Flag Status Register represents the Protection Status bit. It indicates that an Erase or Program operation has tried to modify the contents of a protected array sector, or that a modify operation has tried to access to a locked OTP space. The Protection Status bit is related to all possible protection violations as follows: The sector is protected by Software Protection Mode 1 (SPM1) Lock registers, The sector is protected by Software Protection Mode 2 (SPM2) Block Protect Bits (standard SPI Status Register), An attempt to program OTP when locked, A Write Status Register command (WRSR) on STD SPI Status Register when locked by the SRWD bit in conjunction with the Write Protect (W/VPP) signal (Hardware Protection Mode). Once set High, the Protection Status bit can only be reset Low (FSR<1>=0) by a Clear Flag Status Register command (CLFSR). If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. 47/185 Protection modes 7 N25Q128 - 1.8 V Protection modes There are protocol-related and specific hardware and software protection modes. They are described below. 7.1 SPI Protocol-related protections This applies to all three protocols. The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the N25Q128 features the following data protection mechanisms: Power On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase, and Write Status Register instructions are checked to ensure the instruction includes a number of clock pulses that is a multiple of a byte before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events (in Extended SPI protocol mode): – Power-up – Write Disable (WRDI) instruction completion – Write Status Register (WRSR) instruction completion – Write to Lock Register (WRLR) instruction completion – Program OTP (POTP) instruction completion – Page Program (PP) instruction completion – Dual Input Fast Program (DIFP) instruction completion – Dual Input Extended Fast Program (DIEFP) instruction completion – Quad Input Fast Program (QIFP) instruction completion – Quad Input Extended Fast Program (QIEFP) instruction completion – Subsector Erase (SSE) instruction completion – Sector Erase (SE) instruction completion – Bulk Erase (BE) instruction completion This bit is also returned to its reset state after all the analogous events in DIO-SPI and QIOSPI protocol modes. 7.2 Specific hardware and software protection There are two software protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. The SPM2 can be locked by hardware with the help of the W input pin. SPM1 The first software protected mode (SPM1) is managed by specific Lock Registers assigned to each 64 Kbyte sector. 48/185 N25Q128 - 1.8 V Protection modes The Lock Registers can be read and written using the Read Lock Register (RDLR) and Write to Lock Register (WRLR) instructions. In each Lock Register two bits control the protection of each sector: the Write Lock bit and the Lock Down bit. Write Lock bit: The Write Lock bit determines whether the contents of the sector can be modified (using the Write, Program, or Erase instructions). When the Write Lock bit is set to '1', the sector is write protected - any operations that attempt to change the data in the sector will fail. When the Write Lock bit is reset to '0', the sector is not write protected by the Lock Register, and may be modified. Lock Down bit: The Lock Down bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down bit is set to '1', further modification to the Write Lock and Lock Down bits cannot be performed. A powerup is required before changes to these bits can be made. When the Lock Down bit is reset to '0', the Write Lock and Lock Down bits can be changed. The definition of the Lock Register bits is given in Table 9: Lock Register out. SPM2 The second software protected mode (SPM2) uses the Block Protect bits (BP3, BP2, BP1, BP0) and the Top/Bottom bit (TB bit) to allow part of the memory to be configured as readonly. See Section 16: Ordering information. Table 9. Software protection truth table (Sectors 0 to 255, 64 Kbyte) Sector Lock Register Protection Status Lock Down bit Write Lock bit 0 0 Sector unprotected from Program/Erase/Write operations, protection status reversible. 0 1 Sector protected from Program/Erase/Write operations, protection status reversible. 1 0 Sector unprotected from Program/Erase/Write operations. Sector protection status cannot be changed except by a power-up. 1 1 Sector protected from Program/Erase/Write operations. Sector protection status cannot be changed except by a power-up. As a second level of protection, the Write Protect signal (applied on the W/VPP pin) can freeze the Status Register in a read-only mode. In this mode, the Block Protect bits (BP3, BP2, BP1, BP0) and the Status Register Write Disable bit (SRWD) are protected. 49/185 Protection modes Table 10. N25Q128 - 1.8 V Protected area sizes (TB bit = 0) Status Register Content Memory Content TB bit BP3 Bit PB2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area 0 0 0 0 0 None All sectors (sectors 0 to 255) 0 0 0 0 1 Upper 256th (1/2 Mbit, sector 255) Sectors 0 to 254 0 0 0 1 0 Upper 128th (1 Mbit, 2 sectors: 254 to 255) Sectors 0 to 253 0 0 0 1 1 Upper 64th (2 Mbit, 4 sectors: 252 to 255) Sectors 0 to 251 0 0 1 0 0 Upper 32nd (4 Mbit, 8 sectors: 248 to 255) Sectors 0 to 247 0 0 1 0 1 Upper 16th (8 Mbit, 16 sectors: 240 to 255) Sectors 0 to 239 0 0 1 1 0 Upper 8th Sectors 0 to 223 (16 Mbit, 32 sectors: 224 to 255) 0 0 1 1 1 Upper quarter Lower 3 quarters (sectors 0 to (32 Mbit, 64 sectors: 193 to 255) 191) 0 1 0 0 0 Upper half (64 Mbit, 128 sectors: 128 to 255) Lower half (sectors 0 to 127) 0 1 0 0 1 All sectors (128 Mbit, 256 sectors) None 0 1 0 1 0 All sectors (128 Mbit, 256 sectors) None 0 1 0 1 1 All sectors (128 Mbit, 256 sectors) None 0 1 1 0 0 All sectors (128 Mbit, 256 sectors) None 0 1 1 0 1 All sectors (128 Mbit, 256 sectors) None 0 1 1 1 0 All sectors (128 Mbit, 256 sectors) None 0 1 1 1 1 All sectors (128 Mbit, 256 sectors) None 50/185 N25Q128 - 1.8 V Table 11. Protection modes Protected area sizes (TB bit = 1) Status Register Content Memory Content TB bit BP3 Bit PB2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area 1 0 0 0 0 None All sectors (sectors 0 to 255) 1 0 0 0 1 Lower 256th (1/2 Mbit, sector 0) Sectors 1 to 255 1 0 0 1 0 Lower 128th (1 Mbit, 2 sectors: 0 to 1) Sectors 2 to 255 1 0 0 1 1 Lower 64th (2 Mbit, 4 sectors: 0 to 3) Sectors 4 to 255 1 0 1 0 0 Lower 32nd (4 Mbit, 8 sectors: 0 to 7) Sectors 8 to 255 1 0 1 0 1 Lower 16th (8 Mbit, 16 sectors: 0 to 15) Sectors 16 to 255 1 0 1 1 0 Lower 8th (16 Mbit, 32 sectors: 0 to 31) Sectors 33 to 255 1 0 1 1 1 Lower quarter (32 Mbit, 64 sectors: 0 to 63) Upper 3 quarters (sectors 64 to 255) 1 1 0 0 0 Lower half (64 Mbit, 128 sectors: 0 to 127) Upper half (sectors 128 to 255) 1 1 0 0 1 All sectors (128 Mbit, 256 sectors) None 1 1 0 1 0 All sectors (128 Mbit, 256 sectors) None 1 1 0 1 1 All sectors (128 Mbit, 256 sectors) None 1 1 1 0 0 All sectors (128 Mbit, 256 sectors) None 1 1 1 0 1 All sectors (128 Mbit, 256 sectors) None 1 1 1 1 0 All sectors (128 Mbit, 256 sectors) None 1 1 1 1 1 All sectors (128 Mbit, 256 sectors) None The N25Q128 is available in the following architecture versions: Bottom version, 64 KB uniform sectors plus 8 bottom boot sectors (each with 16 subsectors), Top version, 64 KB uniform sectors plus 8 top boot sectors (each with 16 subsectors) Uniform version, 64 KB uniform sectors without any boot sectors and subsectors. 51/185 Memory organization 8 N25Q128 - 1.8 V Memory organization The memory is organized as: 16,777,216 bytes (8 bits each) 256 sectors (64 Kbytes each) In Bottom and Top versions: 8 bottom (top) 64 Kbytes boot sectors with 16 subsectors (4 Kbytes) and 248 standard 64 KB sectors 65,536 pages (256 bytes each) 64 OTP bytes located outside the main memory array Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable, Subsector Erase is allowed on the 8 boot sectors (for devices with bottom or top architecture). Figure 9. Block diagram HOLD W/VPP High Voltage Generator Control Logic 64 OTP bytes S C DQ0 DQ1 DQ2 DQ3 I/O Shift Register Address Register and Counter Status Register 256 Byte Data Buffer Y Decoder FFFFFFh 00000h 000FFh 256 bytes (page size) X Decoder AI13722a 52/185 N25Q128 - 1.8 V Table 12. Memory organization Memory organization (uniform) (page 1 of 8) Sector Address range 255 FF0000 FFFFFF 254 FE0000 FEFFFF 253 FD0000 FDFFFF 252 FC0000 FCFFFF 251 FB0000 FBFFFF 250 FA0000 FAFFFF 249 F90000 F9FFFF 248 F80000 F8FFFF 247 F70000 F7FFFF 246 F60000 F6FFFF 245 F50000 F5FFFF 244 F40000 F4FFFF 243 F30000 F3FFFF 242 F20000 F2FFFF 241 F10000 F1FFFF 240 F00000 F0FFFF 239 EF0000 EFFFFF 238 EE0000 EEFFFF 237 ED0000 EDFFFF 236 EC0000 ECFFFF 235 EB0000 EBFFFF 234 EA0000 EAFFFF 233 E90000 E9FFFF 232 E80000 E8FFFF 231 E70000 E7FFFF 230 E60000 E6FFFF 229 E50000 E5FFFF 228 E40000 E4FFFF 227 E30000 E3FFFF 226 E20000 E2FFFF 225 E10000 E1FFFF 224 E00000 E0FFFF 223 DF0000 DFFFFF 222 DE0000 DEFFFF 53/185 Memory organization Table 12. N25Q128 - 1.8 V Memory organization (uniform) (page 2 of 8) Sector 54/185 Address range 221 DD0000 DDFFFF 220 DC0000 DCFFFF 219 DB0000 DBFFFF 218 DA0000 DAFFFF 217 D90000 D9FFFF 216 D80000 D8FFFF 215 D70000 D7FFFF 214 D60000 D6FFFF 213 D50000 D5FFFF 212 D40000 D4FFFF 211 D30000 D3FFFF 210 D20000 D2FFFF 209 D10000 D1FFFF 208 D00000 D0FFFF 207 CF0000 CFFFFF 206 CE0000 CEFFFF 205 CD0000 CDFFFF 204 CC0000 CCFFFF 203 CB0000 CBFFFF 202 CA0000 CAFFFF 201 C90000 C9FFFF 200 C80000 C8FFFF 199 C70000 C7FFFF 198 C60000 C6FFFF 197 C50000 C5FFFF 196 C40000 C4FFFF 195 C30000 C3FFFF 194 C20000 C2FFFF 193 C10000 C1FFFF 192 C00000 C0FFFF 191 BF0000 BFFFFF 190 BE0000 BEFFFF 189 BD0000 BDFFFF 188 BC0000 BCFFFF 187 BB0000 BBFFFF N25Q128 - 1.8 V Table 12. Memory organization Memory organization (uniform) (page 3 of 8) Sector Address range 186 BA0000 BAFFFF 185 B90000 B9FFFF 184 B80000 B8FFFF 183 B70000 B7FFFF 182 B60000 B6FFFF 181 B50000 B5FFFF 180 B40000 B4FFFF 179 B30000 B3FFFF 178 B20000 B2FFFF 177 B10000 B1FFFF 176 B00000 B0FFFF 175 AF0000 AFFFFF 174 AE0000 AEFFFF 173 AD0000 ADFFFF 172 AC0000 ACFFFF 171 AB0000 ABFFFF 170 AA0000 AAFFFF 169 A90000 A9FFFF 168 A80000 A8FFFF 167 A70000 A7FFFF 166 A60000 A6FFFF 165 A50000 A5FFFF 164 A40000 A4FFFF 163 A30000 A3FFFF 162 A20000 A2FFFF 161 A10000 A1FFFF 160 A00000 A0FFFF 159 9F0000 9FFFFF 158 9E0000 9EFFFF 157 9D0000 9DFFFF 156 9C0000 9CFFFF 155 9B0000 9BFFFF 154 9A0000 9AFFFF 153 990000 99FFFF 152 980000 98FFFF 55/185 Memory organization Table 12. N25Q128 - 1.8 V Memory organization (uniform) (page 4 of 8) Sector 56/185 Address range 151 970000 97FFFF 150 960000 96FFFF 149 950000 95FFFF 148 940000 94FFFF 147 930000 93FFFF 146 920000 92FFFF 145 910000 91FFFF 144 900000 90FFFF 143 8F0000 8FFFFF 142 8E0000 8EFFFF 141 8D0000 8DFFFF 140 8C0000 8CFFFF 139 8B0000 8BFFFF 138 8A0000 8AFFFF 137 890000 89FFFF 136 880000 88FFFF 135 870000 87FFFF 134 860000 86FFFF 133 850000 85FFFF 132 840000 84FFFF 131 830000 83FFFF 130 820000 82FFFF 129 810000 81FFFF 128 800000 80FFFF 127 7F0000 7FFFFF 126 7E0000 7EFFFF 125 7D0000 7DFFFF 124 7C0000 7CFFFF 123 7B0000 7BFFFF 122 7A0000 7AFFFF 121 790000 79FFFF 120 780000 78FFFF 119 770000 77FFFF 118 760000 76FFFF 117 750000 75FFFF N25Q128 - 1.8 V Table 12. Memory organization Memory organization (uniform) (page 5 of 8) Sector Address range 116 740000 74FFFF 115 730000 73FFFF 114 720000 72FFFF 113 710000 71FFFF 112 700000 70FFFF 111 6F0000 6FFFFF 110 6E0000 6EFFFF 109 6D0000 6DFFFF 108 6C0000 6CFFFF 107 6B0000 6BFFFF 106 6A0000 6AFFFF 105 690000 69FFFF 104 680000 68FFFF 103 670000 67FFFF 102 660000 66FFFF 101 650000 65FFFF 100 640000 64FFFF 99 630000 63FFFF 98 620000 62FFFF 97 610000 61FFFF 96 600000 60FFFF 95 5F0000 5FFFFF 94 5E0000 5EFFFF 93 5D0000 5DFFFF 92 5C0000 5CFFFF 91 5B0000 5BFFFF 90 5A0000 5AFFFF 89 590000 59FFFF 88 580000 58FFFF 87 570000 57FFFF 86 560000 56FFFF 85 550000 55FFFF 84 540000 54FFFF 83 530000 53FFFF 82 520000 52FFFF 57/185 Memory organization Table 12. N25Q128 - 1.8 V Memory organization (uniform) (page 6 of 8) Sector 58/185 Address range 81 510000 51FFFF 80 500000 50FFFF 79 4F0000 4FFFFF 78 4E0000 4EFFFF 77 4D0000 4DFFFF 76 4C0000 4CFFFF 75 4B0000 4BFFFF 74 4A0000 4AFFFF 73 490000 49FFFF 72 480000 48FFFF 71 470000 47FFFF 70 460000 46FFFF 69 450000 45FFFF 68 440000 44FFFF 67 430000 43FFFF 66 420000 42FFFF 65 410000 41FFFF 64 400000 40FFFF 63 3F0000 3FFFFF 62 3E0000 3EFFFF 61 3D0000 3DFFFF 60 3C0000 3CFFFF 59 3B0000 3BFFFF 58 3A0000 3AFFFF 57 390000 39FFFF 56 380000 38FFFF 55 370000 37FFFF 54 360000 36FFFF 53 350000 35FFFF 52 340000 34FFFF 51 330000 33FFFF 50 320000 32FFFF 49 310000 31FFFF 48 300000 30FFFF 47 2F0000 2FFFFF N25Q128 - 1.8 V Table 12. Memory organization Memory organization (uniform) (page 7 of 8) Sector Address range 46 2E0000 2EFFFF 45 2D0000 2DFFFF 44 2C0000 2CFFFF 43 2B0000 2BFFFF 42 2A0000 2AFFFF 41 290000 29FFFF 40 280000 28FFFF 39 270000 27FFFF 38 260000 26FFFF 37 250000 25FFFF 36 240000 24FFFF 35 230000 23FFFF 34 220000 22FFFF 33 210000 21FFFF 32 200000 20FFFF 31 1F0000 1FFFFF 30 1E0000 1EFFFF 29 1D0000 1DFFFF 28 1C0000 1CFFFF 27 1B0000 1BFFFF 26 1A0000 1AFFFF 25 190000 19FFFF 24 180000 18FFFF 23 170000 17FFFF 22 160000 16FFFF 21 150000 15FFFF 20 140000 14FFFF 19 130000 13FFFF 18 120000 12FFFF 17 110000 11FFFF 16 100000 10FFFF 15 F0000 FFFFF 14 E0000 EFFFF 13 D0000 DFFFF 12 C0000 CFFFF 59/185 Memory organization N25Q128 - 1.8 V Table 12. Memory organization (uniform) (page 8 of 8) Sector Address range 11 B0000 BFFFF 10 A0000 AFFFF 9 90000 9FFFF 8 80000 8FFFF 7 70000 7FFFF 6 60000 6FFFF 5 50000 5FFFF 4 40000 4FFFF 3 30000 3FFFF 2 20000 2FFFF 1 10000 1FFFF 0 0 FFFF Table 13. Memory organization (bottom) (page 1 of 9) Sector 60/185 Subsector Address range 255 - FF0000 FFFFFF 254 - FE0000 FEFFFF 253 - FD0000 FDFFFF 252 - FC0000 FCFFFF 251 - FB0000 FBFFFF 250 - FA0000 FAFFFF 249 - F90000 F9FFFF 248 - F80000 F8FFFF 247 - F70000 F7FFFF 246 - F60000 F6FFFF 245 - F50000 F5FFFF 244 - F40000 F4FFFF 243 - F30000 F3FFFF 242 - F20000 F2FFFF 241 - F10000 F1FFFF 240 - F00000 F0FFFF 239 - EF0000 EFFFFF 238 - EE0000 EEFFFF 237 - ED0000 EDFFFF 236 - EC0000 ECFFFF N25Q128 - 1.8 V Memory organization Table 13. Memory organization (bottom) (page 2 of 9) Sector Subsector Address range 235 - EB0000 EBFFFF 234 - EA0000 EAFFFF 233 - E90000 E9FFFF 232 - E80000 E8FFFF 231 - E70000 E7FFFF 230 - E60000 E6FFFF 229 - E50000 E5FFFF 228 - E40000 E4FFFF 227 - E30000 E3FFFF 226 - E20000 E2FFFF 225 - E10000 E1FFFF 224 - E00000 E0FFFF 223 - DF0000 DFFFFF 222 - DE0000 DEFFFF 221 - DD0000 DDFFFF 220 - DC0000 DCFFFF 219 - DB0000 DBFFFF 218 - DA0000 DAFFFF 217 - D90000 D9FFFF 216 - D80000 D8FFFF 215 - D70000 D7FFFF 214 - D60000 D6FFFF 213 - D50000 D5FFFF 212 - D40000 D4FFFF 211 - D30000 D3FFFF 210 - D20000 D2FFFF 209 - D10000 D1FFFF 208 - D00000 D0FFFF 207 - CF0000 CFFFFF 206 - CE0000 CEFFFF 205 - CD0000 CDFFFF 204 - CC0000 CCFFFF 203 - CB0000 CBFFFF 202 - CA0000 CAFFFF 201 - C90000 C9FFFF 61/185 Memory organization N25Q128 - 1.8 V Table 13. Memory organization (bottom) (page 3 of 9) Sector 62/185 Subsector Address range 200 - C80000 C8FFFF 199 - C70000 C7FFFF 198 - C60000 C6FFFF 197 - C50000 C5FFFF 196 - C40000 C4FFFF 195 - C30000 C3FFFF 194 - C20000 C2FFFF 193 - C10000 C1FFFF 192 - C00000 C0FFFF 191 - BF0000 BFFFFF 190 - BE0000 BEFFFF 189 - BD0000 BDFFFF 188 - BC0000 BCFFFF 187 - BB0000 BBFFFF 186 - BA0000 BAFFFF 185 - B90000 B9FFFF 184 - B80000 B8FFFF 183 - B70000 B7FFFF 182 - B60000 B6FFFF 181 - B50000 B5FFFF 180 - B40000 B4FFFF 179 - B30000 B3FFFF 178 - B20000 B2FFFF 177 - B10000 B1FFFF 176 - B00000 B0FFFF 175 - AF0000 AFFFFF 174 - AE0000 AEFFFF 173 - AD0000 ADFFFF 172 - AC0000 ACFFFF 171 - AB0000 ABFFFF 170 - AA0000 AAFFFF 169 - A90000 A9FFFF 168 - A80000 A8FFFF 167 - A70000 A7FFFF 166 - A60000 A6FFFF N25Q128 - 1.8 V Memory organization Table 13. Memory organization (bottom) (page 4 of 9) Sector Subsector Address range 165 - A50000 A5FFFF 164 - A40000 A4FFFF 163 - A30000 A3FFFF 162 - A20000 A2FFFF 161 - A10000 A1FFFF 160 - A00000 A0FFFF 159 - 9F0000 9FFFFF 158 - 9E0000 9EFFFF 157 - 9D0000 9DFFFF 156 - 9C0000 9CFFFF 155 - 9B0000 9BFFFF 154 - 9A0000 9AFFFF 153 - 990000 99FFFF 152 - 980000 98FFFF 151 - 970000 97FFFF 150 - 960000 96FFFF 149 - 950000 95FFFF 148 - 940000 94FFFF 147 - 930000 93FFFF 146 - 920000 92FFFF 145 - 910000 91FFFF 144 - 900000 90FFFF 143 - 8F0000 8FFFFF 142 - 8E0000 8EFFFF 141 - 8D0000 8DFFFF 140 - 8C0000 8CFFFF 139 - 8B0000 8BFFFF 138 - 8A0000 8AFFFF 137 - 890000 89FFFF 136 - 880000 88FFFF 135 - 870000 87FFFF 134 - 860000 86FFFF 133 - 850000 85FFFF 132 - 840000 84FFFF 131 - 830000 83FFFF 63/185 Memory organization N25Q128 - 1.8 V Table 13. Memory organization (bottom) (page 5 of 9) Sector 64/185 Subsector Address range 130 - 820000 82FFFF 129 - 810000 81FFFF 128 - 800000 80FFFF 127 - 7F0000 7FFFFF 126 - 7E0000 7EFFFF 125 - 7D0000 7DFFFF 124 - 7C0000 7CFFFF 123 - 7B0000 7BFFFF 122 - 7A0000 7AFFFF 121 - 790000 79FFFF 120 - 780000 78FFFF 119 - 770000 77FFFF 118 - 760000 76FFFF 117 - 750000 75FFFF 116 - 740000 74FFFF 115 - 730000 73FFFF 114 - 720000 72FFFF 113 - 710000 71FFFF 112 - 700000 70FFFF 111 - 6F0000 6FFFFF 110 - 6E0000 6EFFFF 109 - 6D0000 6DFFFF 108 - 6C0000 6CFFFF 107 - 6B0000 6BFFFF 106 - 6A0000 6AFFFF 105 - 690000 69FFFF 104 - 680000 68FFFF 103 - 670000 67FFFF 102 - 660000 66FFFF 101 - 650000 65FFFF 100 - 640000 64FFFF 99 - 630000 63FFFF 98 - 620000 62FFFF 97 - 610000 61FFFF 96 - 600000 60FFFF N25Q128 - 1.8 V Memory organization Table 13. Memory organization (bottom) (page 6 of 9) Sector Subsector Address range 95 - 5F0000 5FFFFF 94 - 5E0000 5EFFFF 93 - 5D0000 5DFFFF 92 - 5C0000 5CFFFF 91 - 5B0000 5BFFFF 90 - 5A0000 5AFFFF 89 - 590000 59FFFF 88 - 580000 58FFFF 87 - 570000 57FFFF 86 - 560000 56FFFF 85 - 550000 55FFFF 84 - 540000 54FFFF 83 - 530000 53FFFF 82 - 520000 52FFFF 81 - 510000 51FFFF 80 - 500000 50FFFF 79 - 4F0000 4FFFFF 78 - 4E0000 4EFFFF 77 - 4D0000 4DFFFF 76 - 4C0000 4CFFFF 75 - 4B0000 4BFFFF 74 - 4A0000 4AFFFF 73 - 490000 49FFFF 72 - 480000 48FFFF 71 - 470000 47FFFF 70 - 460000 46FFFF 69 - 450000 45FFFF 68 - 440000 44FFFF 67 - 430000 43FFFF 66 - 420000 42FFFF 65 - 410000 41FFFF 64 - 400000 40FFFF 63 - 3F0000 3FFFFF 62 - 3E0000 3EFFFF 61 - 3D0000 3DFFFF 65/185 Memory organization N25Q128 - 1.8 V Table 13. Memory organization (bottom) (page 7 of 9) Sector 66/185 Subsector Address range 60 - 3C0000 3CFFFF 59 - 3B0000 3BFFFF 58 - 3A0000 3AFFFF 57 - 390000 39FFFF 56 - 380000 38FFFF 55 - 370000 37FFFF 54 - 360000 36FFFF 53 - 350000 35FFFF 52 - 340000 34FFFF 51 - 330000 33FFFF 50 - 320000 32FFFF 49 - 310000 31FFFF 48 - 300000 30FFFF 47 - 2F0000 2FFFFF 46 - 2E0000 2EFFFF 45 - 2D0000 2DFFFF 44 - 2C0000 2CFFFF 43 - 2B0000 2BFFFF 42 - 2A0000 2AFFFF 41 - 290000 29FFFF 40 - 280000 28FFFF 39 - 270000 27FFFF 38 - 260000 26FFFF 37 - 250000 25FFFF 36 - 240000 24FFFF 35 - 230000 23FFFF 34 - 220000 22FFFF 33 - 210000 21FFFF 32 - 200000 20FFFF 31 - 1F0000 1FFFFF 30 - 1E0000 1EFFFF 29 - 1D0000 1DFFFF 28 - 1C0000 1CFFFF 27 - 1B0000 1BFFFF 26 - 1A0000 1AFFFF N25Q128 - 1.8 V Memory organization Table 13. Memory organization (bottom) (page 8 of 9) Sector Subsector Address range 190000 19FFFF 24 - 180000 18FFFF 23 - 170000 17FFFF 22 - 160000 16FFFF 21 - 150000 15FFFF 20 - 140000 14FFFF 19 - 130000 13FFFF 18 - 120000 12FFFF 17 - 110000 11FFFF 16 - 100000 10FFFF 15 - F0000 FFFFF 14 - E0000 EFFFF 13 - D0000 DFFFF 12 - C0000 CFFFF 11 - B0000 BFFFF 10 - A0000 AFFFF 9 - 90000 9FFFF 8 - 80000 8FFFF 127 7F000 7FFFF ... 7 ... - ... 25 70FFF 111 6F000 6FFFF ... 6 ... 70000 ... 112 60FFF 95 5F000 5FFFF ... 5 ... 60000 ... 96 50FFF 79 4F000 4FFFF ... 4 ... 50000 ... 80 40FFF 63 3F000 3FFFF ... 3 ... 40000 ... 64 30FFF 47 2F000 2FFFF ... 2 32 20000 ... 30000 ... 48 20FFF 67/185 Memory organization N25Q128 - 1.8 V Memory organization (bottom) (page 9 of 9) Subsector 31 1F000 ... 1 1FFFF 10FFF 15 F000 FFFF ... 0 FFF Memory organization (top) Subsector 127 FFF000 ... 255 Address range ... Sector FFFFFF ... Table 14. 0 ... 10000 ... 16 0 112 FF0000 FF0FFF 111 FEF000 FEFFFF ... ... ... 254 96 FE0000 FE0FFF 95 FDF000 FDFFFF ... ... ... 253 80 FD0000 FD0FFF 79 FCF000 FCFFFF ... ... ... 252 64 FC0000 FC0FFF 63 FBF000 FBFFFF ... FB0000 FB0FFF 47 FAF000 FAFFFF ... 250 ... ... 48 ... ... 251 FA0FFF 31 F9F000 F9FFFF ... ... FA0000 ... 32 249 F90FFF 15 F8F000 F8FFFF ... ... F90000 ... 16 248 68/185 Address range ... Sector ... Table 13. 0 F80000 F80FFF 247 - F70000 F7FFFF 246 - F60000 F6FFFF 245 - F50000 F5FFFF N25Q128 - 1.8 V Memory organization Table 14. Memory organization (top) Sector Subsector Address range 244 - F40000 F4FFFF 243 - F30000 F3FFFF 242 - F20000 F2FFFF 241 - F10000 F1FFFF 240 - F00000 F0FFFF 239 - EF0000 EFFFFF 238 - EE0000 EEFFFF 237 - ED0000 EDFFFF 236 - EC0000 ECFFFF 235 - EB0000 EBFFFF 234 - EA0000 EAFFFF 233 - E90000 E9FFFF 232 - E80000 E8FFFF 231 - E70000 E7FFFF 230 - E60000 E6FFFF 229 - E50000 E5FFFF 228 - E40000 E4FFFF 227 - E30000 E3FFFF 226 - E20000 E2FFFF 225 - E10000 E1FFFF 224 - E00000 E0FFFF 223 - DF0000 DFFFFF 222 - DE0000 DEFFFF 221 - DD0000 DDFFFF 220 - DC0000 DCFFFF 219 - DB0000 DBFFFF 218 - DA0000 DAFFFF 217 - D90000 D9FFFF 216 - D80000 D8FFFF 215 - D70000 D7FFFF 214 - D60000 D6FFFF 213 - D50000 D5FFFF 212 - D40000 D4FFFF 211 - D30000 D3FFFF 210 - D20000 D2FFFF 69/185 Memory organization N25Q128 - 1.8 V Table 14. Memory organization (top) Sector 70/185 Subsector Address range 209 - D10000 D1FFFF 208 - D00000 D0FFFF 207 - CF0000 CFFFFF 206 - CE0000 CEFFFF 205 - CD0000 CDFFFF 204 - CC0000 CCFFFF 203 - CB0000 CBFFFF 202 - CA0000 CAFFFF 201 - C90000 C9FFFF 200 - C80000 C8FFFF 199 - C70000 C7FFFF 198 - C60000 C6FFFF 197 - C50000 C5FFFF 196 - C40000 C4FFFF 195 - C30000 C3FFFF 194 - C20000 C2FFFF 193 - C10000 C1FFFF 192 - C00000 C0FFFF 191 - BF0000 BFFFFF 190 - BE0000 BEFFFF 189 - BD0000 BDFFFF 188 - BC0000 BCFFFF 187 - BB0000 BBFFFF 186 - BA0000 BAFFFF 185 - B90000 B9FFFF 184 - B80000 B8FFFF 183 - B70000 B7FFFF 182 - B60000 B6FFFF 181 - B50000 B5FFFF 180 - B40000 B4FFFF 179 - B30000 B3FFFF 178 - B20000 B2FFFF 177 - B10000 B1FFFF 176 - B00000 B0FFFF 175 - AF0000 AFFFFF N25Q128 - 1.8 V Memory organization Table 14. Memory organization (top) Sector Subsector Address range 174 - AE0000 AEFFFF 173 - AD0000 ADFFFF 172 - AC0000 ACFFFF 171 - AB0000 ABFFFF 170 - AA0000 AAFFFF 169 - A90000 A9FFFF 168 - A80000 A8FFFF 167 - A70000 A7FFFF 166 - A60000 A6FFFF 165 - A50000 A5FFFF 164 - A40000 A4FFFF 163 - A30000 A3FFFF 162 - A20000 A2FFFF 161 - A10000 A1FFFF 160 - A00000 A0FFFF 159 - 9F0000 9FFFFF 158 - 9E0000 9EFFFF 157 - 9D0000 9DFFFF 156 - 9C0000 9CFFFF 155 - 9B0000 9BFFFF 154 - 9A0000 9AFFFF 153 - 990000 99FFFF 152 - 980000 98FFFF 151 - 970000 97FFFF 150 - 960000 96FFFF 149 - 950000 95FFFF 148 - 940000 94FFFF 147 - 930000 93FFFF 146 - 920000 92FFFF 145 - 910000 91FFFF 144 - 900000 90FFFF 143 - 8F0000 8FFFFF 142 - 8E0000 8EFFFF 141 - 8D0000 8DFFFF 140 - 8C0000 8CFFFF 71/185 Memory organization N25Q128 - 1.8 V Table 14. Memory organization (top) Sector 72/185 Subsector Address range 139 - 8B0000 8BFFFF 138 - 8A0000 8AFFFF 137 - 890000 89FFFF 136 - 880000 88FFFF 135 - 870000 87FFFF 134 - 860000 86FFFF 133 - 850000 85FFFF 132 - 840000 84FFFF 131 - 830000 83FFFF 130 - 820000 82FFFF 129 - 810000 81FFFF 128 - 800000 80FFFF 127 - 7F0000 7FFFFF 126 - 7E0000 7EFFFF 125 - 7D0000 7DFFFF 124 - 7C0000 7CFFFF 123 - 7B0000 7BFFFF 122 - 7A0000 7AFFFF 121 - 790000 79FFFF 120 - 780000 78FFFF 119 - 770000 77FFFF 118 - 760000 76FFFF 117 - 750000 75FFFF 116 - 740000 74FFFF 115 - 730000 73FFFF 114 - 720000 72FFFF 113 - 710000 71FFFF 112 - 700000 70FFFF 111 - 6F0000 6FFFFF 110 - 6E0000 6EFFFF 109 - 6D0000 6DFFFF 108 - 6C0000 6CFFFF 107 - 6B0000 6BFFFF 106 - 6A0000 6AFFFF 105 - 690000 69FFFF N25Q128 - 1.8 V Memory organization Table 14. Memory organization (top) Sector Subsector Address range 104 - 680000 68FFFF 103 - 670000 67FFFF 102 - 660000 66FFFF 101 - 650000 65FFFF 100 - 640000 64FFFF 99 - 630000 63FFFF 98 - 620000 62FFFF 97 - 610000 61FFFF 96 - 600000 60FFFF 95 - 5F0000 5FFFFF 94 - 5E0000 5EFFFF 93 - 5D0000 5DFFFF 92 - 5C0000 5CFFFF 91 - 5B0000 5BFFFF 90 - 5A0000 5AFFFF 89 - 590000 59FFFF 88 - 580000 58FFFF 87 - 570000 57FFFF 86 - 560000 56FFFF 85 - 550000 55FFFF 84 - 540000 54FFFF 83 - 530000 53FFFF 82 - 520000 52FFFF 81 - 510000 51FFFF 80 - 500000 50FFFF 79 - 4F0000 4FFFFF 78 - 4E0000 4EFFFF 77 - 4D0000 4DFFFF 76 - 4C0000 4CFFFF 75 - 4B0000 4BFFFF 74 - 4A0000 4AFFFF 73 - 490000 49FFFF 72 - 480000 48FFFF 71 - 470000 47FFFF 70 - 460000 46FFFF 73/185 Memory organization N25Q128 - 1.8 V Table 14. Memory organization (top) Sector 74/185 Subsector Address range 69 - 450000 45FFFF 68 - 440000 44FFFF 67 - 430000 43FFFF 66 - 420000 42FFFF 65 - 410000 41FFFF 64 - 400000 40FFFF 63 - 3F0000 3FFFFF 62 - 3E0000 3EFFFF 61 - 3D0000 3DFFFF 60 - 3C0000 3CFFFF 59 - 3B0000 3BFFFF 58 - 3A0000 3AFFFF 57 - 390000 39FFFF 56 - 380000 38FFFF 55 - 370000 37FFFF 54 - 360000 36FFFF 53 - 350000 35FFFF 52 - 340000 34FFFF 51 - 330000 33FFFF 50 - 320000 32FFFF 49 - 310000 31FFFF 48 - 300000 30FFFF 47 - 2F0000 2FFFFF 46 - 2E0000 2EFFFF 45 - 2D0000 2DFFFF 44 - 2C0000 2CFFFF 43 - 2B0000 2BFFFF 42 - 2A0000 2AFFFF 41 - 290000 29FFFF 40 - 280000 28FFFF 39 - 270000 27FFFF 38 - 260000 26FFFF 37 - 250000 25FFFF 36 - 240000 24FFFF 35 - 230000 23FFFF N25Q128 - 1.8 V Memory organization Table 14. Memory organization (top) Sector Subsector Address range 34 - 220000 22FFFF 33 - 210000 21FFFF 32 - 200000 20FFFF 31 - 1F0000 1FFFFF 30 - 1E0000 1EFFFF 29 - 1D0000 1DFFFF 28 - 1C0000 1CFFFF 27 - 1B0000 1BFFFF 26 - 1A0000 1AFFFF 25 - 190000 19FFFF 24 - 180000 18FFFF 23 - 170000 17FFFF 22 - 160000 16FFFF 21 - 150000 15FFFF 20 - 140000 14FFFF 19 - 130000 13FFFF 18 - 120000 12FFFF 17 - 110000 11FFFF 16 - 100000 10FFFF 15 - F0000 FFFFF 14 - E0000 EFFFF 13 - D0000 DFFFF 12 - C0000 CFFFF 11 - B0000 BFFFF 10 - A0000 AFFFF 9 - 90000 9FFFF 8 - 80000 8FFFF 7 - 70000 7FFFF 6 - 60000 6FFFF 5 - 50000 5FFFF 4 - 40000 4FFFF 3 - 30000 3FFFF 2 - 20000 2FFFF 1 - 10000 1FFFF 0 - 0 FFFF 75/185 Instructions 9 N25Q128 - 1.8 V Instructions The device can work in three different protocols: Extended SPI, DIO-SPI and QIO-SPI. Each protocol has a dedicated instruction set, and each instruction set features the same functionality: Read, program and erase the memory and the 64 byte OTP area, Suspend and resume the program or erase operations, Read and modify all the registers and to read the device ID: please note that in this case there is a small functionality difference among the single and the multiple I/O read ID instructions. See Section 9.2.1: Multiple I/O Read Identification protocol and Section 9.3.1: Multiple I/O Read Identification (MIORDID). The application can choose in every time of the device life which protocol to use by setting the dedicated bits either in the Non Volatile Configuration Register or the Volatile Enhanced Configuration Register. Note: In multiple SPI protocols, all instructions, addresses, and data are parallel on two lines (DIOSPI protocol) or four lines (QIO-SPI protocol). All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data input(s) is (are) sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data input(s), each bit being latched on the rising edges of Serial Clock (C). Instruction code is shifted into the device just on DQ0 in Extended SPI protocol, on DQ0 and DQ1 in DIO-SPI protocol and on DQ0, DQ1, DQ2, and DQ3 in QIO-SPI protocol. In standard mode every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In XIP modes only read operation and exit XIP mode can be performed, and to read the memory content no instructions code are needed: the device directly receives addresses and after a configurable number of dummy clock cycle it outputs the required data. 9.1 Extended SPI Instructions In Extended SPI protocol instruction set the instruction code is always shifted into the device just on DQ0 pin, while depending on the instruction addresses and input/output data can run on single, two or four wires. In the case of a Read Instructions Data Bytes (READ), Read Data Bytes at Higher Speed (FAST_READ), Dual Output Fast Read (DOFR), Dual Input/Output Fast Read (DIOFR), Quad Output Fast Read (QOFR), Quad Input/Output Fast Read (QIOFR), Read OTP (ROTP), Read Lock Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR), Read Volatile Enhanced Configuration Register (RDVECR) and Read Identification (RDID) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. 76/185 N25Q128 - 1.8 V Instructions In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program (DIFP), Dual Input Extended Fast Program (DIEFP), Quad Input Fast Program (QIFP), Quad Input Extended Fast Program (QIEFP), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Clear Flag Status Register (CLFSR), Write to Lock Register (WRLR), Write Configuration Register (WRVCR), Write Enhanced Configuration Register (WRVECR), Write NV Configuration Register (WRNVCR), Write Enable (WREN) or Write Disable (WRDI) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array are ignored during: – Write Status Register cycle – Write Non Volatile Configuration Register – Program cycle – Erase cycle The following continue unaffected, with one exception: – Internal Write Status Register cycle, – Write Non Volatile Configuration Register, – Program cycle, – Erase cycle The only exception is the Program/Erase Suspend instruction (PES), that can be used to pause all the program and the erase cycles except for: – Program OTP (POTP), – Bulk Erase, – Write Non Volatile Configuration Register. The suspended program or erase cycle can be resumed by the Program/Erase Resume instruction (PER). During the program/erase cycles, the polling instructions (both on the Status register and on the Flag Status register) are also accepted to allow the application to check the end of the internal modify cycles. Note: These polling instructions don't affect the internal cycles performing. 77/185 Instructions Table 15. N25Q128 - 1.8 V Instruction set: extended SPI protocol (page 1 of 2) Instruction Description One-byte Instruction Code (BIN) One-byte Dummy Instruction Address clock Code (HEX) bytes cycle RDID Read Identification 1001 111x 9Eh / 9Fh 0 0 READ Read Data Bytes 0000 0011 03h 3 0 Data bytes 1 to 20 1 to ∞ (1) 1 to ∞ FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 8 DOFR Dual Output Fast Read 0011 1011 3Bh 3 8 (1) 1 to ∞ DIOFR Dual Input/Output Fast Read 1011 1011 BB 3 8 (1) 1 to ∞ 3 (1) 1 to ∞ QOFR Quad Output Fast Read 0110 1011 6Bh 8 (1 1 to ∞ QIOFR Quad Input/Output Fast Read 1110 1011 EBh 3 10 ROTP Read OTP (Read of OTP area) 0100 1011 4Bh 3 8 (1) 1 to 65 WREN Write Enable 0000 0110 06h 0 0 0 WRDI Write Disable 0000 0100 04h 0 0 0 PP Page Program 0000 0010 02h 3 0 1 to 256 DIFP Dual Input Fast Program 1010 0010 A2h 3 0 1 to 256 DIEFP Dual Input Extended Fast Program 1101 0010 D2h 3 0 1 to 256 QIFP Quad Input Fast Program 0011 0010 32h 3 0 1 to 256 QIEFP Quad Input Extended Fast Program 0001 0010 12h 3 0 1 to 256 POTP Program OTP (Program of OTP area) 0100 0010 42h 3 0 1 to 65 SSE (2) SubSector Erase 0010 0000 20h 3 0 0 SE Sector Erase 1101 1000 D8h 3 0 0 BE Bulk Erase 1100 0111 C7h 0 0 0 PER Program/Erase Resume 0111 1010 7Ah 0 0 0 PES Program/Erase Suspend 0111 0101 75h 0 0 0 RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞ WRSR Write Status Register 0000 0001 01h 0 0 1 RDLR Read Lock Register 1110 1000 E8h 3 0 1 to ∞ WRLR Write to Lock Register 1110 0101 E5h 3 0 1 RFSR Read Flag Status Register 0111 0000 70h 0 0 1 to ∞ CLFSR Clear Flag Status Register 0101 0000 50h 0 0 0 RDNVCR Read NV Configuration Register 1011 0101 B5h 0 0 2 WRNVCR Write NV Configuration Register 1011 0001 B1h 0 0 2 RDVCR Read Volatile Configuration Register 1000 0101 85h 0 0 1 to ∞ WRVCR Write Volatile Configuration Register 1000 0001 81h 0 0 1 78/185 N25Q128 - 1.8 V Table 15. Instructions Instruction set: extended SPI protocol (page 2 of 2) Instruction Description One-byte Instruction Code (BIN) One-byte Dummy Instruction Address clock Code (HEX) bytes cycle Data bytes RDVECR Read Volatile Enhanced Configuration Register 0110 0101 65h 0 0 1 to ∞ WRVECR Write Volatile Enhanced Configuration Register 0110 0001 61h 0 0 1 DP Deep Power-down 1011 1001 B9h 0 0 0 RDP Release from Deep Power-down 1010 1011 ABh 0 0 0 1) The Number of dummy clock cycles is configurable by user 2) Subsector erase instruction is only available in Bottom or Top parts 9.1.1 Read Identification (RDID) The Read Identification (RDID) instruction allows to read the device identification data: – Manufacturer identification (1 byte) – Device identification (2 bytes) – A Unique ID code (UID) (17 bytes, of which 14 factory programmed upon customer request). The manufacturer identification is assigned by JEDEC, and has the value 20h. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (BBh), and the memory capacity of the device in the second byte (18h). The UID is composed by 17 read only bytes, containing the length of the following data in the first byte (set to 10h), 2 bytes of Extended Device ID (EDID) to identify the specific device configuration (Top, Bottom or uniform architecture, Hold or Reset functionality), and 14 bytes of the optional Customized Factory Data (CFD) content. The CFD bytes can be factory programmed with customers data upon their demand. If the customers do not make requests, the devices are shipped with all the CFD bytes programmed to zero (00h). Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in. After this, the 24-bit device identification, stored in the memory, the 17 bytes of UID content will be shifted out on Serial Data output (DQ1). Each bit is shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 10. The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. 79/185 Instructions Table 16. N25Q128 - 1.8 V Read Identification data-out sequence Manufacturer Identification Device identification 20h Table 17. Bit 7 UID Memory type Memory capacity EDID+CFD length EDID CFD BBh 18h 10h 2 bytes 14 bytes Extended Device ID table (first byte) Bit 6 Bit 5 Bit 4 Reserved Reserved Reserved VCR XIP bit setting: 0 = required, 1 = not required Bit 3 Bit 2 Hold/Reset function: 0 = HOLD, 1 = Reset Bit 1 Addressing: 0 = by Byte, Bit 0 Architecture: 00 = Uniform, 01 = Bottom, 11 = Top Figure 10. Read identification instruction and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 C Instruction DQ0 Manufacturer identification UID Device identification High Impedance DQ1 15 14 13 MSB MSB 3 2 1 0 MSB AI06809d 9.1.2 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data output (DQ1), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 80/185 N25Q128 - 1.8 V Instructions Figure 11. Read Data Bytes instruction and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction 24-bit address (1) 23 22 21 DQ0 3 2 1 0 MSB Data out 1 High Impedance DQ1 7 6 5 4 3 Data out 2 2 1 0 7 MSB AI13736b 9.1.3 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on Serial Data output (DQ1) at a maximum frequency fC, during the falling edge of Serial Clock (C). The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 81/185 Instructions N25Q128 - 1.8 V Figure 12. Read Data Bytes at Higher Speed instruction and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 C Instruction 24-bit address 23 22 21 DQ0 3 2 1 0 High Impedance DQ1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy cycles DQ0 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 DQ1 7 6 5 4 MSB 3 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB Read_Data_Bytes_Fast_Speed 9.1.4 Dual Output Fast Read (DOFR) The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at Higher Speed (FAST_READ) instruction, except that the data are shifted out on two pins (pin DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one doubles the data transfer bandwidth compared to the Read Data Bytes at Higher Speed (FAST_READ) instruction. The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency Fc, during the falling edge of Serial Clock (C). The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction. When the highest address is reached, the address counter rolls over to 00 0000h, so that the read sequence can be continued indefinitely. 82/185 N25Q128 - 1.8 V Instructions Figure 13. Dual Output Fast Read instruction sequence S Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 Mode 2 Instruction 24-bit address 23 22 21 DQ0 DQ1 28 29 30 31 3 2 1 0 High Impedance S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy cycles DQ0 6 4 2 0 DATA OUT 1 DQ1 7 MSB 5 3 1 6 4 2 0 DATA OUT 2 7 MSB 5 3 1 6 4 2 0 DATA OUT 3 7 MSB 5 3 1 6 4 2 0 DATA OUT n 7 MSB 5 3 1 MSB Dual_Output_Data_Fast_Read 9.1.5 Dual I/O Fast Read The Dual I/O Fast Read (DIOFR) instruction is very similar to the Dual Output Fast Read (DOFR), except that the address bits are shifted in on two pins (pin DQ0 and pin DQ1) instead of only one. 83/185 Instructions N25Q128 - 1.8 V Figure 14. Dual I/O Fast Read instruction sequence S Mode 3 C 1 0 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 8 Mode 0 Instruction DQ0 6 4 2 0 6 4 2 0 6 4 2 0 DQ1 7 5 3 1 7 5 3 1 7 5 3 1 Address Dummy Cycles S 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 C IO switches from Input to Output 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 DQ0 DQ1 Byte 1 Byte 2 Byte 3 Byte 4 Dual_IO_Fast_Read 9.1.6 Quad Output Fast Read The Quad Output Fast Read (QOFR) instruction is very similar to the Dual Output Fast Read (DOFR) instruction, except that the data are shifted out on four pins (pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 (1) instead of only two. Outputting the data on four pins instead of one doubles the data transfer bandwidth compared to the Dual Output Fast Read (DOFR) instruction. The device is first selected by driving Chip Select (S) Low. The instruction code for the Quad Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 (1) at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 15. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out on pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 (1). The whole memory can, therefore, be read with a single Quad Output Fast Read (QOFR) instruction. When the highest address is reached, the address counter rolls over to 00 0000h, so that the read sequence can be continued indefinitely. 84/185 N25Q128 - 1.8 V Note: Instructions Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16: Ordering information. Figure 15. Quad Input/Output Fast Read instruction sequence S Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mode 0 Instruction DQ2 IO switches from Input to Output Address 0 DQ0 DQ1 21 22 23 24 25 26 27 1 2 3 4 5 6 7 4 0 4 0 4 5 1 5 1 5 6 2 6 2 6 7 3 7 3 7 Don’t Care Don’t Care DQ3 ‘1’ A23-16 A15-8 A7-0 Dummy (ex.: 10) Byte 1 Byte 2 Quad_Output_Fast_Read 9.1.7 Quad I/O Fast Read The Quad I/O Fast Read (QIOFR) instruction is very similar to the Quad Output Fast Read (QOFR), except that the address bits are shifted in on four pins (pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 (1)) instead of only one. Note: Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16: Ordering information. 85/185 Instructions N25Q128 - 1.8 V Figure 16. Quad Input/ Output Fast Read instruction sequence S Mode 3 C 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 23 24 25 26 27 Mode 0 IO switches from Input to Output Instruction DQ0 DQ1 DQ2 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 Don’t Care Don’t Care DQ3 ‘1’ A23-16 A15-8 A7-0 Dummy (ex.: 10) Byte 1 Byte 2 Quad_IO_Fast_Read 9.1.8 Read OTP (ROTP) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each bit is latched in on the rising edge of Serial Clock (C). Then the memory contents at that address are shifted out on Serial Data output (DQ1). Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 17. The address is automatically incremented to the next higher address after each byte of data is shifted out. There is no rollover mechanism with the Read OTP (ROTP) instruction. This means that the Read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read. All other bytes outside the OTP area are “Don’t Care.” The Read OTP (ROTP) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read OTP (ROTP) instruction issued while an Erase, Program or Write cycle is in progress, is rejected without having any effect on the cycle that is in progress. 86/185 N25Q128 - 1.8 V Instructions Figure 17. Read OTP instruction and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 C Instruction 24-bit address 23 22 21 DQ0 3 2 1 0 High Impedance DQ1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy cycles DQ0 7 6 5 4 3 2 1 0 DATA OUT n DATA OUT 1 7 DQ1 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB Read_OTP 9.1.9 Write Enable (WREN) The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Program, Erase or Write instructions: Page Program (PP), Dual Input Fast Program (DIFP), Dual Input Extended Fast Program (DIEFP), Quad Input Fast Program (QIFP), Quad Input Extended Fast Program (QIEFP), Program OTP (POTP), Write to Lock Register (WRLR), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Configuration Register (WRCR), Write Enhanced Configuration Register (WRECR) and Write NV Configuration Register (WRNVCR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. When the Fast POR feature is selected (Non Volatile Configuration Register bit 5) after the first Write Enable instruction, the device enters in a latency time (~500 us), necessary to internally complete the POR sequence with the modify algorithms. (See Section 11.1: Fast POR.) During the POR latency time all the instructions are ignored with the exception of the 87/185 Instructions N25Q128 - 1.8 V polling instructions (to check if the internal cycle is finished by mean of the WIP bit of the Status Register or of the Program/Erase controller bit of the Flag Status register): to verify if the POR sequence is completed is possible to check the WIP bit in the Status Register or the Program/Erase Controller bit in the Flag Status Register, please note that the Program/Erase Controller bit in the Flag status register has the reverse logical polarity with respect to the Status Register WIP bit. At the end of the POR sequence the WEL bit is low, so the next modify instruction can be accepted. Figure 18. Write Enable instruction sequence S 0 1 2 3 4 5 6 7 C Instruction DQ0 High Impedance DQ1 AI13731 9.1.10 Write Disable (WRDI) The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. 88/185 N25Q128 - 1.8 V Instructions The Write Enable Latch (WEL) bit is reset under the following conditions: Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Write lo Lock Register (WRLR) instruction completion Write Non Volatile Configuration Register (WRNVCR) instruction completion Write Volatile Configuration Register (WRVCR) instruction completion Write Volatile Enhanced Configuration Register (WRVECR) instruction completion Page Program (PP) instruction completion Dual Input Fast Program (DIFP) instruction completion Dual Input Extended Fast Program (DIEFP) instruction completion Quad Input Fast Program (QIFP) instruction completion Quad Input Extended Fast Program (QIEFP) instruction completion Program OTP (POTP) instruction completion Subsector Erase (SSE) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Figure 19. Write Disable instruction sequence S 0 1 2 3 4 5 6 7 C Instruction DQ0 High Impedance DQ1 AI13732 9.1.11 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data input (DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the 89/185 Instructions N25Q128 - 1.8 V same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes. See Table 33.: AC Characteristics. Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is top) is initiated. While the Page Program cycle is in progress, the Status Register and the Flag Status Register may be read to check if the internal modify cycle is finished. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP3,BP2, BP1, BP0 and TB) bits is not executed. Page Program cycle can be paused by mean of Program/Erase Suspend (PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction. 90/185 N25Q128 - 1.8 V Instructions Figure 20. Page Program instruction sequence S 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 39 9 10 C Instruction 24-bit address (1) 23 22 21 DQ0 3 2 Data byte 1 1 0 7 6 5 4 3 2 1 0 MSB MSB 2078 2079 2077 2076 2075 2074 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 S 1 0 C Data byte 2 DQ0 7 6 MSB 5 4 3 2 Data byte 3 1 0 7 6 5 4 3 MSB 2 Data byte 256 1 0 7 6 5 4 3 2 MSB AI13739b 9.1.12 Dual Input Fast Program (DIFP) The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP) instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of only one. Inputting the data on two pins instead of one doubles the data transfer bandwidth compared to the Page Program (PP) instruction. The Dual Input Fast Program (DIFP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data input (DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes in the same page. For optimized timings, it is recommended to use the Dual Input Fast Program (DIFP) instruction to program all consecutive targeted bytes in a single sequence rather to using 91/185 Instructions N25Q128 - 1.8 V several Dual Input Fast Program (DIFP) sequences each containing only a few bytes. See Table 33.: AC Characteristics. Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Dual Input Fast Program (DIFP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is top) is initiated. While the Dual Input Fast Program (DIFP) cycle is in progress, the Status Register and the Flag Status Register may be read to check if the internal modify cycle is finished. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Dual Input Fast Program (DIFP) instruction applied to a page that is protected by the Block Protect (BP3, BP2, BP1, BP0 and TB) bits is not executed. Dual Input Fast Program cycle can be paused by mean of Program/Erase Suspend (PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction. Figure 21. Dual Input Fast Program instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 C Instruction 24-bit address 23 22 21 DQ0 3 2 1 0 High Impedance DQ1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C DQ0 6 4 2 0 DATA IN 1 DQ1 7 MSB 5 3 6 4 2 0 DATA IN 2 1 7 MSB 5 3 6 4 2 0 6 DATA IN 3 1 7 MSB 5 3 4 2 0 6 DATA IN 4 1 7 MSB 5 3 4 2 0 DATA IN 5 1 7 MSB 5 3 6 4 2 0 DATA IN 256 1 7 5 3 1 MSB AI14229 92/185 N25Q128 - 1.8 V 9.1.13 Instructions Dual Input Extended Fast Program The Dual Input Extended Fast Program (DIEFP) instruction is very similar to the Dual Input Fast Program (DIFP), except that the address bits are shifted in on two pins (pin DQ0 and pin DQ1) instead of only one. Figure 22. Dual Input Extended Fast Program instruction sequence S Mode 3 C 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mode 0 Instruction DQ0 6 4 2 0 6 4 2 0 6 4 2 0 DQ1 7 5 3 1 7 5 3 1 7 5 3 1 Address Dummy Cycles S 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 C DQ0 6 4 2 0 6 Data In 1 DQ1 7 5 3 MSB 4 2 0 6 Data In 2 1 7 5 3 1 MSB 4 2 0 6 5 3 MSB 1 2 0 6 7 5 3 MSB 1 4 2 0 Data In 256 Data In 4 Data In 3 7 4 7 5 3 1 MSB Dual_Input_Extended_Fast_Program 9.1.14 Quad Input Fast Program The Quad Input Fast Program (QIFP) instruction is very similar to the Dual Input Fast Program (DIFP) instruction, except that the data are entered on four pins (pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/ (DQ3) instead of only two. Inputting the data on four pins instead of two doubles the data transfer bandwidth compared to the Dual Input Fast Program (DIFP) instruction. The Quad Input Fast Program (QIFP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data input (DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. 93/185 Instructions N25Q128 - 1.8 V If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes in the same page. For optimized timings, it is recommended to use the Quad Input Fast Program (QIFP) instruction to program all consecutive targeted bytes in a single sequence rather to using several Quad Input Fast Program (QIFP) sequences each containing only a few bytes See Table 33.: AC Characteristics. Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Quad Input Fast Program (QIFP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Quad Input Fast Program (QIFP) cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Quad Input Fast Program (QIFP) instruction applied to a page that is protected by the Block Protect (BP3, BP2, BP1, BP0 and TB) bits is not executed. A Quad Input Fast Program cycle can be paused by mean of Program/Erase Suspend (PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction. Figure 23. Quad Input Fast Program instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 C Instruction 1 23 22 21 DQ0 3 2 1 0 4 Data In Data In Data In 24-bit address 2 3 4 0 4 0 4 0 4 5 1 5 1 5 1 6 2 6 2 6 7 3 7 3 7 5 6 0 4 0 4 0 5 1 5 1 5 1 2 6 2 6 2 6 2 3 7 3 7 3 7 3 Don’t Care DQ1 Don’t Care DQ2 Don’t Care DQ3 ‘1’ MSB MSB MSB MSB MSB MSB Quad_Input_Fast_Program 9.1.15 Quad Input Extended Fast Program The Quad Input Extended Fast Program (QIEFP) instruction is very similar to the Quad Input Extended Fast Program (QIFP), except that the address bits are shifted in on four pins (pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3) instead of only one. 94/185 N25Q128 - 1.8 V Instructions Figure 24. Quad Input Extended Fast Program instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 C Instruction Data In 24-bit address 2 1 DQ0 Data In Data In 3 5 4 7 6 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Don’t Care DQ1 Don’t Care DQ2 DQ3 ‘1’ MSB MSB MSB MSB MSB MSB MSB Quad_Input_Extended_Fast_Program 9.1.16 Program OTP instruction (POTP) The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) bit. The Program OTP instruction is entered by driving Chip Select (S) Low, followed by the instruction opcode, three address bytes and at least one data byte on Serial Data input (DQ0). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Program OTP instruction is not executed. There is no rollover mechanism with the Program OTP (POTP) instruction. This means that the Program OTP (POTP) instruction must be sent with a maximum of 65 bytes to program, once all 65 bytes have been latched in, any following byte will be discarded. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Program OTP cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program OTP cycle, and it is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. To lock the OTP memory: Bit 0 of the OTP control byte, that is byte 64, is used to permanently lock the OTP memory array. When bit 0 of byte 64 = '1', the 64 bytes of the OTP memory array can be programmed. When bit 0 of byte 64 = '0', the 64 bytes of the OTP memory array are read-only and cannot be programmed anymore. 95/185 Instructions N25Q128 - 1.8 V Once a bit of the OTP memory has been programmed to '0', it can no longer be set to '1'. Therefore, as soon as bit 0 of byte 64 (control byte) is set to '0', the 64 bytes of the OTP memory array become read-only in a permanent way. Any Program OTP (POTP) instruction issued while an Erase, Program or Write cycle is in progress is rejected without having any effect on the cycle that is in progress. Figure 25. Program OTP instruction sequence S 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 39 9 10 C Instruction 24-bit address 23 22 21 DQ0 3 2 Data byte 1 1 0 7 6 5 4 3 2 0 1 MSB MSB S 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data byte 2 DQ0 7 6 MSB 5 4 3 2 Data byte 3 1 0 7 MSB 6 5 4 3 2 Data byte n 1 0 7 6 5 4 3 2 1 0 MSB AI13575 96/185 N25Q128 - 1.8 V Instructions Figure 26. How to permanently lock the OTP bytes 64 data bytes OTP control byte Byte Byte Byte 0 1 2 Byte Byte 63 64 X X X X X X X bit 0 When bit 0 = 0 the 64 OTP bytes become read only Bit 1 to bit 7 are not programmable ai13587 9.1.17 Subsector Erase (SSE) For devices with bottom or top architecture, at the bottom (or top) of the addressable area there are 8 boot sectors, each one having 16 4Kbytes subsectors. The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Subsector Erase (SSE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data input (DQ0). Any address inside the subsector is a valid address for the Subsector Erase (SSE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Subsector Erase (SSE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Subsector Erase cycle (whose duration is tSSE) is initiated. While the Subsector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Subsector Erase (SSE) instruction issued to a sector that is hardware or software protected, is not executed. Any Subsector Erase (SSE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Any Subsector Erase (SSE) instruction in devices with uniform architecture (meaning no boot sectors with subsectors) is rejected without having any effects on the device. 97/185 Instructions N25Q128 - 1.8 V Figure 27. Subsector Erase instruction sequence S 0 1 2 3 4 5 6 7 8 9 29 30 31 C Instruction DQ0 24 Bit Address 23 22 2 1 0 MSB Subsector_Erase 9.1.18 Sector Erase (SE) The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data input (DQ0). Any address inside the sector is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP3, BP2, BP1, BP0 and TB) bits is not executed. A Sector Erase cycle can be paused by mean of Program/Erase Suspend (PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction. 98/185 N25Q128 - 1.8 V Instructions Figure 28. Sector Erase instruction sequence S 0 1 2 3 4 5 6 7 8 9 29 30 31 C Instruction 24 Bit Address 23 22 DQ0 2 1 0 MSB Sector_Erase 9.1.19 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the entire duration of the sequence. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if all Block Protect (BP3, BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 29. Bulk Erase instruction sequence S 0 1 2 3 4 5 6 7 C Instruction DQ0 AI13743 99/185 Instructions 9.1.20 N25Q128 - 1.8 V Program/Erase Suspend The Program/Erase Suspend instruction allows the controller to interrupt a Program or an Erase instruction, in particular: Sector Erase, Subsector Erase, Page Program, Dual Input Page Program, Dual Input Extended Page program, Quad Input Page Program and Quad Input Extended Page program can be suspended and erased. Note: Bulk Erase, Write Non Volatile Configuration register and Program OTP cannot be suspended. After a Program/Erase Suspend instruction the bit 2 of the Flag Status register is immediately set to 1 and, after a latency time, both the WIP bit of the Status Register and the Program/Erase controller bit (Not WIP) of the Flag Status Register are cleared (to 0 and to 1 respectively). The Suspended state is reset if a power-off is performed or after resume. After a sector erase instruction has been suspended, another erase instruction is not allowed; however, it is possible to perform program and reading instructions on all the sectors except the one whose erase cycle is suspended. Any read instruction issued on this sector outputs Don't Care data. After a subsector erase instruction has been suspended, neither an erase instruction or a program instruction is allowed; only a read instruction is allowed on all sectors except the one containing the subsector whose erase cycle is suspended. Any read instruction issued on this sector outputs Don't Care data. After a program instruction has been suspended, neither a program instruction or an erase instructions is allowed; however, it is possible to perform a read instruction on all pages except the one whose program cycle is suspended. Any read instruction issued on this page outputs Don't Care data. It's possible to nest a suspend instruction inside another suspended one just once, meaning that it's possible for example to send to the device an erase instruction, then suspend it, then send a program instruction and in the end suspend it as well. In this case the next Program/Erase Resume Instruction resumes the more recent suspended modify cycles, another Program/Erase Resume Instruction is need to resume also the former one. Table 18. Suspend Parameters Parameter Condition Typ Max Unit Note Erase to Suspend Sector Erase or Erase Resume to Erase Suspend 40 µs Timing not internally controlled Program to Suspend Program Resume to Program Suspend 5 µs Timing not internally controlled SSErase to Suspend Sub Sector Erase or Sub Sector Erase Resume to Erase Suspend 40 µs Timing not internally controlled Suspend Latency Program 7 µs Any Read instruction accepted Sub Sector Erase 15 µs Any Read instruction accepted Erase 15 µs Any instruction accepted but DP, SE, SSE, BE, WRSR, WRNVCR, POTP 100/185 N25Q128 - 1.8 V Table 19. Instructions Operations Allowed / Disallowed During Device States Device States and Sector (Same/Other) in Which Operation is Allowed/Disallowed (Yes/No) Standby State Program State Operation Sector Erase State (SE/SSE) Subsector Erase Suspended State Program Suspended State Erase Suspended State Sector Sector Sector Sector Sector Same Other Same Other Same Other Same Other Same Other Same Other Yes Yes No No No No Yes(1) Yes Yes Yes Yes(1) Yes Array Program: PP / DIFP / Yes QWIFP / DIEFP / QIEFP Yes No No No No No No No No No Yes Sector Erase Yes Yes No No No No No No No No No No Sub-Sector Erase Yes Yes No No No No No No No No No No All Reads except RDSR / RDFSR WRLR / POTP / BE / WRSR / Yes WRNVCR No No No No No WVCR / WVECR No No Yes Yes Yes RDSR / RDFSR Yes Yes Yes Yes Yes Yes Program / No Erase Suspend Yes Yes No No No Yes 1. The Read operation is accepted but the data output is not guaranetted until the program or erase has completed. Note: The device can be in only one state at a time, such as Standby, Program, Erase, and so on. Device states are shown in Table 19.: Operations Allowed / Disallowed During Device States. 9.1.21 Program/Erase Resume After a Program/Erase suspend instruction, a Program/Erase Resume instruction is required to continue performing the suspended Program or Erase sequence. Program/Erase Resume instruction is ignored if the device is not in a Program/Erase Suspended status. The WIP bit of the Status Register and Program/Erase controller bit (Not WIP) of the Flag Status Register both switch to the busy state (1 and 0 respectively) after Program/Erase Resume instruction until the Program or Erase sequence is completed. In this case the next Program/Erase Resume Instruction resumes the more recent suspended modify cycles, another Program/Erase Resume Instruction is need to resume also the former one. 101/185 Instructions 9.1.22 N25Q128 - 1.8 V Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit (or the Program/Erase controller bit of the Flag Status Register) before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown here. Figure 30. Read Status Register instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction DQ0 Status register out Status register out High Impedance DQ1 7 6 5 MSB 4 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB AI13734 9.1.23 Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded and executed, the device sets the write enable latch (WEL). The write status register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on serial data input (DQ0). The write status register (WRSR) instruction has no effect on b1 and b0 of the status register. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the write status register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed write status register cycle (whose duration is tow) is initiated. While the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. When the cycle is completed, the write enable latch (WEL) is reset. The write status register (WRSR) instruction allows the user to change the values of the block protect (BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3. The write status register (WRSR) instruction also allows the user to set and reset the status register write disable (SRWD) bit in accordance with the Write Protect (W/VPP) signal. The status register write disable (SRWD) bit and Write Protect (W/VPP) signal allow the device to be put in the hardware protected mode (HPM). The write 102/185 N25Q128 - 1.8 V Instructions status register (WRSR) instruction is not executed once the hardware protected mode (HPM) is entered. Figure 31. Write Status Register instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction Status register in 7 DQ0 High Impedance 6 5 4 3 2 1 0 MSB DQ1 AI13735 The protection features of the device are summarized in Table 8. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W/VPP) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to '1', two cases need to be considered, depending on the state of Write Protect (W/VPP): If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction (attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected mode (HPM) can be entered in either of the following ways: setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W/VPP) Low driving Write Protect (W/VPP) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write Protect (W/VPP) High. If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can never be activated, and only the Software Protected mode (SPM), using the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, can be used. 103/185 Instructions Table 20. W / VPP Signal Protection modes SRWD bit 1 0 0 0 1 1 0 N25Q128 - 1.8 V 1 Mode Write protection of the status register Memory content Protected area (1) Unprotected area (1) Software protected (SPM) Status register is writeable, if the WREN instruction has set the WEL bit. The values in the SRWD, TB, BP3, BP2, BP1, and BP0 bits can be changed. Protected against PP, DIFP, DIEFP, QIFP, QIEFP, SSE, SE and BE instructions. Ready to accept PP, DIFP, DIEFP, QIFP, QIEFP, SSE, and SE instructions. Hardware protected (HPM) Status Register is hardware write protected. The values in the SRWD, TB, BP3, BP2, BP1 and BP0 bits cannot be changed PP, DIFP, DIEFP, QIFP, QIEFP, SSE, SE and BE instructions. PP, DIFP, DIEFP, QIFP, QIEFP, SSE, and SE instructions. 1. As defined by the values in the Block Protect (TB, BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 3: Status register format. 9.1.24 Read Lock Register (RDLR) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any location inside the concerned sector. Each address bit is latched-in during the rising edge of Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output (DQ1), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at any time during data output. Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 32. Read Lock Register instruction and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction 24-bit address 23 22 21 DQ0 3 2 1 0 MSB Lock register out High Impedance DQ1 7 6 5 4 3 2 1 0 MSB AI13738 104/185 N25Q128 - 1.8 V Table 21. Bit Instructions Lock Register out(1) Bit name Value Function b7-b2 b1 b0 Reserved Sector Lock Down ‘1’ The Write Lock and Lock Down bits cannot be changed. Once a ‘1’ is written to the Lock Down bit it cannot be cleared to ‘0’, except by a power-up. ‘0’ The Write Lock and Lock Down bits can be changed by writing new values to them. ‘1’ Write, Program and Erase operations in this sector will not be executed. The memory contents will not be changed. ‘0’ Write, Program and Erase operations in this sector are executed and will modify the sector contents. Sector Write Lock 1. Values of (b1, b0) after power-up are defined in Section 7: Protection modes. 9.1.25 Write to Lock Register (WRLR) The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes (pointing to any address in the targeted sector and one data byte on Serial Data input (DQ0). The instruction sequence is shown in Figure 22. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not executed. Lock Register bits are volatile, and therefore do not require time to be written. When the Write to Lock Register (WRLR) instruction has been successfully executed, the Write Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value. Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 33. Write to Lock Register instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction DQ0 Lock register in 24-bit address 23 22 21 MSB 3 2 1 0 7 6 5 4 3 2 1 0 MSB AI13740 105/185 Instructions N25Q128 - 1.8 V Table 22. Lock Register in(1) Sector Bit Value b7-b2 ‘0’ All sectors b1 Sector Lock Down bit value (refer to Table 21) b0 Sector Write Lock bit value (refer to Table 21) 1. Values of (b1, b0) after power-up are defined in Section 7: Protection modes. 9.1.26 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be read. The Status Register may be read at any time, even while a Program, Erase. When one of these cycles is in progress, it is recommended to check the P/E Controller bit (Not WIP) bit before sending a new instruction to the device. It is also possible to read the Flag Register continuously, as shown here. Figure 34. Read Flag Status Register instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction DQ0 Flag Status Register Out Flag Status Register Out High Impedance DQ1 7 6 5 4 MSB 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB Read_Flag_SR 9.1.27 Clear Flag Status Register The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits (Erase Error bit, Program Error bit, VPP Error bit, Protection Error bit). It is not necessary to set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit will be unchanged after this command is executed. 106/185 N25Q128 - 1.8 V Instructions Figure 35. Clear Flag Status Register instruction sequence S 0 1 2 3 4 5 6 7 8 C Instruction DQ0 High Impedance MSB DQ1 Clear_Flag_SR 9.1.28 Read NV Configuration Register The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile Configuration Register to be read. Figure 36. Read NV Configuration Register instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 C Instruction DQ0 NVCR Out NVCR Out High Impedance DQ1 7 6 5 4 3 LS Byte 2 1 0 15 14 13 12 11 10 9 8 MS Byte Read_NVCR 9.1.29 Write NV Configuration Register The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to be written to the Non Volatile Configuration register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded and executed, the device sets the write enable latch (WEL). The Write Non Volatile Configuration register (WRNVCR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data bytes on serial data input (DQ0). Chip Select (S) must be driven High after the 16th bit of the data bytes has been latched in. If not, the Write Non Volatile Configuration register (WRNVCR) instruction is not executed. 107/185 Instructions N25Q128 - 1.8 V As soon as Chip Select (S) is driven High, the self-timed write NV configuration register cycle (whose duration is tnvcr) is initiated. While the Write Non Volatile Configuration register cycle is in progress, it is possible to monitor the end of the process by polling status Register write in progress (WIP) bit or the Flag Status Register Program/Erase Controller bit. The write in progress (WIP) bit is 1 during the self-timed Write Non Volatile Configuration register cycle, and is 0 when it is completed. When the cycle is completed, the write enable latch (WEL) is reset. The Write Non Volatile Configuration register (WRNVCR) instruction allows the user to change the values of all the Non Volatile Configuration Register bits, described in Table 4.: Non-Volatile Configuration Register. The Write Non Volatile Configuration Register impacts the memory behavior only after the next power on sequence. Figure 37. Write NV Configuration Register instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C NVCR In Instruction Byte 7 DQ0 6 5 4 Byte 3 LS Byte 2 1 0 15 14 13 12 11 10 9 8 MS Byte High Impedance DQ1 Write_NVCR 9.1.30 Read Volatile Configuration Register The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile Configuration Register to be read. See Table 6.: Volatile Configuration Register. 108/185 N25Q128 - 1.8 V Instructions Figure 38. Read Volatile Configuration Register instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction DQ0 Volatile Configuration Register Out High Impedance DQ1 7 6 5 4 3 2 MSB 1 Volatile Configuration Register Out 0 7 6 5 4 3 2 1 0 7 MSB Read_VCR 9.1.31 Write Volatile Configuration Register The Write Volatile Configuration register (WRVCR) instruction allows new values to be written to the Volatile Configuration register. Before it can be accepted, a write enable (WREN) instruction must have been executed. After the write enable (WREN) instruction has been decoded and executed, the device sets the write enable latch (WEL). In case of Fast POR (see section 11.1 for further details) the WREN instruction is not required because a WREN instruction gets the device out from the Fast POR state. The Write Volatile Configuration register (WRVCR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on serial data input (DQ0). Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Volatile Configuration register (WRVCR) instruction is not executed. When the new data are latched, the write enable latch (WEL) is reset. The Write Volatile Configuration register (WRVCR) instruction allows the user to change the values of all the Volatile Configuration Register bits, described in Table 6.: Volatile Configuration Register. The Write Volatile Configuration Register impacts the memory behavior right after the instruction is received by the device. 109/185 Instructions N25Q128 - 1.8 V Figure 39. Write Volatile Configuration Register instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction Volatile Configuration Register In 7 DQ0 6 5 4 3 2 1 0 MSB High Impedance DQ1 Write_VCR 9.1.32 Read Volatile Enhanced Configuration Register The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the Volatile Configuration Register to be read. Figure 40. Read Volatile Enhanced Configuration Register instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction DQ0 High Impedance DQ1 Volatile Enhanced Configuration Register Out Volatile Enhanced Configuration Register Out 7 6 5 4 3 2 1 0 7 6 MSB 5 4 3 2 1 0 7 MSB Read_VECR 9.1.33 Write Volatile Enhanced Configuration Register The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new values to be written to the Volatile Enhanced Configuration register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded and executed, the device sets the write enable latch (WEL). In case of Fast POR, the WREN instruction is not required because a WREN instruction gets the device out from the Fast POR state (see Section 11.1: Fast POR). 110/185 N25Q128 - 1.8 V Instructions The Write Volatile Enhanced Configuration register (WRVECR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on serial data input (DQ0). Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Volatile Enhanced Configuration register (WRVECR) instruction is not executed. When the new data are latched, the write enable latch (WEL) is reset. The Write Volatile Enhanced Configuration register (WRVECR) instruction allows the user to change the values of all the Volatile Enhanced Configuration Register bits, described in Table 7.: Volatile Enhanced Configuration Register. The Write Volatile Enhanced Configuration Register impacts the memory behavior right after the instruction is received by the device. Figure 41. Write Volatile Enhanced Configuration Register instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction VECR In 7 DQ0 High Impedance 6 5 4 3 2 1 0 MSB DQ1 Write_VECR 9.1.34 Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as a software protection mechanism, while the device is not in active use, as in this mode, the device ignores all Write, Program and Erase instructions. Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to ICC2, as specified in Table 32). To take the device out of Deep Power-down mode, the Release from Deep Power-down (RDP) instruction must be issued. No other instruction must be issued while the device is in Deep Power-down mode. 111/185 Instructions N25Q128 - 1.8 V The Deep Power-down mode automatically stops at power-down, and the device always powers up in the Standby Power mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 42. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 42. Deep Power-down instruction sequence S 0 1 2 3 4 5 6 7 tDP C Instruction DQ0 Standby mode Deep power-down mode AI13744 9.1.35 Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 43. The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the instruction to be rejected, and not executed. After Chip Select (S) has been driven High, followed by a delay, tRDP, the device is put in the Standby mode. Chip Select (S) must remain High at least until this period is over. The device waits to be selected, so that it can receive, decode and execute instructions. Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 112/185 N25Q128 - 1.8 V Instructions Figure 43. Release from Deep Power-down instruction sequence S 0 1 2 3 4 5 6 7 tRDP C Instruction DQ0 High Impedance DQ1 Deep power-down mode Standby mode AI13745 9.2 DIO-SPI Instructions In DIO-SPI protocol, instructions, addresses and input/Output data always run in parallel on two wires: DQ0 and DQ1. In the case of a Dual Command Fast Read (DCFR), Read OTP (ROTP), Read Lock Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR), Read Volatile Enhanced Configuration Register (RDVECR) and Read Identification (RDID) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Dual Command Page Program (DCPP), Program OTP (POTP), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Program/Erase Suspend (PES), Program/Erase Resume (PER), Write Status Register (WRSR), Clear Flag Status Register (CLFSR), Write to Lock Register (WRLR), Write Configuration Register (WRVCR), Write Enhanced Configuration Register (WRVECR), Write NV Configuration Register (WRNVCR), Write Enable (WREN) or Write Disable (WRDI) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. All attempts to access the memory array during a Write Status Register cycle, a Write Non Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the internal Write Status Register cycle, Write Non Volatile Configuration Register, Program cycle or Erase cycle continues unaffected, the only exception is the Program/Erase Suspend instruction (PES), that can be used to pause all the program and the erase cycles but the Program OTP (POT),, Bulk Erase (BE) and Write Non Volatile Configuration Register. The suspended program or erase cycle can be resumed by mean of the Program/Erase Resume instruction (PER). During the program/erase cycles also the polling instructions (to check if the internal modify cycle is finished by mean of the WIP bit of the Status Register or of the Program/Erase controller bit of the Flag Status register) are also accepted to allow the application checking the end of the internal modify cycles, of course these polling instructions don't affect the internal cycles performing. 113/185 Instructions Table 23. N25Q128 - 1.8 V Instruction set: DIO-SPI protocol Instruction MIORDID Description Multiple I/O read identification One-byte Instruction Code (BIN) 1010 1111 0000 1011 DCFR Dual Command Fast Read One-byte Dummy Instruction Address clock Code bytes cycle (HEX) AFh 0Bh 0 0 Data bytes 1 to 3 (1) 1 to ∞ 3 8 1 to ∞ 0011 1011 3Bh 3 8(1) 1011 1011 BBh 3 8 (1) 1 to ∞ ROTP Read OTP 0100 1011 4Bh 3 8 (1) 1 to 65 WREN Write Enable 0000 0110 06h 0 0 0 WRDI Write Disable 0000 0100 04h 0 0 0 0000 0010 02h 3 0 1 to 256 1010 0010 A2h 3 0 1 to 256 1101 0010 D2h 3 0 1 to 256 DCPP Dual Command Page Program POTP Program OTP 0100 0010 42h 3 0 1 to 65 SSE (2) SubSector Erase 0010 0000 20h 3 0 0 SE Sector Erase 1101 1000 D8h 3 0 0 BE Bulk Erase 1100 0111 C7h 0 0 0 PER Program/Erase Resume 0111 1010 7Ah 0 0 0 PES Program/Erase Suspend 0111 0101 75h 0 0 0 RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞ WRSR Write Status Register 0000 0001 01h 0 0 1 RDLR Read Lock Register 1110 1000 E8h 3 0 1 to ∞ WRLR Write to Lock Register 1110 0101 E5h 3 0 1 RFSR Read Flag Status Register 0111 0000 70h 0 0 1 to ∞ CLFSR Clear Flag Status Register 0101 0000 50h 0 0 0 RDNVCR Read NV Configuration Register 1011 0101 B5h 0 0 2 WRNVCR Write NV Configuration Register 1011 0001 B1h 0 0 2 RDVCR Read Volatile Configuration Register 1000 0101 85h 0 0 1 to ∞ WRVCR Write Volatile Configuration Register 1000 0001 81h 0 0 1 RDVECR Read Volatile Enhanced Configuration Register 0110 0101 65h 0 0 1 to ∞ WRVECR Write Volatile Enhanced Configuration Register 0110 0001 61h 0 0 1 DP Deep Power-down 1011 1001 B9h 0 0 0 RDP Release from Deep Power-down 1010 1011 ABh 0 0 0 114/185 N25Q128 - 1.8 V Instructions 1) The number of Dummy Clock cycles is configurable by the user 2) SSE is only available in devices with Bottom or Top architecture. 9.2.1 Multiple I/O Read Identification protocol The Multiple Input/Output Read Identification (MIORDID) instruction allows to read the device identification data in the DIO-SPI protocol: – Manufacturer identification (1 byte) – Device identification (2 bytes) Unlike the RDID instruction of the Extended SPI protocol, the Multiple Input/Output instruction can not read the Unique ID code (UID) (17 bytes). For further details on the manufacturer and device identification codes please refer to Section 9.1.1: Read Identification (RDID). Any Multiple Input/Output Read Identification (MIORDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in parallel on the 2 pins DQ0 and DQ1. After this, the 24-bit device identification, stored in the memory, will be shifted out on again in parallel on DQ1 and DQ0. Each two bits are shifted out during the falling edge of Serial Clock (C). The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Figure 44. Multiple I/O Read Identification instruction and data-out sequence DIOSPI S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C DEV. code MAN. code AFh SIZE code DQ0 6 4 2 0 6 4 2 0 6 4 2 0 DQ1 7 5 3 1 7 5 3 1 7 5 3 1 Dual_Multi_Read_IO 115/185 Instructions 9.2.2 N25Q128 - 1.8 V Dual Command Fast Read (DCFR) The Dual Command Fast Read (DCFR) instruction allows to read the memory in DIO-SPI protocol, parallelizing the instruction code, the address and the output data on two pins (DQ0 and DQ1). The Dual Command Fast Read (DCFR) instruction can be issued, when the device is set in DIO-SPI mode, by sending to the memory indifferently one of the 3 instructions codes: 0Bh, 3Bh or BBh, the effect is exactly the same. The 3 instruction codes are all accepted to help the application code porting from Extended SPI protocol to DIO-SPI protocol. Apart for the parallelizing on two pins of the instruction code, the Dual Command Fast Read instruction functionality is exactly the same as the Dual I/O Fast Read of the Extended SPI protocol, please refer to Section 9.1.5: Dual I/O Fast Read for further details. Figure 45. Dual Command Fast Read instruction and data-out sequence DIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 C Instruction 24-Bit Address DQ0 22 20 18 16 14 12 10 8 6 4 2 0 DQ1 23 21 19 17 15 13 11 9 7 5 3 1 Data Out n Data Out 1 Dummy cycles 6 4 2 0 7 5 3 1 MSB 6 4 2 0 7 5 3 1 MSB Dual_Command_Fast_Read 9.2.3 Read OTP (ROTP) The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the DIO-SPI protocol. The instruction functionality is exactly the same as the Read OTP instruction of the Extended SPI protocol; the only difference is that in the DIO-SPI protocol instruction code, address and output data are all parallelized on the two pins DQ0 and DQ1. Note: 116/185 The dummy bits can not be parallelized since these clock cycles are requested to perform the internal reading operation. N25Q128 - 1.8 V Instructions Figure 46. Read OTP instruction and data-out sequence DIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 C Instruction 24-Bit Address DQ0 22 20 18 16 14 12 10 8 6 4 2 0 DQ1 23 21 19 17 15 13 11 9 7 5 3 1 Data Out n Data Out 1 Dummy cycles 6 4 2 0 7 5 3 1 MSB 6 4 2 0 7 5 3 1 MSB Dual_Read_OTP 9.2.4 Write Enable (WREN) The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Write Enable (WREN) instruction of the Extended SPI protocol. Figure 47. Write Enable instruction sequence DIO-SPI S 0 1 2 3 4 C Instruction DQ0 DQ1 Dual_Write_Enable 9.2.5 Write Disable (WRDI) The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit. Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Write Disable (WRDI) instruction of the Extended SPI protocol, please refer to Section 9.1.10: Write Disable (WRDI) for further details. 117/185 Instructions N25Q128 - 1.8 V Figure 48. Write Disable instruction sequence DIO-SPI S 1 0 2 3 4 C Instruction DQ0 DQ1 Dual_Write_Disable 9.2.6 Dual Command Page Program (DCPP) The Dual Command Page Program (DCPP) instruction allows to program the memory content in DIO-SPI protocol, parallelizing the instruction code, the address and the input data on two pins (DQ0 and DQ1). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. The Dual Command Page Program (DCPP) instruction can be issued, when the device is set in DIO-SPI mode, by sending to the memory indifferently one of the 3 instructions codes: 02h, A2h or D2h, the effect is exactly the same. The 3 instruction codes are all accepted to help the application code porting from Extended SPI protocol to DIO-SPI protocol. Apart for the parallelizing on two pins of the instruction code, the Dual Command Page Program instruction functionality is exactly the same as the Dual Input Extended Fast Program of the Extended SPI protocol, please refer to Section 9.1.13: Dual Input Extended Fast Program for further details. Figure 49. Dual Command Page Program instruction sequence DSP, 02h S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1037 1039 1036 1038 C Instruction 24-Bit Address Data Byte 1 Data Byte 256 Data Byte 2 DQ0 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 DQ1 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 Dual_Page_Program_02h 118/185 N25Q128 - 1.8 V Instructions Figure 50. Dual Command Page Program instruction sequence DSP, A2h S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1037 1039 1036 1038 C Instruction 24-Bit Address Data Byte 1 Data Byte 256 Data Byte 2 DQ0 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 DQ1 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 Dual_Page_Program_A2h Figure 51. Dual Command Page Program instruction sequence DSP, D2h S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1037 1039 1036 1038 C Instruction 24-Bit Address Data Byte 1 Data Byte 256 Data Byte 2 DQ0 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 DQ1 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 Dual_Page_Program_D2h 9.2.7 Program OTP instruction (POTP) The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code, address and input data on the two pins DQ0 and DQ1, the instruction functionality (as well as the locking OTP method) is exactly the same as the Program OTP (POTP) instruction of the Extended SPI protocol, please refer to Section 9.1.16: Program OTP instruction (POTP) for further details. 119/185 Instructions N25Q128 - 1.8 V Figure 52. Program OTP instruction sequence DIO-SPI S 0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 8 C Instruction 24-Bit Address Data Byte 1 Data Byte n Data Byte 2 DQ0 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 DQ1 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 Dual_Program_OTP 9.2.8 Subsector Erase (SSE) For devices with bottom or top architecture, at the bottom (or top) of the addressable area there are 8 boot sectors, each one having 16 4Kbytes subsectors. The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code and the address on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Subsector Erase (SSE) instruction of the Extended SPI protocol, please refer to Section 9.1.17: Subsector Erase (SSE) for further details. Figure 53. Subsector Erase instruction sequence DIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction 24-Bit Address DQ0 22 20 18 16 14 12 10 8 6 4 2 0 DQ1 23 21 19 17 15 13 11 9 7 5 3 1 Dual_Subsector_Erase 120/185 N25Q128 - 1.8 V 9.2.9 Instructions Sector Erase (SE) The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code and the address on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Sector Erase (SE) instruction of the Extended SPI protocol, please refer to Section 9.1.18: Sector Erase (SE) for further details. Figure 54. Sector Erase instruction sequence DIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction 24-Bit Address DQ0 22 20 18 16 14 12 10 8 6 4 2 0 DQ1 23 21 19 17 15 13 11 9 7 5 3 1 Dual_Sector_Erase 9.2.10 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Bulk Erase (BE) instruction of the Extended SPI protocol, please refer to Section 9.1.19: Bulk Erase (BE) for further details. 121/185 Instructions N25Q128 - 1.8 V Figure 55. Bulk Erase instruction sequence DIO-SPI S 0 1 2 3 C Instruction DQ0 DQ1 Dual_Bulk_Erase 9.2.11 Program/Erase Suspend The Program/Erase Suspend instruction allows the controller to interrupt a Program or an Erase instruction, in particular: Sector Erase and Dual Command Page Program can be suspended and erased while Subsector Erase, Bulk Erase, Write Non Volatile Configuration register, and Program OTP cannot be suspended. Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Program/Erase Suspend (PES) instruction of the Extended SPI protocol. Figure 56. Program/Erase Suspend instruction sequence DIO-SPI S 0 1 2 3 4 C Instruction DQ0 DQ1 Dual_Program_Erase_Suspend 9.2.12 Program/Erase Resume After a Program/Erase suspend instruction, a Program/Erase Resume instruction is required to continue performing the suspended Program or Erase sequence. Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Program/Erase Resume (PER) 122/185 N25Q128 - 1.8 V Instructions instruction of the Extended SPI protocol, please refer to Section 9.1.21: Program/Erase Resume for further details. Figure 57. Program/Erase Resume instruction sequence DIO-SPI S 0 1 2 3 4 C Instruction DQ0 DQ1 Dual_Program_Erase_Resume 123/185 Instructions 9.2.13 N25Q128 - 1.8 V Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. Apart form the parallelizing of the instruction code and the output data on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Read Status Register (RDSR) instruction of the Extended SPI protocol, please refer to Section 9.1.22: Read Status Register (RDSR) for further details. Figure 58. Read Status Register instruction sequence DIO-SPI S 0 1 2 3 4 5 6 8 7 9 10 11 C Status Register Out Byte Byte Instruction DQ0 6 4 2 0 6 4 2 0 DQ1 7 5 3 1 7 5 3 1 Dual_Read_SR 9.2.14 Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code and the input data on the two pins DQ0 and DQ1, the instruction functionality and the protection feature management is exactly the same as the Write Status Register (WRSR) instruction of the Extended SPI protocol, please refer to Section 9.1.23: Write status register (WRSR) for further details. Figure 59. Write Status Register instruction sequence DIO-SPI S 0 1 2 3 4 5 6 7 C Status Register In Byte Instruction DQ0 6 4 2 0 DQ1 7 5 3 1 Dual_Write_SR 124/185 N25Q128 - 1.8 V 9.2.15 Instructions Read Lock Register (RDLR) The Read Lock Register instructions is used to read the lock register content. Apart form the parallelizing of the instruction code, the address and the output data on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Read Lock Register (RDLR) instruction of the Extended SPI protocol, please refer to Section 9.1.24: Read Lock Register (RDLR) for further details. Figure 60. Read Lock Register instruction and data-out sequence DIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 12 13 14 15 C Instruction 24-Bit Address Lock Register Out DQ0 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 DQ1 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 Dual_Read_LR 9.2.16 Write to Lock Register (WRLR) The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code, the address and the input data on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Write to Lock Register (WRLR) instruction of the Extended SPI protocol, please refer to Section 9.1.25: Write to Lock Register (WRLR) for further details. 125/185 Instructions N25Q128 - 1.8 V Figure 61. Write to Lock Register instruction sequence DIO-SPI S 0 1 2 3 4 5 6 9 10 11 12 13 14 15 12 13 14 15 8 7 C Instruction Lock Register In 24-Bit Address DQ0 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 DQ1 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 Dual_Write_LR 9.2.17 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be read. Apart form the parallelizing of the instruction code and the output data on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Read Flag Status Register (RFSR) instruction of the Extended SPI protocol, please refer to Section 9.1.26: Read Flag Status Register for further details. Figure 62. Read Flag Status Register instruction sequence DIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 C Instruction Flag Status Register Out Byte Byte DQ0 6 4 2 0 6 4 2 0 DQ1 7 5 3 1 7 5 3 1 Dual_Read_Flag_SR 126/185 N25Q128 - 1.8 V 9.2.18 Instructions Clear Flag Status Register The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits (Erase Error bit, Program Error bit, VPP Error bit, Protection Error bit). It is not necessary to set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit will be unchanged after this command is executed. Figure 63. Clear Flag Status Register instruction sequence DIO-SPI S 0 1 2 3 C Instruction DQ0 DQ1 Dual_Clear_Flag_SR 9.2.19 Read NV Configuration Register The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile Configuration Register to be read. Figure 64. Read NV Configuration Register instruction sequence DIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 C NVCR Out Byte Instruction Byte DQ0 6 4 2 0 14 12 10 8 DQ1 7 5 3 1 15 13 11 9 LS Byte MS Byte Dual_Read_NVCR 127/185 Instructions 9.2.20 N25Q128 - 1.8 V Write NV Configuration Register The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to be written to the Non Volatile Configuration register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code and the input data on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Write Non Volatile Configuration Register (WNVCR) instruction of the Extended SPI protocol, please refer to Section 9.1.29: Write NV Configuration Register for further details. Figure 65. Write NV Configuration Register instruction sequence DIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 C NVCR In Byte Instruction Byte DQ0 6 4 2 0 14 12 10 8 DQ1 7 5 3 1 15 13 11 9 LS Byte MS Byte Dual_Write_NVCR 9.2.21 Read Volatile Configuration Register The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile Configuration Register to be read. See Table 6.: Volatile Configuration Register. 128/185 N25Q128 - 1.8 V Instructions Figure 66. Read Volatile Configuration Register instruction sequence DIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 C Volatile Configuration Register Out Byte Byte Instruction DQ0 6 4 2 0 6 4 2 0 DQ1 7 5 3 1 7 5 3 1 Dual_Read_VCR 9.2.22 Write Volatile Configuration Register The Write Volatile Configuration register (WRVCR) instruction allows new values to be written to the Volatile Configuration register. Before it can be accepted, a write enable (WREN) instruction must have been executed previously. In case of Fast POR, the WREN instruction is not required because a WREN instruction gets the device out from the Fast POR state (See Section 11.1: Fast POR). Apart form the parallelizing of the instruction code and the input data on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Write Volatile Configuration Register (WVCR) instruction of the Extended SPI protocol, please refer to Section 9.1.31: Write Volatile Configuration Register for further details. Figure 67. Write Volatile Configuration Register instruction sequence DIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 C Volatile Configuration Register In Byte Byte Instruction DQ0 6 4 2 0 6 4 2 0 DQ1 7 5 3 1 7 5 3 1 Dual_Write_VCR 129/185 Instructions 9.2.23 N25Q128 - 1.8 V Read Volatile Enhanced Configuration Register The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the Volatile Configuration Register to be read. Figure 68. Read Volatile Enhanced Configuration Register instruction sequence DIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 C Volatile Enhanced Configuration Register Out Byte Byte Instruction DQ0 6 4 2 0 6 4 2 0 DQ1 7 5 3 1 7 5 3 1 Dual_Read_VECR 9.2.24 Write Volatile Enhanced Configuration Register The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new values to be written to the Volatile Enhanced Configuration register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. In case of Fast POR, the WREN instruction is not required because a WREN instruction gets the device out from the Fast POR state (See Section 11.1: Fast POR). Apart form the parallelizing of the instruction code and the input data on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Write Volatile Enhanced Configuration Register (WRVECR) instruction of the Extended SPI protocol, please refer to Section 9.1.33: Write Volatile Enhanced Configuration Register for further details. 130/185 N25Q128 - 1.8 V Instructions Figure 69. Write Volatile Enhanced Configuration Register instruction sequence DIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 C Volatile Enhanced Configuration Register In Byte Byte Instruction DQ0 6 4 2 0 6 4 2 0 DQ1 7 5 3 1 7 5 3 1 Dual_Write_VECR 9.2.25 Deep Power-down (DP) The Deep-Power-down (DP) instruction sets the device in Deep Power-down mode. Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Deep Power-down (DP) instruction of the Extended SPI protocol. The instruction sequence is shown in Figure 70: Deep Power-down instruction sequence. Figure 70. Deep Power-down instruction sequence S 0 1 2 3 t DP C Instruction DQ0 DQ1 Standby mode Deep power-down mode Dual_DP 131/185 Instructions 9.2.26 N25Q128 - 1.8 V Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Release from Deep-Power-down (RDP) instruction of the Extended SPI protocol. The instruction sequence is shown in Figure 71: Release from Deep Power-down instruction sequence. Figure 71. Release from Deep Power-down instruction sequence S 0 1 2 t RDP 3 C Instruction DQ0 High Impedance DQ1 Deep power-down mode Standby mode Dual_RDP 9.3 QIO-SPI Instructions In QIO-SPI protocol, instructions, addresses and Input/Output data always run in parallel on four wires: DQ0, DQ1, DQ2 and DQ3 with the already mentioned exception of the modify instruction (erase and program) performed with the VPP=VPPh. In the case of a Quad Command Fast Read (QCFR), Read OTP (ROTP), Read Lock Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR), Read Volatile Enhanced Configuration Register (RDVECR) and Read Identification (RDID) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Quad Command Page Program (QCPP), Program OTP (POTP), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Program/Erase Suspend (PES), Program/Erase Resume (PER), Write Status Register (WRSR), Clear Flag Status Register (CLFSR), Write to Lock Register (WRLR), Write Configuration Register (WRVCR), Write Enhanced Configuration Register (WRVECR), Write NV Configuration Register (WRNVCR), Write Enable (WREN) or Write Disable (WRDI) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. 132/185 N25Q128 - 1.8 V Instructions All attempts to access the memory array during a Write Status Register cycle, a Write Non Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the internal Write Status Register cycle, Write Non Volatile Configuration Register, Program cycle or Erase cycle continues unaffected, the only exception is the Program/Erase Suspend instruction (PES), that can be used to pause all the program and the erase cycles but the Program OTP (POT), Bulk Erase (BE) and Write Non Volatile Configuration Register. The suspended program or erase cycle can be resumed by mean of the Program/Erase Resume instruction (PER). During the program/erase cycles also the polling instructions (to check if the internal modify cycle is finished by mean of the WIP bit of the Status Register or of the Program/Erase controller bit of the Flag Status register) are also accepted to allow the application checking the end of the internal modify cycles, of course these polling instructions don't affect the internal cycles performing. Table 24. Instruction set: QIO-SPI protocol (page 1 of 2) Instruction MIORDID Description Multiple I/O read identification One-byte Instruction Code (BIN) 1010 1111 0000 1011 QCFR Quad Command Fast Read One-byte Dummy Instruction Address clock Code bytes cycle (HEX) AFh 0Bh 0 3 0 Data bytes 1 to 3 10 (1) 1 to ∞ (1) 1 to ∞ 0110 1011 6Bh 3 10 1110 1011 EBh 3 10 (1) 1 to ∞ ROTP Read OTP (Read of OTP area) 0100 1011 4Bh 3 10 (1) 1 to 65 WREN Write Enable 0000 0110 06h 0 0 0 WRDI Write Disable 0000 0100 04h 0 0 0 0000 0010 02h 3 0 1 to 256 0011 0010 32h 3 0 1 to 256 0001 0010 12h 3 0 1 to 256 QCPP Quad Command Page Program POTP Program OTP (Program of OTP area) 0100 0010 42h 3 0 1 to 65 SSE(2) SubSector Erase 0010 0000 20h 3 0 0 SE Sector Erase 1101 1000 D8h 3 0 0 BE Bulk Erase 1100 0111 C7h 0 0 0 PER Program/Erase Resume 0111 1010 7Ah 0 0 0 PES Program/Erase Suspend 0111 0101 75h 0 0 0 RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞ WRSR Write Status Register 0000 0001 01h 0 0 1 RDLR Read Lock Register 1110 1000 E8h 3 0 1 to ∞ WRLR Write to Lock Register 1110 0101 E5h 3 0 1 RFSR Read Flag Status Register 0111 0000 70h 0 0 1 to ∞ CLFSR Clear Flag Status Register 0101 0000 50h 0 0 0 RDNVCR Read NV Configuration Register 1011 0101 B5h 0 0 2 133/185 Instructions Table 24. N25Q128 - 1.8 V Instruction set: QIO-SPI protocol (page 2 of 2) Instruction Description One-byte Instruction Code (BIN) One-byte Dummy Instruction Address clock Code bytes cycle (HEX) Data bytes WRNVCR Write NV Configuration Register 1011 0001 B1h 0 0 2 RDVCR Read Volatile Configuration Register 1000 0101 85h 0 0 1 to ∞ WRVCR Write Volatile Configuration Register 1000 0001 81h 0 0 1 RDVECR Read Volatile Enhanced Configuration Register 0110 0101 65h 0 0 1 to ∞ WRVECR Write Volatile Enhanced Configuration Register 0110 0001 61h 0 0 1 DP Deep Power-down 1011 1001 B9h 0 0 0 RDP Release from Deep Power-down 1010 1011 ABh 0 0 0 1) The number of Dummy Clock cycles is configurable by the user. 2) SSE is only available in devices with Bottom or Top architecture 9.3.1 Multiple I/O Read Identification (MIORDID) The Multiple Input/Output Read Identification (MIORDID) instruction allows to read the device identification data in the QIO-SPI protocol: Manufacturer identification (1 byte) Device identification (2 bytes) Unlike the RDID instruction of the Extended SPI protocol, the Multiple Input/Output instruction can not read the Unique ID code (UID) (17 bytes). For further details on the manufacturer and device identification codes, see 9.1.1: Read Identification (RDID). Any Multiple Input/Output Read Identification (MIORDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in parallel on the 4 pins DQ0, DQ1, DQ2 and DQ3. After this, the 24-bit device identification, stored in the memory, will be shifted out on again in parallel on DQ0, DQ1, DQ2 and DQ3. The identification bits are shifted out 4 at a time during the falling edge of Serial Clock (C). The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Multiple I/O Read Identification (MIORDID) instruction sequence and data-out sequence QIO-SPI. 134/185 N25Q128 - 1.8 V Instructions Figure 72. Multiple I/O Read Identification instruction and data-out sequence QIOSPI S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C MAN. code DEV. code SIZE code DQ0 4 0 4 0 4 0 DQ1 5 1 5 1 5 1 DQ2 6 2 6 2 6 2 DQ3 7 3 7 3 7 3 AFh Quad_Multi_Read_IO 9.3.2 Quad Command Fast Read (QCFR) The Quad Command Fast Read (QCFR) instruction allows to read the memory in QIO-SPI protocol, parallelizing the instruction code, the address and the output data on four pins (DQ0, DQ1, DQ2 and DQ3). The Quad Command Fast Read (QCFR) instruction can be issued, after the device is set in QIO-SPI mode, by sending to the memory indifferently one of the 3 instructions codes: 0Bh, 6Bh or EBh, the effect is exactly the same. The 3 instruction codes are all accepted to help the application code porting from Extended SPI protocol to QIO-SPI protocol. Apart for the parallelizing on four pins of the instruction code, the Quad Command Fast Read instruction functionality is exactly the same as the Quad I/O Fast Read of the Extended SPI protocol, please refer to Section 9.1.7: Quad I/O Fast Read for further details. 135/185 Instructions N25Q128 - 1.8 V Figure 73. Quad Command Fast Read instruction and data-out sequence QSP, 0Bh S Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21 22 23 24 25 26 27 Mode 0 IO switches from Input to Output Instruction DQ0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 DQ1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 4 0 4 0 DQ2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 4 0 4 0 DQ3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 4 0 4 0 A23-16 A15-8 A7-0 Dummy (ex.: 10) Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Quad_Command_Fast_Read_0Bh Figure 74. Quad Command Fast Read instruction and data-out sequence QSP, 6Bh S Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21 22 23 24 25 26 27 Mode 0 IO switches from Input to Output Instruction DQ0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 DQ1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 4 0 4 0 DQ2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 4 0 4 0 DQ3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 4 0 4 0 A23-16 A15-8 A7-0 Dummy (ex.: 10) Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Quad_Command_Fast_Read_EBh 136/185 N25Q128 - 1.8 V Instructions Figure 75. Quad Command Fast Read instruction and data-out sequence QSP, EBh S Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21 22 23 24 25 26 27 Mode 0 IO switches from Input to Output Instruction DQ0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 DQ1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 4 0 4 0 DQ2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 4 0 4 0 DQ3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 4 0 4 0 A23-16 A15-8 A7-0 Dummy (ex.: 10) Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Quad_Command_Fast_Read_EBh 9.3.3 Read OTP (ROTP) The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the QIO-SPI protocol. The instruction functionality is exactly the same as the Read OTP instruction of the Extended SPI protocol. The only difference is that in the QIO-SPI protocol instruction code, address and output data are all parallelized on the four pins DQ0, DQ1, DQ2 and DQ3. Note: The dummy byte bits can not be parallelized: 8 clock cycles are requested to perform the internal reading operation. 137/185 Instructions N25Q128 - 1.8 V Figure 76. Read OTP instruction and data-out sequence QIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21 22 23 C Instruction Data out 1 Data out n DQ0 4 0 4 0 4 0 4 0 4 0 4 0 DQ1 5 1 5 1 5 1 5 1 5 1 5 1 DQ2 6 2 6 2 6 2 6 2 6 2 6 2 DQ3 7 3 7 3 7 3 7 3 7 3 7 3 Dummy (ex.: 10) Quad_Read_OTP 9.3.4 Write Enable (WREN) The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Enable instruction of the Extended SPI protocol, please refer to Section 9.1.9: Write Enable (WREN) for further details. Figure 77. Write Enable instruction sequence QIO-SPI S 0 1 C Instruction DQ0 DQ1 DQ2 DQ3 Quad_Write_Enable 138/185 N25Q128 - 1.8 V 9.3.5 Instructions Write Disable (WRDI) The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit. Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Disable (WRDI) instruction of the Extended SPI protocol, please refer to Section 9.1.10: Write Disable (WRDI) for further details. Figure 78. Write Disable instruction sequence QIO-SPI S 0 1 C Instruction DQ0 DQ1 DQ2 DQ3 Quad_Write_Disable 9.3.6 Quad Command Page Program (QCPP) The Quad Command Page Program (QCPP) instruction allows to program the memory content in DIO-SPI protocol, parallelizing the instruction code, the address and the input data on four pins (DQ0, DQ1, DQ2 and DQ3). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. The Quad Command Page Program (QCPP) instruction can be issued, when the device is set in QIO-SPI mode, by sending to the memory indifferently one of the 3 instructions codes: 02h, 12h or 32h, the effect is exactly the same. The 3 instruction codes are all accepted to help the application code porting from Extended SPI protocol to QIO-SPI protocol. Apart for the parallelizing on four pins of the instruction code, the Quad Command Page Program instruction functionality is exactly the same as the Quad Input Extended Fast Program of the Extended SPI protocol, please refer to Section 9.1.15: Quad Input Extended Fast Program for further details. 139/185 Instructions N25Q128 - 1.8 V Figure 79. Quad Command Page Program instruction sequence QIO-SPI, 02h S Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 514 515 516 517 518 519 Mode 0 24-bit address 1 2 Data In 3 Data In 254 255 4 256 DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 3 7 3 7 3 MSB MSB MSB 7 MSB MSB MSB Quad_Command_Page_Program_02h Figure 80. Quad Command Page Program instruction sequence QIO-SPI, 12h S Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 514 515 516 517 518 519 Mode 0 24-bit address 1 2 Data In 3 Data In 254 255 4 256 DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 3 7 3 7 3 MSB MSB MSB 7 MSB MSB MSB Quad_Command_Page_Program_12h 140/185 N25Q128 - 1.8 V Instructions Figure 81. Quad Command Page Program instruction sequence QIO-SPI, 32h S Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 514 515 516 517 518 519 Mode 0 24-bit address 1 2 Data In 3 DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 DQ2 22 18 14 10 6 2 6 2 6 2 6 DQ3 23 19 15 11 7 3 7 3 7 3 7 MSB Data In 254 255 4 256 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 2 6 2 6 2 6 2 6 2 3 7 3 7 3 7 3 7 3 MSB MSB MSB MSB MSB Quad_Command_Page_Program_12h 9.3.7 Program OTP instruction (POTP) The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code, address and input data on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality (as well as the locking OTP method) is exactly the same as the Program OTP (POTP) instruction of the Extended SPI protocol, please refer to Section 9.1.16: Program OTP instruction (POTP) for further details. 141/185 Instructions N25Q128 - 1.8 V Figure 82. Program OTP instruction sequence QIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C Instruction 24-Bit Address Data byte1 Data Data byte 2 byte n DQ0 20 16 12 8 4 0 4 0 4 0 4 0 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 DQ2 22 18 14 10 6 2 6 2 6 2 6 2 DQ3 23 19 15 11 3 7 3 7 3 7 3 7 Quad_Program_OTP 9.3.8 Subsector Erase (SSE) For devices with a dedicated part number, at the bottom (or top) of the addressable area there are 8 boot sectors, each one having 16 4Kbytes subsectors. (See Section 16: Ordering information.) The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code and the address on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Subsector Erase (SSE) instruction of the Extended SPI protocol, please refer to Section 9.1.17: Subsector Erase (SSE) for further details. 142/185 N25Q128 - 1.8 V Instructions Figure 83. Subsector Erase instruction sequence QIO-SPI S 0 1 2 3 4 5 6 7 8 9 C Instruction 24-Bit Address DQ0 20 16 12 8 4 0 DQ1 21 17 13 9 5 1 DQ2 22 18 14 10 6 2 DQ3 23 19 15 11 3 7 Quad_Subsector_Erase 9.3.9 Sector Erase (SE) The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code and the address on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Sector Erase (SE) instruction of the Extended SPI protocol, please refer to Section 9.1.18: Sector Erase (SE) for further details. Figure 84. Sector Erase instruction sequence QIO-SPI S 0 1 2 3 4 5 6 7 8 9 C Instruction 24-Bit Address DQ0 20 16 12 8 4 0 DQ1 21 17 13 9 5 1 DQ2 22 18 14 10 6 2 DQ3 23 19 15 11 3 7 Quad_Sector_Erase 143/185 Instructions 9.3.10 N25Q128 - 1.8 V Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Bulk Erase (BE) instruction of the Extended SPI protocol, please refer to Section 9.1.19: Bulk Erase (BE) for further details. Figure 85. Bulk Erase instruction sequence QIO-SPI S 0 1 C Instruction DQ0 DQ1 DQ2 DQ3 Quad_Bulk_Erase 9.3.11 Program/Erase Suspend The Program/Erase Suspend instruction allows the controller to interrupt a Program or an Erase instruction, in particular: Sector Erase and Quad Command Page Program can be suspended and erased while that Subsector Erase, Bulk Erase, Write Non Volatile Configuration register and Program OTP can not be suspended. Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Program/Erase Suspend (PES) instruction of the Extended SPI protocol, please refer to Section 9.1.20: Program/Erase Suspend for further details. 144/185 N25Q128 - 1.8 V Instructions Figure 86. Program/Erase Suspend instruction sequence QIO-SPI S 0 1 C Instruction DQ0 DQ1 DQ2 DQ3 Quad_Program_Erase_Suspend 9.3.12 Program/Erase Resume After a Program/Erase suspend instruction, a Program/Erase Resume instruction is required to continue performing the suspended Program or Erase sequence. Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Program/Erase Resume (PER) instruction of the Extended SPI protocol, please refer to Section 9.1.21: Program/Erase Resume for further details. 145/185 Instructions N25Q128 - 1.8 V Figure 87. Program/Erase Resume instruction sequence QIO-SPI S 0 1 C Instruction DQ0 DQ1 DQ2 DQ3 Quad_Program_Erase_Resume 9.3.13 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. Apart form the parallelizing of the instruction code and the output data on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Read Status Register (RDSR) instruction of the Extended SPI protocol, please refer to Section 9.1.22: Read Status Register (RDSR) for further details. 146/185 N25Q128 - 1.8 V Instructions Figure 88. Read Status Register instruction sequence QIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 C Status Register Out Instruction DQ0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 DQ1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 DQ2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 DQ3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Quad_Read_SR 9.3.14 Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. The instruction code and the input data are sent on four pins DQ0, DQ1, DQ2 and DQ3. The instruction functionality is exactly the same as the Write Status Register (WRSR) instruction of the Extended SPI protocol (See Section 9.1.23: Write status register (WRSR)). However, the protection feature management is different. In particular, once SRWD bit is set to '1' the device enters in the hardware protected mode (HPM) independently from Write Protect (W/VPP) signal value. To exit the HPM mode is needed to switch temporarily to the Extended SPI protocol. 147/185 Instructions N25Q128 - 1.8 V Figure 89. Write Status Register instruction sequence QIO-SPI S 0 1 2 3 C Status Register In DQ0 4 0 DQ1 5 1 DQ2 6 2 DQ3 7 3 Quad_Write_SR 9.3.15 Read Lock Register (RDLR) The Read Lock Register instructions is used to read the lock register content. Apart form the parallelizing of the instruction code, the address and the output data on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Read Lock Register (RDLR) instruction of the Extended SPI protocol, please refer to Section 9.1.24: Read Lock Register (RDLR) for further details. 148/185 N25Q128 - 1.8 V Instructions Figure 90. Read Lock Register instruction and data-out sequence QIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction 24-bit address Lock Register Out DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 Quad_Read_LR 9.3.16 Write to Lock Register (WRLR) The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code, the address and the input data on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write to Lock Register (WRLR) instruction of the Extended SPI protocol, please refer to Section 9.1.25: Write to Lock Register (WRLR) for further details. 149/185 Instructions N25Q128 - 1.8 V Figure 91. Write to Lock Register instruction sequence QIO-SPI S 0 1 2 3 4 5 6 7 8 9 C Instruction 24-Bit Address Lock Register In DQ0 20 16 12 8 4 0 4 0 DQ1 21 17 13 9 5 1 5 1 DQ2 22 18 14 10 6 2 6 2 DQ3 23 19 15 11 3 7 3 7 Quad_Write_LR 9.3.17 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be read. Apart form the parallelizing of the instruction code and the output data on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Read Flag Status Register (RFSR) instruction of the Extended SPI protocol, please refer to Section 9.1.26: Read Flag Status Register for further details. 150/185 N25Q128 - 1.8 V Instructions Figure 92. Read Flag Status Register instruction sequence QIO-SPI S Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 0 Flag Status Register Out Instruction DQ0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 DQ1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 DQ2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 DQ3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Quad_Read_Flag_SR 9.3.18 Clear Flag Status Register The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits (Erase Error bit, Program Error bit, VPP Error bit, Protection Error bit). It is not necessary to set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit will be unchanged after this command is executed. 151/185 Instructions N25Q128 - 1.8 V Figure 93. Clear Flag Status Register instruction sequence QIO-SPI S 0 1 C Instruction DQ0 DQ1 DQ2 DQ3 Quad_Clear_Flag_SR 9.3.19 Read NV Configuration Register The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile Configuration Register to be read. 152/185 N25Q128 - 1.8 V Instructions Figure 94. Read NV Configuration Register instruction sequence QIO-SPI S 0 1 2 3 4 5 C Instruction Nonvolatile Configuration Register Out DQ0 4 0 12 8 DQ1 5 1 13 9 DQ2 6 2 14 10 DQ3 7 3 15 11 LS Byte MS Byte Quad_Read_NVCR 9.3.20 Write NV Configuration Register The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to be written to the Non Volatile Configuration register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code and the input data on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Non Volatile Configuration Register (WRNVCR) instruction of the Extended SPI protocol, please refer to Section 9.1.29: Write NV Configuration Register for further details. 153/185 Instructions N25Q128 - 1.8 V Figure 95. Write NV Configuration Register instruction sequence QIO-SPI S 0 1 2 3 4 5 C Instruction Nonvolatile Configuration Register In DQ0 4 0 12 8 DQ1 5 1 13 9 DQ2 6 2 14 10 DQ3 7 3 15 11 LS Byte MS Byte Quad_Write_NVCR 9.3.21 Read Volatile Configuration Register The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile Configuration Register to be read. 154/185 N25Q128 - 1.8 V Instructions Figure 96. Read Volatile Configuration Register instruction sequence QIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Volatile Configuration Register Out Instruction DQ0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 DQ1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 DQ2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 DQ3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Quad_Read_VCR 9.3.22 Write Volatile Configuration Register The Write Volatile Configuration register (WRVCR) instruction allows new values to be written to the Volatile Configuration register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. In case of Fast POR, the WREN instruction is not required because a WREN instruction gets the device out from the Fast POR state (See Section 11.1: Fast POR). Apart form the parallelizing of the instruction code and the input data on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Volatile Configuration Register (WRVCR) instruction of the Extended SPI protocol, please refer to Section 9.1.31: Write Volatile Configuration Register for further details. 155/185 Instructions N25Q128 - 1.8 V Figure 97. Write Volatile Configuration Register instruction sequence QIO-SPI S 0 1 2 3 C Volatile Configuration Register In DQ0 4 0 DQ1 5 1 DQ2 6 2 DQ3 7 3 Quad_Write_VCR 9.3.23 Read Volatile Enhanced Configuration Register The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the Volatile Configuration Register to be read. 156/185 N25Q128 - 1.8 V Instructions Figure 98. Read Volatile Enhanced Configuration Register instruction sequence QIO-SPI S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Volatile Enhanced Configuration Register Out Instruction DQ0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 DQ1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 DQ2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 DQ3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Quad_Read_VECR 9.3.24 Write Volatile Enhanced Configuration Register The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new values to be written to the Volatile Enhanced Configuration register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. In case of Fast POR the WREN instruction is not required because a WREN instruction gets the device out from the Fast POR state (See Section 11.1: Fast POR). Apart form the parallelizing of the instruction code and the input data on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Volatile Enhanced Configuration Register (WRVECR) instruction of the Extended SPI protocol, please refer to Section 9.1.33: Write Volatile Enhanced Configuration Register for further details. 157/185 Instructions N25Q128 - 1.8 V Figure 99. Write Volatile Enhanced Configuration Register instruction sequence QIO-SPI S 0 1 2 3 C Instruction Volatile Enhanced Configuration Register In DQ0 4 0 DQ1 5 1 DQ2 6 2 DQ3 7 3 Quad_Write_VECR 158/185 N25Q128 - 1.8 V 9.3.25 Instructions Deep Power-down (DP) The Deep-Power-down (DP) instruction sets the device in Deep Power-down mode. Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Deep Power-down (DP) instruction of the Extended SPI protocol. The instruction sequence is shown in Figure 100. Figure 100. Deep Power-down instruction sequence S 0 1 t DP C Instruction DQ0 DQ1 DQ2 DQ3 Standby mode Deep power-down mode 159/185 Instructions 9.3.26 N25Q128 - 1.8 V Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. Apart form the parallelizing of the instruction code on the two pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Release from Deep-Power-down (RDP) instruction of the Extended SPI protocol. The instruction sequence is shown in Figure 101. Figure 101. Deep Power-down instruction sequence S 0 t RDP 1 C Instruction DQ0 DQ1 DQ2 High Impedance DQ3 Deep power-down mode Standby mode Quad_RDP 160/185 N25Q128 - 1.8 V 10 XIP Operations XIP Operations XIP (eXecution in Place) mode is available in each protocol: Extended SPI, DIO-SPI, and QIO-SPI. XIP mode allows the memory to be read simply by sending an address to the device and then receiving the data on one, two, or four pins in parallel, depending on the customer requirements. It offers maximum flexibility to the application, saves instruction overhead, and allows a dramatic reduction to the Random Access time. You can enable XIP mode in two ways: Using the Volatile Configuration Register: this is dedicated to applications that boot in SPI mode (Extended SPI, DIO-SPI or QIO-SPI) and then during the application life need to switch to XIP mode to directly execute some code in the flash. Using the Non Volatile Configuration Register: this is dedicated to applications that need to boot directly in XIP mode. Setting to 0 the bit 3 of the Volatile Configuration Register the device is ready to enter in XIP mode right after the next fast read instruction (by 1, 2 or 4 pin). While acting on the Non Volatile Configuration Register (bit 11 to bit 9, depending on which XIP type is required, single, dual or quad I/O) the memory enters in the selected XIP mode only after the next power-on sequence. The Non Volatile Configuration Register XIP configuration bits allows the memory to start directly in the required XIP mode (Single, Dual or Quad) after the power on. The XIP mode status must be confirmed forcing the XIP confirmation bit to "0", the XIP confirmation bit is the value on the DQ0 pin during the first dummy clock cycle after the address in XIP reading instruction. Forcing the bit "1" on DQ0 during the first dummy clock cycle after the address (XIP Confirmation bit) the memory returns in the previous standard read mode, that means it will codify as an instruction code the next byte received on the input pin(s) after the next chip select. Instead, if the XIP mode is confirmed (by forcing the XIP confirmation bit to 0), after the device next de-selection and selection cycle, the memory codify the first 3 bytes received on the inputs pin(s) as a new address. Besides not confirming the XIP mode during the first dummy clock cycle, it is possible to exit the XIP mode by mean of a dedicated rescue sequence. Note: For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), it is not necessary to set the Volatile Configuration Register bit 3 to enter XIP mode: it is possible to enter XIP mode directly by setting XIP Confirmation bit to 1 during the first dummy clock cycle after a fast read instruction.See Section 16: Ordering information. 161/185 XIP Operations N25Q128 - 1.8 V Figure 102. N25Q128 Read functionality Flow Chart Power On NVCR Check No Is XIP enabled ? Yes SPI standard mode (no XiP, VCR <3> = 1) VCR<3> = 0 ? Yes SPI mode (no XIP) but ready to enter XIP No No XIP mode Read Instructions ? Yes Yes No XiP Confirmation bit = 0 ? No XiP Confirmation bit = 0 ? Yes 10.1 Enter XIP mode by setting the Non Volatile Configuration Register To use the Non Volatile Configuration Register method to enter in XIP mode it is necessary to set the Non Volatile Configuration Register bits from 11 to 9 with the pattern corresponding to the required XIP mode by mean of the Write Non Volatile Configuration Register (WRNVCR) instruction. (See Table 25.: NVCR XIP bits setting example.) This instruction doesn't affect the XIP state until the next Power on sequence. In this case, after the next power on sequence, the memory directly accept addresses and then, after the dummy clock cycles (configurable), outputs the data as described in Table 25.: NVCR XIP bits setting example. For example to enable fast POR and XIP on QIOFR in normal SPI protocol with six dummy clock cycles the following pattern must be issued: 162/185 N25Q128 - 1.8 V Table 25. XIP Operations NVCR XIP bits setting example B1h (WRNVCR opcode) + 0110 100 111 0 1 11 xx 6 dummy cycles for fast read instructions XIP set as default; Quad I/O mode Output Buffer driver strength default FAST POR enabled Hold/Reset not disabled Extended SPI protocol Don’t Care Figure 103. XIP mode directly after power on NVCR check: XIP enabled Vd tVSI (<100μ) S Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mode 0 IO switches from Input to Output DQ0 4 0 4 0 4 0 Xb 4 0 4 0 4 DQ1 5 1 5 1 5 1 5 1 5 1 5 DQ2 6 2 6 2 6 2 6 2 6 2 6 DQ3 7 3 7 3 7 3 7 3 7 3 7 A23-16 A15-8 A7-0 Dummy (ex.: 6) Byte 1 Byte 2 Quad_XIP_After_Power-On Note: Xb is the XIP Confirmation bit, and it should be set to '0' to keep XIP state or '1' to exit XIP mode and return to standard read mode. 163/185 XIP Operations 10.2 N25Q128 - 1.8 V Enter XIP mode by setting the Volatile Configuration Register To use the Volatile Configuration Register method to enter XIP mode, it is necessary to write a 0 to bit 3 of the Volatile Configuration Register to make the device ready to enter XIP mode (2). This instruction doesn't permit to enter XIP state directly: a Fast Read instruction (either Single, Dual or Quad) is needed once to start the XIP Reading. After the Fast Read instruction (Single, Dual or Quad) the XIP confirmation bit must be set to 0. (first bit on DQ0 during the first dummy cycle after the address has been received), Then after the next de-select and select cycle (S pin set to 1 and then to 0) the memory codify the first 3 bytes received on the input pin(s) directly as an address, without any instruction code, and after the dummy clock cycles (configurable) directly outputs the data. For example to enable the XIP (without enter) with six dummy clock cycles, the pattern in Table 26.: VCR XIP bits setting example must be issued, and after that it is possible to enter, for example, in XIP mode from extended SPI read mode by mean of Quad Input Output Fast Read instruction, as described in Table 26.: VCR XIP bits setting example. Note: For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), it is not necessary to set the Volatile Configuration Register bit 3 to enter in XIP mode: it is possible to enter directly in XIP mode by setting XIP Confirmation bit to 1 during the first dummy clock cycle after a fast read instruction. See Section 16: Ordering information. Table 26. VCR XIP bits setting example 81h (WRVCR opcode) + 0110 0 000 6 dummy cycles Ready for XIP Reserved 164/185 N25Q128 - 1.8 V XIP Operations Figure 104. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example) S Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 IO switches from Input to Output Instruction DQ0 4 0 4 0 4 0 Xb 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 Don’t Care DQ1 Don’t Care DQ2 DQ3 ‘1’ A23-16 A15-8 A7-0 Dummy (ex.: 6) Byte 1 Byte 2 XIP_VCR Note: Xb is the XIP Confirmation bit, and it should be set to '0' to keep XIP state or '1' to exit XIP mode and return to standard read mode. 10.3 XIP mode hold and exit The XIP mode does require at least one additional clock cycle to allow the XIP Confirmation bit to be sent to the memory on DQ0 during the first dummy clock cycle. The device decodes the XIP Confirmation bit with the scheme: XIP Confirmation bit=0 means to hold XIP Mode XIP Confirmation bit=1 means to exit XIP Mode and comes back to read mode, that means codifying the first byte after the next chip select as an instruction code. In Dual I/O XIP mode, the values of DQ1 during the first dummy clock cycle after the addresses is always Don't Care. In Quad I/O XIP mode, the values of DQ3, DQ2 and DQ1 during the first dummy clock cycle after the addresses are always Don't Care. In Dual and Single I/O XIP mode, in presence of the RESET pin enabled (in devices with a dedicated part number), a low pulse on that pin resets the XIP protocol as defined by the Volatile Configuration Register, reporting the memory at the state of last power up, as defined by the Non Volatile Configuration Register. In Quad I/O XiP modes, it is possible to reset the memory (for devices with a dedicated part number) only when the device is deselected. See Section 16: Ordering information. 165/185 XIP Operations 10.4 N25Q128 - 1.8 V XIP Memory reset after a controller reset If during the application life the system controller is reset during operation, and the device features the RESET functionality (in devices with a dedicated part number), and the feature has not been disabled, after the controller resets, the memory returns to POR state and there is no issue. See Section 16: Ordering information. In all the other cases, it is possible to exit the memory from the XIP mode by sending the following rescue sequence at the first chip selection after a system reset: DQ0= '1' for: 7 clock cycles within S low (S becomes high before 8th clock cycle) + 13 clock cycles within S low (S becomes high before 14th clock cycle) + 25 clock cycles within S low (S becomes high before 26th clock cycle) The global effect is only to exit from XIP without any other reset. 166/185 N25Q128 - 1.8 V 11 Power-up and power-down Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value: VCC(min) at power-up, and then for a further delay of tVSL VSS at power-down A safe configuration is provided in Section 3: SPI Modes. To avoid data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset (POR) threshold voltage, VWI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores the Write Enable (WREN) instruction and all the modify instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of: tPUW after VCC has passed the VWI threshold tVSL after VCC has passed the VCC(min) level These values are specified in Table 27.: Power-up timing and VWI threshold. If the time, tVSL, has elapsed, after VCC rises above VCC(min), the device can be selected for READ instructions even if the tPUW delay has not yet fully elapsed. After power-up, the device is in the following state: The device is in the Standby Power mode (not the Deep Power-down mode) The Write Enable Latch (WEL) bit is reset The Write In Progress (WIP) bit is reset The Lock Registers are configured as: (Write Lock bit, Lock Down bit) = (0,0). Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply. Each device in a system should have the VCC line decoupled by a suitable capacitor close to the package pins (generally, this capacitor is of the order of 100 nF). At power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction (the designer needs to be aware that if power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption may result). VPPH must be applied only when VCC is stable and in the VCC(min) to VCC(max) voltage range. 167/185 Power-up and power-down N25Q128 - 1.8 V Figure 105. Power-up timing, Fast POR selected Vcc VCC(max) WREN issued Chip selection not allowed VCC(min) tVTR Chip tDTW Polling allowed reset Polling WRECR allowed allowed Starting protocol defined by NVCR SPI protocol VWI Device fully accessible All read, WRCR, WIP = 1 WIP = 0 WIP = 1 WIP = 0 WEL = 0 WEL = 0 WEL = 1 WEL = 1 time Figure 106. Power-up timing, Fast POR not selected Vcc VCC(max) Chip selection not allowed VCC(min) tVTW = tVTR + tDTW Chip Polling allowed Device fully accessible reset SPI protocol VWI Starting protocol defined by NVCR WIP = 1 WIP = 0 WEL = 0 WEL = 0 time Table 27. Power-up timing and VWI threshold Symbol tVTR(1) Max Unit VCC(min) to Read when Fast POR is selected 100 µs Time delay to write instruction when Fast POR is selected 500 µs (1) VCC(min) to device fully accessible 600 µs 2.5 V VWI(1) Write inhibit voltage 1. These parameters are characterized only. 168/185 Min (1) tDTW tVTW Parameter 1.5 N25Q128 - 1.8 V 11.1 Power-up and power-down Fast POR The Fast POR feature is available to speed up the power-on sequence for applications that only require reading the memory after the power on sequence (no modify instructions). If enabled, the Fast POR allows read operations and Volatile Configuration Register and Volatile Enhanced Configuration Register modifications after less than 100us, providing a substantially faster application boot phase. In any case, even if the Fast POR sequence is selected, it is still possible to execute a modify instruction (erase or program) issuing a WREN instruction. In this case the device will have a latency time (~500us) after the first WREN instruction to complete POR sequence. During this latency time, when the power on second phase is running, no instruction will be accepted except for the polling instruction. During the power on second phase, both WEL & WIP bits are set to 1. At the end of POR sequence only the WEL bit is still set to 1. To select or deselect the Fast POR feature, a Write non Volatile Configuration Register (WRNVCR) instruction is needed to properly set the dedicated bit (bit 5) of the Non Volatile Configuration Register. 11.2 Rescue sequence in case of power loss during WRNVCR If a power loss occurs during a Write Non Volatile Configuration Register instruction, after the next power on the device could eventually wake up in a not determined state, for example a not required protocol or XIP mode. In that case a particular rescue sequence must be used to recover the device at a fixed state (Extended SPI protocol without XIP) until the next power up. Then to fix the problem definitively is recommended to run the Write Non Volatile configuration Register again. The rescue sequence is composed of two parts that have to be run in the correct order. During all the sequence the TSHSL must be 50ns at least. The sequence is: DQ0 (PAD DATA) equal to '1' for: 7 clock cycles within S low (S becomes high before 8th clock cycle) + 13 clock cycles within S low S becomes high before 14th clock cycle) + 25 clock cycles within S low (S becomes high before 26th clock cycle) To exit from XIP. DQ0 (PAD DATA) and DQ3 (PAD HOLD) equal to '1' for: 8 clock cycles within S low (S becomes high before 9th clock cycle) to force Normal SPI protocol. 169/185 Initial delivery state 12 N25Q128 - 1.8 V Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 13 Maximum rating Stressing the device outside the ratings listed here may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 28. Absolute maximum ratings Symbol Parameter TSTG TLEAD Storage temperature Min Max Unit –65 150 °C see(1) °C Lead temperature during soldering VIO Input and output voltage (with respect to ground) –0.6 VCC + 0.6 V VCC Supply voltage –0.6 4.0 V –0.2 10.0 V –2000 2000 V VPP VESD Fast program/erase voltage(2) Electrostatic discharge voltage (human body model)(3) 1. Compliant with JEDEC Std. J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. Avoid applying VPPH to the W/VPP pin during Bulk Erase. 3. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω). 170/185 N25Q128 - 1.8 V 14 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 29. Operating conditions Symbol VCC VPPH TA Table 30. Parameter Min Typ Unit Supply voltage 1.7 2 V Supply voltage on VPP 8.5 9.5 V Ambient operating temperature –40 85 °C AC measurement conditions Symbol Parameter Min Max Unit 30(1) Load capacitance Input rise and fall times CL Max pF 5 ns Input pulse voltages 0.2VCC to 0.8VCC V Input timing reference voltages 0.3VCC to 0.7VCC V VCC / 2 V Output timing reference voltages 1) Output Buffers are configurable by user. Figure 107. AC measurement I/O waveform Input levels Input and output timing reference levels 0.8VCC 0.7VCC 0.5VCC 0.3VCC 0.2VCC AI07455 Table 31. Symbol CIN/OUT CIN Capacitance(1) Parameter Input/output capacitance (DQ0/DQ1/DQ2/DQ3) Input capacitance (other pins) Test condition Min Max Unit VOUT = 0 V 8 pF VIN = 0 V 6 pF 1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 54 MHz. 171/185 DC and AC parameters Table 32. Symbol N25Q128 - 1.8 V DC Characteristics Parameter Test condition (in addiction to those in Table 29.: Operating conditions) Min Max Unit ILI Input leakage current ±2 µA ILO Output leakage current ±2 µA ICC1 Standby current S = VCC, VIN = VSS or VCC 70 µA ICC2 Deep Power-down current S = VCC, VIN = VSS or VCC 10 µA C = 0.1VCC / 0.9VCC at 108 MHz, DQ1 = open 15 mA C = 0.1VCC / 0.9VCC at 54 MHz, DQ1 = open 6 mA Operating current (Fast Read Dual I/O) C = 0.1VCC / 0.9VCC at 108 MHz 18 mA Operating current (Fast Read Quad I/O) C = 0.1VCC / 0.9VCC at 108 MHz 20 mA ICC4 Operating current (Page Program Single, Dual and Quad I/O) S = VCC 20 mA ICC5 Operating current (WRSR) S= VCC 20 mA ICC6 Operating current (SE) S = VCC 20 mA VIL Input low voltage – 0.5 0.3VCC V VIH Input high voltage 0.7VCC VCC+0.4 V VOL Output low voltage IOL = 1.6 mA 0.4 V VOH Output high voltage IOH = –100 µA Operating current (Fast Read Single I/O) ICC3 172/185 VCC–0.2 V N25Q128 - 1.8 V DC and AC parameters Note: The AC Characteristics data is preliminary. Table 33. AC Characteristics (page 1 of 2) Symbol fC Alt. fC fR Parameter Min Typ(2) Max Clock frequency for the all the instructions (Extended SPI, DIO-SPI and D.C. QIO-SPI protocol) but the READ instruction 108 Clock frequency for read instructions D.C. 54 Unit MHz MHz (1) tCLH Clock High time 4 ns (2) tCLL Clock Low time 4 ns tCLCH(3) Clock rise time(4) (peak to peak) 0.1 V/ns tCHCL(3) Clock fall time(4) (peak to peak) 0.1 V/ns S active setup time (relative to C) 4 ns 4 ns tCH tCL tSLCH tCSS tCHSL tDVCH tDSU Data in setup time 2 ns tCHDX tDH Data in hold time 3 ns tCHSH S active hold time (relative to C) 4 ns tSHCH S not active setup time (relative to C) 4 ns S deselect time after a correct read instruction 20 ns S deselect time after a not correct read or after any different instruction 50 ns tSHSL tCSH tSHQZ(3) tDIS tCLQV tV tCLQX tHO Output disable time 8 ns Clock Low to Output valid under 30 pF 7 ns Clock Low to Output valid under 10 pF 5 ns Output hold time 1 ns tHLCH HOLD setup time (relative to C) 4 ns tCHHH HOLD hold time (relative to C) 4 ns tHHCH HOLD setup time (relative to C) 4 ns tCHHL HOLD hold time (relative to C) 4 ns tHHQX(3) tLZ HOLD to Output Low-Z 8 ns (3) tHZ HOLD to Output High-Z 8 ns tHLQZ tWHSL (5) tSHWL(5) Write protect setup time 20 ns Write protect hold time 100 ns 173/185 DC and AC parameters Table 33. Symbol N25Q128 - 1.8 V AC Characteristics (page 2 of 2) Alt. Parameter Typ(2) Min Max Unit tVPPHSL(6) Enhanced program supply voltage High (VPPH) to Chip Select Low for Single and Dual I/O Page Program tW Write status register cycle time 1.3 tCFSR Clear flag status register cycle time 40 tWNVCR Write non volatile configuration register cycle time 0.2 tWVCR Write volatile configuration register cycle time 40 ns tWRVECR Write volatile enhanced configurationregister cycle time 40 ns tPP(7) Page program cycle time (n bytes) int(n/8) × 0.015(8) Program OTP cycle time (64 bytes) 0.4 tSSE Subsector erase cycle time 0.2 2 s tSE Sector erase cycle time 0.7 3 s tBE Bulk erase cycle time 170 250 s ns 200 8 ms ns s 3 ms 5 ms 1. tCH + tCL must be greater than or equal to 1/ fC. 2. Typical values given for TA = 25 °C 3. Value guaranteed by characterization, not 100% tested in production. 4. Expressed as a slew-rate. 5. Only applicable as a constraint for a WRSR instruction when SRWD is set to '1'. 6. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is known. Avoid applying VPPH to the W/VPP pin during Bulk Erase. 7. When using the page program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 < n < 256). 8. int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4 int(15.3) =16. Figure 108. Reset AC waveforms: program or erase cycle is in progress S tSHRH Reset tRHSL tRLRH AI06808 See Table 34.: Reset Conditions. 174/185 N25Q128 - 1.8 V Table 34. Symbol tRLRH(1)(2) DC and AC parameters Reset Conditions Alt. tRST Parameter Conditions Min Reset pulse width tRHSL(1) tREC Max Unit 50 ns 40 ns Under completion of an internal erase or program cycle related to POTP, PP, DIEFP, 30 DIFP, QIEFP, QIFP, SE, BE, PER, PES. µs Device selected (S low), while decoding any modify instruction, during all read operations, CLFSR, WRDI, WREN, WRLR, WRVCR, WRVECR. Reset Recovery Time Typ Under completion of an SSE operation. tSSE ms Under completion of an WRSR operation. tW ms Under completion of an WRNVCR operation. tWNVCR ms Under completion of the first WREN issued when Fast POR selected. tDTW µs Device deselected (S high) and in XiP mode. 40 ns Device deselected (S high) and in Standby 40 mode. ns Deselect to R valid in Quad Output or in QIO-SPI. 2 ns tDP S High to Deep Power Down mode 3 µs tRDP S High to Standby mode 30 µs S# deselect to R valid tSHRV(1) 1. All values are guaranteed by characterization and not 100% tested in production. 2. The device reset is possible but not guaranteed if tRLRH < 50 ns. Figure 109. Serial input timing tSHSL S tCHSL tSLCH tCHSH tSHCH C tDVCH tCHCL tCHDX DQ0 DQ1 MSB IN tCLCH LSB IN High Impedance AI13728 175/185 DC and AC parameters N25Q128 - 1.8 V Figure 110. Write protect setup and hold timing during WRSR when SRWD=1 W/VPP tSHWL tWHSL S C DQ0 High Impedance DQ1 AI07439c Figure 111. Hold timing S tHLCH tCHHL tHHCH C tCHHH tHLQZ tHHQX DQ1 DQ0 HOLD AI13746 176/185 N25Q128 - 1.8 V DC and AC parameters Figure 112. Output timing S tCH C tCLQV tCLQX tCLQV tCL tCLQX LSB OUT DQ1 DQ0 tSHQZ ADDR. LSB IN AI13729 Figure 113. VPPH timing End of command (identified by WIP polling) S C DQ0 VPPH VPP tVPPHSL ai13726-b 177/185 Package mechanical 15 N25Q128 - 1.8 V Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS compliant packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 114. VDFPN8 (MLP8) 8-lead very thin dual flat package no lead, 8 × 6 mm, package outline D E E2 e b D2 A L L1 K ddd A1 VDFPN-02 1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table 35. VDFPN8 (MLP8) 8-lead very thin dual flat package no lead, 8 × 6 mm, package mechanical data Millimeters Inches Symbol Typ A Min 0.85 A1 b 0.40 D 8.00 D2 5.16 6.00 E2 4.80 e 1.27 K 0.033 0.05 0.35 0.48 0.016 Max 0.000 0.002 0.014 0.019 0.039 0.315 (1) 0.203 0.002 0.236 0.189 – – 0.050 0.82 0.50 0.45 L1 – 8 – 0.032 0.60 0.020 0.018 0.15 1. D2 Max must not exceed (D – K – 2 × L). 178/185 1.00 Min 0.05 E N Typ 0.00 ddd L Max 0.024 0.006 8 N25Q128 - 1.8 V Package mechanical Figure 115. SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline D 16 h x 45˚ 9 C E 1 θ 8 A2 B H A1 A L ddd e SO-H 1. Drawing is not to scale. Table 36. SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data Millimeters Inches Symbol Typ Min Max A 2.35 A1 Min Max 2.65 0.093 0.104 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 10.10 10.50 0.398 0.413 E 7.40 7.60 0.291 0.299 – – – – H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 θ 0° 8° 0° 8° e ddd 1.27 0.10 Typ 0.050 0.004 179/185 Package mechanical Figure 116. TBGA - 6 x 8 mm, 24-ball, mechanical package outline 1. Drawing is not to scale. 180/185 N25Q128 - 1.8 V N25Q128 - 1.8 V Package mechanical Table 37. TBGA 6x8 mm 24-ball package dimensions MIN NOM A A1 MAX 1.20 0.20 A2 0.79 Øb 0.35 0.40 0.45 D 5.90 6.00 6.10 D1 E 4.00 7.90 8.00 E1 4.00 eD 1.00 eE 1.00 FD 1.00 FE 2.00 MD 5 ME 5 n 24 balls 8.10 aaa 0.15 bbb 0.10 ddd 0.10 eee 0.15 fff 0.08 Control unit: mm 181/185 Ordering information N25Q128 - 1.8 V 16 Ordering information Note: For further information on line items not listed here or on any aspect of this device, please contact your nearest Numonyx Sales Office. Table 38. Ordering information scheme Example: N25Q128 Device type N25Q = serial Flash memory, Quad I/O, XiP Device density 128 = 128 Mbit Technology A = 65 nm Feature set 1 = Byte addressability, Hold pin, Numonyx XiP 2 = Byte addressability, Hold pin, Basic XiP 3 = Byte addressability, Reset pin, Numonyx XiP 4 = Byte addressability, Reset pin, Basic XiP Operating voltage 1 = VCC = 1.7 V to 2 V Block Structure B = Bottom T = Top E = Uniform (no boot sectors) Package F8 = VDFPN8 8 x 6 mm (MLP8) (RoHS compliant) SF = SO16 (300 mils width) (RoHS compliant) 12 = TBGA24 6 x 8 mm (RoHS compliant) Temperature and test flow 4 = Industrial temperature range, –40 to 85 °C Device tested with standard test flow A = Automotive temperature range, –40 to 125 °C Device tested with high reliability certified test flow H = Industrial temperature range, –40 to 85 °C Device tested with high reliability certified test flow Security features (1) 0 = No extra security Packing options E = Tray packing F = Tape and reel packing G = Tube packing 1. Additional secure options are available upon customer request. 182/185 A 1 1 B F8 4 0 E N25Q128 - 1.8 V Table 39. Ordering information Valid Order Information Line Items Part Number Features Block Structure Package Temperature and Test Flow Security N25Q128A11BF840E N25Q128A11BF840F Byte addressability, Hold pin, Numonyx XiP Bottom VDFPN8 8x6 mm Industrial temp; Standard test flow No extra security N25Q128A21BF840E N25Q128A21BF840F Byte addressability, Hold pin, Basic XiP Bottom VDFPN8 8x6 mm Industrial temp; Standard test flow No extra security N25Q128A11TF840E N25Q128A11TF840F Byte addressability, Hold pin, Numonyx XiP Top VDFPN8 8x6 mm Industrial temp; Standard test flow No extra security N25Q128A21TF840E N25Q128A21TF840F Byte addressability, Hold pin, Basic XiP Top VDFPN8 8x6 mm Industrial temp; Standard test flow No extra security N25Q128A11B1240E N25Q128A11B1240F Byte addressability, Hold pin, Numonyx XiP Bottom TBGA24 6x8 mm Industrial temp; Standard test flow No extra security N25Q128A21B1240E N25Q128A21B1240F Byte addressability, Hold pin, Basic XiP Bottom TBGA24 6x8 mm Industrial temp; Standard test flow No extra security N25Q128A11T1240E N25Q128A11T1240F Byte addressability, Hold pin, Numonyx XiP Top TBGA24 6x8 mm Industrial temp; Standard test flow No extra security N25Q128A21T1240E N25Q128A21T1240F Byte addressability, Hold pin, Basic XiP Top TBGA24 6x8 mm Industrial temp; Standard test flow No extra security N25Q128A11BSF40F N25Q128A11BSF40G Byte addressability, Hold pin, Numonyx XiP Bottom SO16 (300 Industrial temp; mils width) Standard test flow No extra security N25Q128A21BSF40F N25Q128A21BSF40G Byte addressability, Hold pin, Basic XiP Bottom SO16 (300 Industrial temp; mils width) Standard test flow No extra security N25Q128A11TSF40F N25Q128A11TSF40G Byte addressability, Hold pin, Numonyx XiP Top SO16 (300 Industrial temp; mils width) Standard test flow No extra security N25Q128A21TSF40F N25Q128A21TSF40G Byte addressability, Hold pin, Basic XiP Top SO16 (300 Industrial temp; mils width) Standard test flow No extra security Note: Packing information details: E= tray, F= tape-n-reel, G= tube (16th digit of part number). 183/185 Revision history 17 N25Q128 - 1.8 V Revision history Table 40. 184/185 Document revision history Date Revision 12-Feb-2010 1.0 Changes Initial public release. N25Q128 - 1.8 V Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2010, Numonyx B.V. All Rights Reserved. 185/185