PHILIPS N74F524D 8-bit register comparator open-collector 3-state Datasheet

INTEGRATED CIRCUITS
74F524
8-bit register comparator (open-collector
+ 3-State)
Product specification
IC15 Data Handbook
1990 Aug 07
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
FEATURES
74F524
PIN CONFIGURATION
• 8-Bit bidirectional register with bus-oriented input-output
• Independent serial input-output to register
• Register bus comparator with ‘equal to’, ‘greater than’ and
‘less than’ outputs
• Cascadable in groups of 8-bits
• Open collector comparator outputs for AND-wired expansion
• Two’s complement or magnitude compare
DESCRIPTION
The 74F524 is an 8-bit bidirectional register with parallel input and
output, plus serial input and output progressing from MSB to LSB.
All data inputs, serial and parallel, are loaded by the rising edge of
the clock. The device functions are controlled by two control lines
(S0, S1) to execute shift, load, hold and read out. An 8-bit
comparator examines the data stored in the registers and on the
data bus. Three true-High, open collector outputs representing
‘register equal to bus’, ‘register greater than bus’ and ‘register less
than bus’ are provided. These outputs can be disabled to the OFF
state by the use of Status Enable (SE). A mode control has also
been provided to allow Two’s Complement as well as magnitude
compare. Linking inputs are provided for expansion to longer words.
S0
1
20 VCC
I/O0
2
19 S1
I/O1
3
18 SE
I/O2
4
17 C/SI
I/O3
5
16 C/SO
I/O4
6
15 EQ
I/O5
7
14 GT
I/O6
8
13 LT
I/O7
9
12 M
GND
10
11 CP
SF00970
TYPE
TYPICAL fMAX
TYPICAL SUPPLY CURRENT
(TOTAL)
74F524
65MHz
110mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL
RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
20-pin plastic DIP
N74F524N
SOT146-1
20-pin plastic SOL
N74F524D
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
I/On
Parallel data inputs
3.5/1.0
70µA/0.6mA
S0, S1
Mode select inputs
1.0/1.0
20µA/0.6mA
C/SI
Status priority or serial data input
1.0/1.0
20µA/0.6mA
CP
Clock pulse input (active rising edge)
1.0/1.0
20µA/0.6mA
SE
Status enable input (active Low)
1.0/1.0
20µA/0.6mA
M
Compare mode select input
1.0/1.0
20µA/0.6mA
I/On
3-state parallel data outputs
150/40
3.0mA/24mA
C/SO
Status priority or serial data output
50/33
1.0mA/20mA
LT
Register less than bus output
OC/33
OC/20mA
EQ
Register equal to bus output
OC/33
OC/20mA
OC/33
OC/20mA
GT
Register greater than bus output
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as 20µA in the High state and 0.6mA in the Low state.
OC=Open Collector
1990 Aug 07
2
853–0373 00135
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
LOGIC SYMBOL for 74F456
17
74F524
SELECT FUNCTION TABLE
12
18
M
SE
S0
C/SI
C/SO
16
1
S0
LT
13
19
S1
GT
14
11
CP
EQ
15
S1
OPERATION
L
L
HOLD–Retains data in shift register
L
H
READ–Read contents in register onto data bus
H
L
SHIFT–Allows serial shifting on next rising clock
edge
H
H
LOAD–Load data on bus into register
H = High voltage level
L = Low voltage level
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
2
3
4
5
6
7
8
One port of an 8-bit comparator is attached to the data bus while the
other port is tied to the outputs of the internal register. Three
active-OFF Open Collector outputs indicate whether the contents
held in the shift register are ‘greater than’ (GT). ‘less than’ (LT), or
‘equal to’ (EQ) the data on the input bus. A High signal on the Status
Enable (SE) input disables these outputs to the OFF state. A mode
control (M) input allows selection between a straightforward
magnitude compare or a comparison between Two’s complement
numbers.
9
VCC = Pin 20
GND = Pin 10
SF00971
LOGIC SYMBOL (IEEE/IEC) for 74F456
COMP
1
19
0
1
11
12
17
2
3
4
0
3
0=HOLD
1=READ
2=SHIFT
3=LOAD
NUMBER REPRESENTATION SELECT TABLE
M
C4/2/4
M5 MAGNITUDE
2D
M6 TWO’s COMPLEMENT
&
18
M
L
16
H
Two’s Complement compare
H = High voltage level
L = Low voltage level
G7
3, 4D
1,5,6,7>I/O
13
1,5,6,7<I/O
14
1,5,6,7=I/O
15
For ‘greater than’ or ‘less than’ detection, the C/SI input must be
held High, as indicated in the Function Table. The internal logic is
arranged such that a Low signal on the C/SI input places the
‘greater than’ and ‘less than’ outputs in their off state. (Note that this
off state serves also as the active state when C/SI is High. It is
intended for use in expansion to word lengths greater than 8 bits
using multiple 74S524s as explained in the next 3 paragraphs.) The
C/SO output will be forced High if the ‘equal to’ status condition
exists; otherwise, C/SO will be held Low.
5
6
7
8
9
Word length expansion (in groups of 8 bits) can be achieved by
connecting the C/SO output of the more significant byte to the C/SI
input of the next less significant byte and also to its own SE input
(see Application Figure 1). The CS/I input of the most significant
device is held High while the SE input of the least significant device
is held Low. The corresponding status outputs are AND-wired
together. In the case of two’s complement number compare, only the
Mode input to the most significant device should be High. the Mode
inputs to all other cascaded devices are held Low.
SF00972
FUNCTIONAL DESCRIPTION
The 74F524 contains eight D-type flip-flops connected as a shift
register with provision for either parallel or serial loading. Parallel
data may be read from or loaded into the registers via the data bus
I/O0–I/O7. Serial data is loaded into the register from the C/SI input
and may be shifted through the register and out through the C/SO
output. Both parallel and serial data entry occurs on the rising edge
of the clock (CP). The operation of the shift register is controlled by
two signals, S0 and S1, according to the Select Function Table. The
3-State parallel output buffers are enabled only in the READ mode.
1990 Aug 07
OPERATION
Magnitude compare
Suppose that an inequality condition is detected in the most
significant device. Assuming that the byte stored in the register is
greater than the byte on the data bus, then the EQ and LT outputs
will be pulled Low, whereas the GT output will float High. Also, the
3
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
device and disables its own status outputs. In this way, the status
output proximity is handed down to the next less significant device
which now effectively becomes the most significant byte. The worst
case propagation delay for a compare operation involving ‘n’
cascaded 74F524s will be when an equality condition is detected in
all but the least significant byte. In this case, the status priority has
to ripple all the way down the chain before the correct status output
is established. Typically, this will take 35+6(n–2) ns.
CS/O output of the most significant device will be forced Low,
disabling the subsequent devices but enabling its own status
outputs. The corrected status condition is thus indicated. The same
applies if the register byte is less than the data byte, only in this
case the EQ and GT outputs go Low, whereas the LT output floats
High.
If an equality condition is detected in the most significant device, its
C/SO output is forced High. This enables the next less significant
APPLICATION
VCC
GREATER THAN
EQUAL TO
LESS THAN
L
H = TWO’s COMPLEMENT
L
L = MAGNITUDE
M
GT
EQ
M
LT
GT
EQ
LT
GT
EQ
LT
SE
SE
H
M
SE
C/SI
C/SO
S0
S1
C/SO
C/SI
S0
I/O
S1
C/SO
C/SI
I/O
S0
S1
L
I/O
RD
WR
MSB
8
8
LSB
8
SF01012
Figure 1. Cascading 74F524s for Comparing Longer Words
FUNCTION TABLE
INPUTS
OUTPUTS
SE
C/SI
S0
S1
Data comparison
EQ
GT
LT
C/SO
H
H
L
L
X
H
H
H
(1)
H
L
L
L
X
H
H
H
L
H
X
H
L
X
H
H
H
Q0
H
H
L
H
X
H
H
H
(1)
H
L
L
H
X
H
H
H
L
H
H
H
H
X
H
H
H
(1)
H
L
H
H
X
H
H
H
L
L
L
H or L2
H or L2
OA–OH > I/O0–I/O7
L
H
H
L
L
L
H or L2
H or L2
OA–OH = I/O0–I/O7
H
H
H
L
L
L
H or L2
H or L2
OA–OH < I/O0–I/O7
L
H
H
L
L
H
H or L2
H or L2
OA–OH > I/O0–I/O7
L
H
L
L
H
L2
L2
OA–OH = I/O0–I/O7
H
L
L
H
H
H or L2
H or L2
OA–OH < I/O0–I/O7
High if I/On=Dn, otherwise Low
Must meet setup and hold time requirements
High voltage level
Low voltage level
Don’t care
L
L
H
L
L
L
(1) =
2 =
H =
L =
X =
1990 Aug 07
H or
H or
4
OPERATING MODE
Hold
Shift
Read
Load
Compare
(GT=CT=off)
Compare
(GT=CT=on)
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
LOGIC DIAGRAM
S0
1
S1 19
16
C/SO
SE 18
17
C/SI
15
EQ
CP Q
I/O0
2
D
Q
CP Q
I/O1
3
I/O2
4
D
Q
CP Q
D
Q
14
GT
13
LT
CP Q
I/O3
5
D
Q
CP Q
I/O4
6
D
Q
CP Q
I/O5
7
D
Q
CP Q
I/O6
I/O7
8
D
9
Q
CP Q
D
Q
CP 11
12
M
VCC = Pin 20
GND = Pin 10
1990 Aug 07
SF00973
5
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
VCC
Supply voltage
–0.5 to +7.0
V
VIN
Input voltage
–0.5 to +7.0
V
IIN
Input current
–30 to +5
mA
VOUT
Voltage applied to output in High output state
–0.5 to +VCC
V
All except I/O
40
mA
IOUT
O
Current applied to output in Low output state
I/O only
48
mA
Tamb
Operating free-air temperature range
0 to +70
°C
Tstg
Storage temperature range
–65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
NOM
MAX
5.0
5.5
VCC
Supply voltage
4.5
VIH
High-level input voltage
2.0
VIL
Low-level input voltage
0.8
V
IIK
Input clamp current
–18
mA
VOH
High-level output voltage
IOH
O
High level output current
High-level
IOL
O
Low level output current
Low-level
Tamb
Operating free-air temperature range
1990 Aug 07
V
V
LT, EQ, GT only
4.5
V
Not LT, EQ, GT, C/SO
–3
mA
C/SO only
–1
mA
All except I/O
20
mA
I/O only
24
mA
70
°C
0
6
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
IOH
TEST CONDITIONSNO TAG
PARAMETER
High-level output current
LT, EQ, GT
only
C/SO only
VOH
High-level output voltage
I/On only
VOL
O
Low level output voltage
Low-level
VIK
Input clamp voltage
II
Input current at maximum
input voltage
IIH
High-level input current
IIL
Low-level input current
IOZH
Off-state output current
High-level voltage applied
LIMITS
MIN
TYP2
VCC = MIN, VIL = MAX,
VIH = MIN, VOH = MAX
MIN
VCC = MIN,
VIL = MAX,
VIH = MIN
IOH=MAX
VCC = MIN,
VIL = MAX
MAX,
VIH = MIN
IOL
O = MAX
MAX
250
UNIT
µA
±10%VCC
2.5
V
±10%VCC
2.4
V
±5%VCC
2.7
3.4
V
±10%VCC
0.35
0.50
V
±5%VCC
0.35
0.50
V
–0.73
–1.2
V
I/On
VCC = MIN, II = IIK
VCC = MAX, VI = 5.5V
1
mA
Except I/On
VCC = MAX, VI = 7.0V
100
µA
Except I/On
VCC = MAX, VI = 2.7V
20
µA
VCC = MAX, VI = 0.5V
–0.6
mA
VCC = MAX, VO = 2.7V
70
µA
VCC = MAX, VO = 0.5V
–0.6
mA
–150
mA
150
mA
I/On only
IOZL
Off-state output current
Low-level voltage applied
IOS
Short-circuit output
current3
ICC
Supply current (total)
Except LT,
EQ, GT
VCC = MAX
–60
VCC = MAX
110
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
1990 Aug 07
7
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
VCC = +5V
Tamb = +25°C
CL = 50pF, RL = 500Ω
TEST
CONDITION
MIN
TYP
VCC = +5V ± 10%
Tamb = 0°C to +70°C
CL = 50pF, RL = 500Ω
MAX
MIN
UNIT
MAX
fMAX
Maximum clock frequency
Waveform 4
50
65
tPLH
tPHL
Propagation delay
I/On to EQ
Waveform 2
9.0
4.5
11.5
7.5
17.0
11.0
9.0
4.5
18.0
12.0
ns
tPLH
tPHL
Propagation delay
I/On to GT
Waveform 2
8.5
6.5
11.0
9.5
17.0
15.5
8.5
6.5
18.0
16.5
ns
tPLH
tPHL
Propagation delay
I/On to LT
Waveform 2
8.0
6.0
11.0
10.5
17.0
14.0
8.0
6.0
18.0
15.0
ns
tPLH
tPHL
Propagation delay
I/On to C/SO
Waveform 2
7.0
6.5
13.0
9.0
16.0
14.0
7.0
5.5
17.0
15.0
ns
tPLH
tPHL
Propagation delay
CP to EQ
Waveform 4
11.0
4.0
17.0
8.0
22.0
14.0
10.0
4.0
23.0
15.0
ns
tPLH
tPHL
Propagation delay
CP to GT
Waveform 4
11.0
10.0
16.0
16.5
20.0
21.0
10.0
10.0
21.0
22.0
ns
tPHL
tPLH
Propagation delay
CP to LT
Waveform 4
11.0
8.0
16.0
14.0
23.0
18.0
10.0
8.0
24.0
19.0
ns
tPLH
Propagation delay
CP to C/SO (Load)
Waveform 4
10.0
16.0
20.0
10.0
21.0
ns
tPLH
tPHL
Propagation delay
CP to C/SO (Serial shift)
Waveform 4
5.0
4.5
10.0
9.0
13.0
11.5
5.0
4.5
14.0
12.5
ns
tPLH
tPHL
Propagation delay
C/SI to GT
Waveform 1
8.0
3.0
10.5
4.5
16.0
8.5
9.0
2.5
17.0
9.5
ns
tPLH
tPHL
Propagation delay
C/SI to LT
Waveform 1
8.0
3.0
10.5
6.0
17.0
8.5
8.0
2.5
18.0
9.5
ns
tPLH
tPHL
Propagation delay
Sn to C/SO
Waveform 2
6.5
5.5
8.0
10.0
14.5
17.0
6.5
5.5
15.5
18.0
ns
tPLH
tPHL
Propagation delay
SE to EQ
Waveform 2
3.5
2.5
7.0
4.5
10.5
8.0
3.5
2.5
11.5
9.0
ns
tPLH
tPHL
Propagation delay
SE to GT
Waveform 2
6.0
3.5
8.0
5.0
13.0
8.0
6.0
3.0
14.0
9.0
ns
tPLH
tPHL
Propagation delay
SE to LT
Waveform 2
5.0
3.5
8.0
5.5
12.0
8.0
5.0
3.0
13.0
9.0
ns
tPLH
tPHL
Propagation delay
C/SI to C/SO
Waveform 2
4.0
4.0
7.0
7.0
11.0
11.0
4.0
4.0
12.0
12.0
ns
tPLH
tPHL
Propagation delay
M to GT
Waveform 2
8.0
8.0
13.0
10.0
18.0
15.5
8.0
8.0
19.0
16.5
ns
tPLH
tPHL
Propagation delay
M to LT
Waveform 2
10.0
6.0
15.0
8.0
20.0
12.0
10.0
5.0
21.0
13.0
ns
tPZH
tPZL
Output Enable time
Sn to I/On
Waveform
NO TAG
Waveform
NO TAG
4.5
5.5
7.0
9.0
13.0
15.0
4.5
5.5
14.0
16.0
ns
tPHZ
tPLZ
Output Disable time
Sn to I/On
Waveform
NO TAG
Waveform
NO TAG
3.0
4.5
5.0
8.0
12.0
12.5
2.0
4.5
13.0
13.5
ns
1990 Aug 07
8
45
MHz
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
TYP
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN
UNIT
MAX
ts(H)
ts(L)
Setup time, High or Low
I/On to CP
Waveform 3
6.0
6.0
6.0
6.0
ns
th(H)
th(L)
Hold time, High or Low
I/On to CP
Waveform 3
0
0
0
0
ns
ts(H)
ts(L)
Setup time, High or Low
S0, S1 to CP
Waveform 3
13.5
10.0
15.0
10.0
ns
th(H)
th(L)
Hold time, High or Low
S0, S1 to CP
Waveform 3
0
0
0
0
ns
ts(H)
ts(L)
Setup time, High or Low
C/SI to CP
Waveform 3
7.0
7.0
7.0
7.0
ns
th(H)
th(L)
Hold time, High or Low
C/SI to CP
Waveform 3
0
0
0
0
ns
tw(H)
tw(L)
CP pulse width,
High or Low
Waveform 4
5.0
10.0
5.0
10.0
ns
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
C/SI
VM
tPHL
GT, LT
SE, C/SI, M
I/On, Sn
VM
VM
VM
tPHL
tPLH
VM
EQ, C/SO
GT, LT
VM
tPLH
VM
VM
SF00974
SF00975
Waveform 1. Propagation Delay for Inverting Outputs
Waveform 2. Propagation Delay for Non-Inverting Outputs
1/fMAX
C/SI,
I/On,
Sn
VM
ts(H)
VM
th(H)
VM
ts(L)
CP
VM
VM
VM
tW(L)
tW(H)
th(L)
tPHL
CP
VM
tPLH
VM
EQ, C/SO,
GT, LT
SF00976
VM
VM
SF00977
Waveform 3. Setup and Hold Times
Waveform 4. Propagation Delay, Clock to Output,
Clock Pulse Width, and Maximum Clock Frequency
1990 Aug 07
9
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
AC WAVEFORMS (Continued)
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VM
Sn
tPZH
VM
tPZL
VOH -0.3V
tPHZ
I/On
VM
Sn
VM
tPLZ
VM
I/On
VM
0V
VOL +0.3V
SF00978
SF00979
Waveform 6. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
Waveform 5. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
TEST CIRCUIT AND WAVEFORMS
VCC
7.0V
VIN
RL
VOUT
PULSE
GENERATOR
tw
90%
NEGATIVE
PULSE
VM
CL
AMP (V)
VM
10%
D.U.T.
RT
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
0V
RL
AMP (V)
90%
90%
Test Circuit for 3-State Outputs
and Open Collector Outputs
POSITIVE
PULSE
VM
VM
10%
10%
tw
0V
SWITCH POSITION
TEST
tPLZ, tPZL
Open Collector
All other
SWITCH
closed
closed
open
DEFINITIONS:
RL = Load resistor;
see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude VM
74F
3.0V
1.5V
rep. rate
tw
tTLH
tTHL
1MHz
500ns
2.5ns
2.5ns
SF00980
1990 Aug 07
10
Philips Semiconductors
Product specification
8-bit register comparator (open-collector + 3-State)
DIP20: plastic dual in-line package; 20 leads (300 mil)
1990 Aug 07
11
74F524
SOT146-1
Philips Semiconductors
Product specification
8-bit register comparator (open-collector + 3-State)
SO20: plastic small outline package; 20 leads; body width 7.5 mm
1990 Aug 07
12
74F524
SOT163-1
Philips Semiconductors
Product specification
8-bit register comparator (open-collector + 3-State)
NOTES
1990 Aug 07
13
74F524
Philips Semiconductors
Product specification
8-bit register comparator (open-collector + 3-State)
74F524
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Document order number:
yyyy mmm dd
14
Date of release: 10-98
9397-750-05131