Numonyx NAND16GW3C2BZL1F 8 or 16 gbit, 2112 byte page, 3 v supply, multilevel, multiplane, nand flash memory Datasheet

NAND08GW3C2B
NAND16GW3C4B
8 or 16 Gbit, 2112 byte page,
3 V supply, multilevel, multiplane, NAND Flash memory
Target Specification
Features
■
High density multilevel cell (MLC) Flash
memory
– Up to 16 Gbit memory array
– Up to 512 Mbit spare area
– Cost-effective solutions for mass storage
applications
■
NAND interface
– x8 bus width
– Multiplexed address/data
■
Supply voltage: VDD = 2.7 to 3.6 V
■
Page size: (2048 + 64 spare) bytes
■
Block size: (256K + 8K spare) bytes
■
Multiplane architecture
– Array split into two independent planes
– Program/erase operations can be
performed on both planes at the same time
TSOP48 12 x 20 mm (N)
LGA52 12 x 17 mm (N)
■
Serial number option
■
Chip enable ‘don’t care’
■
Memory cell array:
(2 K + 64 ) bytes x 128 pages x 4096 blocks
■
■
Page read/program
– Random access: 60 µs (max)
– Sequential access: 25 ns (min)
– Page program operation time: 800 µs (typ)
Data protection
– Hardware program/erase locked during
power transitions
■
Development tools
– Error correction code models
– Bad block management and wear leveling
algorithm
– HW simulation models
■
Data integrity
– 10,000 program/erase cycles (with ECC)
– 10 years data retention
■
ECOPACK® packages available
■
Multipage program time (2 pages): 800 µs (typ)
■
Copy-back program
– Fast page copy
■
Fast block erase
– Block erase time: 2.5 ms (typ)
■
Multiblock erase time (2 blocks): 2.5 ms (typ)
■
Status register
■
Electronic signature
March 2008
Rev 2
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1/60
www.numonyx.com
1
NAND08GW3C2B, NAND16GW3C4B
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
3
4
Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2
Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3
Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
Chip Enable (E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5
Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8
Ready/Busy (RB1, RB2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9
VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.10
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4
Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5
Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/60
6.1
Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2
Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3
Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4
Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
NAND08GW3C2B, NAND16GW3C4B
6.5
Sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.6
Random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.7
Copy-back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.8
Multiplane copy-back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.9
Multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.10
Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.11
Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.12
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.13
Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.14
6.13.1
Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.13.2
P/E/R controller bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.13.3
Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7
Concurrent operations and ERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8
Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9
Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1
Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.2
NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.3
Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.4
Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.5
Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.5.1
Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.5.2
IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 41
11
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12.1
13
Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 54
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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NAND08GW3C2B, NAND16GW3C4B
14
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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NAND08GW3C2B, NAND16GW3C4B
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Address definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Paired page address information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Device identifier codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Electronic signature byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Electronic signature byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Extended Read Status Register commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Program and erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . 41
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 56
LGA52 12 x 17 mm, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 57
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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NAND08GW3C2B, NAND16GW3C4B
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
6/60
Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TSOP48 connections for NAND08GW3C2B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TSOP48 connections for NAND16GW3C4B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ULGA52 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Random data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Copy-back Program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Copy-back Program operation with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Multiplane Copy-back Program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Block Erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Multiplane block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Command latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Address latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Data input latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Sequential data output after Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Sequential data output after Read AC waveforms (EDO mode). . . . . . . . . . . . . . . . . . . . . 48
Read Status Register AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Read electronic signature AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Page read operation AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Page program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Block erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Program/erase enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Program/erase disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 55
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 56
LGA52 12 x 17 mm, 1 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
NAND08GW3C2B, NAND16GW3C4B
1
1 Description
Description
The NAND08GW3C2B and NAND16GW3C4B are multilevel cell (MLC) devices from the
NAND Flash 2112-byte page family of non-volatile Flash memories. The NAND08GW3C2B
and the NAND16GW3C4B have a density of 8- and 16-Gbit, respectively. The
NAND16GW3C4B is composed of two 8-Gbit dice; each die can be accessed independently
using two Chip Enable and two Ready/Busy signals. The devices operate from a 3 V VDD
power supply.
The address lines are multiplexed with the data input/output signals on a multiplexed
x8 input/output bus. This interface reduces the pin count and makes it possible to migrate to
other densities without changing the footprint.
Each block can be programmed and erased over 10,000 cycles (with error correction code
(ECC) on). The device also has hardware security features; a write protect pin is available to
provide hardware protection against program and erase operations.
The devices feature an open-drain, ready/busy output that identifies if the
Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output
allows the ready/busy pins of several memories to be connected to a single pull-up resistor.
The memory array is split into 2 planes of 2048 blocks each. This multiplane architecture
makes it possible to program 2 pages at a time (one in each plane) or to erase 2 blocks at a
time (one in each plane), dividing by two the average program and erase times.
The devices have the Chip Enable ’don’t care’ feature, which allows code to be directly
downloaded by a microcontroller, as Chip Enable transitions during the latency time do not
stop the Read operation.
There is the option of a unique identifier (serial number), which allows the
NAND08GW3C2B and the NAND16GW3C4B to be uniquely identified. It is subject to an
NDA (non-disclosure agreement) and is, therefore, not described in the datasheet. For more
details of this option contact your nearest Numonyx sales office.
The devices are available in TSOP48 (12 × 20 mm) and LGA52 (12 x 17 x 0.65 mm)
packages. They are shipped from the factory with block 0 always valid and the memory
content bits, in valid blocks, erased to ‘1’.
Refer to the list of available part numbers and to Table 26: Ordering information scheme for
information on how to order these options.
7/60
1 Description
Table 1.
NAND08GW3C2B, NAND16GW3C4B
Device summary
Timings
Part number
Density
NAND08GW3
C2B
Bus
width
Page
size
Block
size
8 Gb
x8
NAND16GW3
C4B(1)
2048+
64
bytes
256K
+8K
bytes
16 Gb
Memory
array
Operating
Random
Block Package
Page
Sequential
voltage
access
program erase
access
(VDD)
time
(typ)
(typ)
time (min)
(max)
128
pages x
4096
blocks
128
pages x
8192
blocks
TSOP48
ULGA52
2.7 to
3.6 V
25 ns
60 µs
800 µs
2.5
ms
TSOP48
ULGA52
1. The NAND16GW3C4B is composed of two 8-Gbit dice.
Figure 1.
Logic block diagram
AL
CL
W
E1
E2
WP
R
Command
interface
logic
P/E/R controller
high voltage
generator
X Decoder
Address
register/counter
NAND Flash
memory array
Page buffer
Y decoder
Command register
Data register
Buffers
RB1
RB2
I/O
AI13296b
1. E2 and RB2 are only present in the NAND16GW3C4B.
8/60
NAND08GW3C2B, NAND16GW3C4B
Figure 2.
1 Description
Logic diagram
VDD
E1
I/O0 - I/O7 x8
E2
R
NAND Flash
W
RB1
AL
RB2
CL
WP
VSS
AI13632b
1. E2 and RB2 are only present in the NAND16GW3C4A.
Table 2.
Signal names
Signal
Function
Direction
I/O0 - I/O7
Data input/outputs(1)
Input/output
CL
Command Latch Enable
Input
AL
Address Latch Enable
Input
E1, E2
Chip Enable(2)
Input
R
Read Enable
Input
W
Write Enable
Input
WP
Write Protect
Input
RB1, RB2
Ready/Busy (open drain output)(2)
Output
VDD
Power supply
Power supply
VSS
Ground
Ground
NC
No connection
DU
Do not use
1. On the LGA52 package, each 8-Gbit die is accessed and controlled via two sets of I/Os and control
signals.
2. E2 and RB2 are only present in the NAND16GW3C4B.
9/60
1 Description
Figure 3.
NAND08GW3C2B, NAND16GW3C4B
TSOP48 connections for NAND08GW3C2B
NC
NC
NC
NC
NC
NC
RB
R
E
NC
NC
VDD
VSS
NC
NC
CL
AL
W
WP
NC
NC
NC
NC
NC
1
48
NAND Flash
12
13
24
37
36
25
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
VDD
VSS
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
AI13633
10/60
NAND08GW3C2B, NAND16GW3C4B
Figure 4.
1 Description
TSOP48 connections for NAND16GW3C4B
NC
NC
NC
NC
NC
RB2
1
48
RB1
R
E1
E2
NC
VDD
VSS
NC
NC
CL
AL
W
WP
NC
NC
NC
NC
NC
12
37
NAND FLASH
13
36
24
25
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
VDD
VSS
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
AI13169
11/60
1 Description
Figure 5.
NAND08GW3C2B, NAND16GW3C4B
ULGA52 connections
0
OA
1
2
5
NC
CL1
E1
VSS
NC
W1
I/O61
VSS
NC
NC
I/O42
NC
K
L
I/O52
VDD
I/O32
J
I/O62
I/O41
VSS
NC
G
H
I/O51
I/O31
I/O22
F
I/O71
I/O21
D
E
I/O72
WP2
I/O11
NC
NC
RB2
RB1
B
C
R1
VSS
I/O01
I/O12
A
NC
R2
AL2
I/O02
OF
8
NC
E2
WP1
OE
7
VDD
CL2
W2
OD
6
NC
AL1
OC
4
NC
NC
OB
3
NC
M
N
NC
NC
AI13634
1. On the LGA52 package, each 8-Gbit die is accessed and controlled via two sets of signals.
12/60
NAND08GW3C2B, NAND16GW3C4B
2
2 Memory array organization
Memory array organization
The memory array is comprised of NAND structures where 32 cells are connected in series.
The memory array is organized into blocks where each block contains 128 pages. The array
is split into two areas, the main area and the spare area. The main area of the array stores
data, whereas the spare area typically stores software flags or bad block identification.
The pages are split into a 2048-byte main area and a spare area of 64 bytes. Refer to
Figure 6: Memory array organization.
2.1
Bad blocks
The NAND08GW3C2B and NAND16GW3C4B devices may contain bad blocks, where the
reliability of blocks that contain one or more invalid bits is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
The bad block Information is written prior to shipping (refer to Section 9.1: Bad block
management for more details).
Table 3: Valid blocks shows the minimum number of valid blocks in each device. The values
shown include both the bad blocks that are present when the device is shipped and the bad
blocks that could develop later on.
These blocks need to be managed using bad blocks management and block replacement
(refer to Section 9: Software algorithms).
Table 3.
Valid blocks(1)
Density of device
Minimum
Maximum
8 Gbits
4016
4096
16 Gbits
8032
8192
1. The NAND16GW3C4B is composed of two 8-Gbit dice. The minimum number of valid blocks is 4096 for
each die.
13/60
2 Memory array organization
Figure 6.
NAND08GW3C2B, NAND16GW3C4B
Memory array organization
x8 bus width
Plane = 2048 blocks
Block = 128 Pages
Page = 2112 Bytes (2,048 + 64)
First Plane
Second Plane
a
re
a
Sp
Are
a
re
pa
Are
S
Main Area
Main Area
2048 Bytes
2048 Bytes
Block
Page
8 bits
64
Bytes
Page Buffer, 2112 Bytes
2,048 Bytes
64
Bytes
64
Bytes
Page Buffer, 2112 Bytes
2,048 Bytes
64
Bytes
8 bits
2 Page Buffer, 2x 2112 Bytes
AI13170
14/60
NAND08GW3C2B, NAND16GW3C4B
3
3 Signal descriptions
Signal descriptions
See Figure 1: Logic block diagram, and Table 2: Signal names for a brief overview of the
signals connected to this device.
3.1
Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 are used to input the selected address, output the data during a read
operation, or input a command or data during a write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
3.2
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
3.3
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
3.4
Chip Enable (E1, E2)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, VIL, the device is selected. If Chip Enable goes
High, vIH, while the device is busy, the device remains selected and does not go into standby
mode.
E2 is only available on the NAND16GW3C4B.
3.5
Read Enable (R)
The Read Enable pin, R, controls the sequential data output during read operations. Data is
valid tRLQV after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
3.6
Write Enable (W)
The Write Enable input, W, controls writing to the command interface, input address, and
data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 µs (min) is required before the
command interface is ready to accept a command. It is recommended to keep Write Enable
High during the recovery time.
15/60
3 Signal descriptions
3.7
NAND08GW3C2B, NAND16GW3C4B
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted
Program or Erase operations. When Write Protect is Low, VIL, the device does not accept
any Program or Erase operations.
It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.
3.8
Ready/Busy (RB1, RB2)
The Ready/Busy output, RB, is an open-drain output that can identify if the P/E/R controller
is currently active.
When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the
operation completes, Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low indicates that one, or more, of the memories is
busy.
During power-up and power-down a minimum recovery time of 10 µs is required before the
command interface is ready to accept a command. During this period the Ready/Busy signal
is Low, VOL.
RB2 is only available on the NAND16GW3C4B.
Refer to Section 12.1: Ready/Busy signal electrical characteristics for details on how to
calculate the value of the pull-up resistor.
3.9
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for operations (read, program and erase).
3.10
VSS ground
Ground, VSS, is the reference for the power supply. It must be connected to the system
ground.
16/60
NAND08GW3C2B, NAND16GW3C4B
4
4 Bus operations
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section. See the summary in Table 4: Bus operations.
Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
4.1
Command input
Command input bus operations give commands to the memory. Commands are accepted
when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low
and Read Enable is High. They are latched on the rising edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 20 and Table 22 for details of the timings requirements.
4.2
Address input
Address input bus operations input the memory addresses. Five bus cycles are required to
input the addresses (refer to Table 5: Address insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See Figure 21 and Table 22 for details of the timings requirements.
4.3
Data input
Data input bus operations input the data to be programmed. Data is only accepted when
Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read
Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is
input sequentially using the Write Enable signal.
See Figure 22 and Table 22 for details of the timing requirements.
4.4
Data output
Data output bus operations read the data in the memory array, the status register, the
electronic signature, and the unique identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
If the Read Enable pulse frequency is lower then 33 MHz (tRLRL higher than 30 ns), the
output data is latched on the rising edge of Read Enable signal (see Figure 23).
17/60
4 Bus operations
NAND08GW3C2B, NAND16GW3C4B
For higher frequencies (tRLRL lower than 30 ns), the extended data out (EDO) mode must be
considered. In this mode, data output is valid on the input/output bus for a time of tRLQX after
the falling edge of Read Enable signal (see Figure 24).
See Table 23 for details on the timings requirements.
4.5
Write protect
Write protect bus operations protect the memory against program or erase operations.
When the Write Protect signal is Low the device does not accept program or erase
operations, therefore, the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection, even during power-up.
4.6
Standby
The memory enters standby mode by holding Chip Enable, E, High for at least 10 µs. In
standby mode, the device is deselected, outputs are disabled and power consumption is
reduced.
Table 4.
Bus operations
Bus operation
E
AL
CL
R
WP
I/O0 - I/O7
Command
Command input
VIL
VIL
VIH
VIH
Rising
X(1)
Address input
VIL
VIH
VIL
VIH
Rising
X
Address
Data input
VIL
VIL
VIL
VIH
Rising
VIH
Data input
Data output
VIL
VIL
VIL
Falling
VIH
X
Data output
Write protect
X
X
X
X
X
VIL
X
Standby
VIH
X
X
X
X
VIL/VDD
X
1. WP must be VIH when issuing a program or erase command.
18/60
W
NAND08GW3C2B, NAND16GW3C4B
Table 5.
4 Bus operations
Address insertion(1)
Bus cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
A7
A6
A5
A4
A3
A2
A1
A0
nd
VIL
VIL
VIL
VIL
A11
A10
A9
A8
rd
A19
A18
A17
A16
A15
A14
A13
A12
4th
A27
A26
A25
A24
A23
A22
A21
A20
A30
A29
A28
2
3
th
5
VIL
VIL
VIL
VIL
A31
(2)
1. Any additional address input cycles are ignored.
2. A31 is valid only for the NAND16GW3C4B.
Table 6.
Address definitions
Address
Definition
A0 - A11
Column address
A12 - A18
Page address
A19 - A31
Block address
19/60
5 Command set
5
NAND08GW3C2B, NAND16GW3C4B
Command set
All bus write operations to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is High. Device operations are selected by writing
specific commands to the Command Register. The two-step command sequences for
Program and Erase operations are imposed to maximize data security.
The commands are summarized in Table 7: Commands.
Table 7.
Commands
Bus write operations(1)
Command
1st cycle
2nd cycle
Page Read
00h
30h
Read for copy-back
00h
35h
Read ID
90h
Reset
FFh
Page Program
80h
10h
Multiplane Page Program
80h
11h
Copy-back Program
85h
10h
Multiplane Copy Back Program
85h
11h
Block Erase
60h
D0h
Multiplane Block Erase
60h
60h
Read Status Register
70h
Random Data Input
85h
Random Data Output
05h
3rd cycle
4th cycle
Commands
accepted
during busy
Yes
81h
10h
81h
10h
D0h
Yes
E0h
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or
input/output data are not shown.
20/60
NAND08GW3C2B, NAND16GW3C4B
6
6 Device operations
Device operations
This section gives the details of the device operations.
6.1
Read memory array
At power-up the device defaults to read mode. To enter read mode from another mode the
Read command must be issued, see Table 7: Commands. Once a read command is issued,
subsequent consecutive read commands only require the confirm command code (30h).
Once a read command is issued, two types of operations are available: random read and
page read.
6.2
Random read
Each time the Read command is issued, the first read is random-read.
6.3
Page read
After the first random read access, the page data (2112 bytes) is transferred to the page
buffer in a time of tWHBH (refer to Table 23 for value). Once the transfer is complete, the
Ready/Busy signal goes High. The data can then be read out sequentially (from the
selected column address to last column address) by pulsing the Read Enable signal.
The device can output random data in a page, instead of the consecutive sequential data, by
issuing a Random Data Output command. The Random Data Output command can be used
to skip some data during a sequential data output.
The sequential operation can be resumed by changing the column address of the next data
to be output, to the address which follows the Random Data Output command.The Random
Data Output command can be issued as many times as required within a page.
21/60
6 Device operations
Figure 7.
NAND08GW3C2B, NAND16GW3C4B
Read operations
CL
E
W
AL
R
tBLBH1
RB
I/O
00h
Address Input
Command
Code
30h
Command
Code
Data Output (sequentially)
Busy
Ai11016
1. Highest address depends on device density.
22/60
NAND08GW3C2B, NAND16GW3C4B
Figure 8.
6 Device operations
Random data output
tBLBH1
(Read Busy time)
RB
Busy
R
I/O
000h
Address
Inputs
Cmd
Code
30h
Data Output
Cmd
Code
05h
Address
Inputs
Cmd
Code
5 Add cycles
Row Add 1,2,3 Col Add 1,2
E0h
Data Output
Cmd
Code
2Add cycles
Col Add 1,2
Main Area
Spare
Area
Main Area
Spare
Area
ai08658b
6.4
Page program
The page program operation is the standard operation to program data to the memory array.
Generally, data is programmed sequentially, however, the device does support random input
within a page.
The memory array is programmed by page, however, partial page programming is allowed
where any number of bytes (1 to 2112) can be programmed.
Only one consecutive partial page program operation is allowed on the same page. After
exceeding this a Block Erase command must be issued before any further program
operations can take place in that page.
When a program operation is abnormally aborted (such as during a power-down), the page
data under program data as well as the paired page data may be damaged (see Table 8:
Paired page address information).
23/60
6 Device operations
NAND08GW3C2B, NAND16GW3C4B
Table 8.
Paired page address information
Paired page address
24/60
Paired page address
00h
04h
01h
05h
02h
08h
03h
09h
06h
0Ch
07h
0Dh
0Ah
10h
0Bh
11h
0Eh
14h
0Fh
15h
12h
18h
13h
19h
16h
1Ch
17h
1Dh
1Ah
20h
1Bh
21h
1Eh
24h
1Fh
25h
22h
28h
23h
29h
26h
2Ch
27h
2Dh
2Ah
30h
2Bh
31h
2Eh
34h
2Fh
35h
32h
38h
33h
39h
36h
3Ch
37h
3Dh
3Ah
40h
3Bh
41h
3Eh
44h
3Fh
45h
42h
48h
43h
49h
46h
4Ch
47h
4Dh
4Ah
50h
4Bh
51h
4Eh
54h
4Fh
55h
52h
58h
53h
59h
56h
5Ch
57h
5Dh
5Ah
60h
5Bh
61h
5Eh
64h
5Fh
65h
62h
68h
63h
69h
66h
6Ch
67h
6Dh
6Ah
70h
6Bh
71h
6Eh
74h
6Fh
75h
72h
78h
73h
79h
76h
7Ch
77h
7Dh
7Ah
7Eh
7Bh
7Fh
NAND08GW3C2B, NAND16GW3C4B
6.5
6 Device operations
Sequential input
To input data sequentially the addresses must be sequential and remain in one block.
For sequential input, each page program operation comprises five steps:
6.6
1.
One bus cycle is required to set up the Page Program (sequential input) command (see
Table 7).
2.
Five bus cycles are then required to input the program address (refer to Table 5).
3.
The data is loaded into the data registers.
4.
One bus cycle is required to issue the Page Program Confirm command to start the
P/E/R controller. The P/E/R only starts if the data has been loaded in step 3.
5.
The P/E/R controller then programs the data into the array.
Random data input
During a sequential input operation, the next sequential address to be programmed can be
replaced by a random address issuing a Random Data Input command. The following two
steps are required to issue the command:
1.
One bus cycle is required to setup the Random Data Input command (see Table 7).
2.
Two bus cycles are then required to input the new column address (refer to Table 5).
Random data input operations can be repeated as often as required in any given page.
Once the program operation has started the Status Register can be read using the Read
Status Register command. During program operations the status register only flags errors
for bits set to ‘1’ that have not been successfully programmed to ‘0’.
During the program operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored. Once the program operation has completed, the
P/E/R controller bit SR6 is set to ‘1’ and the Ready/Busy signal goes High.
The device remains in read Status Register mode until another valid command is written to
the command interface.
Figure 9.
Page program operation
tBLBH2
(Program Busy time)
RB
Busy
I/O
80h
Page Program
Setup Code
Address Inputs
Data Input
10h
Confirm
Code
70h
SR0
Read Status Register
ai08659
25/60
6 Device operations
NAND08GW3C2B, NAND16GW3C4B
Figure 10. Random data input during sequential data input
tBLBH2
(Program Busy time)
RB
Busy
I/O
80h
Address
Inputs
Data Intput
85h
Cmd
Code
Cmd
Code
5 Add cycles
Row Add 1,2,3 Col Add 1,2
Main Area
Spare
Area
Address
Inputs
2 Add cycles
Col Add 1,2
Data Input
10h
Confirm
Code
Main Area
70h
SR0
Read Status Register
Spare
Area
ai08664
6.7
Copy-back program
The copy-back program with read for copy-back operation is configured to quickly and
efficiently rewrite data stored in one page without data reloading when the bit error is not in
data stored.
Since the time-consuming re-loading cycles are removed, the system performance is
improved. The benefit is especially obvious when a portion of a block is updated and the rest
of the block also needs to be copied to the newly-assigned free block. The copy-back
operation is a sequential execution of read for copy-back and copy-back program with the
destination page address. A read operation with a 35h command in the address of the
source page moves the entire 2112 bytes into the internal data buffer. A bit error is checked
by sequentially reading the data output. In the case where there is no bit error, the data does
not need to be reloaded. Therefore, the copy-back program operation is initiated by issuing
the Page-Copy Data-Input command (85h) with destination page address.
The actual programming operation begins after the Program Confirm command (10h) is
issued. Once the program process starts, the Read Status Register command (70h) may be
entered to read the Status Register. The system controller can detect the completion of a
program cycle by monitoring the RB#output, or the status bit (I/O 6) of the Status Register.
When the copy-back program is complete, the write status bit (I/O 0) may be checked. The
Command Register remains in read status command mode until another valid command is
written to the command register. During the copy-back program, data modification is
possible using random data input command (85h) as shown in Figure 11.
26/60
NAND08GW3C2B, NAND16GW3C4B
6 Device operations
Figure 11. Copy-back Program operation
I/O
00h
Source
Add Inputs
35h
85h
Read
Code
Target
Add Inputs
10h
70h
Copy Back
Code
SR0
Read Status Register
tBLBH1
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Busy
ai09858b
Figure 12. Copy-back Program operation with random data input
I/O
00h
Source
Add Inputs 35h
Read
Code
85h
Copy Back
Code
tBLBH1
Target
Add Inputs
Data
85h
2 Cycle
Add Inputs
Data
10h
70h
SR0
Unlimited number of repetitions
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Busy
ai11001
27/60
6 Device operations
6.8
NAND08GW3C2B, NAND16GW3C4B
Multiplane copy-back program
The two-plane copy-back program operation is an extension of the copy-back program
operation, which is for a single plane with 2112 byte page registers. As the device is
equipped with two memory planes, this operation activates the two sets of 2112 bytes.
Figure 13. Multiplane Copy-back Program operation
I/O
00h
Add. 5
cycles
35h
00h
Copy back
code
Copy back
code
Read
code
Read
code
Add. 5
cycles
35h
85h
Col. Add. 1, 2
Col. Add. 1, 2
Row Add. 1, 2, 3
Row Add. 1, 2, 3
Source address on 1st plane Source address on 2nd plane
tBLBH1
tBLBH1
(Read Busy time)
(Read Busy time)
Add. 5
cycles
2
11h
Col. Add. 1, 2
Row Add. 1, 2, 3
Destination address
A0-A11 = set to 'Low'
A12-A18 = set to 'Low'
A19 = set to 'Low'
A20-A30 = set to 'Low'
Add. 5
cycles
10h
tIPBSY
tBLBH2
(Program Busy time)
Busy
Busy
Busy
Second plane
First plane
Source page
Source page
Target page
Target page
(1)
Main area
(1): Read for copy back on first plane
(2): Read for copy back on second plane
(3)
(2)
Spare area
Main area
(3)
(3): Two-plane copy back program
Spare area
ai13172d
28/60
70h
Col. Add. 1, 2
Row Add. 1, 2, 3
Destination address
A0-A11 = set to 'Low'
A12-A18 = Valid
A19 = set to 'High'
A20-A30 = Valid
RB
Busy
81h
Read Status Register
SR0
NAND08GW3C2B, NAND16GW3C4B
6.9
6 Device operations
Multiplane page program
The devices support multiplane page program, that allows the programming of two pages in
parallel, one in each plane.
A multiplane page program operation requires two steps:
1.
2.
The first step loads serially up to two pages of data (4224 bytes) into the data buffer. It
requires:
–
One clock cycle to set up the Page Program command (see Section 6.5:
Sequential input).
–
Five bus write cycles to input the first page address and data. The address of the
first page must be within the first plane (A19 = 0).
–
One bus write cycle to issue the Page Program Confirm code. After this the device
is busy for a time of tBLBH5.
–
When the device returns to the ready state (Ready/Busy High), a multiplane page
program setup code must be issued, followed by the second page address (5 write
cycles) and data. The address of the second page must be within the second
plane (A19=1), and A18 to A12 must be the address bits loaded during the first
address insertion.
The second step programs, in parallel, the two pages of data loaded into the data buffer
into the appropriate memory pages. It is started by issuing a Program Confirm
command.
As for standard page program operations, the device supports random data input during
both data loading phases.
Once the multiplane page program operation has started, maintaining a delay of tBLBH5, the
Status Register can be read using the Read Status Register command. Once the multiplane
page program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
If the multiplane page program fails, an error is signaled on bit SR0 of the Status Register.
However, there is no way to identify for which page the program operation failed.
29/60
6 Device operations
NAND08GW3C2B, NAND16GW3C4B
Figure 14. Multiplane page program
tBLBH2
tBLBH5
(Program Busy time)
RB
Busy
Busy
I/O
80h
Address Inputs
Data Input
Page Program
A0-A11: Valid
Setup Code A12-A18: Fixed 'Low'
A19: Fixed 'Low'
A20-A30: Fixed 'Low'
11h
Confirm
Code
80h
81h
Data Input
Address Inputs
Multiplane Page A0-A11: Valid
Program Setup A12-A18: Valid
A19: Fixed 'High'
Code
A20-A30: Valid
11h
10h
Confirm
Code
81h
70h
SR0
Read Status Register
10h
Data
Input
Plane 0
(2048 blocks)
Plane 1
(2048 blocks)
Block 0
Block 2
Block 1
Block 3
..
..
Block 4092
Block 4094
Block 4093
Block 4095
ai13636b
1. Note that the same addresses except for A19 apply to both blocks.
2. No command between 11h and 81h is permitted except 70h and FFh.
6.10
Block Erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to Figure 15):
1.
One bus cycle is required to setup the Block Erase command. Only addresses A19 to
A31 are used; the other address inputs are ignored.
2.
Three bus cycles are then required to load the address of the block to be erased. Refer
to Table 6 for the block addresses of each device.
3.
One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
controller.
The erase operation is initiated on the rising edge of Write Enable, W, after the Confirm
command is issued. The P/E/R Controller handles block erase and implements the verify
process.
During the block erase operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Once the program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completes successfully, the write status bit
SR0 is ‘0’, otherwise it is set to ‘1’.
30/60
NAND08GW3C2B, NAND16GW3C4B
6 Device operations
Figure 15. Block Erase operation
tBLBH3
(Erase Busy time)
RB
Busy
I/O
60h
Block Address
Inputs
D0h
70h
Confirm
Code
Block Erase
Setup Code
SR0
Read Status Register
ai07593
6.11
Multiplane block erase
The multiplane block erase operation allows the erasure of two blocks in parallel, one in
each plane. It consists of three steps (refer to Figure 16: Multiplane block erase operation):
1.
Eight bus cycles are required to set up the Block Erase command and load the
addresses of the blocks to be erased. The Setup command, followed by the address of
the block to be erased, must be issued for each block. No dummy busy time is required
between the first and second block address insertion. As for multiplane page program,
the address of the first and second page must be within the first plane (A19 = 0) and
second plane (A19 = 1), respectively.
2.
One bus cycle is then required to issue the Multiplane Block Erase Confirm command
and start the P/E/R controller.
If the multiplane block erase fails, an error is signaled on bit SR0 of the status register.
However, there is no way to identify for which page the multiplane block erase operation
failed.
Figure 16. Multiplane block erase operation
tBLBH3
(Erase Busy time)
RB
Busy
I/O
60h
Block Erase
Setup Code
Block Address
Inputs
A12-A18: Fixed 'Low'
A19: Fixed 'Low'
A20-A30: Fixed 'Low'
60h
Block Address
Inputs
D0h
Block Erase A12-A18: Valid Confirm
Setup Code A19: Fixed 'High' Code
A20-A30: Valid
70h
SR0
Read Status Register
ai13637b
31/60
6 Device operations
6.12
NAND08GW3C2B, NAND16GW3C4B
Reset
The Reset command resetd the command interface and Status Register. If the Reset
command is issued during any operation, the operation is aborted. If it is a program or erase
operation that is being aborted, the contents of the memory locations being modified are no
longer valid as the data is partially programmed or erased.
If the device has already been reset, then the new Reset command is not accepted.
The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value
of tBLBH4 depends on the operation that the device was performing when the command was
issued. Refer to Table 23 for the values.
6.13
Read Status Register
The device contains a Status Register that provides information on the current or previous
program or erase operation. The various bits in the Status Register convey information and
errors on the operation.
The Status Register is read by issuing the Read Status Register command. The Status
Register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable, or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary to
toggle the Chip Enable or Read Enable signals to update the contents of the status register.
After the Read Status Register command has been issued, the device remains in read
Status Register mode until another command is issued. Therefore, if a Read Status Register
command is issued during a random read cycle a new read command must be issued to
continue with a page read operation.
Refer to Table 9 which summarizes Status Register bits and should be read in conjunction
with the following text descriptions.
Table 9.
32/60
Status Register bits
I/O
Page program
(SP/DP)
Block erase
(SD/DP)
Page read
0
Pass/fail
Pass/fail
NA
Pass: ‘0’, Fail: ‘1’
1
Plane 0: Pass/fail
Plane 0 Pass/fail
NA
Plane 0: Pass: ‘0’, Fail: ‘1’
2
Plane 1: Pass/fail
Plane 1 Pass/fail
NA
Plane 1: Pass: ‘0’, Fail: ‘1’
3
NA
NA
NA
-
4
NA
NA
NA
-
5
NA
NA
NA
-
6
Ready/busy
Ready/busy
Ready/busy
7
Write protect
Write protect
Write protect Protected: ‘0’, Not protected: ‘1’
Definition
Busy: ‘0’, Ready: ‘1’
NAND08GW3C2B, NAND16GW3C4B
6.13.1
6 Device operations
Write protection bit (SR7)
The write protection bit can identify if the device is protected or not. If the write protection bit
is set to ‘1’ the device is not protected and program or erase operations are allowed. If the
write protection bit is set to ‘0’ the device is protected and program or erase operations are
not allowed.
6.13.2
P/E/R controller bit (SR6)
Status Register bit SR6 acts as a P/E/R controller bit, which indicates whether the P/E/R
controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller
is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is
ready).
6.13.3
Error bit (SR0)
The error bit identifyies if any errors have been detected by the P/E/R controller. The error bit
is set to ‘1’ when a program or erase operation has failed to write the correct data to the
memory. If the error bit is set to ‘0’, the operation has completed successfully.
6.14
Read electronic signature
The device contains a manufacturer code and device code. The following three steps are
required to read these codes:
Table 10.
1.
One bus write cycle to issue the Read Electronic Signature command (90h)
2.
One bus write cycle to input the address (00h)
3.
Four bus read cycles to sequentially output the data (as shown in Table 11: Electronic
signature).
Device identifier codes
Device identifier cycle
Description
1st
Manufactuer code
2nd
Device identifier
3rd
Internal chip number, cell type, etc.
4th
Page size, block size, spare size orgranization
5th
Multiplane information
Table 11.
Electronic signature
Byte/word 1
Part number
Manufacturer
code
20h
Byte/word 2
Byte 3
Byte 4
Byte 5
Device code
(see Table 12)
(see Table 13)
(see Table 14)
D3h
14h
A5h
34h
NAND08GW3C2B
NAND16GW3C4B(1)
1. Each 8-Gbit die returns its own electronic signature.
33/60
6 Device operations
Table 12.
Electronic signature byte 3
I/O
Definition
Value
Description
Die/package
00
01
10
11
1
2
4
8
Cell type
00
01
10
11
2-level cell
4-level cell
8-level cell
16-level cell
I/O5-I/O4
Number of simultaneously
programmed pages
00
01
10
11
1
2
4
8
I/O6
Interleaved programming
between multiple devices
0
1
Not supported
Supported
I/O7
Write cache
0
1
Not supported
Supported
I/O1-I/O0
I/O3-I/O2
34/60
NAND08GW3C2B, NAND16GW3C4B
NAND08GW3C2B, NAND16GW3C4B
Table 13.
6 Device operations
Electronic signature byte 4
I/O
Definition
Value
Description
I/O1-I/O0
Page size
(without spare area)
00
01
10
11
1 KBytes
2 KBytes
4 KBytes
8 KBytes
I/O2
Spare area size
(byte/512 byte)
0
1
8
16
Serial access time
00
01
10
11
50 ns
30 ns
25 ns
Reserved
I/O5-I/O4
Block size
(without spare area)
00
01
10
11
64 KBytes
128 KBytes
256 KBytes
512 KBytes
I/O6
Organization
0
1
x8
x16
I/O7, I/O3
Table 14.
Electronic signature byte 5
I/O
Definition
Value
I/O1 - I/O0
Reserved
0 0
I/O3 - I/O2
Plane number
I/O6 - I/O4
Plane size
(without redundant area)
I/O7
Reserved
0
0
1
1
0
0
0
0
1
1
1
1
Description
0
1
0
1
1 plane
2 planes
4 planes
8 planes
0 0
0 1
1 0
1 1
0 0
0 1
1 0
11
512 Mbits
1 Gbyte
2 Gbytes
4 Gbytes
8 Gbytes
Reserved
Reserved
Reserved
0
35/60
7 Concurrent operations and ERS
7
NAND08GW3C2B, NAND16GW3C4B
Concurrent operations and ERS
The NAND16GW3C4B is composed of two 8-Gbit dice stacked together. This configuration
allows the device to support concurrent operations. This means that while performing an
operation in one die (erase, read, program, etc.), another operation is possible in the other
die.
The standard Read Status Register (ERS) operation returns the status of the
NAND16GW3C4B device. To provide information on each 8-Gbit die, the NAND16GW3C4B
features an Extended Read Status Register command that allows to check independently
the status of each die.
The following steps are required to perform concurrent operations:
1.
Select one of the two dice by setting the most significant address bit A31 to ‘0’ or ‘1’.
2.
Execute one operation on this die.
3.
Launch a concurrent operation on the other die.
4.
Check the status of these operations by performing an extended read Status Register
operation.
All combinations of operations are possible except executing read on both dice. This is due
to the fact that the input/output bus is common to both dice.
Refer to Table 15 for the description of the Extended Read Status Register command
sequence, and to Table 9. for the definition of the Status Register bits.
Table 15.
36/60
Extended Read Status Register commands
Command
Address range
1 bus write cycle
Read 1st die status
Address ≤0x7FFFFFFF
F1h
Read 2nd die status
0x7FFFFFFF < Address ≤0xFFFFFFF
F2h
NAND08GW3C2B, NAND16GW3C4B
8
8 Data protection
Data protection
The device has hardware features to protect against spurious program and erase
operations. An internal voltage detector disables all functions whenever VCC is below the
VLKO threshold. It is recommended to keep WP at VIL during power-up and power-down.
In the VDD range from VLKO to the lower limit of nominal range, the WP pin should be kept
Low (VIL) to guarantee hardware protection during power transitions, as shown in Figure 17.
Figure 17. Data protection
VDD
Nominal Range
VLKO
Locked
Locked
WP
Ai11086b
9
Software algorithms
This section provides information on the software algorithms that Numonyx recommends
implementing to manage the bad blocks and extend the lifetime of the NAND device.
NAND Flash memories are programmed and erased by Fowler-Nordheim tunneling using
high voltage. Exposing the device to high voltage for extended periods can cause the oxide
layer to be damaged. For this reason, the number of program and erase cycles is limited
(see Table 17 for value). It is recommended to implement garbage collection, wear-leveling
and error correction code algorithms to extend the number of program and erase cycles and
to increase data retention.
To help integrate a NAND memory into an application Numonyx can provide a File System
OS native reference software, which supports the basic commands of file management.
Contact the nearest Numonyx sales office for more details.
37/60
9 Software algorithms
9.1
NAND08GW3C2B, NAND16GW3C4B
Bad block management
Devices with bad blocks have the same quality level and the same AC and DC
characteristics as devices where all the blocks are valid. A bad block does not affect the
performance of valid blocks because it is isolated from the bit line and common source line
by a select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The bad
block information is written prior to shipping. Any block, where the 1st byte in the spare area
of the last page, does not contain FFh, is a bad block.
The bad block information must be read before any erase is attempted as the bad block
Information may be erased. For the system to be able to recognize the bad blocks based on
the original information it is recommended to create a bad block table following the flowchart
shown in Figure 18.
9.2
NAND Flash memory failure modes
The NAND08GW3C2B and NAND16GW3C4B devices may contain bad blocks, where the
reliability of blocks that contain one or more invalid bits is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
To implement a highly reliable system, all the possible failure modes must be considered:
●
Program/erase failure
in this case, the block has to be replaced by copying the data to a valid block. These
additional bad blocks can be identified as attempts to program or erase them and give
errors in the Status Register.
Because the failure of a Page Program operation does not affect the data in other
pages in the same block, the block can be replaced by re-programming the current data
and copying the rest of the replaced block to an available valid block. The Copy Back
Program command can be used to copy the data to a valid block. See Section Figure
10.: Random data input during sequential data input for more details.
●
Read failure
in this case, ECC correction must be implemented. To efficiently use the memory
space, it is recommended to recover single-bit errors in read by ECC, without replacing
the whole block.
Refer to Table 16 for the procedure to follow if an error occurs during an operation.
Table 16.
38/60
Block Failure
Operation
Procedure
Erase
Block replacement
Program
Block replacement or ECC (with 4 bit/528 byte)
Read
ECC (with 4 bit/528 byte)
NAND08GW3C2B, NAND16GW3C4B
9 Software algorithms
Figure 18. Bad block management flowchart
START
Block Address =
Block 0
Data
= FFh?
Increment
Block Address
NO
Update
Bad Block table
YES
Last
block?
NO
YES
END
AI07588C
9.3
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page and
mark the previous page as invalid. After several updates it is necessary to remove invalid
pages to free some memory space.
To free this memory space and allow further program operations, it is recommended to
implement a garbage collection algorithm. In a garbage collection software the valid pages
are copied into a free area and the block containing the invalid pages is erased (see
Figure 19).
Figure 19. Garbage collection
New Area (After GC)
Old Area
Valid
Page
Invalid
Page
Free
Page
(Erased)
AI07599B
39/60
9 Software algorithms
9.4
NAND08GW3C2B, NAND16GW3C4B
Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear-leveling algorithm
to monitor and spread the number of write cycles per block.
In memories that do not use a wear-leveling algorithm, not all blocks get used at the same
rate. The wear-leveling algorithm ensures that equal use is made of all the available write
cycles for each block.
There are two wear-leveling levels:
1.
First level wear-leveling, where new data is programmed to the free blocks that have
had the fewest write cycles
2.
Second level wear-leveling, where long-lived data is copied to another block so that the
original block can be used for more frequently changed data.
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
9.5
Hardware simulation models
9.5.1
Behavioral simulation models
Denali Software Corporation models are platform-independent functional models designed
to assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic behavior and timings of NAND Flash devices, and, therefore,
allow software to be developed before hardware.
9.5.2
IBIS simulations models
I/O buffer information specification (IBIS) models describe the behavior of the I/O buffers
and electrical characteristics of Flash devices.
These models provide information such as AC characteristics, rise/fall times, and package
mechanical data, all of which are measured or simulated at voltage and temperature ranges
wider than those allowed by target specifications.
IBIS models are used to simulate PCB connections and can be used to resolve compatibility
issues when upgrading devices. They can be imported into SPICETOOLS.
40/60
NAND08GW3C2B, NAND16GW3C4B
10
10 Program and erase times and endurance cycles
Program and erase times and endurance cycles
Table 17 shows the program and erase times and the number of program/erase cycles per
block.
Table 17.
Program and erase times and program erase endurance cycles
NAND08GW3C2B, NAND16GW3C4B
Parameters
Unit
Min
Typ
Max
Page program time
800
2000
µs
Block erase time
2.5
10
ms
Program/erase cycles (per block (with ECC)
Data retention
Number of partial program cycles (NOP)
within the same page (main array or spare
arrary)
10,000
cycles
10
years
1
cycle
41/60
11 Maximum ratings
11
NAND08GW3C2B, NAND16GW3C4B
Maximum ratings
Stressing the device above the ratings listed in Table 18: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE program
and other relevant quality documents.
Table 18.
Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min
Max
TBIAS
Temperature under bias
– 50
125
°C
TSTG
Storage temperature
– 65
150
°C
VIO(1)
Input or output voltage
– 0.6
4.6
V
Supply voltage
– 0.6
4.6
V
VDD
1. Minimum voltage may undershoot to –2 V for less than 20 ns during transitions on input and I/O pins.
Maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.
42/60
NAND08GW3C2B, NAND16GW3C4B
12
12 DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristics
tables are derived from tests performed under the measurement conditions summarized in
Table 19: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Table 19.
Operating and AC measurement conditions
NAND08GW3C2B,
NAND16GW3C4B
Parameter
Supply voltage (VDD)
Ambient temperature (TA)
Min
Max
2.7
3.6
V
0
70
°C
–40
85
°C
Load capacitance (CL) (1 TTL GATE and CL)
50
Input pulses voltages
Units
0.4
pF
2.4
V
Input and output timing ref. voltages
1.5
V
Output circuit resistor Rref
8.35
kΩ
5
ns
Input rise and fall times
Table 20.
Capacitance(1)
Symbol
Parameter
Test condition
CIN
Input capacitance
CI/O
Input/output
capacitance
Typ
Max
Unit
VIN = 0 V
10
pF
VIL = 0 V
10
pF
1. TA = 25°C, f = 1 MHz. CIN and CI/O are not 100% tested.
43/60
12 DC and AC parameters
Table 21.
DC characteristics
Symbol
Parameter
IDD1
IDD2
NAND08GW3C2B, NAND16GW3C4B
Operating
current
Test conditions
Min
Typ
Max
Unit
Sequential
read
tRLRL minimum
E=VIL, IOUT = 0 mA
-
15
30
mA
Program
-
-
15
30
mA
Erase
-
-
15
30
mA
1
mA
IDD3
IDD4
Standby current (TTL)
E=VIH, WP=0/VDD
IDD5
Standby current (CMOS)
E=VDD-0.2,
WP=0/VDD
-
10
50
µA
ILI
Input leakage Current
VIN= 0 to 3.6 V
-
-
±10
µA
ILO
Output leakage Current
VOUT= 0 to 3.6 V
-
-
±10
µA
VIH
Input high voltage
-
2.0
-
VDD+0.3
V
VIL
Input low voltage
-
-0.3
-
0.8
V
VOH
Output high voltage level
IOH = -400 µA
2.4
-
-
V
VOL
Output low voltage level
IOL = 2.1 mA
-
-
0.4
V
IOL (RB)
Output low current (RB)
VOL = 0.4 V
8
10
VLKO
VDD supply voltage (erase and
program lockout)
-
-
-
Table 22.
Symbol
tALLWH
tALHWH
tCLHWH
tCLLWH
mA
2.5
V
AC characteristics for command, address, data input
Alt. symbol
Parameter
Value
Unit
Address Latch Low to Write Enable High
tALS
AL setup time
Min
12
ns
CL setup time
Min
12
ns
Address Latch High to Write Enable High
Command Latch High to Write Enable High
tCLS
Command Latch Low to Write Enable High
tDVWH
tDS
Data Valid to Write Enable High
Data setup time
Min
12
ns
tELWH
tCS
Chip Enable Low to Write Enable High
E setup time
Min
20
ns
AL hold time
Min
5
ns
CL hold time
Min
5
ns
tWHALH
tWHALL
tWHCLH
tWHCLL
Write Enable High to Address Latch High
tALH
Write Enable High to Address Latch Low
Write Enable High to Command Latch High
tCLH
Write Enable High to Command Latch Low
tWHDX
tDH
Write Enable High to Data Transition
Data hold time
Min
5
ns
tWHEH
tCH
Write Enable High to Chip Enable High
E hold time
Min
5
ns
tWHWL
tWH
Write Enable High to Write Enable Low
W High hold time Min
10
ns
tWLWH
tWP
Write Enable Low to Write Enable High
W pulse width
Min
12
ns
tWLWL
tWC
Write Enable Low to Write Enable Low
Write cycle time
Min
25
ns
44/60
NAND08GW3C2B, NAND16GW3C4B
Table 23.
Symbol
tALLRL1
tALLRL2
tBHRL
12 DC and AC parameters
AC characteristics for operations
Value
Alt.
Symbol
tAR
Parameter
Unit
Min Typ Max
Address Latch Low to Read Enable
Low
tRR
Read electronic signature
10
ns
Read cycle
10
ns
20
ns
Ready/Busy High to Read Enable Low
tBLBH1
tBLBH2
tPROG
tBLBH3
tBERS
tBLBH4
Read Busy time
60
µs
Program Busy time
2000
µs
Erase Busy time
3
ms
Reset Busy time, during ready
5
µs
Reset Busy time, during read
20
µs
Reset Busy time, during program
20
µs
Reset Busy time, during erase
500
µs
2
µs
Ready/Busy Low to Ready/Busy High
tRST
tBLBH5
tCBSY
Dummy Busy Time for Multiplane operations
tCLLRL
tCLR
Command Latch Low to Read Enable Low
10
ns
tDZRL
tIR
Data Hi-Z to Read Enable Low
0
ns
tEHQZ
tCHZ
Chip Enable High to Output Hi-Z
50
ns
tELQV
tCEA
Chip Enable Low to Output Valid
25
ns
tRHRL
tREH
Read Enable High to Read Enable Low
tEHQX
tCOH
tRHQX
Read Enable High Hold time
1
10
ns
Chip Enable High to Output Hold
15
ns
tRHOH
Read Enable High to Output Hold
15
ns
tRLQX
tRLOH
Read Enable Low to Output Hold (EDO Mode)
5
ns
tRHQZ
tRHZ
tRLRH
tRP
Read Enable Low to Read Enable High
Read Enable Pulse Width
12
ns
tRLRL
tRC
Read Enable Low to Read Enable Low
Read Cycle time
25
ns
tRLQV
tREA
Read Enable Low to Output Valid
tWHBH
tR
Write Enable High to Ready/Busy High
tWHBL
tWB
Write Enable High to Ready/Busy Low
tWHRL
tWHR
Write Enable High to Read Enable Low
80
ns
tWHWH(2)
tADL
Last Address latched on Data Loading Time during Program operations
70
ns
100
ns
tWW
Write Protection time
100
ns
Read Enable High to Output Hi-Z
100
ns
Read Enable Access time
tVHWH
tVLWH
Read ES Access time(1)
(3)
(3)
Read Busy time
20
ns
60
µs
100
ns
1. ES = Electronic Signature.
2. tWHWH is the delay from Write Enable rising edge during the final address cycle to Write Enable rising edge during the first
data cycle.
3. WP High to W High during Program/Erase Enable operations.
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12 DC and AC parameters
NAND08GW3C2B, NAND16GW3C4B
Figure 20. Command latch AC waveforms
CL
tWHCLL
tCLHWH
(CL Setup time)
(CL Hold time)
tWHEH
tELWH
(E Hold time)
H(E Setup time)
E
tWLWH
W
tALLWH
tWHALH
(ALSetup time)
(AL Hold time)
AL
tDVWH
tWHDX
(Data Setup time)
(Data Hold time)
I/O
Command
ai12470b
Figure 21. Address latch AC waveforms
tCLLWH
(CL Setup time)
CL
tWLWL
tELWH
tWLWL
tWLWL
tWLWL
(E Setup time)
E
tWLWH
tWLWH
tWLWH
tWLWH
tWLWH
W
tWHWL
tWHWL
tWHWL
tWHWL
tALHWH
(AL Setup time)
tWHALL
tWHALL
tWHALL
tWHALL
(AL Hold time)
AL
tDVWH
tDVWH
(Data Setup time)
tDVWH
tDVWH
tWHDX
tWHDX
tDVWH
tWHDX
tWHDX
tWHDX
(Data Hold time)
I/O
Adrress
cycle 1
Adrress
cycle 2
Adrress
cycle 3
Adrress
cycle 4
Adrress
cycle 5
ai12471
46/60
NAND08GW3C2B, NAND16GW3C4B
12 DC and AC parameters
Figure 22. Data input latch AC waveforms
tWHCLH
(CL Hold time)
CL
tWHEH
(E Hold time)
E
tALLWH
(ALSetup time)
tWLWL
AL
tWLWH
tWLWH
tWLWH
W
tDVWH
tDVWH
tDVWH
(Data Setup time)
tWHDX
tWHDX
tWHDX
(Data Hold time)
I/O
Data In 0
Data In
Last
Data In 1
ai12472
1. The last data input is the 2112th.
Figure 23. Sequential data output after Read AC waveforms
tRLRL
(Read Cycle time)
E
tEHQX
tEHQZ
tRHRL
(R High Holdtime)
R
tRHQZ
tRLQV
tRLQV
tRHQZ
tRHQX(2)
tRLQV
(R Accesstime)
I/O
Data Out
Data Out
Data Out
tBHRL
RB
ai13174
1. CL = Low, AL = Low, W = High.
2. tRHQX is applicable for frequencies lower than 33 MHz (i.e. tRLRL higher than 30 ns).
47/60
12 DC and AC parameters
NAND08GW3C2B, NAND16GW3C4B
Figure 24. Sequential data output after Read AC waveforms (EDO mode)
tRLRL
E
tEHQX
tRLRH
tEHQZ
tRHRL
R
tELQV
tRHQZ
tRLQX
tRLQV
tRHQX(2)
tRLQV
(R Accesstime)
I/O
Data Out
Data Out
Data Out
tBHRL
RB
ai13175
1. In EDO mode, CL and AL are Low, VIL, and W is High, VIH.
2. tRLQX is applicable for frequencies higher than 33 MHz (i.e. tRLRL lower than 30 ns).
Figure 25. Read Status Register AC waveform
tCLLRL
CL
tWHCLL
tCLHWH
tWHEH
E
tELWH
tWLWH
W
tELQV
tWHRL
tEHQZ
tEHQX
R
tDZRL
tDVWH
tWHDX
tRLQV
tRHQX
(Data Hold time)
(Data Setup time)
I/O
tRHQZ
70h or 7Bh
Status Register
Output
ai13177
48/60
NAND08GW3C2B, NAND16GW3C4B
12 DC and AC parameters
Figure 26. Read electronic signature AC waveform
CL
E
W
AL
tALLRL1
R
tRLQV
(Read ES Access time)
I/O
90h
Read Electronic
Signature
Command
00h
Byte1
Byte2
1st Cycle
Address
Man.
code
Device
code
Byte3
Byte4
Byte5
see Note.1
ai13178
1. Refer to Table 11 for the values of the manufacturer and device codes, and to Table 12, Table 13, and Table 14 for the
information contained in Byte 3, Byte 4, and Byte 5.
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12 DC and AC parameters
NAND08GW3C2B, NAND16GW3C4B
Figure 27. Page read operation AC waveform
CL
E
tWLWL
tEHQZ
W
tWHBL
AL
tALLRL2
tWHBH
tRLRL
tRHQZ
(Read Cycle time)
R
tRLRH
tBLBH1
RB
I/O
00h
Add.N
cycle 1
Command
Code
Add.N
cycle 2
Add.N
cycle 3
Address N Input
Add.N
cycle 4
Add.N
cycle 5
Data
N
30h
Busy
Data
N+1
Data
N+2
Data
Last
Data Output
from Address N to Last Byte or Word in Page
ai13638
50/60
NAND08GW3C2B, NAND16GW3C4B
12 DC and AC parameters
Figure 28. Page program AC waveform
CL
E
tWLWL
tWLWL
tWLWL
(Write Cycle time)
W
tWHWH
tWHBL
tBLBH2
(Program Busy time)
AL
R
I/O
80h
Add.N
cycle 1
Add.N
cycle 2
Add.N Add.N Add.N
cycle 3 cycle 4 cycle 5
N
Last
10h
70h
SR0
RB
Page Program
Setup Code
Address Input
Data Input
Confirm
Code
Page
Program Read Status Register
ai13639
51/60
12 DC and AC parameters
NAND08GW3C2B, NAND16GW3C4B
Figure 29. Block erase AC waveform
CL
E
tWLWL
(Write Cycle time)
W
tBLBH3
tWHBL
(Erase Busy time)
AL
R
I/O
60h
Add.
Add.
Add.
cycle 1 cycle 2 cycle 3
70h
D0h
SR0
RB
Block Erase
Setup Command
Block Address Input
Confirm
Code
Block Erase
Read Status Register
ai08038c
Figure 30. Reset AC waveform
W
AL
CL
R
I/O
FFh
tBLBH4
(Reset Busy time)
RB
ai08043
52/60
NAND08GW3C2B, NAND16GW3C4B
12 DC and AC parameters
Figure 31. Program/erase enable waveform
W
tVHWH
WP
RB
I/O
80h
10h
ai12477
Figure 32. Program/erase disable waveform
W
tVLWH
WP
High
RB
I/O
80h
10h
ai12478
53/60
12 DC and AC parameters
12.1
NAND08GW3C2B, NAND16GW3C4B
Ready/Busy signal electrical characteristics
Figure 34, Figure 33 and Figure 35 show the electrical characteristics for the Ready/Busy
signal. The value required for the resistor RP can be calculated using the following equation:
(V
–
)
DDmax V OLmax
R P min = ------------------------------------------------------------+
I
I OL
L
So,
3,2V R P min = -------------------------8mA + I L
where IL is the sum of the input currents of all the devices tied to the Ready/Busy signal. RP
max is determined by the maximum value of tr.
Figure 33. Ready/Busy AC waveform
ready VDD
VOH
VOL
busy
tr
tf
AI07564B
Figure 34. Ready/Busy load circuit
VDD
RP
ibusy
DEVICE
RB
Open Drain Output
VSS
AI07563B
54/60
NAND08GW3C2B, NAND16GW3C4B
12 DC and AC parameters
Figure 35. Resistor value versus waveform timings for Ready/Busy signal
VDD = 3.3 V, CL = 50 pF
381
3.3
290
ibusy (mA)
tr, tf (ns)
1.65
189
1.1
96
0.825
4.2
4.2
1
4.2
2
4.2
3
4
RP (KΩ)
tf
tr
ibusy
ai
1. T = 25°C.
55/60
13 Package mechanical
13
NAND08GW3C2B, NAND16GW3C4B
Package mechanical
To meet environmental requirements, Numonyx offers the devices in ECOPACK® packages.
ECOPACK packages are lead-free. In compliance with JEDEC Standard JESD97, the
category of second level interconnect is marked on the package and on the inner box label.
The maximum ratings related to soldering conditions are also marked on the inner box label.
Figure 36. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline
1
48
e
D1
B
24
L1
25
A2
E1
E
A
A1
DIE
α
L
C
CP
TSOP-G
1. Drawing is not to scale.
Table 24.
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data
Millimeters
Inches
Symbol
Typ
Min
A
Typ
Min
1.200
Max
0.0472
A1
0.100
0.050
0.150
0.0039
0.0020
0.0059
A2
1.000
0.950
1.050
0.0394
0.0374
0.0413
B
0.220
0.170
0.270
0.0087
0.0067
0.0106
0.100
0.210
0.0039
0.0083
C
CP
56/60
Max
0.080
0.0031
D1
12.000
11.900
12.100
0.4724
0.4685
0.4764
E
20.000
19.800
20.200
0.7874
0.7795
0.7953
E1
18.400
18.300
18.500
0.7244
0.7205
0.7283
e
0.500
–
–
0.0197
–
L
0.600
0.500
0.700
0.0236
0.0197
0.0276
L1
0.800
a
3°
0°
5°
0.0315
0°
5°
3°
NAND08GW3C2B, NAND16GW3C4B
13 Package mechanical
Figure 37. LGA52 12 x 17 mm, 1 mm pitch, package outline
D
FD1
D2
D1
FD
FE1
FE
BALL "A1"
eE1
E E2
E1
e
ddd
e
b1 b2
A2
A
LGA-9G
Table 25.
LGA52 12 x 17 mm, 1 mm pitch, package mechanical data
Millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.650
0.0256
A2
0.650
0.0256
b1
0.700
0.650
0.750
0.0276
0.0256
0.0295
b2
1.000
0.950
1.050
0.0394
0.0374
0.0413
D
12.000
11.900
12.100
0.4724
0.4685
0.4764
D1
6.000
0.2362
D2
10.000
0.3937
ddd
0.100
16.900
17.100
0.0039
E
17.000
0.6693
0.6654
0.6732
E1
12.000
0.4724
E2
13.000
0.5118
e
1.000
–
–
0.0394
–
–
eE1
2.000
–
–
0.0787
–
–
FD
3.000
0.1181
FD1
1.000
0.0394
FE
2.500
0.0984
FE1
2.000
0.0787
57/60
14 Part numbering
14
NAND08GW3C2B, NAND16GW3C4B
Part numbering
Table 26.
Ordering information scheme
Example:
NAND08G W 3
C 2 B
N 1
E
Device type
NAND Flash memory
Density
08G = 8 Gbits
16G = 16 Gbits
Operating voltage
W = VDD = 2.7 to 3.6 V
Bus width
3 = x8
Family identifier
C = 2112 bytes page MLC
Device options
2 = Chip Enable ‘don't care’ enabled
4 = Chip Enable ‘don't care’ enabled with 2 Chip
Enable and 2 Ready/Busy signals
Product version
B = second version
Package
N = TSOP48 12 x 20 mm
ZL = ULGA52 12 x 17 mm
Temperature range
1 = 0 to 70 °C
6 = −40 to 85 °C
Option
E = ECOPACK® package, standard packing
F = ECOPACK® package, tape and reel packing
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to
‘1’. For further information on any aspect of this device, please contact your nearest
Numonyx sales office.
58/60
NAND08GW3C2B, NAND16GW3C4B
15
15 Revision history
Revision history
Table 27.
Document revision history
Date
Revision
Changes
25-Feb-2008
1
Initial release.
19-Mar-2008
2
Applied Numonyx branding.
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NAND08GW3C2B, NAND16GW3C4B
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