NC7WV07 TinyLogic® ULP-A Bual Buffer (Open-Drain Output) Features Description 0.9V to 3.6V VCC Supply Operation Extremely High Speed tPD - 1.0ns: Typical for 2.7V to 3.6V VCC - 1.2ns: Typical for 2.3V to 2.7V VCC - 2.0ns: Typical for 1.65V to 1.95V VCC - 3.2ns: Typical for 1.4V to 1.6V VCC - 6.0ns: Typical for 1.1V to 1.3V VCC - 13.0ns: Typical for 0.9V VCC The NC7WV07 is a dual buffer with open drain output from Fairchild's Ultra Low Power-A series of TinyLogic® ULP-A is ideal for applications that require extreme high speed, high drive and low power. This product is designed for a wide low voltage operating range (0.9V to 3.6V VCC) and applications that require more drive and speed than the TinyLogic ULP series, but still offer best in class low power operation. 3.6V Over-Voltage Tolerant I/Os at VCC from 0.9V to 3.6V The NC7WV07 is uniquely designed for optimized power and speed, and is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low CMOS power dissipation. Power-Off High-Impedance Inputs and Outputs High Static Drive (IOH/IOL) - 24mA at 3.00V VCC -18mA at 2.30V VCC -6mA at 1.65V VCC - 4mA at 1.4V VCC - 2mA at 1.1V VCC - 0.1mA at 0.9V VCC Uses Proprietary Quiet Series™ Noise/EMI Reduction Circuitry Ultra-Small MicroPak™ Packages Ultra-Low Dynamic Power Ordering Information Part Number Top Mark Package Packing Method NC7WV07P6X V07 6-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3000 Units on Tape & Reel NC7WV07L6X BC 6-Lead MicroPak™, 1.00mm Wide 5000 Units on Tape & Reel TinyLogic®is a registered trademark of Fairchild Semiconductor Corporation. MicroPak™and Quiet Series™are trademarks of Fairchild Semiconductor Corporation. © 2006 Fairchild Semiconductor Corporation NC7WV07 • Rev. 1.0.2 www.fairchildsemi.com NC7WV07 — TinyLogic® ULP-A Dual Buffer (Open-Drain Output) July 2012 700 600 500 ULP (SP) Battery Life 400 (Days) 300 ULP-A (SV) 200 100 0 0.9 1.2 UHS (SZ) 1.5 1.8 2.5 3.3 VCC Supply Voltage 5.0 Figure 1. Battery Life vs. VCC Supply Voltage Notes: 1. TinyLogic® ULP and ULP-A with up to 50% less power consumption can extend battery life significantly. Battery Life (Vbattery•Ibattery•.9)/(Pdevice)/24hrs/day where, Pdevice (ICC • VCC) (CPD CL) • VCC2 • f. 2. Assumes ideal 3.6V Lithium Ion battery with current rating of 900mAH and derated 90% and device frequency at 10MHz, with CL=15pF load. Pin Configurations Figure 2. SC70 (Top View) NC7WV07 — TinyLogic® ULP-A Dual Buffer (Open-Drain Output) Battery Life Figure 3. MicroPak (Top Through View) Pin Definitions Pin # SC70 Pin # MicroPak Name Description 1 1 A1 2 2 GND 3 3 A2 Data Inputs 4 4 Y2 Output 5 5 VCC Supply Voltage 6 6 Y1 Output Data Inputs Ground Function Table Inputs Output A Y L L H *H H=HIGH Logic Level L=LOW Logic Level *H=HIGH Impedance Output Status (Open Drain) © 2006 Fairchild Semiconductor Corporation NC7WV07 • Rev. 1.0.2 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Supply Voltage -0.5 4.6 V VIN DC Input Voltage -0.5 4.6 V VOUT 4.6 V IIK DC Input Diode Current VIN < 0V -50 mA IOK DC Output Diode Current VOUT < 0V -50 mA DC Output Sink Current +50 mA DC VCC or Ground Current per Supply Pin ±50 mA +150 °C IOL ICC or IGND TSTG DC Output Voltage -0.5 Storage Temperature Range -65 TJ Junction Temperature Under Bias +150 °C TL Junction Lead Temperature, Soldering 10 Seconds +260 °C PD Power Dissipation at +85°C SC70-5 150 MicroPak-6 130 MicroPak2-6 ESD mW 120 Human Body Model, JEDEC:JESD22-A114 4000 Charge Device Model, JEDEC:JESD22-C101 2000 V NC7WV07 — TinyLogic® ULP-A Dual Buffer (Open-Drain Output) Absolute Maximum Ratings Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VCC Supply Voltage VIN Input Voltage VOUT IOL TA t/V JA Conditions Output Voltage Output Current in IOL Thermal Resistance Max. Unit 0.9 3.6 V 0 3.6 V 3.6 V 0 VCC=3.0V to 3.6V +24.0 VCC=2.3V to 3.6V +18.0 VCC=1.65V to 1.95V +6.0 VCC=1.4V to 1.6V +4.0 VCC=1.1V to 1.3V +2.0 VCC=0.9V +0.1 Operating Temperature, Free Air Minimum Input Edge Rate Min. -40 mA +85 °C ns/V VIN=0.8V to 2.0, VCC=3.0V 10 SC70-5 425 MicroPak-6 500 °C/W Note: 3. Unused inputs must be held HIGH or LOW. They may not float. © 2006 Fairchild Semiconductor Corporation NC7WV07 • Rev. 1.0.2 www.fairchildsemi.com 3 Symbol VIH Parameter HIGH Level Input Voltage VCC Conditions 1.10 VCC 1.30 .65 x VCC .65 x VCC 1.40 VCC 1.60 .65 x VCC .65 x VCC 1.65 VCC 1.95 .65 x VCC .65 x VCC 1.6 1.6 2.0 1.10 VCC 1.30 .35 x VCC 1.65 VCC 1.95 .35 x VCC .35 x VCC 2.30 VCC 2.70 0.7 0.7 2.70 VCC 3.60 0.8 0.8 0.90 0.1 0.1 1.10 VCC 1.30 0.1 0.1 0.2 0.2 0.2 0.2 2.30 VCC 2.70 0.2 0.2 2.70 VCC 3.60 0.2 0.2 1.10 VCC 1.30 IOL=2mA 0.25 x VCC 0.25 x VCC 1.40 VCC 1.60 IOL=4mA 0.25 x VCC 0.25 x VCC 1.65 VCC 1.95 IOL=6mA 0.3 0.3 2.70 VCC 3.60 2.30 VCC 2.70 2.70 VCC 3.60 2.70 VCC 3.60 Input Leakage Current Power Off Leakage Current ICC Quiescent Supply Current .35 x VCC .35 x VCC 2.30 VCC 2.70 IOFF 2.0 .35 x VCC .35 x VCC IOL=100µA © 2006 Fairchild Semiconductor Corporation NC7WV07 • Rev. 1.0.2 0.90 to 3.60 0 0.90 to 3.60 IOL=12mA Units V .35 x VCC 1.65 VCC 1.95 IIN Max. 1.40 VCC 1.60 1.40 VCC 1.60 LOW Level Output Voltage Min. .65 x VCC 0.90 VOL Max. .65 x VCC 2.70 VCC 3.60 LOW Level Input Voltage Min. TA=-40 to 85°C 0.90 2.30 VCC 2.70 VIL TA=25°C 0.4 0.4 0.4 0.4 V V 0.6 0.6 0.4 0.4 IOL=24mA 0.55 0.55 0 VIN 3.60 ±0.1 ±0.5 µA 0 (VIN, VO) 3.60 0.5 0.5 µA VIN=VCC, or GND 0.9 0.9 IOL=18mA NC7WV07 — TinyLogic® ULP-A Dual Buffer (Open-Drain Output) DC Electrical Characteristics µA VCC VIN 3.6V ±0.9 www.fairchildsemi.com 4 Symbol Parameter VCC 1.10 VCC 1.30 tPZL, tPLZ Min. Typ. CL=15pF, RU=RD=1M 0.90 Propagation Delay TA=25°C Conditions 1.40 VCC 1.60 2.70 VCC 3.60 Max. Min. Max. Units Figure ns Figure 4 Figure 5 13 CL=15pF, RU=RD=2k 1.65 VCC 1.95 2.30 VCC 2.70 TA=-40 to 85°C CL=30pF, RU=RD=500 2.0 6.0 15.0 1.0 18.6 1.0 3.2 8.7 1.0 9.7 1.0 2.0 6.0 1.0 6.8 0.7 1.2 3.6 0.6 4.7 0.5 1.0 3.3 0.4 4.0 CIN Input Capacitance 0 2 COUT Output Capacitance 0 6.5 CPD Power Dissipation Capacitance 0.90 to 3.60 VIN=0V or VCC, f=10MHz pF 10 pF AC Loadings and Waveforms Figure 4. AC Test Circuit Test Switch tPZL, tPLZ 6V at VCC=3.3±0.3V; VCC x 2 at VCC=0.9-2.7V NC7WV07 — TinyLogic® ULP-A Dual Buffer (Open-Drain Output) AC Electrical Characteristics Figure 5. AC Waveforms for Inverting and Non-Inverting Functions VCC Symbol 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V 1.5V ± 0.1V 1.2V ± 0.1V 0.9V Vmi 1.5V VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 Vmo VOL + 0.30V VOL + 0.15V VOL + 0.15V VOL + 0.10V VOL + 0.10V VOL + 0.10V © 2006 Fairchild Semiconductor Corporation NC7WV07 • Rev. 1.0.2 www.fairchildsemi.com 5 NC7WV07 — TinyLogic® ULP-A Dual Buffer (Open-Drain Output) Physical Dimensions SYMM C L 2.00±0.20 0.65 A 0.50 MIN 4 6 B PIN ONE 1.25±0.10 1 1.90 3 0.30 0.15 (0.25) 0.40 MIN 0.10 0.65 A B 1.30 LAND PATTERN RECOMMENDATION 1.30 1.00 0.80 SEE DETAIL A 1.10 0.80 0.10 C 0.10 0.00 C 2.10±0.30 SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE (R0.10) 0.25 0.10 0.20 A) THIS PACKAGE CONFORMS TO EIAJ SC-88, 1996. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. D) DRAWING FILENAME: MKT-MAA06AREV6 30° 0° 0.46 0.26 DETAIL A SCALE: 60X Figure 6. 6-Lead, SC70, EIAJ SC-88a, 1.25mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specification Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf. Package Designator P6X © 2006 Fairchild Semiconductor Corporation NC7WV07 • Rev. 1.0.2 Tape Section Cavity Number Leader (Start End) 125 (Typical) Cavity Status Cover Type Status Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 6 NC7WV07 — TinyLogic® ULP-A Dual Buffer (Open-Drain Output) Physical Dimensions 2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 0.25 0.15 6X 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X BOTTOM VIEW DETAIL A PIN 1 TERMINAL 0.075 X 45 CHAMFER (0.13) 4X Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M-1994 4. FILENAME AND REVISION: MAC06AREV4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT. Figure 7. 6-Lead, MicroPak™, 1.0mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specification Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. Package Designator L6X © 2006 Fairchild Semiconductor Corporation NC7WV07 • Rev. 1.0.2 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 7 NC7WV07 — TinyLogic® ULP-A Dual Buffer (Open-Drain Output) © 2006 Fairchild Semiconductor Corporation NC7WV07 • Rev. 1.0.2 www.fairchildsemi.com 8