NCP1232 Microprocessor Monitor The NCP1232 is a fully–integrated processor supervisor. It provides three important functions to safeguard processor functionality: precision power on/off reset control, watchdog timer and external reset override. On power–up, the NCP1232 holds the processor in the reset state for a minimum of 250 msec after VCC is within tolerance to ensure a stable system start–up. Microprocessor functionality is monitored by the on–board watchdog circuit. The microprocessor must provide a periodic low–going signal on the ST input. Should the processor fail to supply this signal within the selected time–out period (150 msec, 600 msec or 1200 msec), an out–of–control processor is indicated and the NCP1232 issues a processor reset as a result. The outputs of the NCP1232 are immediately driven active when the PB input is brought low by an external push–button switch or other electronic signal. When connected to a push–button switch, the NCP1232 provides contact debounce. The NCP1232 is packaged in a space–saving 8–pin plastic SOIC package and requires no external components. http://onsemi.com MARKING DIAGRAM 8 SO–8 D SUFFIX CASE 751 8 1 1 YY, Y WW X Z = Year = Work Week = Assembly ID Code = Subcontractor ID Code PIN CONNECTIONS Features • Precision Voltage Monitor • 8–Pin SOIC (Adjustable +4.5 V or +4.75 V) Reset Pulse Width (250 msec Min) No External Components Adjustable Watchdog Timer (150 msec, 600 msec or 1.2 sec) Debounced Manual Reset Input for External Override May, 2000 – Rev. 0 2 TOL 3 GND 4 8 VCC 7 ST 6 RST 5 RST ORDERING INFORMATION Computers Controllers Intelligent Instruments Automotive Systems Critical µP Power Monitoring Semiconductor Components Industries, LLC, 2000 1 TD (Top View) Applications • • • • • PB RST NCP1232D • • • NCP 1232 YWWXZ 1 Device Package Shipping NCP1232DR2 SO–8 2500 Tape & Reel Publication Order Number: NCP1232/D NCP1232 FUNCTIONAL BLOCK DIAGRAM RST VDCC 5%/10% TOLERANCE SELECT TOL RESET GENERATOR RST REF PB RST NCP1232 DEBOUNCE TD WATCHDOG TIMEBASE SELECT WATCHDOG TIMER ST GND PIN DESCRIPTION Pin No. (8–Pin SOIC) Symbol Description 1 PB RST Push–button Reset Input. A debounced active–low input that ignores pulses less than 1 msec in duration and is guaranteed to recognize inputs of 20 msec or greater. 2 TD Time Delay Set. The watchdog time–out select input (tTD = 150 msec for TD = 0 V, tTD = 600 msec for TD = open, tTD = 1.2 sec for TD = VCC.) 3 TOL Tolerance Input. Connect to GND for 5% tolerance or to VCC for 10% tolerance. 4 GND Ground. 5 RST Reset Output (Active High) – goes active: 1. If VCC falls below the selected reset voltage threshold 2. If PB RST is forced low 3. If ST is not strobed within the minimum time–out period 4. During power–up 6 RST Reset Output (Active Low, Open Drain) – see RST. 7 ST 8 VCC Strobe Input. Input for watchdog timer. The +5 V Power Supply Input. http://onsemi.com 2 NCP1232 ABSOLUTE MAXIMUM RATINGS* Voltage on any pin (with respect to GND) –0.3 V to +5.8 V Rating Operating Temperature Range Storage Temperature Range, Tstg Lead Temperature (Soldering, 10 sec) Value Unit –40 to +85 °C –65 to +150 °C +300 °C *Stresses beyond those listed under “Absolute Maximum Ratings’’ may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX; VCC = +4.5 V to 5.5 V, unless otherwise specified.) Characteristic Symbol Test Conditions Min Typ Max Unit Supply Voltage VCC – 4.5 5.0 5.5 V ST and PB RST Input High Level VIH Note 1. 2.0 – VCC +0.3 V ST and PB RST Input Low Level VIL – –0.3 – +0.8 V IL – –1.0 – +1.0 µA Output Current RST IOH VOH = 2.4 V –1.0 –12 – mA Current RST, RST IOL VOL = 0.4 V 2.0 10 – mA Operating Current ICC Note 2. – 50 200 µA VCC 5% Trip Point (Note 3.) VCCTP TOL = GND 4.50 4.62 4.74 V VCC 10% Trip Point (Note 3.) VCCTP TOL = VCC 4.25 4.37 4.49 V Symbol Test Conditions Min Typ Max Unit CIN – – – 5.0 pF COUT – – – 7.0 pF Input Leakage ST, TOL CAPACITANCE (Note 4.) (TA = +25°C) Characteristic Input Capacitance ST, TOL Output Capacitance RST, RST AC ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX; VCC = +5.0 V to Characteristic Symbol Test Conditions Min Typ Max Unit tPB Figure 3 20 – – msec PB RST Delay tPBD Figure 3 1.0 4.0 20 msec Reset Active Time tRST – 250 610 1000 msec ST Pulse Width tST Figure 4 20 – – nsec ST Time–out Period tTD Figure 4 TD Pin = 0 V TD Pin = Open TD Pin = VCC 62.5 250 500 150 600 1200 250 1000 2000 PB RST (Note 5.) 1. 2. 3. 4. 5. 6. "10%, unless otherwise specified.) msec VCC Fall Time (Note 4.) tF Figure 5 10 – – µsec VCC Rise Time (Note 4.) tR Figure 6 0 – – µsec VCC Detect to RST High and RST Low tRPD Figure 7, VCC Falling – – 100 nsec VCC Detect to RST High and RST Open (Note 6.) tRPU Figure 8, VCC Rising 250 610 1000 msec PB RST is internally pulled up to VCC with an internal impedance of typically 40 kΩ. Measured with outputs open. All voltages references to GND. Guaranteed by design. PB RST must be held low for a minimum of 20 msec to guarantee a reset. tR = 5 µsec. http://onsemi.com 3 NCP1232 Power Monitor The NCP1232 detects out–of–tolerance power supply conditions and warns a processor–based system of an impending power failure. When VCC is detected as below the preset level defined by TOL, the VCC comparator outputs the signals RST and RST. If TOL is connected to ground, the RST and RST signals become active as VCC falls below 4.75 volts. If TOL is connected to VCC, the RST and RST become active as VCC falls below 4.5 volts. Because the processing is stopped at the last possible moment of valid VCC, the RST and RST are excellent control signals for a µP. The reset outputs will remain in their active states until VCC has been continuously in–tolerance for a minimum of 250 msec allowing the power supply and µP to stabilize before RST is released. I/O line high while operating in the foreground mode and set it low while in the background or interrupt mode. If both modes do not execute correctly, the watchdog timer issues reset pulses. Supply Monitor Noise Sensitivity The NCP1232 is optimized for fast response to negative–going changes in VDD. Systems with an inordinate amount of electrical noise on VDD (such as systems using relays), may require a 0.01 µF or 0.1 µF bypass capacitor to reduce detection sensitivity. This capacitor should be installed as close to the NCP1232 as possible to keep the capacitor lead length short. +5 V Push–button Reset Input The debounced manual reset input (PB RST) manually forces the reset outputs into their active states. Once PB RST has been low for a time, tPBD, the push–button delay time, the reset outputs go active. The reset outputs remain in their active states for a minimum of 250 msec after PB RST rises above VIH (Figure 3). A mechanical push–button or active logic signal can drive the PB RST input. The debounced input ignores input pulses less than 1 msec and is guaranteed to recognize pulses of 20 msec or greater. No external pull–up resistor is required because the PB RST input has an internal pull–up to VCC of approximately 100 µA. VCC TD I/O MICRO– PROCESSOR ST PB RST RESET RST NCP1232 GND TOL Figure 1. Push–button Reset Watchdog Timer When the ST input is not stimulated for a preset time period, the watchdog timer function forces RST and RST signals to the active state. The preset time period is determined by the TD inputs to be 150 msec with TD connected to ground, 600 msec with TD open, or 1200 msec with TD connected to VCC, typical. The watchdog timer starts timing out from the set time period as soon as RST and RST are inactive. If a high–to–low transition occurs on the ST input pin prior to time–out, the watchdog timer is reset and begins to time–out again. If the watchdog timer is allowed to time–out, then the RST and RST signals are driven to the active state for 250 msec minimum (Figure 2). The software routine that strobes ST is critical. The code must be in a section of software that is executed regularly so the time between toggles is less than the watchdog time–out period. One common technique controls the µP I/O line from two sections of the program. The software might set the +5 V 10 KΩ 3–TERMINAL REGULATOR +5 V 0.1 µF VCC RST NCP1232 ST TD TOL GND Figure 2. Watchdog Timer http://onsemi.com 4 RESET MICRO– PROCESSOR I/O NCP1232 tPB tPBD PB RST VIH VIL tRST RST RST Figure 3. Push–button Reset. The debounced PB RST input ignores input pulses less than 1 msec and is guaranteed to recognized pulses of 20 msec or greater PUSH–BUTTON RESET tST ST tTD Figure 4. Strobe Input NOTE: tTD is the maximum elapsed time between ST high–to–low transistions (ST is activated by falling edges only) which will keep the watchdog timer from forcing the reset outputs active for a time of tRST. tTD is a function of the voltage at the TD pin, as tabulated below. CONDITION TD PIN = 0 V TD PIN = OPEN TD PIN = VCC t TD TYP MIN 62.5 msec 250 msec 500 msec 150 msec 600 msec 1200 msec http://onsemi.com 5 MAX 250 msec 1000 msec 2000 msec NCP1232 tF tR VCC +4.75 V +4.75 V +4.25 V +4.25 V VCC Figure 5. Power–Down Slew Rate Figure 6. Power–Down Slew Rate VCC = 5 V 4.6 V (5% TRIP POINT) +4.5 V (5% TRIP POINT) 4.5 V (10% TRIP POINT) +4.25 V (10% TRIP POINT) VCC tRPD tRPU RST RST VOH RST VOH VOL RST VOL VCC, SLEW RATE = 1.66mV/µsec (0.5 V/300 µsec) Figure 7. VCC Detect Reset Output Delay (Power–Down) Figure 8. VCC Detect Reset Output Delay (Power–Up) http://onsemi.com 6 NCP1232 PACKAGE DIMENSIONS SO–8 D SUFFIX CASE 751–06 ISSUE T D A 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C 5 0.25 H E M B M 1 4 h B e X 45 _ q A C SEATING PLANE L 0.10 A1 B 0.25 M C B S A S DIM A A1 B C D E e H h L q http://onsemi.com 7 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ NCP1232 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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