NCV8870 Automotive Grade Non-Synchronous Boost Controller The NCV8870 is an adjustable output non−synchronous boost controller which drives an external N−channel MOSFET. The device uses peak current mode control with internal slope compensation. The IC incorporates an internal regulator that supplies charge to the gate driver. Protection features include internally−set soft−start, undervoltage lockout, cycle−by−cycle current limiting, hiccup−mode short−circuit protection and thermal shutdown. Additional features include low quiescent current sleep mode and externally−synchronizable switching frequency. Features • • • • • • • • • • • • Peak Current Mode Control with Internal Slope Compensation 1.2 V ±2% Reference voltage Fixed Frequency Operation Wide Input Voltage Range of 3.2 V to 40 Vdc, 45 V Load Dump Input Undervoltage Lockout (UVLO) Internal Soft−Start Low Quiescent Current in Sleep Mode Cycle−by−Cycle Current Limit Protection Hiccup−Mode Overcurrent Protection (OCP) Hiccup−Mode Short−Circuit Protection (SCP) Thermal Shutdown (TSD) This is a Pb−Free Device http://onsemi.com MARKING DIAGRAM 8 SOIC−8 D SUFFIX CASE 751 8 1 8870xx ALYW G 1 8870xx = Specific Device Code xx = 00, 01 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package PIN CONNECTIONS EN/SYNC 1 8 VFB ISNS 2 7 VC GND 3 6 VIN GDRV 4 5 VDRV (Top View) ORDERING INFORMATION Device Package Shipping† NCV887000D1R2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NCV887001D1R2G SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2012 September, 2012 − Rev. 1 1 Publication Order Number: NCV8870/D NCV8870 6 TEMP VDRV FAULT LOGIC EN/SYNC SYNC 1 OSC SC VC 5 CLK 7 PWM EN/ 4 2 CL + RC DRIVE LOGIC CSA 3 CDRV VDRV Cg L D Vo Q GDRV ISNS GND Co RSNS RF1 SCP CC Vg VIN 8 Gm SS VFB RF2 Vref Figure 1. Simplified Block Diagram and Application Schematic PACKAGE PIN DESCRIPTIONS Pin No. Pin Symbol 1 EN/SYNC 2 ISNS Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense resistor to ground to sense the switching current for regulation and current limiting. 3 GND Ground reference. 4 GDRV Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from GDRV to the gate to tailor EMC performance. 5 VDRV Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VIN. Bypass with a 1.0 mF ceramic capacitor to ground. 6 VIN Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addition to a diode from the output voltage to VDRV and/or VIN. 7 VC Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize the converter. 8 VFB Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND creates a voltage divider for regulation and programming of the output voltage. Function Enable and synchronization input. The falling edge synchronizes the internal oscillator. The part is disabled into sleep mode when this pin is brought low for longer than the enable time−out period. http://onsemi.com 2 NCV8870 ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated) Rating Value Unit −0.3 to 40 V Peak Transient Voltage (Load Dump on VIN) 45 V Dc Supply Voltage (VDRV, GDRV) 12 V −0.3 to 6 V −0.3 to 3.6 V Dc Voltage (EN/SYNC) −0.3 to 6 V Dc Voltage Stress (VIN − VDRV)* −0.7 to 40 V Operating Junction Temperature −40 to 150 °C Storage Temperature Range −65 to 150 °C 265 peak °C Dc Supply Voltage (VIN) Peak Transient Voltage (VFB) Dc Voltage (VC, VFB, ISNS) Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *An external diode from the input to the VIN pin is required if bootstrapping VDRV and VIN off of the output voltage. PACKAGE CAPABILITIES Characteristic ESD Capability (All Pins) Human Body Model Machine Model Value Unit w2.0 w200 kV V Moisture Sensitivity Level Package Thermal Resistance Junction−to−Ambient, RqJA (Note 1) 1 − 100 °C/W 1. 1 in2, 1 oz copper area used for heatsinking. Device Variations The NCV8870 features several variants to better fit a multitude of applications. The table below shows the typical values of parameters for the parts that are currently available. TYPICAL VALUES Part No. Dmax fs tss Sa Vcl Isrc Isink VDRV SCE NCV887000 93% 50 kHz 26 ms 15 mV/ms 400 mV 800 mA 600 mA 10.5 V Y NCV887001 93% 100 kHz 13 ms 33 mV/ms 400 mV 800 mA 600 mA 10.5 V Y DEFINITIONS Symbol Dmax Characteristic Symbol Characteristic Symbol Characteristic Maximum Duty Cycle fs Switching Frequency tss Soft−Start Time Sa Slope Compensating Ramp Vcl Current Limit Trip Voltage Isrc Gate Drive Sourcing Current Isink Gate Drive Sinking Current VDRV Drive Voltage http://onsemi.com 3 SCE Short Circuit Enable NCV8870 ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are guaranteed by test, design or statistical correlation. Characteristic Symbol Conditions Min Typ Max Unit GENERAL Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, TJ = 25°C − 2.0 − mA Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, −40°C < TJ < 125°C − 2.0 6.0 mA Quiescent Current, No switching Iq,off Into VIN pin, EN = 1, No switching − 1.5 2.5 mA Quiescent Current, Switching, normal operation Iq,on Into VIN pin, EN = 1, Switching − 3.0 6.0 mA 200 250 300 ns OSCILLATOR Minimum pulse width ton,min Maximum duty cycle Dmax NCV887000 NCV887001 91 91 93 93 95 95 % Switching frequency fs NCV887000 NCV887001 45 90 50 100 55 110 kHz Soft−start time tss From start of switching with VFB = 0 until reference voltage = VREF NCV887000 NCV887001 21 10.5 26 13 31 15.5 From EN → 1 until start of switching with VFB = 0 − 720 840 NCV887000 NCV887001 12 28 15 33 18 38 mV/ms Soft−start delay Slope compensating ramp tss,dly Sa ms ms ENABLE/SYNCHRONIZATION EN/SYNC pull−down current IEN/SYNC − 5.0 10 mA EN/SYNC input high voltage Vs,ih 2.0 − 5.0 V EN/SYNC input low voltage Vs,il 0 − 800 mV EN/SYNC time−out ratio %ten − − 350 % SYNC minimum frequency ratio SYNC maximum frequency %fsync,min VEN/SYNC = 5 V From SYNC falling edge, to oscillator control (EN high) or shutdown (EN low), Percent of typical switching period Percent of fs − − 80 % 1.1 − − MHz − 50 100 ns 25 − 75 % Input−to−output gain at dc, ISNS v 1 V 0.9 1.0 1.1 V/V 2.5 − − MHz − 30 50 mA 360 360 400 400 440 440 − 80 125 ns 125 150 175 % − 80 125 ns fsync,max Synchronization delay ts,dly Synchronization duty cycle Dsync From SYNC falling edge to GDRV falling edge CURRENT SENSE AMPLIFIER Low−frequency gain Acsa Bandwidth BWcsa Gain of Acsa − 3 dB ISNS input bias current Isns,bias Out of ISNS pin Current limit threshold voltage Vcl Voltage on ISNS pin NCV887000 NCV887001 Current limit, Response time tcl CL tripped until GDRV falling edge, VISNS = Vcl + 40 mV Overcurrent protection, Threshold voltage %Vocp Overcurrent protection, Response Time tocp Percent of Vcl From overcurrent event, Until switching stops, VISNS = VOCP + 40 mV http://onsemi.com 4 mV NCV8870 ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are guaranteed by test, design or statistical correlation. Characteristic Symbol Conditions Min Typ Max Unit 0.8 1.2 1.5 mS 2.0 − − MW VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER Transconductance gm,vea VEA output resistance Ro,vea VFB input bias current Ivfb,bias VFB – Vref = ± 20 mV − 0.5 2.0 mA Vref 1.176 1.200 1.224 V VEA maximum output voltage Vc,max 2.5 − − V VEA minimum output voltage Vc,min − − 0.3 V VEA sourcing current Isrc,vea VEA output current, Vc = 2.0 V 80 100 − mA VEA sinking current Isnk,vea VEA output current, Vc = 0.7 V 80 100 − mA Reference voltage Current out of VFB pin GATE DRIVER Sourcing current Isrc VDRV ≥ 6 V, VDRV − VGDRV = 2 V NCV887000 NCV887001 600 600 800 800 − − Sinking current Isink VGDRV ≥ 2 V NCV887000 NCV887001 500 500 600 600 − − VIN − VDRV, IvDRV = 10 mA − 0.2 0.35 V VIN − VDRV = 1 V 10 15 − mA V Driving voltage dropout Vdrv,do mA mA Driving voltage source current Idrv Backdrive diode voltage drop Vd,bd VDRV − VIN, Id,bd = 5 mA − − 0.7 Driving voltage VDRV IVDRV = 0.1 − 25 mA NCV887000 NCV887001 10 10 10.5 10.5 11 11 Undervoltage lock−out, Threshold voltage Vuvlo VIN falling 3.0 3.1 3.2 V Undervoltage lock−out, Hysteresis Vuvlo,hys VIN rising 50 125 200 mV Startup blanking period %tscp,dly From start of soft−start, Percent of tss 100 120 150 % Hiccup−mode period %thcp,dly From shutdown to start of soft−start, Percent of tss 65 80 95 % VFB as percent of Vref 60 67 75 % tscp From VFB < Vscp to stop switching − 35 100 ns Thermal shutdown threshold Tsd TJ rising 160 170 180 °C Thermal shutdown hysteresis Tsd,hys TJ falling 10 15 20 °C Thermal shutdown delay tsd,dly From TJ > Tsd to stop switching − − 100 ns V UVLO SHORT CIRCUIT PROTECTION Short circuit threshold voltage Short circuit delay %Vscp THERMAL SHUTDOWN http://onsemi.com 5 NCV8870 TYPICAL PERFORMANCE CHARACTERISTICS 6 TJ = 25°C 6 Iq,sleep, SLEEP CURRENT (mA) Iq,sleep, SLEEP CURRENT (mA) 7 5 4 3 2 1 0 0 10 20 30 VIN, INPUT VOLTAGE (V) VIN = 13.2 V 5 4 3 2 1 0 −50 40 Figure 2. Sleep Current vs. Input Voltage ton,min MINIMUM ON TIME (ns) Iq,on, QUIESCENTCURRENT (mA) 150 100 200 252 VIN = 13.2 V fs = 100 kHz 3.30 3.25 3.20 3.15 3.10 3.05 −50 fs = 50 kHz 0 50 100 150 TJ, JUNCTION TEMPERATURE (°C) 250 248 246 244 242 240 238 236 −50 200 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (°C) Figure 4. Quiescent Current vs. Temperature Figure 5. Minimum On Time vs. Temperature 1.010 Vref, REFERENCE VOLTAGE (V) NORMALIZED CURRENT LIMIT (25°C) 1.205 1.005 1.000 0.995 0.990 −40 50 Figure 3. Sleep Current vs. Temperature 3.40 3.35 0 TJ, JUNCTION TEMPERATURE (°C) 10 60 110 TJ, JUNCTION TEMPERATURE (°C) 1.203 1.201 1.199 1.197 1.195 −40 160 10 60 110 TJ, JUNCTION TEMPERATURE (°C) Figure 6. Normalized Current Limit vs. Temperature Figure 7. Reference Voltage vs. Temperature http://onsemi.com 6 160 NCV8870 TYPICAL PERFORMANCE CHARACTERISTICS 8.0 TJ = 25°C 6 Ienable, PULLDOWN CURRENT (mA) Ienable, PULLDOWN CURRENT (mA) 7 5 4 3 2 1 0 0 1 2 3 4 Venable, VOLTAGE (V) 5 6 7.5 7.0 6.5 6.0 5.5 5.0 −40 10 60 110 TJ, JUNCTION TEMPERATURE (°C) Figure 8. Enable Pulldown Current vs. Voltage Figure 9. Enable Pulldown Current vs. Temperature http://onsemi.com 7 160 NCV8870 THEORY OF OPERATION VIN Oscillator PWM Comparator − GDRV S Q VOUT Gate Drive R + + L ISNS + CO RL − CSA Slope Compensation Voltage Error VFB − + VEA NCV8870 Compensation Figure 10. Current Mode Control Schematic Current Mode Control If the voltage across the current sense resistor exceeds the over current threshold voltage the device enters over current hiccup mode. The device will remain off for the hiccup time and then go through the soft−start procedure. The NCV8870 incorporates a current mode control scheme, in which the PWM ramp signal is derived from the power switch current. This ramp signal is compared to the output of the error amplifier to control the on−time of the power switch. The oscillator is used as a fixed−frequency clock to ensure a constant operational frequency. The resulting control scheme features several advantages over conventional voltage mode control. First, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. This eliminates the delay caused by the output filter and the error amplifier, which is commonly found in voltage mode controllers. The second benefit comes from inherent pulse−by−pulse current limiting by merely clamping the peak switching current. Finally, since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. This allows for a simpler compensation. The NCV8870 also includes a slope compensation scheme in which a fixed ramp generated by the oscillator is added to the current ramp. A proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control. Short Circuit Protection If the short circuit enable bit is set (SCE = Y) the device will attempt to protect the power MOSFET from damage. When the output voltage falls below the short circuit trip voltage, after the initial short circuit blanking time, the device enters short circuit latch off. The device will remain off for the hiccup time and then go through the soft−start. EN/SYNC The Enable/Synchronization pin has three modes. When a dc logic high (CMOS/TTL compatible) voltage is applied to this pin the NCV8870 operates at the programmed frequency. When a dc logic low voltage is applied to this pin the NCV8870 enters a low quiescent current sleep mode. When a square wave of at least %fsync,min of the free running switching frequency is applied to this pin, the switcher operates at the same frequency as the square wave. If the signal is slower than this, it will be interpreted as enabling and disabling the part. The falling edge of the square wave corresponds to the start of the switching cycle. If device is disabled, it must be disabled for 7 clock cycles before being re−enabled. Current Limit The NCV8870 features two current limit protections, peak current mode and over current latch off. When the current sense amplifier detects a voltage above the peak current limit between ISNS and GND after the current limit leading edge blanking time, the peak current limit causes the power switch to turn off for the remainder of the cycle. Set the current limit with a resistor from ISNS to GND, with R = VCL / Ilimit. UVLO Input Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VIN is too low to support the internal rails and power the controller. The IC will start up when enabled and VIN surpasses the UVLO threshold plus the UVLO hysteresis http://onsemi.com 8 NCV8870 voltage is higher than the output voltage, the minimum duty cycle will be negative. This is because a boost converter cannot have an output lower than the input. In situations where the input is higher than the output, the output will follow the input, minus the diode drop of the output diode and the converter will not attempt to switch. If the calculated Dmax is higher the Dmax of the NCV8870, the conversion will not be possible. It is important for a boost converter to have a restricted Dmax, because while the ideal conversion ration of a boost converter goes up to infinity as D approaches 1, a real converter’s conversion ratio starts to decrease as losses overtake the increased power transfer. If the converter is in this range it will not be able to regulate properly. If the following equation is not satisfied, the device will skip pulses at high VIN: and will shut down when VIN drops below the UVLO threshold or the part is disabled. Internal Soft−Start To insure moderate inrush current and reduce output overshoot, the NCV8870 features a soft start which charges a capacitor with a fixed current to ramp up the reference voltage. This fixed current is based on the switching frequency, so that if the NCV8870 is synchronized to twice the default switching frequency the soft start will last half as long. VDRV An internal regulator provides the drive voltage for the gate driver. Bypass with a ceramic capacitor to ground to ensure fast turn on times. The capacitor should be between 0.1 mF and 1 mF, depending on switching speed and charge requirements of the external MOSFET. D min w t on(min) fs APPLICATION INFORMATION Where: fs: switching frequency [Hz] ton(min): minimum on time [s] Design Methodology This section details an overview of the component selection process for the NCV8870 in continuous conduction mode boost. It is intended to assist with the design process but does not remove all engineering design work. Many of the equations make heavy use of the small ripple approximation. This process entails the following steps: 1. Define Operational Parameters 2. Select Current Sense Resistor 3. Select Output Inductor 4. Select Output Capacitors 5. Select Input Capacitors 6. Select Feedback Resistors 7. Select Compensator Components 8. Select MOSFET(s) 9. Select Diode 2. Select Current Sense Resistor Current sensing for peak current mode control and current limit relies on the MOSFET current signal, which is measured with a ground referenced amplifier. The easiest method of generating this signal is to use a current sense resistor from the source of the MOSFET to device ground. The sense resistor should be selected as follows: RS + Where: RS: sense resistor [W] VCL: current limit threshold voltage [V] ICL: desire current limit [A] 3. Select Output Inductor 1. Define Operational Parameters The output inductor controls the current ripple that occurs over a switching period. A high current ripple will result in excessive power loss and ripple current requirements. A low current ripple will result in a poor control signal and a slow current slew rate in case of load steps. A good starting point for peak to peak ripple is around 10% of the inductor current at the maximum load at the worst case VIN, but operation should be verified empirically. The worst case VIN is half of VOUT, or whatever VIN is closest to half of VIN. After choosing a peak current ripple value, calculate the inductor value as follows: Before beginning the design, define the operating parameters of the application. These include: VIN(min): minimum input voltage [V] VIN(max): maximum input voltage [V] VOUT: output voltage [V] IOUT(max): maximum output current [A] ICL: desired typical cycle-by-cycle current limit [A] From this the ideal minimum and maximum duty cycles can be calculated as follows: D min + 1 * D max + 1 * V CL I CL V IN(max) V OUT L+ V IN(min) V IN(WC) 2 D WC DI L,max f sV OUT Where: VIN(WC): VIN value as close as possible to half of VOUT [V] DWC: duty cycle at VIN(WC) DIL,max: maximum peak to peak ripple [A] V OUT Both duty cycles will actually be higher due to power loss in the conversion. The exact duty cycles will depend on conduction and switching losses. If the maximum input http://onsemi.com 9 NCV8870 7. Select Compensator Components The maximum average inductor current can be calculated as follows: I L,avg + Current Mode control method employed by the NCV8870 allows the use of a simple, Type II compensation to optimize the dynamic response according to system requirements. V OUTI OUT(max) V IN(min) 8. Select MOSFET(s) The Peak Inductor current can be calculated as follows: I L,peak + I L,avg ) In order to ensure the gate drive voltage does not drop out the MOSFET(s) chosen must not violate the following inequality: V IN(min) 2 D max Lf sV OUT Where: IL,peak: Peak inductor current value [A] Q g(total) v 4. Select Output Capacitors The output capacitors smooth the output voltage and reduce the overshoot and undershoot associated with line transients. The steady state output ripple associated with the output capacitors can be calculated as follows: Where: Qg(total): Total Gate Charge of MOSFET(s) [C] Idrv: Drive voltage current [A] fs: Switching Frequency [Hz] The maximum RMS Current can be calculated as follows: V OUT(ripple) + I OUT(max)ǒV OUT * V IN(min)Ǔ ǒC OUTfǓ 2 ) I D(max) + I out I OUT(max)V OUTR ESR V IN(min) Ǹ V Q(max) + V OUT(max) V OUT * V IN(min) V IN(min) 9. Select Diode The output diode rectifies the output current. The average current through diode will be equal to the output current: The use of parallel ceramic bypass capacitors is strongly encouraged to help with the transient response. I D(avg) + I OUT(max) 5. Select Input Capacitors Additionally, the diode must block voltage equal to the higher of the output voltage and the maximum input voltage: The input capacitor reduces voltage ripple on the input to the module associated with the ac component of the input current. I Cin(RMS) + V D(max) + V OUT(max) The maximum power dissipation in the diode can be calculated as follows: V IN(WC) 2 D WC Lf sV OUT2 Ǹ3 P D + V f (max) I OUT(max) Where: Pd: Power dissipation in the diode [W] Vf(max): Maximum forward voltage of the diode [V] 6. Select Feedback Resistors The feedback resistors form a resistor divider from the output of the converter to ground, with a tap to the feedback pin. During regulation, the divided voltage will equal Vref. The lower feedback resistor can be chosen, and the upper feedback resistor value is calculated as follows: R upper + R lower ǸD DȀ The maximum voltage across the MOSFET will be the maximum output voltage, which is the higher of the maximum input voltage and the regulated output voltaged: The capacitors need to survive an RMS ripple current as follows: I Cout(RMS) + I OUT I drv fs Low Voltage Operation If the input voltage drops below the UVLO or MOSFET threshold voltage, another voltage may be used to power the device. Simply connect the voltage you would like to boost to the inductor and connect the stable voltage to the VIN pin of the device. In boost configuration, the output of the converter can be used to power the device. In some cases it may be desirable to connect 2 sources to VIN pin, which can be accomplished simply by connecting each of the sources through a diode to the VIN pin. ǒV out * V refǓ V ref The total feedback resistance (Rupper + Rlower) should be in the range of 1 kW – 100 kW. http://onsemi.com 10 NCV8870 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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