June 1996 NDS8433 Single P-Channel Enhancement Mode Field Effect Transistor General Description Features These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. -5.2A, -20V. RDS(ON) = 0.055Ω @ VGS = -4.5V RDS(ON) = 0.075Ω @ VGS = -2.7V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. ____________________________________________________________________________________________ Absolute Maximum Ratings Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage ID Drain Current - Continuous (Note 1a) 6 3 7 2 8 1 Maximum Power Dissipation NDS8433 Units -20 V -8 V -5.2 A -20 (Note 1a) 2.5 (Note 1b) 1.2 (Note 1c) TJ,TSTG 4 T A = 25°C unless otherwise noted - Pulsed PD 5 Operating and Storage Temperature Range W 1 -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W © 1997 Fairchild Semiconductor Corporation NDS8433 Rev. B1 Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min -20 Typ Max Units -1 µA OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA IDSS Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V V TJ = 55oC -10 µA IGSSF Gate - Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -8 V, VDS= 0 V -100 nA V ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA TJ = 125oC RDS(ON) Static Drain-Source On-Resistance -0.4 -0.8 -1 -0.3 -0.53 -0.8 0.045 0.055 0.06 0.11 0.062 0.075 VGS = -4.5 V, ID = -5.2 A TJ = 125oC VGS = -2.7 V, ID = -4.6 A ID(on) On-State Drain Current gFS Forward Transconductance VGS = -4.5 V, VDS = -5 V -10 VGS = -2.7 V, VDS = -5 V -5 Ω A VDS = -10 V, ID = -5.2 A 13 S VDS = -10 V, VGS = 0 V, f = 1.0 MHz 1500 pF 710 pF 230 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) tf Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = -5 V, ID = -1 A, VGEN = -4.5 V, RGEN = 6 Ω 16 30 ns 41 60 ns Turn - Off Delay Time 100 150 ns Turn - Off Fall Time 50 80 ns 25 40 nC VDS = -5 V, ID = -5.2 A, VGS = -4.5 V 3.6 nC 7.6 nC NDS8433 Rev. B1 Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units -2.1 A -1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -2.1 A -0.8 (Note 2) Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD (t ) = T J −TA R θJ A(t ) = T J −TA R θJ C+RθCA(t ) = I 2D (t ) × RDS ( ON ) TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 50oC/W when mounted on a 1 in2 pad of 2oz copper. b. 105oC/W when mounted on a 0.04 in2 pad of 2oz copper. c. 125oC/W when mounted on a 0.006 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper. 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDS8433 Rev. B1 Typical Electrical Characteristics VGS = -4.5V 2.4 -3.5 -3.0 R DS(on) , NORMALIZED -2.7 -20 -2.5 -15 -10 -2.0 -5 -1.5 0 0 -1 -2 -3 -4 V DS , DRAIN-SOURCE VOLTAGE (V) DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) -25 2.2 1.8 -2.5 1.6 -2.7 -3.0 1.4 -3.5 1.2 -4.0 -4.5 1 0.8 -5 VGS = -2.0V 2 0 -20 -25 1.8 I D = -5.2A 1.4 R DS(on), NORMALIZED V GS = -4.5V 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) 125 DRAIN-SOURCE ON-RESISTANCE R DS(ON), NORMALIZED -15 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.6 T J = 125°C 1.4 1.2 25°C 1 -55°C 0.8 0.6 0.4 150 V GS = -4.5V 1.6 0 -5 J -10 -15 I D , DRAIN CURRENT (A) -20 -25 Figure 4. On-Resistance Variation with Drain Current and Temperature. Figure 3. On-Resistance Variation with Temperature. -20 T = -55°C J 25°C V th , NORMALIZED -16 125°C -12 -8 -4 0 -0.5 -1 -1.5 -2 -2.5 V GS , GATE TO SOURCE VOLTAGE (V) -3 Figure 5. Transfer Characteristics. -3.5 GATE-SOURCE THRESHOLD VOLTAGE 1.3 V DS = -10V I D , DRAIN CURRENT (A) -10 I D , DRAIN CURRENT (A) Figure 1. On-Region Characteristics. DRAIN-SOURCE ON-RESISTANCE -5 -5.0 VDS = V GS 1.2 I D = -250µA 1.1 1 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 Figure 6. Gate Threshold Variation with Temperature. NDS8433 Rev. B1 Typical Electrical Characteristics (continued) 20 10 5 I D = -250µA -I S , REVERSE DRAIN CURRENT (A) BV DSS, NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.08 1.06 1.04 1.02 1 0.98 0.96 0.94 -50 -25 0 25 50 75 100 T J , JUNCTION TEMPERATURE (°C) 125 1 T = 125°C J -55°C 0.01 0.001 0.4 0.6 0.8 1 -V SD , BODY DIODE FORWARD VOLTAGE (V) 1.2 Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. 5 4000 I D = -5.2A 3000 -V GS , GATE-SOURCE VOLTAGE (V) C iss 2000 C oss 1000 500 C rss 300 f = 1 MHz 200 VGS = 0 V 100 0.1 0.2 0.5 1 2 5 10 20 V DS = -5.0V 3 2 1 0 0 5 10 15 20 Q g , GATE CHARGE (nC) R GEN 25 t on -VDD t d(on) RL 30 t off tr t d(off) tf 90% 90% V OUT D -15V Figure 10. Gate Charge Characteristics. Figure 9. Capacitance Characteristics. V IN -10V 4 -V DS , DRAIN TO SOURCE VOLTAGE (V) VGS 25°C 0.1 0.0001 0.2 150 Figure 7. Breakdown Voltage Variation with Temperature. CAPACITANCE (pF) V GS = 0V VOUT 10% 10% DUT G 90% S V IN 50% 50% 10% PULSE W IDTH Figure 11. Switching Test Circuit. INVERTED Figure 12. Switching Waveforms. NDS8433 Rev. B1 Typical Electrical and Thermal Characteristics (continued) 30 2.5 STEADY-STATE POWER DISSIPATION (W) 25 TJ = -55°C 20 25°C 15 125°C 10 5 g FS , TRANSCONDUCTANCE (SIEMENS) VDS = -5.0V 0 0 -4 -8 ID -12 -16 -20 1.5 1b 1c 1 4.5"x5" FR-4 Board o TA = 2 5 C Still Air 0.5 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) , DRAIN CURRENT (A) 6 40 10 0 1m us s 20 5.5 10 -I D , DRAIN CURRENT (A) 1a 5 4.5 1b 4 1c 4.5"x5" FR-4 Board o 3.5 TA = 2 5 C V G S = -4.5V 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 5 RD S(O N) LIM IT 10 10 1 ms 0m s 1s 10 DC s V GS = -4.5V 0.1 SINGLE PULSE R θJ A = See Note 1c T A = 25°C Still Air 3 1 Figure 14. SO-8 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. Figure 13. Transconductance Variation with Drain Current and Temperature. 0.01 0.1 1 0.2 0.5 1 2 5 10 20 40 - V DS , DRAIN-SOURCE VOLTAGE (V) Figure 16. Maximum Safe Operating Area. Figure 15. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. TRANSIENT THERMAL RESISTANCE 1 r(t), NORMALIZED EFFECTIVE -I D , STEADY-STATE DRAIN CURRENT (A) 1a 2 0 .5 D = 0.5 0 .2 0.2 0 .1 0 .0 5 R JA (t) = r(t) * R JA θ θ R JA = See Note 1c θ 0.1 0.05 P(pk) 0.02 0 .0 2 0.01 0 .0 1 t1 Single Pulse 0 .0 0 5 t2 TJ - T = P * R JA (t) θ Duty Cycle, D = t 1 / t 2 A 0 .0 0 2 0 .0 0 1 0 .0001 0 .001 0 .0 1 0 .1 1 10 100 300 t 1 , TIME (sec) Figure 17. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDS8433 Rev. B1 SO-8 Tape and Reel Data and Package Dimensions SOIC(8lds) Packaging Configuration: Figure 1.0 Packaging Description: EL ECT ROST AT IC SEN SIT IVE DEVICES DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S TNR D ATE PT NUMB ER PEEL STREN GTH MIN ___ __ ____ __ ___gms MAX ___ ___ ___ ___ _ gms Antistatic Cover Tape ESD Label SOIC-8 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 2,500 units per 13" or 330cm diameter reel. The reels are dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or 177cm diameter reel. This and some other options are further described in the Packaging Information table. These full reels are individually barcode labeled and placed inside a standard intermediate box (illustrated in figure 1.0) made of recyclable corrugated brown paper. One box contains two reels maximum. And these boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped. Static Dissipative Embossed Carrier Tape F63TNR Label Customized Label F852 NDS 9959 F852 NDS 9959 F852 NDS 9959 F852 NDS 9959 F852 NDS 9959 Pin 1 SOIC (8lds) Packaging Information Packaging Option Packaging type Qty per Reel/Tube/Bag Standard (no flow code) TNR 2,500 L86Z F011 D84Z Rail/Tube TNR TNR 95 4,000 500 13" Dia - 13" Dia 7" Dia 343x64x343 530x130x83 343x64x343 184x187x47 Max qty per Box 5,000 30,000 8,000 1,000 Weight per unit (gm) 0.0774 0.0774 0.0774 0.0774 Weight per Reel (kg) 0.6060 - 0.9696 0.1182 Reel Size Box Dimension (mm) SOIC-8 Unit Orientation Note/Comments 343mm x 342mm x 64mm Standard Intermediate box ESD Label F63TNR Label sample F63TNLabel F63TN Label LOT: CBVK741B019 QTY: 2500 FSID: FDS9953A SPEC: D/C1: D9842 D/C2: QTY1: QTY2: SPEC REV: CPN: N/F: F ESD Label (F63TNR)3 SOIC(8lds) Tape Leader and Trailer Configuration: Figure 2.0 Carrier Tape Cover Tape Components Trailer Tape 640mm minimum or 80 empty pockets Leader Tape 1680mm minimum or 210 empty pockets July 1999, Rev. B SO-8 Tape and Reel Data and Package Dimensions, continued SOIC(8lds) Embossed Carrier Tape Configuration: Figure 3.0 P0 D0 T E1 F K0 Wc W E2 B0 Tc A0 D1 P1 User Direction of Feed Dimensions are in millimeter Pkg type A0 B0 SOIC(8lds) (12mm) 6.50 +/-0.10 5.30 +/-0.10 W 12.0 +/-0.3 D0 D1 E1 E2 1.55 +/-0.05 1.60 +/-0.10 1.75 +/-0.10 F 10.25 min 5.50 +/-0.05 P1 P0 8.0 +/-0.1 4.0 +/-0.1 K0 2.1 +/-0.10 Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and lateral movement requirements (see sketches A, B, and C). T Wc 0.450 +/0.150 9.2 +/-0.3 0.06 +/-0.02 0.5mm maximum 20 deg maximum Typical component cavity center line B0 Tc 0.5mm maximum 20 deg maximum component rotation Typical component center line Sketch A (Side or Front Sectional View) A0 Component Rotation Sketch C (Top View) Component lateral movement Sketch B (Top View) SOIC(8lds) Reel Configuration: Figure 4.0 Component Rotation W1 Measured at Hub Dim A Max Dim A max See detail AA Dim N 7" Diameter Option B Min Dim C See detail AA W3 13" Diameter Option Dim D min W2 max Measured at Hub DETAIL AA Dimensions are in inches and millimeters Tape Size Reel Option Dim A Dim B 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 2.165 55 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 – 0.606 11.9 – 15.4 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 7.00 178 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 – 0.606 11.9 – 15.4 12mm 7" Dia 7.00 177.8 12mm 13" Dia 13.00 330 1998 Fairchild Semiconductor Corporation Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL) July 1999, Rev. B SO-8 Tape and Reel Data and Package Dimensions, continued SOIC-8 (FS PKG Code S1) 1:1 Scale 1:1 on letter size paper Dimensions shown below are in: inches [millimeters] Part Weight per unit (gram): 0.0774 9 September 1998, Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.