ON NTD110N02R-001 Power mosfet Datasheet

NTD110N02R
Power MOSFET
24 V, 110 A, N−Channel DPAK
Features
•
•
•
•
•
•
Planar HD3e Process for Fast Switching Performance
Low RDS(on) to Minimize Conduction Loss
Low Ciss to Minimize Driver Loss
Low Gate Charge
Optimized for High Side Switching Requirements in
High−Efficiency DC−DC Converters
Pb−Free Packages are Available
http://onsemi.com
V(BR)DSS
RDS(on) TYP
ID MAX
24 V
4.1 m @ 10 V
110 A
N−Channel
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Value
Unit
Drain−to−Source Voltage
VDSS
24
V
Gate−to−Source Voltage − Continuous
VGS
±20
V
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C
Drain Current
− Continuous @ TC = 25°C, Chip
− Continuous @ TC = 25°C,
Limited by Package
− Continuous @ TA = 25°C,
Limited by Wires
− Single Pulse (tp = 10 s)
RJC
PD
1.35
110
°C/W
W
ID
ID
110
110
A
A
ID
32
A
ID
110
A
Thermal Resistance
− Junction−to−Ambient (Note 1)
− Total Power Dissipation @ TA = 25°C
− Drain Current − Continuous @ TA = 25°C
RJA
PD
ID
52
2.88
17.5
°C/W
W
A
Thermal Resistance
− Junction−to−Ambient (Note 2)
− Total Power Dissipation @ TA = 25°C
− Drain Current − Continuous @ TA = 25°C
RJA
PD
ID
100
1.5
12.5
°C/W
W
A
TJ, Tstg
−55 to
175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc,
IL = 15.5 Apk, L = 1.0 mH, RG = 25 )
EAS
120
mJ
Maximum Lead Temperature for Soldering
Purposes, (1/8″ from case for 10 s)
TL
260
°C
Operating and Storage
Temperature Range
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
G
S
4
4
1
1 2
3
2
3
CASE 369D
DPAK
(Straight Lead)
STYLE 2
CASE 369AA
DPAK
(Surface Mount)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4
Drain
4
Drain
YWW
T
110N2
Symbol
YWW
T
110N2
Rating
2
1
3
Drain
Gate
Source
Y
WW
T110N2
1 2 3
Gate Drain Source
= Year
= Work Week
= Device Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
 Semiconductor Components Industries, LLC, 2004
December, 2004 − Rev. 6
1
Publication Order Number:
NTD110N02R/D
NTD110N02R
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
24
28
15
Max
Unit
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 V, ID = 250 A)
Positive Temperature Coefficient
Zero Gate Voltage Drain Current
(VDS = 20 V, VGS = 0 V)
(VDS = 20 V, VGS = 0 V, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ±20 V, VDS = 0 V)
IGSS
V
mV/°C
A
1.5
10
±100
nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 A)
Negative Threshold Temperature Coefficient
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 10 V, ID = 110 A)
(VGS = 4.5 V, ID = 55 A)
(VGS = 10 V, ID = 20 A)
(VGS = 4.5 V, ID = 20 A)
RDS(on)
V
1.0
1.5
5.0
mV/°C
m
4.1
5.5
3.9
5.5
Forward Transconductance (VDS = 10 V, ID = 15 A) (Note 3)
2.0
4.6
6.2
gFS
44
Mhos
Ciss
2710
3440
Coss
1105
1670
Crss
450
640
td(on)
11
22
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 20 V
V, VGS = 0 V,
V
f = 1.0 MHz)
Transfer Capacitance
pF
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VGS = 10 V, VDD = 10 V,
ID = 40 A, RG = 3.0 )
tr
39
80
td(off)
27
40
tf
21
40
QT
23.6
28
nC
QGS
5.1
QDS
11
VSD
0.82
0.99
0.65
1.2
V
trr
36.5
ta
30
tb
25
Qrr
0.048
Fall Time
Gate Charge
(VGS = 4
4.5
5V
V, ID = 40 A
A,
VDS = 10 V) (Note 3)
ns
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 20 A, VGS = 0 V) (Note 3)
(IS = 55 A, VGS = 0 V)
(IS = 20 A, VGS = 0 V, TJ = 125°C)
Reverse Recovery Time
(IS = 30 A,
A VGS = 0 V,
V
dIS/dt = 100 A/s) (Note 3)
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
2
ns
C
NTD110N02R
210
150
5V
4.5 V
6V
125
4.2 V
4V
3.8 V
3.6 V
3.4 V
3.2 V
100
75
50
3V
2.8 V
2.6 V
2.4 V
25
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω)
VDS ≥ 10 V
TJ = 25°C
ID, DRAIN CURRENT (AMPS)
10 V
8V
2
4
6
180
150
120
90
TJ = 175°C
60
TJ = 25°C
30
TJ = −55°C
0
10
8
0
2
Figure 2. Transfer Characteristics
0.02
0.01
0
2
6
4
8
10
0.014
TJ = 25°C
0.012
0.01
0.008
VGS = 4.5 V
0.006
0.004
VGS = 10 V
0.002
0
20
40
60
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
80 100 120 140 160 180 200 220 240
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
100,000
2.0
VGS = 0 V
ID = 55 A
VGS = 10 V
TJ = 175°C
10,000
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
8
Figure 1. On−Region Characteristics
ID = 110 A
TJ = 25°C
1.6
1.4
1.2
1.0
1000
100
TJ = 100°C
0.8
0.6
−50
6
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.03
1.8
4
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω)
ID, DRAIN CURRENT (AMPS)
175
−25
0
25
50
75
100
125
150
175
10
0
5.0
10
15
20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
http://onsemi.com
3
25
C, CAPACITANCE (pF)
VDS = 0 V VGS = 0 V
TJ = 25°C
Ciss
4000
3000
Ciss
2000
Crss
Coss
1000
Crss
0
10
5
0
VGS
5
10
15
20
5
20
QT
4
16
VGS
QGS
3
QDS
12
VDS
2
8
1
4
ID = 40 A
TJ = 25°C
0
0
5
VDS
10
15
20
0
25
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
5000
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTD110N02R
Qg, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
1000
td(off)
tf
100
tr
10
td(on)
1
1
10
100
100
VGS = 0 V
TJ = 25°C
80
60
40
20
0
0.4
0.6
0.8
1.0
RG, GATE RESISTANCE (Ω)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
1000
ID, DRAIN CURRENT (AMPS)
t, TIME (ns)
IS, SOURCE CURRENT (AMPS)
120
VDS = 10 V
ID = 55 A
VGS = 10 V
VGS = 20 V
SINGLE PULSE
TC = 25°C
100
1 ms
10 ms
10
dc
RDS(on) Limit
Thermal Limit
Package Limit
1.0
0.1
1.0
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
http://onsemi.com
4
1.2
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
NTD110N02R
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
0.00001
Single Pulse
0.0001
0.001
0.01
t, TIME (s)
Figure 12. Thermal Response
http://onsemi.com
5
0.1
1.0
10
NTD110N02R
ORDERING INFORMATION
Package
Shipping†
DPAK
75 Units/Rail
DPAK
(Pb−Free)
75 Units/Rail
NTD110N02R−001
DPAK (Straight Lead)
75 Units/Rail
NTD110N02R−001G
DPAK (Straight Lead)
(Pb−Free)
75 Units/Rail
DPAK
2500 Tape & Reel
DPAK
(Pb−Free)
2500 Tape & Reel
Device
NTD110N02R
NTD110N02RG
NTD110N02RT4
NTD110N02RT4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
6
NTD110N02R
PACKAGE DIMENSIONS
DPAK
CASE 369AA−01
ISSUE O
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
−T−
E
R
4
Z
A
S
1
2
DIM
A
B
C
D
E
F
J
L
R
S
U
V
Z
3
U
F
J
L
D
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
2 PL
0.13 (0.005)
M
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.025 0.035
0.018 0.024
0.033 0.045
0.018 0.023
0.090 BSC
0.180 0.215
0.025 0.040
0.020
−−−
0.035 0.050
0.155
−−−
T
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.101
5.80
0.228
3.0
0.118
1.6
0.063
6.172
0.243
SCALE 3:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
7
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.63
0.88
0.46
0.61
0.83
1.14
0.46
0.58
2.29 BSC
4.57
5.45
0.63
1.01
0.51
−−−
0.89
1.27
3.93
−−−
NTD110N02R
PACKAGE DIMENSIONS
DPAK
CASE 369D−01
ISSUE O
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
8
For additional information, please contact your
local Sales Representative.
NTD110N02R/D