NTD4909N Power MOSFET 30 V, 41 A, Single N−Channel, DPAK/IPAK Features Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb−Free Devices http://onsemi.com V(BR)DSS Applications • CPU Power Delivery • DC−DC Converters RDS(on) MAX 8.0 mW @ 10 V 30 V Symbol D Value Unit Drain−to−Source Voltage VDSS 30 V Gate−to−Source Voltage VGS "20 V ID 12.1 A TA = 100°C S 8.6 Power Dissipation (RqJA) (Note 1) TA = 25°C PD 2.6 W Continuous Drain Current (RqJA) (Note 2) TA = 25°C ID 8.8 A Power Dissipation (RqJA) (Note 2) Steady State Continuous Drain Current (RqJC) (Note 1) TA = 25°C TC = 25°C 6.2 PD ID TC = 100°C Power Dissipation (RqJC) (Note 1) Pulsed Drain Current TA = 100°C tp=10ms Current Limited by Package 1.37 W A 41 29 TC = 25°C PD 29.4 W TA = 25°C IDM 167 A TA = 25°C IDmaxPkg 60 A TJ, Tstg −55 to 175 °C IS 27 A dV/dt 7.0 V/ns EAS 28 mJ TL 260 Operating Junction and Storage Temperature Source Current (Body Diode) Drain to Source dV/dt Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, L = 0.1 mH, IL(pk) = 24 A, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. 4 4 4 1 2 1 3 CASE 369AA DPAK (Bent Lead) STYLE 2 2 3 1 2 3 CASE 369AD CASE 369D IPAK IPAK (Straight Lead) (Straight Lead DPAK) MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain YWW 49 09NG TA = 25°C N−Channel G YWW 49 09NG Continuous Drain Current (RqJA) (Note 1) 41 A 12 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter ID MAX 4 Drain YWW 49 09NG • • • • 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 4909N G = Year = Work Week = Device Code = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. © Semiconductor Components Industries, LLC, 2009 June, 2009 − Rev. 1 1 Publication Order Number: NTD4909N/D NTD4909N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 5.1 °C/W Junction−to−TAB (Drain) RqJC−TAB 4.3 Junction−to−Ambient − Steady State (Note 3) RqJA 58.2 Junction−to−Ambient − Steady State (Note 4) RqJA 110 3. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 4. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V 15 VGS = 0 V, VDS = 24 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS = VDS, ID = 250 mA mA "100 nA 2.2 V ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance VGS(TH)/TJ RDS(on) gFS 1.7 4.0 VGS = 10 V VGS = 4.5 V Forward Transconductance 1.0 ID = 30 A 6.5 ID = 15 A 6.5 ID = 30 A 9.5 ID = 15 A 9.5 VDS = 1.5 V, ID = 30 A mV/°C 8.0 mW 12 52 S 1314 pF CHARGES AND CAPACITANCES Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge Total Gate Charge VGS = 0 V, f = 1.0 MHz, VDS = 15 V 17.4 7.6 nC VGS = 4.5 V, VDS = 15 V, ID = 30 A 2.1 VGS = 10 V, VDS = 15 V, ID = 30 A 17.5 nC 11 ns QGD QG(TOT) 487 4.3 1.3 SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W 21 17 tf 2.7 td(on) 8.0 tr td(off) VGS = 10 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 19 21 2.3 5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns NTD4909N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit TJ = 25°C 0.9 1.1 V TJ = 125°C 0.8 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD tRR Charge Time ta Discharge Time tb Reverse Recovery Time VGS = 0 V, IS = 30 A ns 30 VGS = 0 V, dIs/dt = 100 A/ms, IS = 30 A 16 14 QRR 20 nC Source Inductance (Note 7) LS 2.99 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK (Note 7) LD Gate Inductance (Note 7) LG 4.9 Gate Resistance RG 1.0 PACKAGE PARASITIC VALUES TA = 25°C 1.88 2.0 W 7. Assume terminal length of 110 mils. ORDERING INFORMATION Package Shipping† NTD4909NT4G DPAK (Pb−Free) 2500 / Tape & Reel NTD4909N−1G IPAK (Pb−Free) 75 Units / Rail NTD4909N−35G IPAK Trimmed Lead (Pb−Free) 75 Units / Rail Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 3 NTD4909N TYPICAL CHARACTERISTICS 90 80 TJ = 25°C VDS = 10 V 60 3.6 V 50 3.4 V 40 3.2 V 30 3.0 V 20 2.8 V 10 2.6 V 2.4 V 0 1 2 ID, DRAIN CURRENT (A) 3.8 V 3 4 TJ = 25°C 20 0.014 0.012 0.010 0.008 0.006 4.0 5.0 6.0 7.0 8.0 9.0 VGS (V) 2.5 3.0 3.5 4.0 10 4.5 0.014 0.013 TJ = 25°C 0.012 0.011 VGS = 4.5 V 0.010 0.009 0.008 VGS = 10 V 0.007 0.006 0.005 0.004 15 25 35 45 55 65 75 85 95 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. VGS Figure 4. On−Resistance vs. Drain Current and Gate Voltage 10,000 VGS = 0 V ID = 30 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2.0 Figure 2. Transfer Characteristics 0.016 1.8 TJ = −55°C Figure 1. On−Region Characteristics 0.018 2.0 TJ = 125°C VGS, GATE−TO−SOURCE VOLTAGE (V) ID = 30 A TJ = 25°C 3.0 40 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.020 0.004 60 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (A) 4.2 V VGS = 4.0 V 70 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 7 V 4.5 V 10 V 80 TJ = 150°C 1000 1.6 1.4 1.2 1.0 TJ = 125°C 100 TJ = 85°C 0.8 0.6 −50 −25 0 25 50 75 100 125 150 175 10 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 4 30 NTD4909N TYPICAL CHARACTERISTICS VGS, GATE−TO−SOURCE VOLTAGE (V) 2000 C, CAPACITANCE (pF) VGS = 0 V TJ = 25°C 1500 Ciss 1000 Coss 500 0 Crss 0 5 10 15 20 25 30 15.0 13.5 Qgs 4.5 VDD = 15 V VGS = 10 V ID = 30 A 3.0 1.5 0 0 2 4 6 8 10 12 14 16 18 Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 20 30 IS, SOURCE CURRENT (A) t, TIME (ns) Qgd 6.0 Figure 7. Capacitance Variation td(off) tf tr 10 td(on) 1 10 VGS = 0 V 25 20 15 TJ = 125°C 10 5 0 100 TJ = 25°C 0 0.2 0.4 0.6 0.8 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ) 1000 ID, DRAIN CURRENT (A) 7.5 Qg, TOTAL GATE CHARGE (nC) 100 100 10 ms 10 0.1 9.0 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDD = 15 V ID = 15 A VGS = 10 V 1 QT 10.5 1000 1 TJ = 25°C 12.0 100 ms 1 ms VGS = 10 V Single Pulse TC = 25°C RDS(on) Limit Thermal Limit Package Limit 0.1 10 ms dc 1 10 100 30 ID = 24 A 25 20 15 10 5 0 25 50 75 100 125 150 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTD4909N TYPICAL CHARACTERISTICS 100 R(t) (°C/W) 10 1 Duty Cycle = 50% 20% 10% 5% 2% 1% 0.1 Single Pulse 0.01 Psi Tab−A 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 PULSE TIME (sec) Figure 13. FET Thermal Response 60 50 40 GFS (S) 0.001 30 20 10 0 0 5 10 15 20 25 30 35 ID (A) Figure 14. GFS vs. ID http://onsemi.com 6 40 45 50 100 1000 NTD4909N PACKAGE DIMENSIONS DPAK CASE 369AA−01 ISSUE A −T− C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE E R 4 A S 1 2 3 DIM A B C D E F H J L R S U V Z Z H U F J L D 2 PL 0.13 (0.005) M T SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.101 5.80 0.228 3.0 0.118 1.6 0.063 6.172 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.030 0.045 0.386 0.410 0.018 0.023 0.090 BSC 0.180 0.215 0.024 0.040 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.89 0.46 0.61 0.77 1.14 9.80 10.40 0.46 0.58 2.29 BSC 4.57 5.45 0.60 1.01 0.51 −−− 0.89 1.27 3.93 −−− NTD4909N PACKAGE DIMENSIONS 3.5 MM IPAK, STRAIGHT LEAD CASE 369AD−01 ISSUE O A E E3 L2 E2 A1 D2 D L1 NOTES: 1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH. DIM A A1 A2 b b1 D D2 E E2 E3 e L L1 L2 L T SEATING PLANE A1 b1 2X e A2 3X b 0.13 M E2 T D2 MILLIMETERS MIN MAX 2.19 2.38 0.46 0.60 0.87 1.10 0.69 0.89 0.77 1.10 5.97 6.22 4.80 −−− 6.35 6.73 4.70 −−− 4.45 5.46 2.28 BSC 3.40 3.60 −−− 2.10 0.89 1.27 OPTIONAL CONSTRUCTION IPAK (STRAIGHT LEAD DPAK) CASE 369D−01 ISSUE B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. C B E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G H M INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 3 PL 0.13 (0.005) DIM A B C D E F G H J K R S V Z T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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