NXP NTS0102GT Dual supply translating transceiver; open drain; auto direction sensing Datasheet

NTS0102
Dual supply translating transceiver; open drain; auto
direction sensing
Rev. 2 — 11 April 2011
Product data sheet
1. General description
The NTS0102 is a 2-bit, dual supply translating transceiver with auto direction sensing,
that enables bidirectional voltage level translation. It features two 2-bit input-output ports
(An and Bn), one output enable input (OE) and two supply pins (VCC(A) and VCC(B)). VCC(A)
can be supplied at any voltage between 1.65 V and 3.6 V and VCC(B) can be supplied at
any voltage between 2.3 V and 5.5 V, making the device suitable for translating between
any of the voltage nodes (1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An and OE are referenced to
VCC(A) and pins Bn are referenced to VCC(B). A LOW level at pin OE causes the outputs to
assume a high-impedance OFF-state. This device is fully specified for partial power-down
applications using IOFF. The IOFF circuitry disables the output, preventing the damaging
backflow current through the device when it is powered down.
2. Features and benefits
„ Wide supply voltage range:
‹ VCC(A): 1.65 V to 3.6 V and VCC(B): 2.3 V to 5.5 V
„ Maximum data rates:
‹ Push-pull: 50 Mbps
„ IOFF circuitry provides partial Power-down mode operation
„ Inputs accept voltages up to 5.5 V
„ ESD protection:
‹ HBM JESD22-A114E Class 2 exceeds 2500 V for A port
‹ HBM JESD22-A114E Class 3B exceeds 8000 V for B port
‹ MM JESD22-A115-A exceeds 200 V
‹ CDM JESD22-C101E exceeds 1500 V
„ Latch-up performance exceeds 100 mA per JESD 78B Class II
„ Multiple package options
„ Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Applications
„ I2C/SMBus
„ UART
„ GPIO
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
NTS0102DP
−40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
NTS0102GT
−40 °C to +125 °C
XSON8
plastic extremely thin small outline package;
no leads; 8 terminals; body 1 × 1.95 × 0.5 mm
SOT833-1
NTS0102GD
−40 °C to +125 °C
XSON8U
plastic extremely thin small outline package; no
SOT996-2
leads; 8 terminals; UTLP based; body 3 × 2 × 0.5 mm
NTS0102GF
−40 °C to +125 °C
XSON8
extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1 × 0.5 mm
SOT1089
NTS0102GU
−40 °C to +125 °C
XQFN10
plastic, extremely thin quad flat package; no leads;
10 terminals; body 1.40 × 1.80 × 0.50 mm
SOT1160-1
5. Marking
Table 2.
Marking
Type number
Marking code
NTS0102DP
s02
NTS0102GT
s02
NTS0102GD
s02
NTS0102GF
s2
NTS0102GU
s2
6. Functional diagram
OE
A2
GATE BIAS
6
4
1
A1
B2
5
8
VCC(A)
GATE BIAS
B1
VCC(B)
001aal905
Fig 1.
Logic symbol
NTS0102
Product data sheet
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Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
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NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
7. Pinning information
7.1 Pinning
NTS0102
B2
1
8
B1
GND
2
7
VCC(B)
VCC(A)
3
6
OE
A2
4
5
A1
NTS0102
B2
1
8
B1
GND
2
7
VCC(B)
VCC(A)
3
6
OE
A2
4
5
A1
001aam489
Transparent top view
001aam488
Fig 2.
Pin configuration SOT505-2 (TSSOP8)
Fig 3.
Pin configuration SOT833-1 (XSON8) and
SOT1089 (XSON8)
B2
1
8
B1
GND
2
7
VCC(B)
VCC(A)
3
6
OE
A2
4
5
A1
8 B1
terminal 1
index area
NTS0102
9 GND
10 A1
NTS0102
A2 1
7 n.c.
Transparent top view
Product data sheet
B2 5
001aam559
Transparent top view
Pin configuration SOT996-2 (XSON8U)
NTS0102
OE 4
001aam490
Fig 4.
6 VCC(B)
n.c. 3
VCC(A) 2
Fig 5.
Pin configuration SOT1160-1 (XQFN10)
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Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
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NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
7.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT505-2, SOT833-1, SOT1089 and SOT996-2
SOT1160-1
B2, B1
1, 8
5, 8
data input or output (referenced to VCC(B))
GND
2
9
ground (0 V)
VCC(A)
3
2
supply voltage A
A2, A1
4, 5
1, 10
data input or output (referenced to VCC(A))
OE
6
4
output enable input (active HIGH;
referenced to VCC(A))
VCC(B)
7
6
supply voltage B
n.c.
-
3, 7
not connected
8. Functional description
Table 4.
Function table[1]
Supply voltage
Input
Input/output
OE
An
VCC(A)
VCC(B)
Bn
1.65 V to VCC(B)
2.3 V to 5.5 V
L
Z
Z
1.65 V to VCC(B)
2.3 V to 5.5 V
H
input or output
output or input
GND[2]
GND[2]
X
Z
Z
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2]
When either VCC(A) or VCC(B) is at GND level, the device goes into power-down mode.
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC(A)
supply voltage A
VCC(B)
supply voltage B
VI
VO
input voltage
output voltage
Conditions
Unit
−0.5
+6.5
V
−0.5
+6.5
V
A port and OE input
−0.5
+6.5
V
B port
[1][2]
−0.5
+6.5
V
Active mode
[1][2]
−0.5
VCCO + 0.5
V
A port
−0.5
+4.6
V
B port
−0.5
+6.5
V
−50
-
mA
Power-down or 3-state mode
IIK
input clamping current
VI < 0 V
IOK
output clamping current
VO < 0 V
IO
output current
VO = 0 V to VCCO
ICC
supply current
ICC(A) or ICC(B)
Product data sheet
Max
[1][2]
A or B port
NTS0102
Min
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 April 2011
[1]
[2]
−50
-
mA
-
±50
mA
-
100
mA
© NXP B.V. 2011. All rights reserved.
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NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
Table 5.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
IGND
ground current
Tstg
storage temperature
Tamb = −40 °C to +125 °C
total power dissipation
Ptot
[3]
Min
Max
Unit
−100
-
mA
−65
+150
°C
-
250
mW
[1]
The minimum input and minimum output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
VCCO is the supply voltage associated with the output.
[3]
For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For XSON8 and XSON8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
For XQFN10 package: above 128 °C the value of Ptot derates linearly with 11.5 mW/K.
10. Recommended operating conditions
Table 6.
Recommended operating conditions[1][2]
Symbol
Parameter
Min
Max
Unit
VCC(A)
supply voltage A
Conditions
1.65
3.6
V
VCC(B)
supply voltage B
2.3
5.5
V
Tamb
ambient temperature
−40
+125
°C
Δt/ΔV
input transition rise and fall rate
-
10
ns/V
-
10
ns/V
A or B port; push-pull driving
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
OE input
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
[1]
The A and B sides of an unused I/O pair must be held in the same state, both at VCCI or both at GND.
[2]
VCC(A) must be less than or equal to VCC(B).
11. Static characteristics
Table 7.
Typical static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
OE input; VI = 0 V to 3.6 V; VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
-
-
±1
μA
-
-
±1
μA
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0 V to 5.5 V
-
-
±1
μA
B port; VI or VO = 0 V to 5.5 V;
VCC(B) = 0 V; VCC(A) = 0 V to 3.6 V
-
-
±1
μA
OE input; VCC(A) = 3.3 V; VCC(B) = 3.3 V
-
1
-
pF
II
input leakage
current
IOZ
OFF-state output A or B port; VO = 0 V or VCCO; VCC(A) = 1.65 V to 3.6 V;
current
VCC(B) = 2.3 V to 5.5 V
IOFF
power-off
leakage current
CI
input
capacitance
NTS0102
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 April 2011
[1]
© NXP B.V. 2011. All rights reserved.
5 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
Table 7.
Typical static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
CI/O
A port
-
5
-
pF
B port
-
8.5
-
pF
A or B port; VCC(A) = 3.3 V; VCC(B) = 3.3 V
-
11
-
pF
[1]
input/output
capacitance
VCCO is the supply voltage associated with the output.
Table 8.
Typical supply current
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
VCC(A)
VCC(B)
2.5 V
Unit
3.3 V
5.0 V
ICC(A)
ICC(B)
ICC(A)
ICC(B)
ICC(A)
ICC(B)
1.8 V
0.1
0.5
0.1
1.5
0.1
4.6
μA
2.5 V
0.1
0.1
0.1
0.8
0.1
3.8
μA
3.3 V
-
-
0.1
0.1
0.1
2.8
μA
Table 9.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
HIGH-level
input voltage
−40 °C to +85 °C
Conditions
−40 °C to +125 °C
Min
Max
Min
Max
Unit
A port
VCC(A) = 1.65 V to 1.95 V;
VCC(B) = 2.3 V to 5.5 V
[1]
VCCI − 0.2
-
VCCI − 0.2
-
V
VCC(A) = 2.3 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
[1]
VCCI − 0.4
-
VCCI − 0.4
-
V
[1]
VCCI − 0.4
-
VCCI − 0.4
-
V
0.65VCC(A)
-
0.65VCC(A)
-
V
-
0.15
-
0.15
V
-
0.35VCC(A)
-
0.67VCCO
-
0.67VCCO
-
V
-
0.4
-
0.4
V
B port
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
OE input
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
VIL
LOW-level
input voltage
A or B port
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
OE input
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
VOH
VOL
HIGH-level
output voltage
IO = −20 μA
LOW-level
output voltage
A or B port; IO = 1 mA
NTS0102
Product data sheet
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
[2]
0.35VCC(A) V
[2]
VI ≤ 0.15 V;
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
6 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
Table 9.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
−40 °C to +85 °C
Conditions
−40 °C to +125 °C
Unit
Min
Max
Min
Max
-
±2
-
±12
μA
-
±2
-
±12
μA
II
input leakage
current
OE input; VI = 0 V to 3.6 V;
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
IOZ
OFF-state
output current
A or B port; VO = 0 V or VCCO;
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
IOFF
power-off
leakage
current
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0 V to 5.5 V
-
±2
-
±12
μA
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V; VCC(A) = 0 V to 3.6 V
-
±2
-
±12
μA
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
-
2.4
-
15
μA
VCC(A) = 3.6 V; VCC(B) = 0 V
-
2.2
-
15
μA
VCC(A) = 0 V; VCC(B) = 5.5 V
-
−1
-
−8
μA
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
-
12
-
30
μA
VCC(A) = 3.6 V; VCC(B) = 0 V
-
−1
-
−5
μA
VCC(A) = 0 V; VCC(B) = 5.5 V
-
1
-
6
μA
-
14.4
-
30
μA
ICC
supply current
VI = 0 V or VCCI; IO = 0 A
[2]
[1]
ICC(A)
ICC(B)
ICC(A) + ICC(B)
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
[1]
VCCI is the supply voltage associated with the input.
[2]
VCCO is the supply voltage associated with the output.
12. Dynamic characteristics
Table 10. Dynamic characteristics for temperature range −40 °C to +85 °C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
Conditions
VCC(B)
Unit
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5.0 V ± 0.5 V
Min
Max
Min
Max
Min
Max
VCC(A) = 1.8 V ± 0.15 V
tPHL
HIGH to LOW
propagation delay
A to B
-
4.6
-
4.7
-
5.8
ns
tPLH
LOW to HIGH
propagation delay
A to B
-
6.8
-
6.8
-
7.0
ns
tPHL
HIGH to LOW
propagation delay
B to A
-
4.4
-
4.5
-
4.7
ns
tPLH
LOW to HIGH
propagation delay
B to A
-
5.3
-
4.5
-
0.5
ns
NTS0102
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
7 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
Table 10. Dynamic characteristics for temperature range −40 °C to +85 °C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
Conditions
VCC(B)
Unit
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5.0 V ± 0.5 V
Min
Max
Min
Max
Min
Max
ten
enable time
OE to A; B
-
200
-
200
-
200
ns
tdis
disable time
OE to A; no external load
[2]
-
25
-
25
-
25
ns
OE to B; no external load
[2]
-
25
-
25
-
25
ns
-
230
-
230
-
230
ns
OE to A
-
200
-
200
-
200
ns
LOW to HIGH
output transition
time
OE to B
A port
3.2
9.5
2.3
9.3
1.8
7.6
ns
B port
3.3
10.8
2.7
9.1
2.7
7.6
ns
HIGH to LOW
output transition
time
A port
2.0
5.9
1.9
6.0
1.7
13.3
ns
B port
2.9
7.6
2.8
7.5
2.8
10.0
ns
tsk(o)
output skew time
between channels
-
0.7
-
0.7
-
0.7
ns
tW
pulse width
data inputs
20
-
20
-
20
-
ns
fdata
data rate
-
50
-
50
-
50
Mbps
tTLH
tTHL
[3]
VCC(A) = 2.5 V ± 0.2 V
tPHL
HIGH to LOW
propagation delay
A to B
-
3.2
-
3.3
-
3.4
ns
tPLH
LOW to HIGH
propagation delay
A to B
-
3.5
-
4.1
-
4.4
ns
tPHL
HIGH to LOW
propagation delay
B to A
-
3.0
-
3.6
-
4.3
ns
tPLH
LOW to HIGH
propagation delay
B to A
-
2.5
-
1.6
-
0.7
ns
ten
enable time
OE to A; B
tdis
disable time
-
200
-
200
-
200
ns
OE to A; no external load
[2]
-
20
-
20
-
20
ns
OE to B; no external load
[2]
-
20
-
20
-
20
ns
OE to A
-
200
-
200
-
200
ns
OE to B
-
200
-
200
-
200
ns
LOW to HIGH
output transition
time
A port
2.8
7.4
2.6
6.6
1.8
6.2
ns
B port
3.2
8.3
2.9
7.9
2.4
6.8
ns
HIGH to LOW
output transition
time
A port
1.9
5.7
1.9
5.5
1.8
5.3
ns
B port
2.2
7.8
2.4
6.7
2.6
6.6
ns
tsk(o)
output skew time
between channels
-
0.7
-
0.7
-
0.7
ns
tW
pulse width
data inputs
20
-
20
-
20
-
ns
fdata
data rate
-
50
-
50
-
50
Mbps
tTLH
tTHL
[3]
VCC(A) = 3.3 V ± 0.3 V
tPHL
HIGH to LOW
propagation delay
A to B
-
-
-
2.4
-
3.1
ns
tPLH
LOW to HIGH
propagation delay
A to B
-
-
-
4.2
-
4.4
ns
NTS0102
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
8 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
Table 10. Dynamic characteristics for temperature range −40 °C to +85 °C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
Conditions
VCC(B)
Unit
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5.0 V ± 0.5 V
Min
Max
Min
Max
Min
Max
tPHL
HIGH to LOW
propagation delay
B to A
-
-
-
2.5
-
3.3
ns
tPLH
LOW to HIGH
propagation delay
B to A
-
-
-
2.5
-
2.6
ns
ten
enable time
OE to A; B
-
-
-
200
-
200
ns
tdis
disable time
OE to A; no external load
[2]
-
-
-
15
-
15
ns
OE to B; no external load
[2]
-
-
-
15
-
15
ns
OE to A
-
-
-
260
-
260
ns
OE to B
-
-
-
200
-
200
ns
LOW to HIGH
output transition
time
A port
-
-
2.3
5.6
1.9
5.9
ns
B port
-
-
2.5
6.4
2.1
7.4
ns
HIGH to LOW
output transition
time
A port
-
-
2.0
5.4
1.9
5.0
ns
B port
-
-
2.3
7.4
2.4
7.6
ns
tsk(o)
output skew time
between channels
-
-
-
0.7
-
0.7
ns
tW
pulse width
data inputs
-
-
20
-
20
-
ns
fdata
data rate
-
-
-
50
-
50
tTLH
tTHL
[1]
[3]
Mbps
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[2]
Delay between OE going LOW and when the outputs are actually disabled.
[3]
Skew between any two outputs of the same package switching in the same direction.
Table 11. Dynamic characteristics for temperature range −40 °C to +125 °C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
Conditions
VCC(B)
Unit
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5.0 V ± 0.5 V
Min
Max
Min
Max
Min
Max
VCC(A) = 1.8 V ± 0.15 V
tPHL
HIGH to LOW
propagation delay
A to B
-
5.8
-
5.9
-
7.3
ns
tPLH
LOW to HIGH
propagation delay
A to B
-
8.5
-
8.5
-
8.8
ns
tPHL
HIGH to LOW
propagation delay
B to A
-
5.5
-
5.7
-
5.9
ns
tPLH
LOW to HIGH
propagation delay
B to A
-
6.7
-
5.7
-
0.7
ns
ten
enable time
OE to A; B
-
200
-
200
-
200
ns
NTS0102
Product data sheet
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Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
9 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
Table 11. Dynamic characteristics for temperature range −40 °C to +125 °C[1] …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
tdis
disable time
Conditions
VCC(B)
Unit
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5.0 V ± 0.5 V
Min
Max
Min
Max
Min
Max
OE to A; no external load
[2]
-
30
-
30
-
30
ns
OE to B; no external load
[2]
-
30
-
30
-
30
ns
OE to A
-
250
-
250
-
250
ns
OE to B
-
220
-
220
-
220
ns
LOW to HIGH
output transition
time
A port
3.2
11.9
2.3
11.7
1.8
9.5
ns
B port
3.3
13.5
2.7
11.4
2.7
9.5
ns
HIGH to LOW
output transition
time
A port
2.0
7.4
1.9
7.5
1.7
16.7
ns
B port
2.9
9.5
2.8
9.4
2.8
12.5
ns
tsk(o)
output skew time
between channels
-
0.8
-
0.8
-
0.8
ns
tW
pulse width
data inputs
20
-
20
-
20
-
ns
fdata
data rate
-
50
-
50
-
50
Mbps
tTLH
tTHL
[3]
VCC(A) = 2.5 V ± 0.2 V
tPHL
HIGH to LOW
propagation delay
A to B
-
4.0
-
4.2
-
4.3
ns
tPLH
LOW to HIGH
propagation delay
A to B
-
4.4
-
5.2
-
5.5
ns
tPHL
HIGH to LOW
propagation delay
B to A
-
3.8
-
4.5
-
5.4
ns
tPLH
LOW to HIGH
propagation delay
B to A
-
3.2
-
2.0
-
0.9
ns
ten
enable time
OE to A; B
-
200
-
200
-
200
ns
-
25
-
25
-
25
ns
tdis
disable time
OE to A; no external load
[2]
OE to B; no external load
[2]
-
25
-
25
-
25
ns
OE to A
-
220
-
220
-
220
ns
OE to B
-
220
-
220
-
220
ns
LOW to HIGH
output transition
time
A port
2.8
9.3
2.6
8.3
1.8
7.8
ns
B port
3.2
10.4
2.9
9.7
2.4
8.3
ns
HIGH to LOW
output transition
time
A port
1.9
7.2
1.9
6.9
1.8
6.7
ns
B port
2.2
9.8
2.4
8.4
2.6
8.3
ns
tsk(o)
output skew time
between channels
-
0.8
-
0.8
-
0.8
ns
tW
pulse width
data inputs
20
-
20
-
20
-
ns
fdata
data rate
-
50
-
50
-
50
Mbps
tTLH
tTHL
[3]
VCC(A) = 3.3 V ± 0.3 V
tPHL
HIGH to LOW
propagation delay
A to B
-
-
-
3.0
-
3.9
ns
tPLH
LOW to HIGH
propagation delay
A to B
-
-
-
5.3
-
5.5
ns
NTS0102
Product data sheet
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© NXP B.V. 2011. All rights reserved.
10 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
Table 11. Dynamic characteristics for temperature range −40 °C to +125 °C[1] …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
Conditions
VCC(B)
Unit
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5.0 V ± 0.5 V
Min
Max
Min
Max
Min
Max
tPHL
HIGH to LOW
propagation delay
B to A
-
-
-
3.2
-
4.2
ns
tPLH
LOW to HIGH
propagation delay
B to A
-
-
-
3.2
-
3.3
ns
ten
enable time
OE to A; B
-
-
-
200
-
200
ns
tdis
disable time
OE to A; no external load
[2]
-
-
-
20
-
20
ns
OE to B; no external load
[2]
-
-
-
20
-
20
ns
OE to A
-
-
-
280
-
280
ns
OE to B
-
-
-
220
-
220
ns
LOW to HIGH
output transition
time
A port
-
-
2.3
7.0
1.9
7.4
ns
B port
-
-
2.5
8.0
2.1
9.3
ns
HIGH to LOW
output transition
time
A port
-
-
2.0
6.8
1.9
6.3
ns
B port
-
-
2.3
9.3
2.4
9.5
ns
tsk(o)
output skew time
between channels
-
-
-
0.8
-
0.8
ns
tW
pulse width
data inputs
-
-
20
-
20
-
fdata
data rate
-
-
-
50
-
50
tTLH
tTHL
[1]
[3]
ns
Mbps
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[2]
Delay between OE going LOW and when the outputs are actually disabled.
[3]
Skew between any two outputs of the same package switching in the same direction.
13. Waveforms
VI
An, Bn
input
VM
GND
tPHL
VOH
Bn, An
output
tPLH
90 %
VM
VOL
10 %
tTHL
tTLH
001aal918
Measurement points are given in Table 12.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
The data input (An, Bn) to data output (Bn, An) propagation delay times
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Product data sheet
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Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
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NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
VI
OE input
VM
GND
tPLZ
output
LOW-to-OFF
OFF-to-LOW
tPZL
VCCO
VM
VX
VOL
tPHZ
VOH
tPZH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aal919
Measurement points are given in Table 12.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
Table 12.
Enable and disable times
Measurement points[1][2]
Supply voltage
Input
Output
VCCO
VM
VM
VX
VY
1.8 V ± 0.15 V
0.5VCCI
0.5VCCO
VOL + 0.15 V
VOH − 0.15 V
2.5 V ± 0.2 V
0.5VCCI
0.5VCCO
VOL + 0.15 V
VOH − 0.15 V
3.3 V ± 0.3 V
0.5VCCI
0.5VCCO
VOL + 0.3 V
VOH − 0.3 V
5.0 V ± 0.5 V
0.5VCCI
0.5VCCO
VOL + 0.3 V
VOH − 0.3 V
[1]
VCCI is the supply voltage associated with the input.
[2]
VCCO is the supply voltage associated with the output.
NTS0102
Product data sheet
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Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
12 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VEXT
VCC
VI
RL
VO
G
DUT
CL
RL
001aal963
Test data is given in Table 13.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; ZO = 50 Ω; dV/dt ≥ 1.0 V/ns.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
VEXT = External voltage for measuring switching times.
Fig 8.
Table 13.
Test circuit for measuring switching times
Test data
Supply voltage
VCC(A)
Input
VCC(B)
1.65 V to 3.6 V 2.3 V to 5.5 V
Load
VEXT
VI[1]
Δt/ΔV
CL
RL[2]
VCCI
≤ 1.0 ns/V
15 pF
50 kΩ, 1 MΩ open
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ[3]
open
2VCCO
[1]
VCCI is the supply voltage associated with the input.
[2]
For measuring data rate, pulse width, propagation delay and output rise and fall measurements, RL = 1 MΩ; for measuring enable and
disable times, RL = 50 KΩ.
[3]
VCCO is the supply voltage associated with the output.
NTS0102
Product data sheet
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Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
13 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
14. Application information
14.1 Applications
Voltage level-translation applications. The NTS0102 can be used in point-to-point
applications to interface between devices or systems operating at different supply
voltages. The device is primarily targeted at I2C or 1-wire which use open-drain drivers, it
may also be used in applications where push-pull drivers are connected to the ports,
however the NTB0102 may be more suitable.
1.8 V
3.3 V
0.1 μF
1.8 V
SYSTEM
CONTROLLER
VCC(A)
VCC(B)
3.3 V
SYSTEM
0.1 μF
1 μF
OE
NTS0102
A1
B1
A2
B2
DATA
DATA
001aam491
Fig 9.
Typical operating circuit
14.2 Architecture
The architecture of the NTS0102 is shown in Figure 10. The device does not require an
extra input signal to control the direction of data flow from A to B or B to A.
VCC(A)
VCC(B)
T1
T2
ONE
SHOT
ONE
SHOT
10 kΩ
10 kΩ
GATE BIAS
T3
A
B
001aal965
Fig 10. Architecture of NTS0102 I/O cell (one channel)
The NTS0102 is a "switch" type voltage translator, it employs two key circuits to enable
voltage translation:
1. A pass-gate transistor (N-channel) that ties the ports together.
2. An output edge-rate accelerator that detects and accelerates rising edges on the I/O
pins.
NTS0102
Product data sheet
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Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
14 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
The gate bias voltage of the pass gate transistor (T3) is set at approximately one
threshold voltage above the VCC level of the low-voltage side. During a LOW-to-HIGH
transition the output one-shot accelerates the output transition by switching on the PMOS
transistors (T1, T2) bypassing the 10 kΩ pull-up resistors and increasing current drive
capability. The one-shot is activated once the input transition reaches approximately
VCCI/2; it is de-activated approximately 50 ns after the output reaches VCCO/2. During the
acceleration time the driver output resistance is between approximately 50 Ω and 70 Ω. To
avoid signal contention and minimize dynamic ICC, the user should wait for the one-shot
circuit to turn-off before applying a signal in the opposite direction. Pull-up resistors are
included in the device for DC current sourcing capability.
14.3 Input driver requirements
As the NTS0102 is a switch type translator, properties of the input driver directly effect the
output signal. The external open-drain or push-pull driver applied to an I/O determines the
static current sinking capability of the system; the max data rate, HIGH-to-LOW output
transition time (tTHL) and propagation delay (tPHL) are dependent upon the output
impedance and edge-rate of the external driver. The limits provided for these parameters
in the datasheet assume a driver with output impedance below 50 Ω is used.
14.4 Output load considerations
The maximum lumped capacitive load that can be driven is dependant upon the one-shot
pulse duration. In cases with very heavy capacitive loading there is a risk that the output
will not reach the positive rail within the one-shot pulse duration.
To avoid excessive capacitive loading and to ensure correct triggering of the one-shot it's
recommended to use short trace lengths and low capacitance connectors on NTS0102
PCB layouts. To ensure low impedance termination and avoid output signal oscillations
and one-shot re-triggering, the length of the PCB trace should be such that the round trip
delay of any reflection is within the one-shot pulse duration (approximately 50 ns).
14.5 Power up
During operation VCC(A) must never be higher than VCC(B), however during power-up
VCC(A) ≥ VCC(B) does not damage the device, so either power supply can be ramped up
first. There is no special power-up sequencing required. The NTS0102 includes circuitry
that disables all output ports when either VCC(A) or VCC(B) is switched off.
14.6 Enable and disable
An output enable input (OE) is used to disable the device. Setting OE = LOW
causes all I/Os to assume the high-impedance OFF-state. The disable time (tdis with no
external load) indicates the delay between when OE goes LOW and when outputs
actually become disabled. The enable time (ten) indicates the amount of time the user
must allow for one one-shot circuitry to become operational after OE is taken HIGH. To
ensure the high-impedance OFF-state during power-up or power-down, pin OE should be
tied to GND through a pull-down resistor, the minimum value of the resistor is determined
by the current-sourcing capability of the driver.
NTS0102
Product data sheet
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Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
15 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
14.7 Pull-up or pull-down resistors on I/Os lines
Each A port I/O has an internal 10 kΩ pull-up resistor to VCC(A), and each B port I/O has
an internal 10 kΩ pull-up resistor to VCC(B). If a smaller value of pull-up resistor is required,
an external resistor must be added parallel to the internal 10 kΩ, this will effect the VOL
level. When OE goes LOW the internal pull-ups of the NTS0102 are disabled.
NTS0102
Product data sheet
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Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
16 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
15. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
Fig 11. Package outline SOT505-2 (TSSOP8)
NTS0102
Product data sheet
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Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
17 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
1
2
SOT833-1
b
4
3
4×
(2)
L
L1
e
8
7
6
e1
5
e1
e1
8×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
2.0
1.9
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT833-1
---
MO-252
---
EUROPEAN
PROJECTION
ISSUE DATE
07-11-14
07-12-07
Fig 12. Package outline SOT833-1 (XSON8)
NTS0102
Product data sheet
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Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
18 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
B
D
SOT996-2
A
A
E
A1
detail X
terminal 1
index area
e1
v
w
b
e
L1
1
4
8
5
C
C A B
C
M
M
y
y1 C
L2
L
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
L2
v
w
y
y1
mm
0.5
0.05
0.00
0.35
0.15
2.1
1.9
3.1
2.9
0.5
1.5
0.5
0.3
0.15
0.05
0.6
0.4
0.1
0.05
0.05
0.1
REFERENCES
OUTLINE
VERSION
IEC
SOT996-2
---
JEDEC
JEITA
---
EUROPEAN
PROJECTION
ISSUE DATE
07-12-18
07-12-21
Fig 13. Package outline SOT996-2 (XSON8U)
NTS0102
Product data sheet
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Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
19 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
SOT1089
E
terminal 1
index area
A
D
A1
detail X
(4×)(2)
e
L
(8×)(2)
b 4
5
e1
1
terminal 1
index area
8
L1
X
0
0.5
scale
Dimensions
Unit
mm
max
nom
min
1 mm
A(1)
0.5
A1
b
D
E
e
e1
L
L1
0.04 0.20 1.40 1.05
0.35 0.40
0.15 1.35 1.00 0.55 0.35 0.30 0.35
0.27 0.32
0.12 1.30 0.95
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
SOT1089
sot1089_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-09
10-04-12
MO-252
Fig 14. Package outline SOT1089 (XSON8)
NTS0102
Product data sheet
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Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
20 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
XQFN10: plastic, extremely thin quad flat package; no leads;
10 terminals; body 1.40 x 1.80 x 0.50 mm
SOT1160-1
X
A
B
D
terminal 1
index area
A
E
A1
A3
detail X
e1
e
3
5
C
C A B
C
v
w
b
y
y1 C
L
2
6
1
7
e2
terminal 1
index area
10
L1
8
0
1
scale
Dimensions
Unit(1)
mm
max
nom
min
2 mm
A
A1
0.5
0.05
A3
b
0.25
0.127 0.20
0.00
0.15
D
E
1.5
1.4
1.3
1.9
1.8
1.7
e
e1
0.4
0.8
e2
0.4
L
L1
0.45 0.55
0.40 0.50
0.35 0.45
v
0.1
w
y
y1
0.05 0.05 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT1160-1
---
---
---
sot1160-1_po
European
projection
Issue date
09-12-28
09-12-29
Fig 15. Package outline SOT1160-1 (XQFN10)
NTS0102
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
21 of 25
NTS0102
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
16. Abbreviations
Table 14.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
GPIO
General Purpose Input Output
HBM
Human Body Model
I2C
Inter-Integrated Circuit
MM
Machine Model
PCB
Printed Circuit Board
PMOS
Positive Metal Oxide Semiconductor
SMBus
System Management Bus
UART
Universal Asynchronous Receiver Transmitter
UTLP
Ultra Thin Leadless Package
17. Revision history
Table 15.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
NTS0102 v.2
20110411
Product data sheet
-
NTS0102 v.1
Modifications:
NTS0102 v.1
NTS0102
Product data sheet
•
Added a typical total supply current (ICC(A) + ICC(B)) table.
20100921
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 April 2011
-
© NXP B.V. 2011. All rights reserved.
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18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
NTS0102
Product data sheet
suitable for use in medical, military, aircraft, space or life support equipment,
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NTS0102
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
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20. Contents
1
2
3
4
5
6
7
7.1
7.2
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
14.5
14.6
14.7
15
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application information. . . . . . . . . . . . . . . . . . 14
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input driver requirements . . . . . . . . . . . . . . . . 15
Output load considerations . . . . . . . . . . . . . . . 15
Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Enable and disable . . . . . . . . . . . . . . . . . . . . . 15
Pull-up or pull-down resistors on I/Os lines . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Contact information. . . . . . . . . . . . . . . . . . . . . 24
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 11 April 2011
Document identifier: NTS0102
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