IDT NW6005 Enhanced type ii caller id decoder Datasheet

NW6005
ENHANCED TYPE II CALLER ID DECODER
FEATURES
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DESCRIPTION
1200 baud Bell 202 and ITU-T V.23 Frequency Shift Keying
(FSK) Demodulation
Compliant with following specifications:
Bellcore GR-30-CORE & SR-TSV-002476
TIA/EIA-716, TIA/EIA-777 Draft
British Telecom (BT) SIN227 & SIN242
ETSI ETS 300 778-1 and -2
Bellcore “CPE Alerting Signal (CAS)”, British Telecom “Idle State
and Loop State Tone Alert Signal” and ETSI “Dual Tone Alerting
Signal (DT-AS)” detection
Two seperate OP amps with adjustable gain for Tip/Ring and
Telephone Hybrid connections
Monitoring of the stop bit for framing error check
Serial FSK data interface with selectable output of bit stream or 1
byte buffer
FSK carrier detection
3 V or 5 V operation
Low power CMOS with intelligent powerdown mode
Operating temperature range: -40 °C to +85 °C
Packages available:
NW6005-XS 20 pin SOIC
(where ‘X’ is the revision ID)
The NW6005 device is a single-chip, 3/5 Volt CMOS caller ID with
call waiting detection circuit. It can receive signals following Bellcore
GR-30-CORE & SR-TSV-002476, BT SIN227 & SIN242, and ETSI
ETS 300 788-1/-2 specifications.
The NW6005 provides 1200 baud Bell 202 and ITU-T V.23 FSK
demodulation and CAS/DT-AS detection. Two seperate differential
input amplifiers allow the device to be connected with both Tip/Ring
and Telephone Hybrid receive pair. FSK demodulation is
implemented only on Tip/Ring, while DT-AS (or CAS) detection can be
on either Tip/Ring or Hybrid Receive. In addition, NW6005 provides a
serial FSK data interface via which the data can be selected to be
processed as a bit stream or extracted from a 1 byte built-in buffer.
The device can be used in feature or cordless phones for BT
Calling Line Identity Presentation (CLIP), CCA CLIP and Bellcore
Calling Identity Delivery (CID) systems. It can also be used in caller ID
boxes, modem, fax machines, answering machines, database query
systems and Computer Telephony Integration (CTI) systems.
FUNCTIONAL BLOCK DIAGRAM
OSCOUT OSCIN
Bias
Generator
VREF
Oscillator
PWDN
CASEN
IN2+
+
-
Dual Tone
Detector
+
FSK
Demodulator
-
IN2GS2
CB2
Control Bit
Decoder
FSKEN
PWDN
GS1EN
CASEN
MODE
GS2EN
Mux
IN1GS1
CB1
Guard Time
GS1EN
IN1+
CB0
ST/GT
DR/STD
EST
CD
Data/Timing Recovery
DCLK
DATA
GS2EN
FSKEN
MODE
Figure 1. Block Diagram
The IDT logo is a registered trademark of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE
2002 Integrated Device Technology, Inc.
JULY 2002
DSC-6048/3
NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
PIN INFORMATION
VREF
1
20
IN2+
IN1+
2
19
IN2GS2
IN1-
3
18
GS1
4
17
CB2
GND
5
16
CB1
OSCIN
6
15
VCC
OSCOUT
7
14
CD
CB0
8
13
ST/GT
DCLK
9
12
EST
DATA
10
11
DR/STD
Figure 2. Pin Assignment
Name
VREF
Type
O
Pin No.
1
IN1+
IN1GS1
I
I
O
2
3
4
GND
OSCIN
I
5
6
OSCOUT
O
7
CB0
I
8
DCLK
I/NC
9
DATA
O
10
Description
Reference Voltage.
This output is used to bias the input OP amp. It is typically VCC/2.
Non-inverting Input of the gain adjustable Tip/Ring OP amp.
Inverting Input of the gain adjustable Tip/Ring OP amp.
Gain Select Output of the gain adjustable Tip/Ring OP amp.
The Tip/Ring signal can be attenuated or amplified at GS1 by adjusting the feedback resistor between GS1 and
IN1-. The FSK signal is always detected by Tip/Ring OP amp while DT-AS signal can be detected by either
Tip/Ring or Hybrid OP amp. The OP amp selection is controlled by CB1 and CB2 pins.
Ground.
Oscillator Input.
A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCOUT. It can also
be driven by an external clock source.
Oscillator Output.
A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCIN. When an
external clock drives OSCIN, this pin can be left floating.
Control Bit 0 (FSK Data Interface Mode Select).
This pin can select the 3-wire FSK data interface mode. A ‘0’ on this pin indicates interface mode 0; while a ‘1’ on
this pin indicates interface mode 1. (The FSK data interface is consisted of DATA, DCLK and DR/STD pins.)
When CB0 is high and CB1, CB2 are both low, the device is set into the power down state.
Data Clock of the Serial FSK Interface.
In mode 0 (CB0 is low), this pin is unused; In mode 1 (CB0 is high), this pin is an input which clock the FSK data
byte out to the DATA pin.
Data Output of the Serial FSK Interface.
In mode 0 (CB0 is low), the FSK serial bit stream is output to the DATA pin directly.
In mode 1 (CB0 is high), the start bit is stripped off, the data byte and the stop bit is stored in a 9-bit buffer. At the
end of each word signaled by the DR/STD pin, the microcontroller should shift the byte out onto the DATA pin by
applying 8 read pulses to the DCLK pin. A 9th DCLK pulse will shift out the stop bit for framing error checking.
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NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
PIN INFORMATION (CONTINUED)
Name
Type
Pin No.
DR/ STD
O/NC
11
EST
O
12
ST/GT
I/O
13
CD
O
14
VCC
-
15
CB1
I
16
CB2
I
17
GS2
O
18
IN2IN2+
I
I
19
20
Description
Data Ready or DT-AS Detection Delayed Steering Output.
This pin is active low. When FSK demodulation is enabled, this pin is the Data Ready output. In FSK interface mode
0, this pin is unused and reads ‘1’. While mode 1, this pin is normally high and goes low for half a bit time at the end
of a word. If DCLK starts during DR low, the first rising edge of the DCLK input will return DR to high. In this way,
reading of the first DATA bit can clear the interrupt requested by a low going DR.
When DT-AS detection is enabled, this pin is the Delayed Steering Output. An active low signal on this output
indicates the detection of a ‘guard time qualified’ DT-AS.
DT-AS Early Steering Output.
This pin is an active high output to indicate the detection of a raw DT-AS signal. It is used with the ST/GT pin and
external components to time qualify the detection.
DT-AS Detection Steering Input/Guard Time Output.
It’s a CMOS output and an input of voltage comparator. It is used in conjunction with the EST pin and external
components to time qualify a raw DT-AS signal detection.
If the voltage at this pin is greater than the voltage threshold, DR/STD pin is asserted low to indicate that a DT-AS
has been detected. A voltage less than the threshold enable the device to accept a new DT-AS and return the
DR/STD pin to high.
FSK Carrier Detector.
This is an active low CMOS output signal to indicate the presence of in-band FSK signal.
3/5 V Power Supply.
Control Bit 1 (Function Select 1).
This pin is used with CB0 and CB2 to select FSK demodulation, Tip/Ring DT-AS detection or Hybrid DT-AS
detection. See Table 1.
When CB0 is high, CB1 and CB2 pins are both low, the device is set into the power down state.
Control Bit 2 (Function Select 0).
This pin is used with CB0 and CB1 to select FSK demodulation, Tip/Ring DT-AS detection or Hybrid DT-AS
detection. See Table 1.
When CB0 is high, CB1 and CB2 pins are both low, the device is set into the power down state.
Gain Select Output of the gain adjustable Hybrid OP amp.
The hybrid receive signal can be amplified or attenuated at GS2 by adjusting the feedback resistor between GS2
and IN2-. When the CPE is off-hook, DT-AS detection of the GS2 signal should be enabled via the CB1 and CB2
pins.
Inverting Input of the gain adjustable Hybrid OP amp.
Non-inverting Input of the gain adjustable Hybrid OP amp.
Abbreviation Index
CAS
CDS
CID
CIDCW
CLIP
CNAM
CND
CNIC
CO
DT-AS
MEI
TE
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
CPE Alerting Signal
Caller Display Service
Calling Identity Delivery
Calling Identity Delivery on Call Waiting
Calling Line Identity Presentation
Calling Name Delivery
Calling Number Delivery
Calling Number Identification Circuit
Central Office
Dual Tone Alert Signal
Multiple Extension Interworking
Terminal Equipment
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NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
PIN INFORMATION (CONTINUED)
Table 1. Description of Control Bit Pins CB0-2
Pin
CB0
Name
FSK Data Interface
Mode Select
CB1
CB2
Function Select 1
Function Select 0
Description
FSK Data Interface Mode 0: FSK bit stream is output directly.
FSK Data Interface Mode 1: FSK byte is stored in a 1-byte buffer, which can be read
serially by the microcontroller.
0
1
CB1
1
CB2
1
1
0
0
1
0
0
FSK Demodulation is enabled. Tip/Ring input (GS1) is selected. In FSK Mode 1
operation (CB0 = ‘1’), DR/STD is DR.
Hybrid DT-AS Detection is enabled. Hybrid Receive input (GS2) is selected. DR/STD is
STD.
Tip/Ring DT-AS Detection is enabled. Tip/Ring input (GS1) is selected. DR/STD is
STD. Tip/Ring DT-AS detection is required for Bellcore MEI and BT on-hook CLIP.
When CB0 is high (‘1’): the NW6005 will be powered down. It draws minimal power
supply current.
When CB0 is low (‘0’): for factory testing only.
FUNCTIONAL DESCRIPTION
BRITISH TELECOM
CALLER ID SPECS SUPPORTED
BT SIN227 and SIN242 define the signal interface between the
Central Office (CO) and the Terminal Equipment (TE) for the Caller
Display Service (CDS). CDS provides CLIP (Calling Line Identity
Presentation) that delivers to an idle state (on hook) TE the identity of
an incoming caller before the first ring.
The NW6005 is a type II Caller ID device with Call Waiting
capability. It supports Bellcore, BT and ETSI specifications. The major
differences between above specs are as follows (see Fig. 11, Fig. 12
and Fig. 13 for reference):
A polarity reversal on the A and B wires indicates the arrival of a
CDS call. After that comes an Idle State Tone Alert Signal, and then
Caller ID FSK information transmitted in ITU-T V.23 format. When the
subscriber is engaged in a call, the arrival of information about
another incoming call is indicated by a Loop State Tone Alert Signal.
The NW6005 can detect tone alert signal and demodulate the
incoming ITU-T V.23 FSK signals.
BELLCORE AND TIA
Bellcore GR-30-CORE and SR-TSV-002476 define the
requirement for the signalling services of Calling Number Delivery
(CND), Calling Name Delivery (CNAM), VMWI (Visual Message
Waiting Indicator) and Calling Identity Delivery on Call Waiting
(CIDCW).
ETSI
In CND or CNAM service, information of the calling party is
embedded in the silent interval between the first and second ringing.
The NW6005 can detect and demodulate the incoming Bell-202 FSK
data. In CIDCW service, information about an incoming caller is sent
to the subscriber who is engaged in another call. A CPE Alerting
Signal (CAS) indicates that a CIDCW data is incoming. The NW6005
can detect the alerting signal and demodulate the incoming FSK
information which contains CIDCW data. The demodulated data is
output onto the serial interface.
The ETSI caller identity specifications ETS 300 788-1 for on-hook
and ETS 300 788-2 for off-hook define the requirements for CPE,
while ETS 300 659-1 for on-hook and ETS 300 659-2 for off-hook
define the end office requirements. The services such as CLIP and
CLIP with Call Waiting in ETSI specifications are similar to those of
Bellcore. The ETSI specifications are popularly used in Europe.
In North America, Telecommunications Industry Association (TIA)
also defines standards. TIA specification TIA/EIA-716 defines Type I
CPE requirements. A type II CPE specification document is drafted as
TIA/EIA-777. FSK characteristics in TIA specifications differ from those
Bellcore published in its specifications.
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NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
DT-AS DETECTION ON EITHER TIP/RING OR HYBRID
RECEIVE PAIR
BLOCK DESCRIPTION
In off-hook services, the detection of Dual Tone Alert Signal (DT-AS)
will affect the quality of the call waiting service. Even though the end
office has muted the far end party before and after it sends DT-AS, the
near end user who is to receive the FSK information may be still
talking. Therefore, the CPE must be able to detect DT-AS successfully
in the presence of near end speech. Furthermore, imitation of DT-AS
by speech will also affect the DT-AS detector, thus false detection may
be generated.
The NW6005 requires a 3.579545 MHz system clock and consists
of three major functional blocks: Analog Input Circuit, Dual Tone Alert
Signal Detection, and FSK Demodulation.
ANALOG INPUT CIRCUIT
The input signal is processed by the Analog Input Circuit block,
which is comprised of two OP amps and a bias source (VREF). VREF
is the output of a low impedance voltage source used to bias the input
OP amp, and is typically equal to VCC/2. The Tip/Ring OP amp
(IN1+, IN1-, GS1 pins) is for connecting to Tip and Ring, while the
Hybrid OP amp (IN2+, IN2-, GS2 pins) is for connecting to Hybrid
Receive Pair. The gain adjustable OP amps are also used to select
the input gain by connecting a feedback resistor between GS and the
IN- pin. Fig. 3 shows the differential input configuration. In singleended configuration, the gain adjustable OP amp is connected as
shown in Fig. 4.
To achieve better DT-AS detection quality, a method is to put DT-AS
detection on the telephone hybrid receive pair instead of on Tip/Ring.
As the near end speech has been attenuated while the DT-AS level is
the same as on Tip/Ring, the DT-AS immunity is improved.
A CPE capability called Multiple Extension Interworking(MEI), in
process of being defined by Bellcore, requests the CPE be capable of
detecting DT-AS when the line is off-hook, although the CPE itself may
be on-hook. Under some conditions, an on-hook CPE may send an
acknowledgment to the end office. Also, the on-hook CPE’s capability
of detecting DT-AS enables the call logs between on and off-hook
CPEs to be maintained synchronous. In this way, when all off-hook
CPEs are MEI compatible and DT-AS is received, one of the CPEs will
send the acknowledgment signal and all CPEs will receive FSK.
VREF
NW6005
R3
Therefore, if the DT-AS detector is connected only to the hybrid
receive pair, the CPE can not detect DT-AS when it is on-hook. When
the CPE is on-hook, either the hybrid is non-functional or the signal
level is severely attenuated. Thus, an on-hook CPE must be able to
detect DT-AS from Tip/Ring.
C1
R1
C2
The NW6005 provides two input OP amps via which the device can
be connected both to Tip/Ring and to the Hybrid Receive pairs. Both
connection can be differential or single-ended. FSK demodulation is
implemented only on Tip/Ring, while DT-AS detection can be on either
Tip/Ring or Hybrid Receive. Tip/Ring DT-AS detection is required for
MEI and BT’s on-hook CLIP.
R4
IN+
IN-
R2
R5
Differential Input Amplifier
C1=C2
R1=R2 (For unity gain R5=R2)
R3=(R4R5)/(R4+R5)
GS
Voltage Gain
Av = R5/R2
Input Impedance
Zin =2√R1² + (1/ ω C)²
Figure 3. Differential Input Gain Control Circuit
It should be noted here that as the Hybrid OP amp is for DT-AS
detection only, its gain can always be adjusted specifically for the DTAS signal.
C
IN+
IN-
Rin
Rf
Voltage Gain
Av = Rf / Rin
NW6005
GS
VREF
Figure 4. Single-ended Input Gain Control Circuit
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NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
Fig. 5 shows the operation of the guard time circuit and Fig. 6
shows the waveform of the EST, ST/GT and STD pins. The total
recognition time is tREC = tDP + tGP, where tDP is the tone present detection
time and tGP is the tone present guard time. The total absent time is tABS
= tDA + tGA, where tDA is the tone absent detection time and tGA is the tone
absent guard time. The guard time is the RC time constant for the
capacitor charge to VCC or discharge to GND. To get the unequal
present and absent guard time, a diode can be connected as shown
in Fig. 7 to provide different RC time constant (varying resistance
value) during charging and discharging.
DUAL TONE ALERT SIGNAL DETECTION
The Dual Tone Alert Signal is used only in off-hook signalling in
Bellcore system and ETSI system, but in BT system it is used in both
on and off-hook signalling. The low and high tone frequencies of three
different systems are as follows:
Low Tone
Frequency
High Tone
Frequency
BT
2130 Hz ± 1.1% (on-hook)
2130 Hz ± 0.6% (off-hook)
2750 Hz ± 1.1% (on-hook)
2750 Hz ± 0.6% (off-hook)
Bellcore & ETSI
2130 Hz ± 0.5%
2750 Hz ± 0.5%
When the device selects DT-AS detection, the bi-purpose output
pin DR/STD is STD. STD goes low when DT-AS has been detected
and return high after DT-AS has ended.
DT-AS
Alerting Signal
tDP
EST
The incoming Alert Signal goes through anti-alias filter and then is
separated into high band and low band by two bandpass filters. The
tone detection algorithm examines the filter outputs to validate the
arrival of the DT-AS. The EST pin becomes active when both tones
are detected. The EST is only the preliminary indication, it must be
qualified by the “guard time” as required by Bellcore, BT and ETSI (a
minimum duration for valid signals). STD is the guard time qualified
DT-AS detection output, it indicates the correct detection.
tDA
tGP
tGA
VTGT
ST/GT
VTGT
tABS
tREC
STD
Q1
Switch
Q2
Switch
ON
ON
ON
Figure 6. Guard Time Waveform
VCC
NW6005
Dual tone detected
VCC
Q1
P
C3
VCC
NW6005
C
ST/GT
ST/GT
VTGT
Comparator
R5
Q2
R1
R2
tGP < tGA
tGP=RPCIn((VCC-Vd(RP/R2))/
(VCC-V TGT -Vd(RP/R2)))
tGA=R1CIn(VCC/VTGT )
RP=R1R2/(R1+R2)
Vd=diode forward voltage
EST
N
VCC
EST
C
NW6005
STD
ST/GT
R1
R2
tGP > tGA
tGP=R1CIn(VCC/(VCC-V TGT ))
tGA=RPCIn((VCC-Vd(RP/R2))/
(V TGT -Vd(RP/R2)))
RP=R1R2/(R1+R2)
Vd=diode forward voltage
EST
Figure 5. Guard Time Circuit of Dual Tone Alert Signal
Detection
Figure 7. Guard Time Circuits with Unequal Present and
Absent Times
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NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
FSK DEMODULATION
Mode ‘1’ (CB0 is high)
The key part among the functions offered by NW6005 is FSK
demodulation. This function is implemented by several stages: first,
the carrier detector provides an indication of the presence of signal at
the bandpass filter output; second, the device’s dual mode serial
interface allows convenient extraction of the 8-bit data words in the
demodulated FSK bit stream.
In this mode, the received byte is stored on chip. The
microcontroller supplies read pulses (DCLK) to shift the register
contents serially out of the NW6005, onto the DATA pin. The NW6005
asserts DR to denote the word boundary and indicate to the
microprocessor that a new word has become available. Internal to the
device, the demodulated data bits are sampled and stored. Midway
through the stop bit, the 8 data bits and the stop bit are parallel loaded
into an 9-bit shift register and DR goes low. The contents of register
are shifted out to DATA pin on DCLK’s rising edge with LSB (Least
Significant Bit) out first. If DCLK begins while DR is low, DR will return to
high upon the first DCLK rising edge. This feature allows the
associated interrupt to be cleared by the first read pulse. Otherwise,
DR stays low for half a nominal bit time (1/2400 sec) and then returns
to high. After the last bit (Most Signifi cant Bit) has been read,
additional DCLKs are ignored. Fig. 18 shows the timing diagram of
Mode ‘1’ operation.
The FSK characteristics are different in BT, ETSI and Bellcore
specifications. The signal frequencies in BT and ETSI correspond to
ITU-T V.23; the Bellcore frequencies correspond to Bell 202. The
NW6005 is compatible with both formats. It also meets the signal
characteristics by setting the Tip/Ring input OP amp at unity gain in 5V
operation.
Mark Freq. (‘1’)
Space Freq. (‘0’)
ITU-T V.23
1300 Hz ± 1.5%
2100 Hz ± 1.5%
Bell 202
1200 Hz ± 1%
2200 Hz ± 1%
Reading the stop bit is a method of checking framing errors. If it’s
certain that there is no framing error would occur, the microcontroller
only needs to send 8 DCLK pulses to shift the data byte out. After the
checksum byte has be received, all 9 bits should be read and framing
error checked.
For 3 V operation, the FSK receiver becomes easier to accept
lower level signals than in 5 V operation. The Tip/Ring input OP amp
gain should be reduced to maintain the FSK reject level.
SERIAL FSK INTERFACE
FSK CARRIER DETECTION
The three wire DATA, DCLK and DR form the data interface of the
FSK demodulation. The DATA pin is the serial data pin that outputs
data to external devices. The DCLK pin is the data clock which is used
in Mode ‘1’ and is generated by an external device. The DR pin is the
data ready signal used in Mode ‘1’, also an output from the NW6005
to external devices. DR/STD pin is a dual purpose output pin, when
FSK function is selected it is DR.
The carrier detector detects the presence of a signal of sufficient
amplitude at the output of the FSK bandpass filter. If the signal is
qualified by a digital algorithm, it set the CD output to low indicating a
successful carrier detection. NW6005 supplies a 10 ms hysteresis to
allow for momentary signal drop out once CD has been activated.
When there is no activity at the FSK bandpass filter output for 10 ms,
CD is released.
The FSK interface provides the mechanism to extract the 8-bit data
words in the demodulated FSK bit stream without the need either for
an external UART or for the CPE’s microcontroller to perform the
function in software. Two modes are selectable via control of the
device’s CB0 pin: Mode ‘0’ (CB0 is low), where the FSK bit stream is
output directly; Mode ‘1’ (CB0 is high), where the data byte and the
stop bit are stored in a 9 bit buffer.
When CD is inactive (high), the raw output of the FSK
demodulator is ignored by the FSK data output interface. In mode‘0’,
the DATA pin is forced high. In mode ‘1’, the internal shift register is
not updated. If DCLK is clocked, DATA is undefined.
Since signals such as DT-AS, DTMF tones and speech are within
the FSK frequency band and thus may activate the carrier detector.
The NW6005 should be put into DT-AS or power down mode when
FSK is not expected to avoid false carrier detection and false
demodulation.
Mode ‘0’ (CB0 is low)
In this mode, the device demodulates the incoming FSK signal,
and output the data directly to the DATA pin. DCLK and DR pins are
unused. Fig. 19 and Fig. 20 shows the timing diagram of Mode ‘0’
operation.
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NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
OTHER FUNCTIONS
APPLICATION NOTE
POWER-DOWN MODE
CONTROL BITS PROGRAMMING
The device provides the power-down feature to reduce the power
consumption. Power-down can be activated by setting Control Bits 0-2
to ‘100’. Note that momentary transition of CB0-2 into the power-down
code won’t activate power-down but will reset the device.
Functionality of the NW6005 can be selected by coding CB0-CB2,
as shown in Table 2.
Table 2. Control Bits Programming
In this mode, both input OP amps, reference voltage and the
oscillator are non functional. When the device is in power-down, DATA,
DR/STD, CD are high; EST and ST/GT are low.
Functionality Group
FSK Demodulation Mode 0
FSK Demodulation Mode 1
Hybrid DT-AS Detection
Tip/Ring DT-AS Detection
Power Down
Factory Test Only
An intelligent Power-down feature is implemented to futher reduce
the operating current. When FSK is selected, DT-AS detector is
powered down. When DT-AS is selected, FSK demodulator is
powered down. The Tip/Ring and Hybrid input OP amps are not
affected in the intelligent Power-down.
CB0
0
1
1/0
1/0
1
0
CB1
1
1
1
0
0
0
CB2
1
1
0
1
0
0
HYBRID CONNECTION
To optimize the device’s talkdown and talkoff performance, Hybrid
connection is recommended. There are two Op Amps in NW6005
which bring convenience for Hybrid connection. When connected to
the Hybrid Op Amp, the Hybrid circuit will attenuate the speech signal
at least 9 dB from the microphone to the speaker, which leads a much
better performance of near-end talkdown and talkoff.
CRYSTAL OSCILLATOR
A 3.579545 MHz crystal oscillator or other external clock source is
required for NW6005. The crystal can be directly connected between
OSCIN and OSCOUT pins without any external component. If an
external clock source is used, OSCIN pin should be driven by the
clock source and OSCOUT pin is left floating or is used to drive other
devices. Fig. 8 shows some applications.
It is highly recommended to demodulate the FSK signal using the
Tip/Ring OP Amp and to detect the CAS signal using the Hybrid OP
Amp. This implementation brings not only optimized talkdown and
talkoff performance, but also the convenience to adjust FSK and CAS
sensitivity separately.
(a) Connection of One Device with Crystal Oscillator
NW6005
OSCIN
GAIN SETTING
OSCOUT
Ideally, the gain of the two Op Amps would be set to 0 dB. But in
real applications, the gain setting should be determined by industry
standards as well as by customer requirements. The circuit and
calculation method of gain setting is illustrated in Figs. 3 and 4. For
Hybrid connection, the single-ended solution (Fig. 4) is often selected.
3.579545MHz
(b) Common Crystal Connection of Several Devices
Sharing One Timing Source
NW6005
OSCIN
OSCOUT
3.579545MHz
NW6005
OSCIN
Typically, the CAS sensitivity should be lower than the FSK
sensitivity in order to prevent missing the FSK signal while the CAS
signal is detected. Therefore, it is suggested to set the gain of the Op
Amp for FSK demodulation 3 dB higher than that of the Op Amp for
CAS detection.
NW6005
OSCOUT OSCIN
OSCOUT
to the next device
THE DIFFERENCE BETWEEN FSK MODE 0 AND MODE1
Figure 8. Applicaiton of Clock Driven Circuit
In FSK mode 0, the FSK serial bit stream is output to the DATA pin
directly. DCLK and DR pins are unused. The microcontroller reads out
the data by the serial data interface which is implemented by software
programming. The flexibility of using software improves the immunity
to interference.
8
NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
APPLICATION INFORMATION
Microphone
Tx+
TIP
TIP
RING
RING
Telephone
Hybrid
Tx-
Speaker
Rx+
C2 R2
B
470k
39k
GND
Xtal
FSK Interface Mode 1 is selected
IN2+
IN1+
IN2-
IN1-
GS2
GS1
CB2
GND
CB1
OSCIN
VCC
OSCOUT
CB0
470k
56k
56k
56k
39k
VREF
2n2
470k
330k
470k
2n2
VCC= 5V +/-10%
CD
ST/GT
DCLK
EST
DATA
DR/STD
R3
100n, 20%
A
NW6005
100n
C1 R1
56k
470k
Rx-
R4
To Microcontroller
From Microcontroller
Note:
1. Resistors are 1%, 0.1Watt; Unless stated, capacitors are 5%, 6.3 V.
2. All diodes in the circuit are 1N4148 or equivalent.
3. Xtal is 3.579545 MHz, 0.1% crystal or ceramic resonator.
4. Tip/Ring op amp gain = 0 dB; Hybrid Receive op amp gain = -3 dB.
5. For 1000 Vrms, 60 Hz isolation from Tip to Earth and Ring to Earth:
R1, R2 = 430 k, 0.5 W, 5%, 500 V min.
C1, C2 = 2n2, 250 V min.
6. For BT application, R3=R4= 422k;
For Bellcore application, R3=825k, R4=226k.
Figure 9. Typical Application Circuit For Bellcore MEI Compatible Type II Telephone, 5 V Operation
In FSK mode 1, the received byte is stored in an on-chip register.
The microcontroller supplies read pulses (DCLK) to shift the register
contents serially out of the NW6005, onto the DATA pin. The DR pin is
also used to indicate the word boundary.
VALID DT-AS EVALUATION
DT-AS output will generate false detection if being interfered by
speech. In this way, valid DT-AS pulse evaluation becomes necessary.
The evaluation defines a minimum and maximum pulse duration,
and maximum drop out time within that pulse duration. See Figure 21
for reference.
9
NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
Microphone
Tx+
TIP
TIP
RING
RING
Telephone
Hybrid
Tx-
Speaker
Rx+
A
39k
C2 R2
282k
39k
B
GND Xtal
FSK Interface Mode 1 is selected
IN1+
IN2-
IN1-
GS2
GS1
CB2
GND
CB1
OSCIN
VCC
OSCOUT
CB0
282k
56k
2n2
IN2+
470k
200k
470k
2n2
VCC= 3V +/-10%
CD
ST/GT
DCLK
EST
DATA
DR/STD
R3
100n, 20%
VREF
56k
56k
NW6005
100n
C1 R1
56k
282k
Rx-
R4
To Microcontroller
From Microcontroller
Note:
1. Resistors are 1%, 0.1Watt; Unless stated, capacitors are 5%, 6.3 V.
2. All diodes in the circuit are 1N4148 or equivalent.
3. Xtal is 3.579545 MHz, 0.1% crystal or ceramic resonator.
4. Tip/Ring op amp gain = 0 dB; Hybrid Receive op amp gain = -3 dB.
5. For 1000 Vrms, 60 Hz isolation from Tip to Earth and Ring to Earth:
R1, R2 = 430 k, 0.5 W, 5%, 500 V min.
C1, C2 = 2n2, 250 V min.
6. For BT application, R3=R4= 422k;
For Bellcore application, R3=825k, R4=226k.
Figure 10. Typical Application Circuit For Bellcore MEI Compatible Type II Telephone, 3 V Operation
10
NW6005 ENHANCED TYPE II CALLER ID DECODER
A/B Wires
PWDN
1st Ringing
Alerting
Signal
A
B
INDUSTRIAL TEMPERATURE RANGE
Ch. Seizure
Mark
Message
C
D
E
Note 1
F
Note 2
Note 2
Note 4
Note 3
Note6
FSKEN
2nd Ringing
Note 5
Note6
CD
DR
Note7
...
...
..101010..
Data
DCLK
Note7
DATA
Figure 11. Bellcore On-hook Data Transmission Timing Diagram
Notes:
1) A= 2 sec typ., B= 250 - 500 ms, C= 250 ms, D= 150ms, E depends on data length, Max C+D+E = 2.9 - 3.7 sec, F ≥ 200 ms.
2) In a battery operated CPE, NW6005 may be enabled only after the end of ringing to conserve power.
3) The microcontroller in the CPE powers down the NW6005 after CD goes inactive.
4) The microcontroller times out if CD is not activated on the 2nd ring and puts the device into Power-down mode.
5) FSK may be always enabled while the CPE is on-hook. To prevent the FSK demodulator from reacting to other inband signals such as speech, DT-AS or DTMT tones. The designer may
choose to disable FSKduring the period that FSK signal is not expected.
6) PWDN and FSKEN are internal signals decoded from Control Bits CB2-0.
7) When CB0 is low, both DR and DCLK pins are unused.
11
NW6005 ENHANCED TYPE II CALLER ID DECODER
CPE mutes handset and
disable keypad
CPE off-hook
A/B wires
INDUSTRIAL TEMPERATURE RANGE
Note 2
CAS
A
CPE unmutes handset and
enable keypad
CPE sends ACK
B
C
D
Mark
Message
E
F
G
Note 3
PWDN
Note7
Note 5
FSKEN
Note 6
Note 4
Note7
STD
Hybrid
DT-ASEN
Note7
CD
DR
...
Note 8
DCLK
Note 8
DATA
Data
Figure 12. Bellcore Off-hook Data Transmission Timing Diagram
Notes:
1) A= 75 - 85 ms, B= 0 -100 ms, C= 55 - 65 ms, D= 0 - 500 ms, E= 58 - 75ms, F depends on data length, G≤ 50 ms.
2) If AC power is not available, the designer may use the line power when the CPE goes off-hook and use battery power while on-hook. The
CPE should also be CID (on-hook) capable .
3) If the end office fails to send the FSK signal, the CPE should disable FSKEN and unmute the handset and enable the keypad after this
interval.
4) When FSK signal is not expected, the FSKEN should be set low to disable the FSK demodulator.
5) FSKEN should be high as soon as the CPE has finished sending the acknowledgement signal ACK.
6) FSKEN should be low when CD become inactive.
7) PWDN, FSKEN and Hybrid DT-ASEN are internal signals decoded from Control Bits CB2-0.
8) When CB0 is low, both DR and DCLK pins are unused.
12
Note 1
NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
Line Reversal
A/B Wires
Alerting
Signal
A
B
C
Ch. Seizure
Mark
Message
D
E
F
Ring
G
Note 1
Tip/Ring
DT-ASEN
Note 5
PWDN
Note 5
STD
TE DC load
TE AC load
15 ±1 ms
Current Wetting Pulse
<120 µ A
50 - 150 ms
< 0.5 mA (optional)
20 ±5 ms
Note 2
Note 3
Zss
Note 4
FSKEN
Note 5
CD
DR
Note 6
...
...
..101010..
Data
DCLK
Note 6
DATA
Figure 13. BT Idle State (on-hook) Data Transmission Timing Diagram
Notes:
1) A≥ 100ms, B=88 - 110 ms, C≥ 45 ms (up to 5 sec), D= 80 -262 ms, E= 45 - 75 ms, F≤ 2.5 sec (typ. 500 ms), G≥ 200 ms.
2) By choosing tGA=15 ms, tABS will be 15-25 ms (refer to Fig. 8). Current wetting pulse and AC/DC load should be applied right after the
STD rising edge.
3) AC and DC loads should be removed between 50-150 ms after the end of the FSK signal. The NW6005 may go to power down mode
to save power.
4) FSKEN should be set low to disable the FSK demodulator, when the FSK signal is not expected.
5) Tip/Ring DT-ASEN, PWDN and FSKEN are internal signals decoded from Control Bits CB2-0.
6) When CB0 is low, both DR and DCLK pins are unused.
13
NW6005 ENHANCED TYPE II CALLER ID DECODER
MAXIMUM RATING
INDUSTRIAL TEMPERATURE RANGE
- Exceeding the following listed values may cause permanent damage.
Power Supply Voltage: -0.3 V to 6 V
Voltage on any pin other than supplies: GND - 0.3 V to VCC + 0.3 V
Current at any pin other than supplies: ≤ 10 mA
Storage Temperature: -65 °C to +150 °C
RECOMMENDED OPERATING CONDITIONS
Operating Temperature: -40 °C to +85 °C
Power Supply Voltage: 3 V ± 10% or 5 V ± 10%
Clock Frequency: 3.579545 MHz ± 0.1%
Input Voltage: 0 V to VCC
CRYSTAL SPECIFICATIONS
Frequency: 3.579545 MHz
Resonancy tolerance: ± 0.1%( -40°C to +85°C)
Resonance mode: Parallel
Load capacitance: 18 pF
Maximum series resistance: 150 Ω
Maximum drive level: 2 mW
DC ELECTRICAL CHARACTERISTICS
Parameter
ICCS
Pin
ICC
VCC
VT+
VTVHYS
VIH
VIL
IOH
DCLK
CB0
CB1
CB2
DCLK, DATA, EST
DR/STD, CD , ST/GT
Description
Power Supply Standby
Current
Operating Supply Current
VCC = 5 V ± 10%
VCC = 3 V ± 10%
Min
Schmitt Trigger Input High
Threshold
Schmitt Trigger Input Low
Threshold
Schmitt Hysteresis
CMOS Input High Voltage
0.5VCC
CMOS Input Low Voltage
Output High Sourcing
Current
GND
-0.8
Typ
0.5
Units
µA
Test Conditions
Test 1
Test 2
2.5
1.8
3.8
2.7
0.7VCC
mA
mA
V
0.3VCC
0.5VCC
V
0.2
0.7VCC
VCC
V
V
Test 1: All inputs are VCC/GND except for oscillator pins. No analog input. Output unloaded. NW6005 in power down mode.
Test 2: All inputs are VCC/GND except for oscillator pins. No analog input. Ouput unloaded. FSK is enabled.
14
Max
15
0.3VCC
V
mA
VOH=0.9VCC
NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Parameter
IOL
Iin1
Iin2
I OZ 1
VREF
RREF
VTGT
Pin
DCLK, DATA
DR/ STD, CD
EST, ST/GT
IN1+, IN1IN2+, IN2DCLK
CB0, CB1, CB2
ST/GT
VREF
ST/GT
Description
Min
Output Low Sinking
Current
Typ
Max
2
Units
Test Conditions
mA
VOL = 0.1VCC
Input Current
1
µA
Input Current
10
µA
V in = VCC to GND
0.5VCC-0.1
5
0.5VCC+0.1
2
µA
V
kΩ
V out = VCC to GND
No Load
0.5VCC-0.05
0.5VCC+0.05
V
Output High Impedance
Output Voltage
Output Resistance
Comparator Threshold
Voltage
AC ELECTRICAL CHARACTERISTICS
Dual Tone Alert Signal Detection
Parameter
FL
FH
FDA
FDR
SIGAC
SIGRJ
TA
SNR
Description
Low Tone Frequency
High Tone Frequency
Frequency Deviation Accept
Frequency Deviation Reject
Accept Signal Level per tone
Reject Signal Level per tone
(VCC = 5 V ± 10%, 3 V ± 10%)
Positive and Negative Twist Accept #
Signal to Noise Ratio
Min
Typ
2130
2750
1.1%
3.5%
-40
20
Max
Units
Hz
Hz
-2
dBV
-47
dBV
7
dB
dB
# Twist = 20 |log ( fH amplitude / fL amplitude )|.
15
Notes
Nominal frequency
Nominal frequency
Within this range, tones are accepted.
Outside this range, tones are rejected.
Input op amp configured to 0 dB gain for 5 V
operation, gain for 3 V operation is TBD. Signal
level is per tone.
Both tones have the same amplitude and at
nominal frequencies. Band limited random noise
300-3400 Hz. Measurement valid only when tone
is present.
NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Gain Adjustable Op Amp
Parameter
IIN
RIN
VOS
PSRR
CMRR
AVOL
fC
VO
CL
RL
VCM
Description
Input Leakage Current
Input Resistance
Input Offset Voltage
Power Supply Rejection Ratio
Common Mode Rejection
DC Open Loop Voltage Gain
Unity Gain Bandwidth
Output Voltage Swing
Maximum Capacitive Load (GS)
Maximum Resistive Load (GS)
Common Mode Range Voltage
Min
Typ
Max
1
Units
µA
MΩ
mV
dB
dB
dB
MHz
V
pF
kΩ
10
10
40
30
50
0.3
0.5
VCC -0.5
50
100
1.0
Test Conditions
GND ≤ VIN ≤ VCC
1kHz ripple on VCC
VCMmin ≤ VIN ≤ VCMmax
Load ≥ 100 kΩ
VCC-1.0
FSK Detection
Parameter
Description
ID
Input Detection Level
RS
Reject Signal Level
TR
Transmission Rate
Input Frequency Detection
Bell 202 ‘1’ (mark)
Input Frequency Detection
Bell 202 ‘0’ (space)
Input Frequency Detection
ITU-T V.23 ‘1’ (mark)
Input Frequency Detection
ITU-T V.23 0 (space)
Positive and Negative Twist Accept *
FMARK
FSPACE
FMARK
FSPACE
TA
SNR
Signal to Noise Ratio
Min
-40
Typ
Max
Units
Notes
-6.45
dBV
-48
dBV
Production tested at VCC =3V ±10%, or 5V
±10%. Both mark and space have the
same amplitude.
1188
1200
1212
baud
1188
1200
1212
Hz
2178
2200
2222
Hz
1280.5
1300
1319.5
Hz
2068.5
2100
2131.5
Hz
10
dB
-10
20
dB
* Twist = 20 |log ( fH amplitude / fL amplitude )|.
# BT band is 200-3400 Hz, while Bellcore band is 0-4 kHz.
Notes:
dBV = decibels above or below a reference voltage of 1 Vrms.
16
Both mark and space have the same
amplitude and at nominal frequencies.
Band limited random noise: 200-3400 Hz.
Present only when FSK signal is present. #
NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
AC TIMING CHARACTERISTICS
Power Up/Down and FSK Detection
Parameter
t1
t2
t3
t4
t5
Description
Power Up Time
Power Down Time
Input FSK to CD low delay
Input FSK to CD high delay
Hysteresis
Min
Typ
Max
50
1
25
Units
ms
ms
ms
ms
ms
Test Conditions
Typ
Max
14
8
Units
ms
ms
Test Conditions
10
10
Dual Tone Alert Signal
Parameter
t6
t7
Description
Alert Signal Present Detect Time
Alert Signal Absent Detect Time
Min
4
0.1
Power down is
enabled by
Control Bits
OSCOUT
t1
t2
Figure 14. Power Up/Down Timing
Tip/Ring
FSK Signal
CD
t3
t4
Figure 15. FSK Detection Time
Tip/Ring
or Hybrid
Receive Pair
Alert Signal
EST
t6
t7
Figure 16. Dual Tone Alert Signal Detection Time
17
NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
AC TIMING CHARACTERISTICS (CONTINUED)
Serial Interface (Mode ‘1’)
Parameter
t11
t12
t13
t14
t15
t16
t17
Description
DCLK Cycle Time
DCLK High Time
DCLK Low Time
DCLK Rise Time
DCLK Fall Time
DCLK Low Setup to DR
DCLK Low Hold Time after DR
Min
1
0.3
0.3
Typ
Max
Units
µs
µs
µs
ns
ns
ns
ns
100
100
500
500
t13
Test Conditions
t12
DCLK
t14
t15
t11
Figure 17. DCLK Timing in Mode ‘1’
Internal
Demodulated Bit
Stream
Nth byte
b7
(N+1)th byte
stop
b0
start
b1
b2
b3
b4
b5
b6
b7
stop
start
note 1
DR
t16
t17
note 2
DCLK
DATA
b7
stop b0
b1
b2
b3 b4 b5
b6 b7
(N-1)th byte
stop
Nth byte
Figure 18. Serial Data Interface Timing in MODE ‘1’
Notes:
1. DCLK clears DR.
2. DR not cleared by DCLK, low for a maximum time of 1/2 bit width.
18
b0
NW6005 ENHANCED TYPE II CALLER ID DECODER
INDUSTRIAL TEMPERATURE RANGE
Serial Interface (Mode ‘0’)
Parameter
DR
t21
t22
t23
Description
Data Rate
Input FSK to DATA Delay
DATA Rise Time
DATA Fall Time
Min
1188
Typ
1200
1
Max
1212
5
200
200
Units
baud
ms
ns
ns
Test Conditions
1
2
2
Test conditions:
1. FSK input data at 1200 ± 12 buad.
2. Load of 50 pF.
DATA
t22
t23
Figure 19. DATA Output Timing in Mode ‘0’
TIP/RING
b7
start
Nth byte
0
b0 b1 b2 b3 b4 b5 b6 b7
1
stop
start
1
0
(N+1)th byte
stop
start
b0 b1 b2 b3 b4 b5 b6 b7
1
0
b0 b1
t21
start
DATA
b7
Nth byte
(N+1)th byte
start
b0 b1 b2 b3 b4 b5 b6 b7
start
b0 b1 b2 b3 b4 b5 b6 b7
stop
Figure 20. Serial Data Interface Timing in MODE ‘0’
Min.
Pulse Duration
Min
Maximum Dropout Span
Figure 21. Valid DT-AS Pulses
19
b0 b1
stop
Max.
PHYSICAL DIMENSIONS
in Millimeters
Symbol
A
A1
B
C
E
e
H
h
L
θ
D
Dimension in MM
Min
Max
2.35
2.65
0.10
0.30
0.33
0.51
0.23
0.32
7.40
7.60
1.27 BSC
10.00
10.65
0.25
0.75
0.40
1.27
0
8
12.60
13.00
Dimension in Inch
Min
Max
0.093
0.104
0.004
0.012
0.013
0.020
0.009
0.013
0.291
0.299
0.050 BSC
0.394
0.419
0.010
0.029
0.016
0.050
0
8
-
Figure 21. NW6005-XS 20 Pin SOIC Package Diagram
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
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20
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408-330-1753
email: [email protected]