AD OP15AJMDA Precision jfet-input operational amplifier Datasheet

a
Precision JFET-Input
Operational Amplifiers
OP15/OP17
FEATURES
Significant Performance Advantages over LF155 and
LF157 Devices
Low Input Offset Voltages: 500 ␮V Max
Low Input Offset Voltage Drift: 2.0 ␮V/ⴗC
Minimum Slew Rate Guaranteed on All Models
Temperature-Compensated Input Bias Currents
Bias Current Specified Warmed-Up Over Temperature
Internal Compensation
÷ Hz
Low Input Noise Current: 0.01 pA/÷
High Common-Mode Rejection Ratio: 100 dB
Models with MIL-STD 883 Processing Available
GENERAL DESCRIPTION
The ADI-JFET input series of devices offer clear advantages over
industry-generic devices and are superior in both cost and performance to many dielectrically-isolated and hybrid op amps. All devices
offer offset voltages as low as 0.5 mV with TCVOS guaranteed to
5 mV/∞C. A unique input bias cancellation circuit reduces the IB
by a factor 10 over conventional designs. In addition ADI specifies
IB and IOS with the devices warmed up and operating at 25∞C ambient.
These devices were designed to provide real precision performance
along with high speed. Although they can be nulled, the design
objective was to provide low offset-voltage without nulling. Systems
generally become more cost effective as the number of trim circuits
is decreased. ADI achieves this performance by use of an improved
bipolar compatible JFET process coupled with on chip, zener-zap
offset trimming.
OP15
156 Speed with 155 Dissipation: 80 mW Typ
Wide Bandwidth: 6 MHz
High Slew Rate: 13 V/␮s
Fast Settling to ±0.1%: 1,200 ns
The OP15 provides an excellent combinations of high speed and
low input offset voltage. In addition, the OP15 offers the speed
of the 156A op amp with the power dissipation of a 155A. The
combination of a low input offset voltage of 500 mV, slew rate of
13 V/ms, and settling time of 1,200 ns to 0.1% makes the OP15
an op amp of both precision and speed. The additional features
of low supply current coupled with an input bias current makes
the OP15 ideal for a wide range of applications.
OP17
Highest Slew Rate: 60 V/␮s
Fastest Settling to ±0.1%: 600 ns
Highest Gain Bandwidth Product (AVCL = 5 Min): 30 MHz
Guaranteed Input Bias Current @ 125ⴗC
The OP17 has a slew rate of 60 V/ms and is the best choice for
applications requiring high closed-loop gain with high speed. See
OP42 datasheet for unity gain applications and the OP215 datasheet
for a dual configuration of the OP15.
V+
J5
Q5
R8*
NULL
*R7, R8 ARE ELECTRONICALLY
ADJUSTED ON CHIP FOR
MINIMUM OFFSET VOLTAGE.
R7*
NULL
J8
Q16
Q6
Q7
R3
Q9
J6
Q19
Q24
Q8
R1
J11
NONINVERTING
INPUT
J1
Q17
J2
R2
–INV
INPUT
Q1
Q22
OUTPUT
Q2
Q3
R13
C2
Q10
Q4
J10
Q12
Q23
J9
Q11
J3
C1
7.4pF
J4
R3
R4
R5
3.6k⍀
Q16
Q13
R6
3.6k⍀
Q15
Q14
Q20
Q21
Q25
R11
V–
Figure 1. Simplified Schematic
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
OP15/OP17–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = ⴞ15 V, T = 25ⴗC, unless otherwise noted)
S
Parameter
A
OP15A, OP15E
OP17A, OP17E
Min
Typ
Max
Symbol
Conditions
Max
Unit
VOS
RS = 50 W
0.2
0.5
0.4
1.0
0.5
3.0
mV
Input Offset Current
OP15
IOS
TJ = 25∞C1
Device Operating
TJ = 25∞C1
Device Operating
3
5
3
5
10
22
10
25
6
10
6
10
20
40
20
50
12
20
12
20
50
100
50
125
pA
pA
pA
pA
TJ = 25∞C1
Device Operating
TJ = 25∞C1
Device Operating
± 15
± 18
± 15
± 20
± 50
± 110
± 50
± 130
± 30
± 40
± 30
± 40
± 100
± 200
± 100
± 250
± 60
± 80
± 60
± 80
± 200
± 400
± 200
± 500
pA
pA
pA
pA
Input Bias Current
OP15
IB
OP17
1012
Max
Min
OP15G
OP17G
Typ
Input Offset Voltage
OP17
Min
OP15F
OP17F
Typ
1012
W
50
200
V/mV
± 12
± 11
± 13
± 12.7
V
V
1012
Input Resistance
RIN
Large-Signal
Voltage Gain
AVO
RL ≥ 2 kW
VO = ± 10 V
100
240
75
220
Output Voltage
Swing
VO
RL = 10 kW
RL = 2 kW
± 12
± 11
± 13
± 12.7
± 12
± 11
± 13
± 12.7
Supply Current
ISY
OP15
OP17
Slew Rate2
SR
AVCL = 1, OP15
AVCL = 5, OP17
10
45
13
60
7.5
35
11
50
5
25
9
40
V/ms
V/ms
Gain Bandwidth3
Product
GBW
OP15
OP17
4.0
20
6.0
30
3.5
15
5.7
28
3.0
11
5.4
26
MHz
MHz
Closed-Loop
Bandwidth
CLBW
AVCL = 1, OP15
AVCL = 5, OP17
14
11
13
10
12
9
MHz
MHz
Settling Time
OP15
tS
To 0.01%
To 0.05%
To 0.10%
To 0.01%
To 0.05%
To 0.10%
4.5
1.5
1.2
1.5
0.7
0.6
4.5
1.5
1.2
1.5
0.7
0.6
4.7
1.6
1.3
1.6
0.8
0.7
ms
ms
ms
ms
ms
ms
OP17
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Input Noise
Voltage Density
Input Noise
Current Density
Input Capacitance
2.7
4.6
4.0
7.0
± 10.5
VCM = ± 10.5 V
VCM = ± 10.3 V
86
2.7
4.6
4.0
7.0
± 10.5
100
86
2.8
4.8
5.0
8.0
± 10.3
V
100
82
mA
mA
dB
dB
96
VS = ± 10 V to ± 18 V
VS = ± 10 V to ± 18 V
10
en
fO = 100 Hz
fO = 1 kHz
20
15
20
15
20
15
nV/÷Hz
nV/÷Hz
in
fO = 100 Hz
fO = 1 kHz
0.01
0.01
0.01
0.01
0.01
0.01
pA/÷Hz
pA/÷Hz
3
3
3
pF
CIN
51
10
51
10
80
mV/V
mV/V
NOTES
1
Input bias current is specified for two different conditions. The T J = 25∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the
curves of I B versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and
IOS are measured at VCM = 0.
2
Settling time is defined here for a unity gain inverter connection using 2 k W resistors. It is the time required for the error voltage (the voltages at the inverting input pit
on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See settling time test circuit.
3
Sample tested.
4
Settling time is defined here for A V = –5 connection with RF = 2 kW. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to
settle to within 0.01% of its final value from the time a 2 V step input is applied to the inverter. See settling time test circuit.
–2–
REV. A
OP15/OP17
Electrical Characteristics (@ V = ±15 V, –55ⴗC £ T £ 125ⴗC, unless otherwise noted.)
S
Parameter
Input Offset Voltage
A
Symbol
Conditions
VOS
TCVOS
TCVOS
Min
Typ
Max
Units
RS = 50 W
0.4
0.9
mV
RP = 100 W
2
2
5
mV/∞C
mV/∞C
1
Average Input Offset Voltage Drift
Without External Trim
With External Trim
Input Offset Current2
OP17
IOS
TJ = 125∞C
TA = 125∞C, device operating
0.6
1.0
4.0
8.5
nA
nA
Input Bias Current2
OP17
IB
TJ = 125∞C
TA = 125∞C, device operating
± 1.2
± 2.0
± 5.0
± 11
nA
nA
Input Voltage Range
IVR
Common-Mode Rejection Ratio
CMRR
VCM = ± 10.4 V
Power Supply Rejection Ratio
PSRR
VS = ± 10 V to ± 18 V
Large Signal Voltage Gain
AVO
RL ≥ 2 kW, VO = ± 10 V
35
120
V/mV
Output Voltage Swing
VO
RL ≥ 10 kW
± 12
± 13
V
± 10.4
85
V
97
dB
15
mV/V
57
NOTES
1
Sample tested.
2
Input bias current is specified for two different conditions. The T J = 25∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the
curves of I B versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and
IOS are measured at VCM = 0.
ELECTRICAL CHARACTERISTICS
Parameter
Input Offset Voltage
OP15E/OP17E
Min
Typ
Max
OP15F/OP17F
Min
Typ
Max
OP15G/OP17G
Min
Typ
Max
Unit
1.5
0.7
3.8
mV
3
3
10
4
4
30
mV/∞C
mV/∞C
0.30
0.55
0.30
0.70
0.06
0.08
0.06
0.10
0.45
0.80
0.45
1.1
0.08
0.10
0.08
0.15
0.85
1.2
0.85
1.7
nA
nA
nA
nA
± 0.40
± 0.75
± 0.40
± 0.90
± 0.12
± 0.16
± 0.12
± 0.20
± 0.60
± 1.1
± 0.60
± 1.4
± 0.14
± 0.19
± 0.14
± 0.25
± 0.80
± 1.5
± 0.80
± 2.0
nA
nA
nA
nA
Symbol
Conditions
VOS
RS = 50 W
0.3
0.75
0.55
RP = 100 W
2
2
5
TJ = 70∞C
TA = 70∞C, Device Operating
TJ = 70∞C
TA = 70∞C, Device Operating
0.04
0.06
0.04
0.07
TJ = 70∞C
TA = 70∞C, Device Operating
TJ = 70∞C
TA = 70∞C, Device Operating
± 0.10
± 0.13
± 0.10
± 0.15
Average Input Offset
Voltage Drift1
Without External Trim TCVOS
With External Trim TCVOSn
Input Offset Current2 IOS
OP15
OP17
Input Bias Current2
OP15
(@ VS = ⴞ15 V, 0ⴗC £ TA £ 70ⴗC for E and F grades, –40ⴗC £ TA £ 85ⴗC for G grades
unless otherwise noted)
IB
OP17
± 10.4
± 10.4
± 10.25
V
80
dB
dB
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Large Signal
Voltage Gain
AVO
RL ≥ 2 kW
VO = ± 10 V
65
200
50
180
35
160
V/mV
Output Voltage
Swing
VO
RL ≥ 10 kW
± 12
± 13
± 12
± 13
± 12
± 13
V
VCM = ± 10.4 V
VCM = ± 10.25 V
85
VS = ± 10 V to ± 18 V
VS = ± 10 V to ± 15 V
98
13
85
57
96
13
94
57
20
100
mV/V
mV/V
NOTES
1
Sample tested.
2
Input bias current is specified for two different conditions. The T J = 25∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the
curves of I B versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and
IOS are measured at VCM = 0.
REV. A
–3–
OP15/OP17–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage
All Devices Except C, G (Packaged)
and GR Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 22 V
C, G (Packaged) and GR Grades . . . . . . . . . . . . . . . . ± 18 V
Operating Temperature
A Grade . . . . . . . . . . . . . . . . . . . . . . . . . . –55∞C to +125∞C
E, F Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . 0∞C to 70∞C
G Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150∞C
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All Devices Except C, G Grades . . . . . . . . . . . . . . . . ± 40 V
C, G Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 V
Input Voltage2
All Devices Except C, G Grades . . . . . . . . . . . . . . . . ± 20 V
C, G Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 16 V
Input Voltage
OP15E, OP15F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 V
OP15G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 16 V
OP17A, OP17E, OP17F . . . . . . . . . . . . . . . . . . . . . . ± 20 V
OP17G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 16 V
Output Short-Circuit Duration
Indefinite
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C
Package Type
␪JA*
␪JC
Unit
8-Lead Hermetic DIP (Z)
8-Lead SO (S)
TO-99 (J)
148
158
150
16
43
18
∞C/W
∞C/W
∞C/W
*␪JA is specified for worst-case mounting conditions, i.e., ␪JA is specified for device
in socket for CERDIP and PDIP packages; ␪JA is specified for device soldered to
printed circuit board for SO packages.
+20V
10k⍀
2
7
8
3
+3V
300⍀
4
10k⍀
–20V
Figure 2. Burn-In Circuit
NOTES
*Absolute Maximum Ratings apply to packaged parts, unless otherwise noted.
8-Lead CERDIP
(Z-Suffix)
8-Lead SOIC
(S-Suffix)
1
8 NC
BAL
–IN
2
7 V+
+IN
3
6 OUT
V–
4
5 BAL
BAL
8-Lead TO-99
(J-Suffix)
1
8 NC
–IN
2
7 V+
+IN
3
6 OUT
V–
4
5 BAL
ORDERING GUIDE
TA = 25∞C
VOS MAX
(mV)
Package Options
TO-99
CERDIP
0.5
OP17EJ
OP15EZ
OP17EZ
COM
1.0
OP15FJ*
OP17FJ
OP15FZ*
OP17FZ
COM
3.0
OP15GJ*
OP15GZ*
OP17GZ
SOIC
OP15GS*
Operating
Temperature
Range
XIND
For military processed devices, please refer to the Standard Microcircuit Drawing
(SMD) available at www.dscc.dl.mil/programs/milspec/default.asp.
SMD Part Number
ADI Equivalent
5962-8954201GA*
5962-8954201PA*
5962-8954301GA*
5962-8954301PA*
OP15AJMDA
OP15AZMDA
OP16AJMDA
OP16AZMDA
*Not recommended for new designs. Obsolete April 2002.
–4–
REV. A
Typical Performance Characteristics –OP15/OP17
30
100
WARMED-UP IN FREE AIR
VS = 15V
TA = 25ⴗC
VS = 15V
PEAK-TO-PEAK OUTPUT SWING – V
27
80
INPUT BIAS CURRENT – pA
24
–55ⴗC
21
+25ⴗC
18
15
+125ⴗC
12
9
60
a. UNDERCANCELLED IB = +16pA @ V CM = 0
b. PERFECTLY CANCELLED IB = 0pA @ V CM = 0
c. UNDERCANCELLED IB = –16pA @ V CM = 0
40
20
a
c
b
6
0
3
0
100
–20
–12 –10
100k
1k
10k
OUTPUT LOAD RESISTANCE – ⍀
–6 –4 –2
0
2
4
6
INPUT COMMON-MODE VOLTAGE – V
8
10
12
TPC 4. Input Bias Current vs. Common-Mode Voltage
TPC 1. Maximum Output Swing vs. Load Performance
1M
20
COMMON-MODE INPUT VOLTAGE RANGE – V
–8
RL = 2k⍀
OPEN-LOOP VOLTAGE GAIN – V/V
TA = 25ⴗC
15
10
POSITIVE
5
FROM –55ⴗC TO –125ⴗC
CHANGE IN CMVR IS < 0.2V
500k
400k
–55ⴗC
300k
200k
25ⴗC
125ⴗC
100k
NEGATIVE
0
10k
0
5
10
SUPPLY VOLTAGE – V
15
20
5
TPC 2. Common-Mode Input Voltage Range vs. Supply
Voltage
40
TA = 25ⴗC
VS = 15V
100Hz < f < 10kHz
10Hz < f < 10kHz FOR RS > 4M⍀
a AMPLIFIER NOISE
b JOHNSON RESISTOR NOISE
c AMPLIFIER NOISE MEASURED
WITH SOURCE RESISTOR
c
PEAK-TO-PEAK OUTPUT SWING – V
INPUT NOISE VOLTAGE – ␮V
10
20
TPC 5. Open-Loop Voltage Gain vs. Supply Voltage
1k
100
10
15
SUPPLY VOLTAGE – V
b
1
0.1
RL = 2k⍀
TA = 25ⴗC
30
20
10
a
0.01
100k
0
1M
10M
100M
SOURCE RESISTANCE – ⍀
1G
10G
5
10
SUPPLY VOLTAGE – V
15
20
TPC 6. Output Voltage Swing vs. Supply Voltage
TPC 3. Voltage Noise vs. Source Resistance
REV. A
0
–5–
OP15/OP17
1n
VS = 15V
TA = 25ⴗC
ISY = 4.0mA FOR MAX CURVES
2.5mA FOR TYP CURVES
7
INPUT BIAS CURRENT – A
NULLED OFFSET VOLTAGE DRIFT – ␮V/ⴗC
9
5
VOS
3
1
TYPICAL DRIFT BAND
–1
155A MAX
OP15A MAX
100p
155A TYP
–3
OP15 TYP
–5
10k
100k
RP-TRIMMING POTENTIOMETER VALUE – ⍀
10p
1M
0
TPC 7. Nulled Offset Voltage Drift vs. Potentiometer Size
20
40
60
80
100
TIME AFTER POWER APPLIED – s
120
140
TPC 10. OP15 Bias Current vs. Time in Free Air
6
1n
VS = 15V
156A/157A MAX
INPUT BIAS CURRENT – A
OFFSET VOLTAGE – mV
4
2
0
–2
156A/157A TYP
100p
OP17A MAX
VS = 15V
TA = 25ⴗC
ISY = 6.7mA FOR MAX CURVES
5.0mA FOR TYP CURVES
–4
OP17A TYP
–6
–50
–25
0
25
50
75
100
10p
125
0
20
TEMPERATURE – ⴗC
TPC 8. Offset Voltage Drift vs. Temperature of
Representative Units
40
60
80
100
TIME AFTER POWER APPLIED – s
120
140
TPC 11. OP17 Bias Current vs. Time in Free Air
100n
100n
VS = 15V
UNITS ARE WARMED UP
INPUT BIAS CURRENT – A
155A MAX
INPUT BIAS CURRENT – A
155A MAX
10n
155A TYP
OP15A MAXP
1n
OP15 TYP
10n
155A TYP
OP15A MAX
1n
OP15A TYP
100p
100p
10p
10
10p
10
30
50
70
90
110
130
30
50
70
90
110
130
150
AMBIENT TEMPERATURE – ⴗC
150
AMBIENT TEMPERATURE – ⴗC
TPC 12. OP15 Input Bias Current vs. Ambient Temperature
(Units Warmed Up in Free Air)
TPC 9. Input Bias Current vs. Ambient Temperature
(Units Warmed Up in Free Air)
–6–
REV. A
OP15/OP17
0
100n
0
0
10n
156A/157A TYP
VOLTAGE – 5V/DIV
INPUT BIAS CURRENT – A
156A/157A MAX
OP17A MAX
1n
OP17A TYP
0
0
0
0
100p
0
10p
10
30
50
70
90
110
130
0
150
0
0
0
0
AMBIENT TEMPERATURE – ⴗC
0
0
0
TIME – 500ns/DIV
0
0
0
0
TPC 16. OP15 Large Signal Transient Response
TPC 13. OP17 Input Bias Current vs. Ambient Temperature
(Units Warmed Up in Free Air)
0
3.5
0
3.0
VOLTAGE – 20mV/DIV
SUPPLY CURRENT – mA
0
–55ⴗC
2.5
25ⴗC
125ⴗC
0
0
0
0
2.0
0
1.5
0
5
10
SUPPLY VOLTAGE – V
15
0
20
0
TPC 14. OP15 Supply Current vs. Supply Voltage
OUTPUT VOLTAGE SWING FROM 0V – V
SUPPLY CURRENT – mA
0
0
0
0
TIME – 100ns/DIV
0
0
0
0
10
5.0
4.5
–55ⴗC
25ⴗC
4.0
125ⴗC
0
5
10
SUPPLY VOLTAGE – V
15
20
VS = 15V
TA = 25ⴗC 10mV
AV = –1
5mV
1mV
10mV
5mV
1mV
5
0
–5
–10
TPC 15. OP17 Supply Current vs. Supply Voltage
REV. A
0
TPC 17. OP15 Small Signal Transient Response
5.5
3.5
0
0
0.5
1.0
1.5
SUPPLY VOLTAGE – V
2.0
TPC 18 OP15 Settling Time
–7–
2.5
OP15/OP17
12
120
10
130
8
140
VOLTAGE GAIN – dB
AV > 10
6
150
4
160
2
170
0
180
–2
190
–4
200
–6
28
PEAK-TO-PEAK OUTPUT SWING – V
14
90
VS = 15V
100
TA = 25ⴗC
110
PHASE MARGIN = 86ⴗ
PHASE SHIFT – Degrees
18
16
AV = 1
VS = 15V
TA = 25ⴗC
AV = 1
24
20
16
12
8
4
–8
–10
1M
10M
FREQUENCY – MHz
0
100k
100M
10M
TPC 22. OP15 Maximum Output Swing vs. Frequency
TPC 19. OP15 Closed-Loop Bandwidth and Phase vs.
Frequency
70
28
VS = 15V
VS = 15V
AV = 1
60
24
BANDWIDTH VARIATION FROM
5V < VS < 20V IS < 5 %
20
SLEW RATE – V/␮sec
BANDWIDTH – MHz
1M
FREQUENCY – MHz
CLOSED-LOOP
BANDWIDTH AV = 1
16
12
GAIN BANDWIDTH
PRODUCT
8
50
NEGATIVE
40
30
20
POSITIVE
10
4
0
–50
0
–25
25
50
75
100
0
–50
125
50
75
100
125
TPC 23. OP15 Slew Rate vs. Temperature
100
120
COMMON-MODE REJECTION RATIO – dB
VS = 15V
TA = 25ⴗC
100
OPEN-LOOP VOLTAGE GAIN – dB
25
AMBIENT TEMPERATURE – ⴗC
TPC 20. OP15 Bandwidth vs. Temperature
80
60
40
20
0
–20
0
–25
TEMPERATURE – ⴗC
1
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
VS = 15V
TA = 25ⴗC
80
60
40
20
0
100M
1
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
100M
TPC 24. OP15 Common-Mode Rejection Ratio vs. Frequency
TPC 21. OP15 Open-Loop Gain vs. Frequency
–8–
REV. A
OP15/OP17
120
0
POWER SUPPLY REJECTION RATIO – dB
TA = 25ⴗC
0
100
VOLTAGE – 5V/DIV
0
80
POSITIVE SUPPLY
60
NEGATIVE SUPPLY
40
0
0
0
0
20
0
0
10
100
1k
10k
100k
FREQUENCY – Hz
1M
0
10M
0
TPC 25. OP15 Power Supply Rejection Ratio vs. Frequency
0
0
0
0
0
0
TIME – 200ns/DIV
0
0
0
0
TPC 28. OP17 Large Signal Transient Response
100
0
VS = 15V
TA = 25ⴗC
0
AV = 100
VOLTAGE – 20mV/DIV
OUTPUT IMPEDANCE – ⍀
0
10
AV = 10
AV = 1
1
0
0
0
0
0
0
1k
10k
100k
FREQUENCY – Hz
1M
0
10M
0
TPC 26. OP15 Output Impedance vs. Frequency
OUTPUT VOLTAGE SWING FROM 0V – V
VOLTAGE NOISE DENSITY – nV/ Hz
80
60
l/f CORNER FREQUENCY
40
20
10k
100k
FREQUENCY – Hz
1M
0
0
0
TIME – 100ns/DIV
0
0
0
0
10mV
5mV
10mV
5mV
VS = 15V
TA = 25ⴗC
AV = –5
1mV
5
0
–5
–10
10M
0
0.5
1mV
1.0
1.5
SUPPLY VOLTAGE – V
2.0
TPC 30. OP17 Settling Time
TPC 27. OP15 Voltage Noise Density vs. Frequency
REV. A
0
10
VS = 15V
TA = 25ⴗC
100
0
1k
0
TPC 29. OP17 Small Signal Transient Response
140
120
0
–9–
2.5
OP15/OP17
120
VS = 15V
TA = 25ⴗC
AV = 5
24
POWER SUPPLY REJECTION RATIO – dB
PEAK-TO-PEAK OUTPUT SWING – V
28
20
16
12
8
4
0
100k
1M
FREQUENCY – MHz
100
POSITIVE
SUPPLY
80
60
NEGATIVE SUPPLY
40
20
0
10
10M
TPC 31. OP17 Maximum Output Swing vs. Frequency
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
TPC 34. OP17 Power Supply Rejection Ratio vs. Frequency
110
100
VS = 15V
NEGATIVE
VS = 15V
TA = 25ⴗC
AV = 5
OUTPUT IMPEDANCE – ⍀
100
SLEW RATE – V/␮sec
TA = 25ⴗC
90
80
POSITIVE
70
60
10
AV = 100
AV = 10
1.0
50
40
–50
0
–25
25
50
75
100
0
1k
125
10k
AMBIENT TEMPERATURE – ⴗC
TPC 32. OP17 Slew Rate vs. Temperature
VOLTAGE NOISE DENSITY – nV/ Hz
COMMON-MODE REJECTION RATIO – dB
80
60
40
20
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
10M
140
VS = 15V
TA = 25ⴗC
1
1M
TPC 35. OP17 Output Impedance vs. Frequency
100
0
100k
FREQUENCY – Hz
120
100
80
60
l/f CORNER FREQUENCY
40
20
0
1k
100M
TPC 33. OP17 Common-Mode Rejection Ration vs.
Frequency
VS = 15V
TA = 25ⴗC
10k
100k
FREQUENCY – Hz
1M
10M
TPC 36. OP17 Voltage Noise vs. Frequency
–10–
REV. A
OP15/OP17
TEST CIRCUITS
2k⍀
0.1%
+15V
V+
400⍀
0.1%
10V
100k⍀
7
2
1
0V
5
3
7
6
OP17
1k⍀
0.1%
6
2
100pF
3k⍀
4
–15V
4
SUMMING
NODE
NOTE: V OS CAN BE TRIMMED WITH POTENTIOMETERS
RANGING FROM 10k⍀ TO 1M⍀. FOR MOST UNITS
TCVOS WILL BE MINIMIZED WHEN VOS IS ADJUSTED
WITH A 100k⍀ POTENTIOMETER
2N4416
3
SCOPE
5k⍀
0.1%
AV = –1
2N4416
Figure 3. Input Offset Voltage Nulling
VOUT
+15V
2k⍀
2k⍀
0.1%
Figure 6. OP17 Settling Time Test Circuit
+15V
2k⍀
0.1%
10V
0V
5k⍀
0.1%
2
APPLICATION INFORMATION
Dynamic Operating Considerations
7
6
OP15
As with most amplifiers, care should be taken with lead dress,
component placement and supply decoupling in order to ensure
stability. For example, resistors from the output to an input should
be placed with the body close to the input to minimize “pick-up”
and maximize the frequency of the feedback pole by minimizing
the capacitance for the input to ground.
2N4416
3
4
100pF
3k⍀
–15V
SUMMING
NODE
SCOPE
VOUT
AV = –1
5k⍀
0.1%
A feedback pole is created when the feedback around any amplifier
is resistive. The parallel resistance and capacitance from the input
of the device (usually the inverting input) to ac ground set the
frequency of this pole. In many instances the frequency of this
pole is much greater than the expected, 3 dB frequency of the
close-loop gain, and consequently there is negligible effect on
stability margin. However, if the feedback pole is less than approximately six times the expected 3 dB frequency, a lead capacitor
should be placed from the output to the negative input of the op
amp. The value of the added capacitor should be such that the
RC time-constant of this capacitor and the resistance it parallels
is greater than, or equal to, the original feedback pole time is constant.
+15V
2N4416
2k⍀
Figure 4. OP15 Settling Time Test Circuit
R1
10k⍀
R2
5k⍀
C2
30pF
DIGITAL INPUTS
+10V
LSB
MSB
+15V
RREF
5k⍀
5
6
8
7
10
9
11 12
B1 B2 B3 B4 B5 B6 B7 B8
14
15
VREF+
DAC08E
VREF–
V+
V–
CC
3
13
+15V
–15V
C1
0.1␮F
16
7
IO
IO
4
2
OP15F
2
6
VO = 0V TO 10V
3
4
VLC
1
–15V
Figure 5. Current-to-Voltage Amplifier Output
REV. A
–11–
OP15/OP17
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches).
0.13 (0.0051) 1.40 (0.0551)
MAX
MIN
8
5.00 (0.1968)
4.80 (0.1890)
5
7.87 (0.3089)
5.59 (0.2201)
PIN 1
1
4.00 (0.1574)
3.80 (0.1497)
4
2.54 (0.1000) BSC
1.52 (0.0600)
0.38 (0.0150)
0.58 (0.0228)
0.36 (0.0142)
SEATING
1.78 (0.0701) PLANE
0.76 (0.0299)
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
3.81 (0.1500)
MIN
5.08 (0.2000)
3.18 (0.1252)
8
COPLANARITY
SEATING
0.10
PLANE
0.38 (0.0150)
0.20 (0.0079)
15
0
6.20 (0.2440)
5.80 (0.2284)
PIN 1
8.13 (0.3201)
7.37 (0.2902)
10.29 (0.4051) MAX
5.08 (0.2000)
MAX
C02789–0–9/02(A)
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
8-Lead Ceramic Dip – Glass Hermetic Seal [CERDIP]
(Q-8)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.33 (0.0130)
0.50 (0.0196)
ⴛ 45ⴗ
0.25 (0.0099)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.41 (0.0160)
0.19 (0.0075)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
8-Lead Metal Can [TO-99]
(H-08)
REFERENCE PLANE
4.70 (0.1850)
4.19 (0.1650)
12.70 (0.5000)
MIN
6.35 (0.2500) MIN
2.54 (0.1000) BSC
4.06 (0.1600)
3.56 (0.1400)
1.27 (0.0500) MAX
8.51 (0.3350)
7.75 (0.3050)
9.40 (0.3700)
8.51 (0.3350)
5
1.02 (0.0400) MAX
1.02 (0.0400)
0.25 (0.0100)
4
5.08
(0.2000)
BSC
6
3
7
2
2.54
(0.1000)
BSC
0.48 (0.0190)
0.41 (0.0160)
0.53 (0.0210)
0.41 (0.0160)
1.14 (0.0450)
0.69 (0.0270)
8
1
0.86 (0.0340)
0.71 (0.0280)
45 BSC
BASE & SEATING PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-002AK
Location
Page
9/02—Data Sheet changed from REV. 0 to REV. A.
Deleted OP16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Deleted 12 TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
REV. A
PRINTED IN U.S.A.
Revision History