AD OP181 Ultralow power, rail-to-rail output operational amplifier Datasheet

a
Ultralow Power, Rail-to-Rail Output
Operational Amplifiers
OP181/OP281/OP481
FEATURES
Low Supply Current: 4 mA/Amplifier max
Single-Supply Operation: 2.7 V to 12 V
Wide Input Voltage Range
Rail-to-Rail Output Swing
Low Offset Voltage: 1.5 mV
No Phase Reversal
APPLICATIONS
Comparator
Battery Powered Instrumentation
Safety Monitoring
Remote Sensors
Low Voltage Strain Gage Amplifiers
PIN CONFIGURATIONS
8-Lead SO
(S Suffix)
1
NULL
–IN A
+IN A
V–
4
The OP181, OP281 and OP481 are single, dual and quad
ultralow power, single-supply amplifiers featuring rail-to-rail
outputs. All operate from supplies as low as 2.0 V and are
specified at +3 V and +5 V single supply as well as ± 5 V dual
supplies.
Fabricated on Analog Devices’ CBCMOS process, the OP181
family features a precision bipolar input and an output that
swings to within millivolts of the supplies and continues to sink
or source current all the way to the supplies.
Applications for these amplifiers include safety monitoring,
portable equipment, battery and power supply control, and
signal conditioning and interface for transducers in very low
power systems.
The output’s ability to swing rail-to-rail and not increase supply
current, when the output is driven to a supply voltage, enables
the OP181 family to be used as comparators in very low power
systems. This is enhanced by their fast saturation recovery time.
Propagation delays are 250 µs.
The OP181/OP281/OP481 are specified over the extended
industrial (–40°C to +85°C) temperature range. The OP181,
single, and OP281, dual, amplifiers are available in 8-pin plastic
DIPs and SO surface mount packages. The OP281 is also
available in 8-lead TSSOP. The OP481 quad is available in 14pin DIPs, narrow 14-pin SO and TSSOP packages.
5
NC
NULL 1
V+
OUT A
NULL
–IN A 2
8 NC
7 V+
OP181
+IN A 3
NC = NO CONNECT
6 OUT A
V– 4
5 NULL
NC = NO CONNECT
8-Lead SO
(S Suffix)
1
OUT A
–IN A
+IN A
V–
GENERAL DESCRIPTION
8
OP181
8-Lead Epoxy DIP
(P Suffix)
8
OP281
4
5
8-Lead Epoxy DIP
(P Suffix)
V+
OUT B
–IN B
+IN B
OUT A 1
8-Lead TSSOP
(RU Suffix)
1
OP281
8 V+
–IN A 2
7 OUT B
+IN A 3
6 –IN B
V– 4
5 +IN B
8
OP281
4
5
14-Lead Epoxy DIP
(P Suffix)
OUT A 1
14 OUT D
–IN A 2
13 –IN D
+IN A 3
12 +IN D
V+ 4
OP481
1
14
OP481
11 V–
+IN B 5
10 +IN C
–IN B 6
9 –IN C
OUT B 7
14-Lead
Narrow-Body SO
(S Suffix)
8 OUT C
7
8
14-Lead TSSOP
(RU Suffix)
1
14
OP481
NOTE: PIN ORIENTATION IS EQUIVALENT FOR
EACH PACKAGE VARIATION
7
8
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
OP181/OP281/OP481–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = +3.0 V, V
S
CM
= 1.5 V, TA = +258C unless otherwise noted)
Parameter
Symbol
Conditions
INPUT CHARACTERISTICS
Offset Voltage
VOS
Note 1
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
∆VOS/∆T
∆IB/∆T
∆IOS/∆T
OUTPUT CHARACTERISTICS
Output Voltage High
IB
IOS
VOH
VOL
Short Circuit Limit
ISC
Supply Current/Amplifier
Typ
3
0.1
0
Output Voltage Low
POWER SUPPLY
Power Supply Rejection Ratio
Min
PSRR
ISY
DYNAMIC PERFORMANCE
Slew Rate
Turn On Time
Turn On Time
Saturation Recovery Time
Gain Bandwidth Product
Phase Margin
GBP
φo
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
SR
VCM = 0 V to 2.0 V,
–40°C ≤ TA ≤ +85°C
RL = 1 MΩ, VO = 0.3 V to 2.7 V
–40°C ≤ TA ≤ +85°C
RL = 100 kΩ to GND,
–40°C ≤ TA ≤ +85°C
RL = 100 kΩ to V+,
–40°C ≤ TA ≤ +85°C
VS = 2.7 V to 12 V
–40°C ≤ TA ≤ +85°C
VO = 0 V
–40°C ≤ TA ≤ +85°C
65
5
2
2.925
Units
1.5
2.5
10
7
2
mV
mV
nA
nA
V
95
13
10
20
2
dB
V/mV
V/mV
µV/°C
pA/°C
pA/°C
2.96
V
25
± 1.1
76
Max
95
3
75
4
5
mV
mA
dB
µA
µA
RL = 100 kΩ, CL = 50 pF
AV = 1, VO = 1
AV = 20, VO = 1
25
40
50
65
95
70
V/ms
µs
µs
µs
kHz
Degrees
0.1 Hz to 10 Hz
f = 1 kHz
10
75
<1
µV p-p
nV/√Hz
pA/√Hz
NOTES
1
VOS is tested under no load condition.
Specifications subject to change without notice.
–2–
REV. 0
OP181/OP281/OP481
ELECTRICAL SPECIFICATIONS (@ V = +5.0 V, V
S
CM
= 2.5 V, TA = +258C unless otherwise noted1)
Parameter
Symbol
Conditions
INPUT CHARACTERISTICS
Offset Voltage
VOS
Note 1
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
∆VOS/∆T
∆IB/∆T
∆IOS/∆T
OUTPUT CHARACTERISTICS
Output Voltage High
IB
IOS
VOH
VOL
Short Circuit Limit
ISC
Supply Current/Amplifier
PSRR
ISY
DYNAMIC PERFORMANCE
Slew Rate
Saturation Recovery Time
Gain Bandwidth Product
Phase Margin
GBP
φo
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
SR
VCM = 0 V to 4.0 V,
–40°C ≤ TA ≤ +85°C
RL = 1 MΩ , VO = 0.5 V to 4.5 V
–40°C ≤ TA ≤ +85°C
–40°C to +85°C
RL = 100 kΩ to GND,
–40°C ≤ TA ≤ +85°C
RL = 100 kΩ to V+,
–40°C ≤ TA ≤ +85°C
VS = 2.7 V to 12 V,
–40°C ≤ TA ≤ +85°C
VO = 0 V
–40°C ≤ TA ≤ +85°C
Max
Units
0.1
1.5
2.5
10
7
4
mV
mV
nA
nA
V
3
0.1
65
5
2
4.925
90
15
10
20
2
dB
V/mV
V/mV
µV/°C
pA/°C
pA/°C
4.96
V
25
± 3.5
76
95
3.2
75
4
5
mV
mA
dB
µA
µA
RL = 100 kΩ, CL = 50 pF
27
120
100
74
V/ms
µs
kHz
Degrees
0.1 Hz to 10 Hz
f = 1 kHz
10
75
<1
µV p-p
nV/√Hz
pA/√Hz
NOTES
1
VOS is tested under a no load condition.
Specifications subject to change without notice.
REV. 0
Typ
0
Output Voltage Low
POWER SUPPLY
Power Supply Rejection Ratio
Min
–3–
OP181/OP281/OP481–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = ±5 V, T = +258C unless otherwise noted)
S
A
Parameter
Symbol
Conditions
INPUT CHARACTERISTICS
Offset Voltage
VOS
Note 1
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection
IB
IOS
Large Signal Voltage Gain
AVO
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
∆VOS/∆T
∆IB/∆T
∆IOS/∆T
OUTPUT CHARACTERISTICS
Output Voltage Swing
Short Circuit Limit
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
Min
Typ
Max
Units
0.1
1.5
2.5
10
7
+4
mV
mV
nA
nA
V
3
0.1
–5
CMRR
VO
VCM = –5.0 V to +4.0 V,
–40°C ≤ TA ≤ +85°C
RL = 1 MΩ, VO = ± 4.0 V,
–40°C ≤ TA ≤ +85°C
–40°C to +85°C
65
5
2
RL = 100 kΩ to GND,
–40°C ≤ TA ≤ +85°C
VS = ± 1.35 V to ± 6 V,
–40°C ≤ TA ≤ +85°C
VO = 0 V
–40°C ≤ TA ≤ +85°C
10
20
2
dB
V/mV
V/mV
µV/°C
pA/°C
pA/°C
± 4.925
± 4.98
12
V
mA
76
95
3.3
ISC
PSRR
ISY
95
13
5
6
dB
µA
µA
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
± SR
GBP
φo
RL = 100 kΩ, CL = 50 pF
28
105
75
V/ms
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Voltage Noise Density
Current Noise Density
en p-p
en
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
10
85
75
<1
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
NOTES
1
VOS is tested under no load condition.
Specifications subject to change without notice.
–4–
REV. 0
OP181/OP281/OP481
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . Gnd to VS + 10 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 3.5 V
Output Short-Circuit Duration to Gnd . . . . . . . . . . Indefinite
Storage Temperature Range
P, S, RU Package . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP181/OP281/OP481G . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S, RU Package . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
Package Type
uJA*
uJC
Units
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
8-Pin TSSOP (RU)
14-Pin Plastic DIP (P)
14-Pin SOIC (S)
14-Pin TSSOP (RU)
103
158
240
76
120
240
43
43
43
33
36
43
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Model
Temperature
Range
Package
Description
Package
Option
OP181GP
OP181GS
OP281GP
OP281GS
OP281GRU
OP481GP
OP481GS
OP481GRU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Pin Plastic DIP
8-Pin SOIC
8-Pin Plastic DIP
8-Pin SOIC
8-Pin TSSOP
14-Pin Plastic DIP
14-Pin SOIC
14-Pin TSSOP
N-8
SO-8
N-8
SO-8
RU-8
N-14
SO-14
RU-14
*θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket
for P-DIP packages; θJA is specified for device soldered in circuit board for TSSOP
and SOIC packages.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP181/OP281/OP481 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–
WARNING!
ESD SENSITIVE DEVICE
OP181/OP281/OP481–Typical Characteristics
50
VS = +2.7V
TA = +258C
30
25
20
15
10
35
30
25
20
15
10
5
5
0
0
0
0.2 0.4 0.6 0.8 1.0
–1.0 –0.8 –0.6 –0.4 –0.2
Figure 1. Input Offset Voltage
Distribution
0
1200
1000
800
600
400
0
–40 –20
0.2 0.4 0.6 0.8 1.0
Figure 2. Input Offset Voltage
Distribution
0
1.0
–0.5
0.5
VS = +5V
–1.0
INPUT BIAS CURRENT – nA
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
0.4
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
VS = +5V
0.3
0.2
0.1
0
–0.1
–0.2
–3.0
–0.3
–5.0
–40 –20
–3.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
COMMON-MODE VOLTAGE – Volts
–0.4
–40
20 40 60 80 100 120
TEMPERATURE – 8C
Figure 4. Input Bias Current vs.
Temperature
Figure 5. Input Bias Current vs.
Common-Mode Voltage
10,000
1,000
OUTPUT VOLTAGE – mV
100
SOURCE
SINK
10
1.0
0.1
1
10
100
LOAD CURRENT – µA
1000
Figure 7. Output Voltage to Supply
Rail vs. Load Current
SOURCE
10
SINK
1.0
0.1
1
10
100
LOAD CURRENT – µA
1000
Figure 8. Output Voltage to Supply
Rail vs. Load Current
–6–
0
20 40 60 80 100 120
TEMPERATURE – 8C
VS = ±5V
TA = +258C
VS = +5V
TA = +258C
100
–20
Figure 6. Input Offset Current vs.
Temperature
1,000
VS = +3V
TA = +258C
1,000
20 40 60 80 100 120
TEMPERATURE – 8C
0.5
VS = +5V
TA = +258C
–4.5
0
0
Figure 3. Input Offset Voltage vs.
Temperature
OUTPUT VOLTAGE – mV
INPUT BIAS CURRENT – nA
1400
INPUT OFFSET VOLTAGE – mV
INPUT OFFSET CURRENT – nA
–1.0 –0.8 –0.6 –0.4 –0.2
VS = +5V
1600
200
INPUT OFFSET VOLTAGE – mV
OUTPUT VOLTAGE – mV
1800
40
35
QUANTITY – Amplifiers
QUANTITY – Amplifiers
2000
VS = +5V
TA = +258C
45
INPUT OFFSET VOLTAGE – µV
45
40
100
SOURCE
10
SINK
1.0
0.1
1
10
100
LOAD CURRENT – µA
1000
Figure 9. Output Voltage to Supply
Rail vs. Load Current
REV. 0
OP181/OP281/OP481
70
30
45
20
90
10
135
0
180
–10
225
–20
270
–30
100
1k
10k
100k
FREQUENCY – Hz
1M
Figure 10. Open-Loop Gain and Phase
vs. Frequency
0
30
45
20
90
10
135
0
180
–10
225
–20
270
10k
100k
FREQUENCY – Hz
1M
40
0
30
45
20
90
10
135
0
180
–10
225
–20
270
–30
100
1k
1M
10k
100k
FREQUENCY – Hz
Figure 12. Open-Loop Gain and Phase
vs. Frequency
60
30
45
20
90
10
135
0
180
–10
225
–20
270
–30
100
1k
10k
100k
FREQUENCY – Hz
90
VS = ±5V
10
0
–10
–20
160
TA = +258C
VS = +5V
120
1M
PSRR – dB
VS = +3V
80
60
40
20
20
10
0
0
–20
10k
100k
1M
FREQUENCY – Hz
10M
Figure 16. CMRR vs. Frequency
–40
10
0
2k
4k
6k
FREQUENCY – Hz
8k
10k
Figure 15. Voltage Noise Density vs.
Frequency
50
100
30
REV. 0
1k
10k
100k
FREQUENCY – Hz
VS = ±5V, +5V, +3V, +2.7V
TA = +258C
RL = INFINITE
140
40
–10
1k
100
Figure 14. Closed-Loop Gain vs.
Frequency
60
50
MARKER @ 67nV/√Hz
20
–40
10
80
70
VS = +5V
TA = +258C
30
–30
1M
Figure 13. Open-Loop Gain and Phase
vs. Frequency
40
50nV/√Hz/Div
0
CLOSED-LOOP GAIN – dB
40
PHASE SHIFT – Degrees
50
VS = +5V
TA = +258C
RL = INFINITE
50
SMALL SIGNAL OVERSHOOT – %
VS = ±5V
TA = +258C
RL = 100kΩ TO GROUND
60
OPEN-LOOP GAIN – dB
1k
Figure 11. Open-Loop Gain and Phase
vs. Frequency
70
CMRR – dB
50
40
–30
100
VS = +2.7V
TA = +258C
RL = 100kΩ
60
PHASE SHIFT – Degrees
0
OPEN-LOOP GAIN – dB
50
40
PHASE SHIFT – Degrees
OPEN-LOOP GAIN – dB
50
70
VS = +3V
TA = +258C
RL = 100kΩ
60
OPEN-LOOP GAIN – dB
VS = +5V
TA = +258C
RL = 100kΩ
60
PHASE SHIFT – Degrees
70
45
40
VS = +5V
VIN = ±50mV
RL = 100kΩ
TA = +258C
–OS
35
+OS
30
25
20
15
10
5
100
1k
10k
100k
FREQUENCY – Hz
1M
Figure 17. PSRR vs. Frequency
–7–
0
10
100
CAPACITANCE – pF
1000
Figure 18. Small Signal Overshoot vs.
Load Capacitance
OP181/OP281/OP481
3
4
VS = +5V
VIN = 4Vp–p
RL = INFINITE
TA = +258C
3
2
1
0
10
100
1k
10k
FREQUENCY – Hz
SUPPLY CURRENT/AMPLIFIER – µA
SUPPLY CURRENT/AMPLIFIER – µA
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–40 –20
0
20 40 60 80 100 120
TEMPERATURE – 8C
Figure 22. Supply Current/Amplifier
vs. Temperature
A2
100
90
0mV
VS = ±1.35V
AV = 1
RL = 100kΩ
CL = 50pF
TA = +258C
1
100
1k
10k
FREQUENCY – Hz
3.50
3.25
VS = +3V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–40 –20
100k
Figure 20. Maximum Output Swing
vs. Frequency
4.5
VS = +5V
2
0
10
100k
Figure 19. Maximum Output Swing
vs. Frequency
4.0
VS = +3V
VIN = 2Vp–p
RL = INFINITE
TA = +258C
SUPPLY CURRENT/AMPLIFIER – µA
MAXIMUM OUTPUT SWING – Vp-p
MAXIMUM OUTPUT SWING – Vp-p
5
TA = +258C
A2
2.75
2.50
2.25
90
2.00
1.75
1.50
1.25
1.00
Figure 23. Supply Current/Amplifier
vs. Supply Voltage
VS = +5V
AV = 1
RL = 100kΩ
CL = 50pF
TA = +258C
2.50V
100
90
0%
50mV
A2
100
90
10
10
0%
1V
100µs
Figure 26. Large Signal Transient
Response
–8–
100µs
Figure 24. Small Signal Transient
Response
0%
Figure 25. Small Signal Transient
Response
VS = ±2.5V
AV = 1
RL = 100kΩ
CL = 50pF
TA = +258C
10
0.75
0.50
0.25
0.00
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE – ±Volts
10
100µs
0mV
100
0%
50mV
20 40 60 80 100 120
TEMPERATURE – 8C
Figure 21. Supply Current/Amplifier
vs. Temperature
3.00
A2
0
500mV
0.50V
VS = +2.7V
AV = 1
RL = 100kΩ
CL = 50pF
TA = +258C
100µs
Figure 27. Large Signal Transient
Response
REV. 0
OP181/OP281/OP481
120
2.50V
VS = +5V
TA = +258C
100
90
10
0%
1V
1V
200µs
CHANNEL SEPARATION – dB
105
A2
VS = +5V
TA = +258C
RL = ∞
90
75
VS = 61.35V
RL = ∞
VIN = 61Vp-p
AT 2kHz
100
90
45
30
15
10
0
0%
500mV
–15
1k
10k
100k
FREQUENCY – Hz
0.00V
VS = 62.5V
CIRCUIT = AVOL
RL = ∞
TA = +258C
100
90
10
0%
1V
500mV
100µs
Figure 31. Saturation Recovery Time
–9–
500mV
50µs
1M
Figure 29. Channel Separation vs.
Frequency
A2
REV. 0
0.00V
60
–30
100
Figure 28. No Phase Reversal
A2
Figure 30. Saturation Recovery Time
OP181/OP281/OP481
APPLICATIONS
where: VEE is the negative power supply for the amplifier, and
THEORY OF OPERATION
VIN, MIN is the lowest input voltage excursion expected
The OPx81 family of op amps is comprised of extremely low
powered, rail-to-rail output amplifiers, requiring less than 4 µA
of quiescent current per amplifier. Many other competitors’
devices may be advertised as low supply current amplifiers but
draw significantly more current as the outputs of these devices
are driven to a supply rail. The OPx81’s supply current remains
under 4 µA even with the output driven to either supply rail.
Supply currents should meet the specification as long as the inputs
and outputs remain within the range of the power supplies.
For example, an OP181 is to be used with a single supply voltage of 5 V where the input signal could possibly go as low as
–1.0 V. Because the amplifier is powered from a single supply,
VEE is ground, so the necessary series resistance should be 2 kΩ.
Input Offset Voltage Nulling
Figure 32 shows a simplified schematic of the OP181. A bipolar
differential pair is used in the input stage. PNP transistors are
used to allow the input stage to remain linear with the commonmode range extending to ground. This is an important consideration for single supply applications. The bipolar front end also
contributes less noise than a MOS front end with only nanoamps of bias currents. The output of the op amp consists of a
pair of CMOS transistors in a common source configuration.
This setup allows the output of the amplifier to swing to within
millivolts of either supply rail. The headroom required by the
output stage is limited by the amount of current being driven
into the load. The lower the output current, the closer the
output can go to either supply rail. Figures 7, 8 and 9 show the
output voltage headroom versus load current. This behavior is
typical of rail-to-rail output amplifiers.
The OPx81 family of op amps was designed for low offset
voltages less than 1 mV. The single OP181 does provide two
offset adjust terminals, should the user require greater precision.
In general, these terminals should be used only to zero amplifier
offsets and should not be used to adjust system offset voltages.
A 20 kΩ potentiometer connected to the offset adjust terminals,
with the wiper connected to VEE, can be used to reduce the
offset voltage of the amplifier. The OP181 should be connected
in the unity-gain configuration (as shown in Figure 33) or in a
gain configuration. The potentiometer should be adjusted until
VOUT is minimized. The wiper of the potentiometer must be
connected to VEE; connecting it to the positive supply rail could
damage the device.
+5V
7
2
OP181
6
VOUT
4
VCC
3
5
1
20kΩ
POT.
VEE = –5V
OUT
Figure 33. Offset Voltage Nulling Circuit
+IN
Input Common-Mode Voltage Range
–IN
VEE
Figure 32. Simplified Schematic of the OP181
Input Overvoltage Protection
The input stage to the OPx81 family of op amps consists of a
PNP differential pair. If the base voltage of either of these input
transistors drops to more than 0.6 V below the negative supply,
the input ESD protection diodes will become forward biased,
and large currents will begin to flow. In addition to possibly
damaging the device, this will create a phase reversal effect at
the output. To prevent these effects from happening, the input
current should be limited to less than 0.5 mA.
This can be done quite easily by placing a resistor in series with
the input to the device. The size of the resistor should be proportional to the lowest possible input signal excursion and can
be found using the following formula:
R=
VEE − VIN , MIN
0.5 × 10 −3
The OPx81 is rated with an input common-mode voltage range
from VEE to 1 volt under VCC. However, the op amp can still
operate even with a common-mode voltage that is slightly less
than VEE. Figure 34 shows an OP181 configured as a difference
amplifier with a single supply voltage of +3 V. Negative dc
voltages are applied at both input terminals creating a commonmode voltage that is less than ground. A 400 mV p-p input
signal is then applied to the noninverting input. Figure 35 shows
a picture of the input and output waves. Notice how the output
of the amplifier also drops slightly negative without distortion.
100kΩ
+3V
100kΩ
VOUT
100kΩ
–0.27V
OP181
VIN = 1kHz AT
400mV p-p
100kΩ
–0.1V
Figure 34. OP181 Configured as a Difference Amplifier
Operating at VCM < 0 V
–10–
REV. 0
OP181/OP281/OP481
0.2ms
VOUT
100
100
90
90
0V
VIN
10
10
0%
0%
0.1V
Figure 35. Input and Output Signals with VCM < 0 V
Overdrive Recovery Time
The amount of time it takes for an amplifier to recover from
saturation can be an important consideration when using an
amplifier as a comparator or when outputs can be driven to the
supplies. The overdrive recovery time for the OP181 is 50 µs
with the amplifier running from a 3 volt supply and increases
to 100 µs with a 10 volt supply. Figure 36 shows the result of
the OP181 running from a 3 V supply with its output being
overdriven.
0.2ms
VIN
SCALE 0.1V
100
90
VS = +3V
AV = +100
0V
Figure 37. Ringing and Overshoot of the Output of the
Amplifier
A Micropower Reference Voltage Generator
Many single supply circuits are configured with the circuit
biased to 1/2 of the supply voltage. In these cases, a falseground reference can be created by using a voltage divider
buffered by an amplifier. Figure 38 shows the schematic for
such a circuit.
The two 1 MΩ resistors generate the reference voltage while
drawing only 1.5 µA of current from a 3 V supply. A capacitor
connected from the inverting terminal to the output of the op
amp provides compensation to allow for a bypass capacitor to be
connected at the reference output. This bypass capacitor helps
establish an ac ground for the reference output. The entire
reference generator draws less than 5 µA from a 3 V supply
source.
VOUT
SCALE 1V
+3V TO +12V
10
0%
0V
10kΩ
0.1V
0.022µF
Figure 36. Output of the Op Amp Recovering from
Saturation
Most low supply current amplifiers have difficulty driving
capacitive loads due to the higher currents required from the
output stage for such loads. Higher capacitance at the output
will increase the amount of overshoot and ringing in the
amplifier’s step response and could even affect the stability of
the device. However, through careful design of the output stage
and its high phase margin, the OPx81 family can tolerate some
degree of capacitive loading. Figure 37 shows the step response
of an OP181 with a 10 nF capacitor connected at the output.
Notice that the overshoot of the output does not exceed more
than 10% with such a load, even with a supply voltage of only
+3 V.
REV. 0
7
2
Capacitive Loading
1MΩ
OP181
3
4
100Ω
6
1µF
VREF
+1.5V TO +6V
1MΩ
1µF
Figure 38. A Micropower Bias Voltage Generator
A Window Comparator
The extremely low power supply current demands of the OPx81
family make it ideal for use in long life battery powered applications such as a monitoring system. Figure 39 shows a circuit
that uses the OP281 as a window comparator.
–11–
OP181/OP281/OP481
+3V
+3V
+3V
R1
VH
5.1kΩ
D1
VOUT
10kΩ
Q1
A1
R2
creates a very small voltage drop. The voltage at the inverting
terminal becomes equal to the voltage at the noninverting
terminal through the feedback of Q1, which is a 2N2222 or
equivalent NPN transistor. This makes the voltage drop across
R1 equal to the voltage drop across RSENSE. Therefore, the
current through Q1 becomes directly proportional to the current
through RSENSE, and the output voltage is given by:
OP281-A
5.1kΩ
VIN
2kΩ
R3
 R2

VOUT = VEE − 
× RSENSE × I L 
 R1

+3V
+3V
D2
VL
The voltage drop across R2 increases with IL increasing, so
VOUT decreases with higher supply current being sensed. For
the element values shown, the VOUT transfer characteristic is
–2.5 V/A, decreasing from VEE.
A2
OP281-B
R4
+5V
Figure 39. Using the OP281 as a Window Comparator
The threshold limits for the window are set by VH and VL,
provided that VH > VL. The output of A1 will stay at the
negative rail, in this case ground, as long as the input voltage is
less than VH. Similarly, the output of A2 will stay at ground as
long the input voltage is higher than VL. As long as VIN remains
between VL and VH, the outputs of both op amps will be 0 V.
With no current flowing in either D1 or D2, the base of Q1 will
stay at ground, putting the transistor in cutoff and forcing VOUT
to the positive supply rail. If the input voltage rises above VH,
the output of A2 stays at ground, but the output of A1 will go to
the positive rail, and D1 will conduct current. This creates a
base voltage that will turn on Q1 and drive VOUT low. The same
condition occurs if VIN falls below VL with A2’s output going
high, and D2 conducting current. Therefore, VOUT will be high
if the input voltage is between VL and VH, and VOUT will be low
if the input voltage moves outside of that range.
The R1 and R2 voltage divider sets the upper window voltage,
and the R3 and R4 voltage divider sets the lower voltage for the
window. For the window comparator to function properly, VH
must be a greater voltage than VL.
R2
2.49kΩ
VOUT
Q1
+5V
R1
100Ω
OP181
0.1Ω
RETURN TO
GROUND
RSENSE
Figure 40. A Low-Side Load Current Monitor
Low Voltage Half-Wave and Full-Wave Rectifiers
Because of its quick overdrive recovery time, an OP281 can be
configured as a full-wave rectifier for low frequency (<500 Hz)
applications. Figure 41 shows the schematic.
R1 = 100kΩ
R2 = 100kΩ
+3V
+3V
VH =
R2
R1 + R2
2kΩ
A2
VIN = 2V p-p
A1
OP281-A
VL =
R4
R3 + R4
OP281-B
FULL-WAVE
RECTIFIED
OUTPUT
HALF-WAVE
RECTIFIED
OUTPUT
The 2 kΩ resistor connects the input voltage to the input terminals to the op amps. This protects the OP281 from possible
excess current flowing into the input stages of the devices. D1
and D2 are small-signal switching diodes (1N4446 or equivalent), and Q1 is a 2N2222 or equivalent NPN transistor.
Figure 41. Single Supply Full- and Half-Wave Rectifiers
Using an OP281
A Low-Side Current Monitor
In the design of power supply control circuits, a great deal of
design effort is focused on ensuring a pass transistor’s long-term
reliability over a wide range of load current conditions. As a
result, monitoring and limiting device power dissipation is of
prime importance in these designs. Figure 40 shows an example
of a +5 V, single-supply current monitor that can be incorporated into the design of a voltage regulator with fold-back
current limiting or a high current power supply with crowbar
protection. The design capitalizes on the OP181’s commonmode range that extends to ground. Current is monitored in the
power supply return path where a 0.1 Ω shunt resistor, RSENSE,
–12–
100
90
10
0%
SCALE 0.1V/DIV
SCALE 0.1ms/DIV
Figure 42. Full-Wave Rectified Signal
REV. 0
OP181/OP281/OP481
Amplifier A1 is used as a voltage follower that will only track the
input voltage when it is greater than 0 V. This provides a halfwave rectification of the input signal to the noninverting
terminal of amplifier A2. When A1’s output is following the
input, the inverting terminal of A2 will also follow the input
from the virtual ground between the inverting and noninverting
terminals of A2. With no potential difference across R1, no
current flows through either R1 or R2, therefore the output of
A2 will also follow the input. Now, when the input voltage goes
below 0 V, the noninverting terminal of A2 becomes 0 V. This
makes A2 work as an inverting amplifier with a gain of 1 and
provides a full-wave rectified version of the input signal. A 2 kΩ
resistor in series with A1’s noninverting input protects the
device when the input signal becomes less than ground.
A Battery Powered Telephone Headset Amplifier
Figure 43 shows how the OP281 can be used as a two-way
amplifier in a telephone headset. One side of the OP281 can be
used as an amplifier for the microphone, while the other side
can be used to drive the speaker. A typical telephone headset
uses a 600 Ω speaker and an electret microphone that requires a
supply voltage and a biasing resistor.
0.1µF
+3V
11kΩ
300kΩ
+3V
2.2kΩ
1µF
+3V
1µF
1MΩ
MIC OUT
OP281-A
ELECTRET 1MΩ
MIC
1µF 10kΩ
50kΩ
+3V
20kΩ
+3V
Q1
INPUT 1µF
1µF
+3V
10kΩ
POT.
OP281-B
Q2
1MΩ
1µF
1MΩ
20kΩ
600Ω
SPEAKER
Figure 43. A Battery Powered Telephone Headset
Two-Way Amplifier
The OP281-A op amp provides about 29 dB of gain for audio
signals coming from the microphone. The gain is set by the
300 kΩ and 11 kΩ resistors. The gain bandwidth product of the
amplifier is 95 kHz, which, for the set gain of 28, yields a –3 dB
rolloff at 3.4 kHz. This is acceptable since telephone audio is
band limited for 300 kHz to 3 kHz signals. If higher gain is
required for the microphone, an additional gain stage should be
used, as adding any more gain to the OP281 would limit the
audio bandwidth. A 2.2 kΩ resistor is used to bias the electret
microphone. This resistor value may vary depending on the
specifications on the microphone being used. The output of the
microphone is ac coupled to the noninverting terminal of the op
amp. Two 1 MΩ resistors are used to provide the dc offset for
single supply use.
REV. 0
The OP281-B amplifier can provide up to 15 dB of gain for the
headset speaker. Incoming audio signals are ac coupled to a
10 kΩ potentiometer that is used to adjust the volume. Again,
two 1 MΩ resistors provide the dc offset with a 1 µF capacitor
establishing an ac ground for the volume control potentiometer.
Because the OP281 is a rail-to-rail output amplifier, it would
have difficulty driving a 600 Ω speaker directly. Here, a class AB
buffer is used to isolate the load from the amplifier and also
provide the necessary current drive to the speaker. By placing
the buffer in the feedback loop of the op amp, crossover
distortion can be minimized. Q1 and Q2 should have minimum
betas of 100. The 600 Ω speaker is ac coupled to the emitters to
prevent any quiescent current from flowing in the speaker. The
1 µF coupling capacitor makes an equivalent high pass filter
cutoff at 265 Hz with a 600 Ω load attached. Again, this does
not pose a problem, as it is outside the frequency range for
telephone audio signals.
The circuit in Figure 43 draws around 250 µA of current. The
class AB buffer has a quiescent current of 140 µA while roughly
100 µA is drawn by the microphone itself. A CR2032 3 V
lithium battery has a life expectancy of 160 mA hours, which
means this circuit could run continuously for 640 hours on a
single battery.
SPICE Macro-Model
* OP181 SPICE Macro-model
* 9/96, Ver. 1
*
* Copyright 1996 by Analog Devices
*
* Refer to “README.DOC” file for License Statement. Use of this
* model indicates your acceptance of the terms and provisions in
* the License Statement.
*
* Node Assignments
*
noninverting input
*
|
inverting input
*
|
|
positive supply
*
|
|
|
negative supply
*
|
|
|
|
output
*
|
|
|
|
|
*
|
|
|
|
|
.SUBCKT OP181
1
2
99
50
45
*
* INPUT STAGE
*
Q1
4
1 3
PIX
Q2
6
7 5
PIX
I1
99
8 1.28E-6
EOS 7
2 POLY(1) (12, 98) 80E-6 1
IOS
1
2 1E-10
RC1 4 50 500E3
RC2 6 50 500E3
RE1
3
8 108
RE2
5
8 108
V1
99 13 DC .9
V2
99 14 DC .9
D1
3 13 DX
D2
5 14 DX
*
* CMRR 76dB, ZERO AT 1kHz
*
–13–
OP181/OP281/OP481
ECM1 11 98 POLY(2) (1, 98) (2, 98) 0 .5 .5
R1
11 12 1.59E6
C1
11 12 100E-12
R2
12 98 283
*
* POLE AT 900kHz
*
EREF 98 0 (90, 0)
1
G1
98 20 (4, 6)
1E-6
R3
20 98 1E6
C2
20 98 177E-15
*
* POLE AT 500kHz
*
E2
21 98 (20, 98)
1
R4
21 22 1E6
C3
22 98 320E-15
*
* GAIN STAGE
*
CF
45 40 8. 5E-12
R5
40 98 65. 65E6
G3
98 40 (22, 98)
4.08E-7
D3
40 41 DX
D4
42 40 DX
V3
99 41 DC 0.5
V4
42 50 DC 0.5
*
* OUTPUT STAGE
*
ISY 99 50 1.375E-6
RS1 99 90 10E6
RS2 90 50 10E6
M1 45 46 99 99
POX L=1.5u W=300u
M2 45 47 50 50
NOX L=1.5u W=300u
EG1 99 46 POLY(1) (98, 40) 0.77 1
EG2 47 50 POLY(1) (40, 98) 0.77 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2, KP=25E-6, VTO=-0.75, LAMBDA=0.01)
.MODEL NOX NMOS (LEVEL=2, KP=25E-6, VTO=0.75, LAMBDA=0.01)
.MODEL PIX PNP (BF=200)
.MODEL DX D(IS=1E-14)
.ENDS
–14–
REV. 0
OP181/OP281/OP481
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Plastic DIP
(N-14)
8-Lead Plastic DIP
(N-8)
0.795 (20.19)
0.725 (18.42)
0.430 (10.92)
0.348 (8.84)
8
5
14
8
1
7
0.280 (7.11)
0.240 (6.10)
1
4
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.325 (8.25)
0.300 (7.62)
0.160 (4.06)
0.115 (2.93)
0.210 (5.33)
MAX
5
1
4
PIN 1
SEATING
PLANE
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
0.0500 0.0192 (0.49)
(1.27) 0.0138 (0.35)
BSC
8°
0°
8
1
7
0.0098 (0.25)
0.0040 (0.10)
0.0500
(1.27)
BSC
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
REV. 0
8°
0°
0.0500 (1.27)
0.0160 (0.41)
8
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
5
1
4
PIN 1
SEATING
PLANE
0.0099 (0.25)
0.0075 (0.19)
0.201 (5.10)
0.193 (4.90)
14
0.006 (0.15)
0.002 (0.05)
0.0192 (0.49)
0.0138 (0.35)
0.0196 (0.50)
x 45°
0.0099 (0.25)
14-Lead TSSOP
(RU-14)
0.122 (3.10)
0.114 (2.90)
1
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
x 45°
0.0099 (0.25)
0.0098 (0.25)
0.0075 (0.19)
14
8-Lead TSSOP
(RU-8)
8
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.3444 (8.75)
0.3367 (8.55)
0.1968 (5.00)
0.1890 (4.80)
8
0.100 0.070 (1.77)
(2.54) 0.045 (1.15)
BSC
14-Lead Narrow Body SOIC
(SO-14)
8-Lead SOIC
(SO-8)
0.1574 (4.00)
0.1497 (3.80)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.022 (0.558) 0.100 0.070 (1.77)
0.014 (0.356) (2.54) 0.045 (1.15)
BSC
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.280 (7.11)
0.240 (6.10)
7
PIN 1
0.0256 (0.65)
BSC
0.0433
(1.10)
MAX
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
0.006 (0.15)
0.002 (0.05)
8°
0°
0.028 (0.70)
0.020 (0.50)
SEATING
PLANE
–15–
0.0433
(1.10)
MAX
0.0256
(0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8°
0°
0.028 (0.70)
0.020 (0.50)
–16–
PRINTED IN U.S.A.
C2195–12–10/96