AD OP282GS Dual/quad low power, high speed jfet operational amplifier Datasheet

a
FEATURES
High Slew Rate: 9 V/ms
Wide Bandwidth: 4 MHz
Low Supply Current: 250 mA/Amplifier
Low Offset Voltage: 3 mV
Low Bias Current: 100 pA
Fast Settling Time
Common-Mode Range Includes V+
Unity Gain Stable
APPLICATIONS
Active Filters
Fast Amplifiers
Integrators
Supply Current Monitoring
GENERAL DESCRIPTION
The OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. Slew rate
exceeds 7 V/µs with supply current under 250 µA per amplifier.
These unity gain stable amplifiers have a typical gain bandwidth
of 4 MHz.
Dual/Quad Low Power, High Speed
JFET Operational Amplifiers
OP282/OP482
PIN CONNECTIONS
8-Lead Narrow-Body SOIC
8-Lead Epoxy DIP
(S Suffix)
(P Suffix)
–IN A
2
+IN A
3
V–
4
OUT A 1
8 V+
OUT A 1
OP282
OP282
8 V+
7 OUT B
–IN A
2
7
6 –IN B
+IN A
3
6 –IN B
5 +IN B
V–
4
14-Lead Epoxy DIP
(P Suffix)
OP-482
OUT B
5 +IN B
14-Lead Narrow-Body SOIC
(S Suffix)
OUT A
1
14 OUT D
OUT A
1
–IN A
2
13 –IN D
–IN A
2
13
–IN D
+IN A
3
12 +IN D
+IN A
3
12
+IN D
V+
4
V+
4
11
V–
+IN B
5
10 +IN C
+IN B
5
10 +IN C
–IN B
6
9
–IN C
–IN B
6
9
–IN C
8
OUT C
OUT B
7
8
OUT C
OUT B
7
OP482
11 V–
14 OUT B
OP482
The JFET input stage of the OP282/OP482 insures bias current
is typically a few picoamps and below 500 pA over the full
temperature range. Offset voltage is under 3 mV for the dual
and under 4 mV for the quad.
With a wide output swing, within 1.5 volts of each supply, low
power consumption and high slew rate, the OP282/OP482 are
ideal for battery-powered systems or power restricted applications. An input common-mode range that includes the positive
supply makes the OP282/OP482 an excellent choice for highside signal conditioning.
The OP282/OP482 are specified over the extended industrial
temperature range. Both dual and quad amplifiers are available
in plastic and ceramic DIP plus SOIC surface mount packages.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
OP282/OP482–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 615.0 V, T
S
A
= +258C unless otherwise noted)
Parameter
Symbol
Conditions
INPUT CHARACTERISTICS
Offset Voltage
VOS
OP282
OP282, –40 ≤ TA ≤ +85°C
OP482
OP482, –40 ≤ TA ≤ +85°C
VCM = 0 V
VCM = 0 V, Note 1
VCM = 0 V
VCM = 0 V, Note 1
Offset Voltage
VOS
Input Bias Current
IB
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection
Large Signal Voltage Gain
CMR
AVO
Offset Voltage Drift
Bias Current Drift
∆VOS/∆T
∆IB/∆T
OUTPUT CHARACTERISTICS
Output Voltage Swing
Short Circuit Limit
–11 V ≤ VCM ≤ +15 V, –40 ≤ TA ≤ +85°C
RL = 10 kΩ
RL = 10 kΩ, –40 ≤ TA ≤ +85°C
VO
ISC
Open-Loop Output Impedance
RL = 10 kΩ
Source
Sink
f = 1 MHz
ZOUT
POWER SUPPLY
Power Supply Rejection Ratio
VS = ± 4.5 V to ± 18 V,
–40 ≤ TA ≤ +85°C
VO = 0 V, 40 ≤ TA ≤ +85°C
PSRR
Supply Current/Amplifier
Supply Voltage Range
ISY
VS
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
SR
BWP
tS
GBP
ØO
RL = 10 kΩ
1% Distortion
To 0.01%
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
Min
Typ
Max
Units
0.2
3
4.5
4
6
100
500
50
250
+15
10
8
mV
mV
mV
mV
pA
pA
pA
pA
V
dB
V/mV
V/mV
µV/°C
pA/°C
± 13.9 13.5
10
–12
200
V
mA
mA
Ω
25
210
µV/V
µA
V
0.2
3
1
–11
70
20
15
–13.5
3
–8
± 4.5
7
90
316
250
± 18
9
125
1.6
4
55
V/µs
kHz
µs
MHz
Degrees
1.3
36
0.01
µV p-p
nV/√Hz
pA/√Hz
NOTE
1
The input bias and offset currents are tested at TA = TJ = +85°C. Bias and offset currents are guaranteed but not tested at –40 °C.
Specifications subject to change without notice.
WAFER TEST LIMITS (@ V = 615.0 V, T = +258C unless otherwise noted)
S
A
Parameter
Symbol
Conditions
Limit
Units
Offset Voltage
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range 1
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Range
Supply Current/Amplifier
VOS
VOS
IB
IOS
OP282
OP482
VCM = 0 V
VCM = 0 V
CMRR
PSRR
AVO
VO
ISY
–11 V ≤ VCM ≤ +15 V
V = ± 4.5 V to ± 18 V
RL = 10 kΩ
RL = 10 kΩ
VO = 0 V, RL = ∞
3
4
100
50
–11, +15
70
316
20
± 13.5
250
mV max
mV max
pA max
pA max
V min/max
dB min
µV/V
V/mV min
V min
µA max
NOTES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
1
Guaranteed by CMR test.
Specifications subject to change without notice.
–2–
REV. B
OP282/OP482
DICE CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Differential Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . 36 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP282A, OP482A . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP282G, OP482G . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . +300°C
Package Type
uJA2
uJC
Units
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
14-Pin Plastic DIP (P)
14-Pin SOIC (S)
103
158
83
120
43
43
39
36
°C/W
°C/W
°C/W
°C/W
OP282 Die Size 0.063 3 0.060 Inch, 3,780 Sq. Mils
NOTES
1
For supply voltages less than ± 18 V, the absolute maximum input voltage is
equal to the supply voltage.
2
θJA is specified for the worst case conditions, i.e., θJA is specified for device in
socket for cerdip, P-DIP; θJA is specified for device soldered in circuit board for
SOIC package.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
OP282GP
OP282GS
OP482GP
OP482GS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Pin Plastic DIP
8-Pin SOIC
14-Pin Plastic DIP
14-Pin SOIC
N-8
SO-8
N-14
SO-14
OP482 Die Size 0.070 3 0.098 Inch, 6,860 Sq. Mils
REV. B
–3–
OP282/OP482
APPLICATIONS INFORMATION
PHASE INVERSION
The OP282 and OP482 are single and dual JFET op amps that
have been optimized for high speed at low power. This
combination makes these amplifiers excellent choices for battery
powered or low power applications requiring above average
performance. Applications benefiting from this performance
combination include telecom, geophysical exploration, portable
medical equipment and navigational instrumentation.
Most JFET-input amplifiers will invert the phase of the input
signal if either input exceeds the input common-mode range.
For the OP282 and OP482 negative signals in excess of approximately 14 volts will cause phase inversion. The cause of this
effect is saturation of the input stage leading to the forwardbiasing of a drain-gate diode. A simple fix for this in noninverting
applications is to place a resistor in series with the noninverting
input. This limits the amount of current through the forwardbiased diode and prevents the shutting down of the output
stage. For the OP282/OP482, a value of 200 kΩ has been found
to work. However, this adds a significant amount of noise.
HIGH SIDE SIGNAL CONDITIONING
There are many applications that require the sensing of signals
near the positive rail. OP282s and OP482s have been tested and
guaranteed over a common-mode range (–11 V ≤ VCM ≤ +15 V)
that includes the positive supply.
15
One application where this is commonly used is in the sensing of
power supply currents. This enables it to be used in current
sensing applications such as the partial circuit shown in Figure
1. In this circuit, the voltage drop across a low value resistor,
such as the 0.1 Ω shown here, is amplified and compared to 7.5
volts. The output can then be used for current limiting.
10
V IN
5
0.1 Ω
+15V
0
-5
500k
-10
100k
RL
100k
-15
-15
+
1/2
OP282
-10
-5
0
VOUT
5
10
15
Figure 2. OP282 Phase Reversal
100k
ACTIVE FILTERS
The OP282 and OP482’s wide bandwidth and high slew rates
make either an excellent choice for many filter applications.
Figure 1. Phase Inversion
There are many types of active filter configurations, but the four
most popular configurations are Butterworth, elliptical, Bessel,
and Chebyshev. Each type has a response that is optimized for a
given characteristic as shown in Table I.
PROGRAMMABLE STATE-VARIABLE FILTER
Table I.
Type
Selectivity
Overshoot
Butterworth
Chebyshev
Elliptical
Bessel (Thompson)
Moderate
Good
Best
Poor
Good
Moderate
Poor
Best
Phase
Nonlinear
Amplitude
(Pass Band)
Amplitude
(Stop Band)
Max Flat
Equal Ripple
Equal Ripple
Equal Ripple
Linear
–4–
REV. B
OP282/OP482
The circuit shown in Figure 3 can be used to accurately
program the “Q,” the cutoff frequency fC, and the gain of a two
pole state-variable filter. OP482s have been used in this design
because of their high bandwidths, low power and low noise.
This circuit takes only three packages to build because of the
quad configuration of the op amps and DACs.
fc =
 D1 
1


2πR1C1  256 
where D1 is the digital code for the DAC.
Gain of this circuit is set by adjusting D3. The gain equation is:
The DACs shown are all used in the voltage mode so all values
are dependent only on the accuracy of the DAC and not on the
absolute values of the DAC’s resistive ladders. This make this
circuit unusually accurate for a programmable filter.
Gain =
R4  D 3 


R5  256 
DAC 2 is used to set the “Q” of the circuit. Adjusting this DAC
controls the amount of feedback from the bandpass node to the
input summing node. Note that the digital value of the DAC is
in the numerator, therefore zero code is not a valid operating point.
Adjusting DAC 1 changes the signal amplitude across R1;
therefore, the DAC attenuation times R1 determines the
amount of signal current that charges the integrating capacitor,
C1. This cutoff frequency can now be expressed as:
Q=
R2  256 


R3  D2 
R7
2k
1/4
DAC8408
R4
2k
VIN
+
R5
2k
1/4
OP482
1/4
DAC8408
C1
1000pF
+
+
1/4
OP482
R1
2k
1/4
OP482
1/4
DAC8408
+
+
1/4
OP482
HIGH PASS
R6
2k
1/4
DAC8408
R3
2k
1/4
OP482
+
BANDPASS
R2
1k
1/4
OP482
+
Figure 3.
REV. B
–5–
C1
1000pF
R1
2k
1/4
OP482
+
LOW
1/4 PASS
OP482
OP282/OP482
minor changes in the circuit values. Contact ADI for a copy of
the latest SPICE model diskette for both listings.
OP282/OP482 SPICE MACRO MODEL
Figure 4 shows the OP282 SPICE macro model. The model for
the OP482 is similar to that of the OP282, but there are some
99
I1
V2
8
4
D1
9
INJ1
J2
G1
2
CIN
IOS
R5
7
R2
C3
3
EOS
5
R1
1
98
6
R3
D2
EREF
C2
IN+
10
R4
V3
50
C4
C14
13
11
14
19
20
12
G2
R6
G3
E2
G11
C5
C13
C6
R9
R8
R7
21
R21
E13
R19
R22
98
99
D5
D6
ISY
R27
G19
R25
23
V4
D3 25
R23
29
G15
L5
30
24
C15
VOUT
V5
98
D4 26
27
R28
28
G20
R26
G17
G18
D8
D7
50
Figure 4.
–6–
REV. B
OP282/OP482
*
* COMMON-MODE GAIN NETWORK
WITH ZERO AT 11 KHZ
*
R21
20 21 1E6
R22
21 98 1
C14
20 21 14.38E-12
E13
98 20 3
24 31.62
*
* POLE AT 15 MHZ
*
R23
23 98 1E6
C15
23 98 10.6E-15
G15
98 23 19
24 1E-6
*
* OUTPUT STAGE
*
R25
24 99 5E6
R26
24 50 5E6
ISY
99 50 107E-6
R27
29 99 700
R28
29 50 700
L5
29 30 1E-8
G17
27 50 23
29 1.43E-3
G18
28 50 29
23 1.43E-3
G19
29 99 99
23 1.43E-3
G20
50 29 23
50 1.43E-3
V4
25 29 2.8
V5
29 26 3.5
D3
23 25 DX
D4
26 23 DX
D5
99 27 DX
D6
99 28 DX
D7
50 27 DY
D8
50 28 DY
*
* MODELS USED
*
.MODEL JX PJF(BETA = 3.34E-4
VTO = –2.000 IS = 3E-12)
.MODEL DX D(IS = 1E-15)
.MODEL DY D(IS = 1E-15 BV = 50)
.ENDS OP282
OP282 SPICE MACRO MODEL
* Node assignments
*
noninverting input
*
inverting input
*
positive supply
*
negative supply
*
output
*
.SUBCKT OP282 1
2
99 50 30
*
* INPUT STAGE & POLE AT 15 MHZ
*
R1
1
3
5E11
R2
2
3
5E11
R3
5
50 3871.3
R4
6
50 3871.3
CIN
1
2
5E-12
C2
5
6
1.37E-12
I1
99 4
0.1E-3
IOS
1
2
5E-13
EOS
7
1
POLY(1) 21 24 200E-6 1
J1
5
2
4
JX
J2
6
7
4
JX
*
EREF 98 0
24
01
*
* GAIN STAGE & POLE AT 124 HZ
*
R5
9
98 1.16E8
C3
9
98 1.11E-11
G1
98 9
56
2.58E-4
V2
99 8
1.2
V3
10 50 1.2
D1
9
8
DX
D2
10 9
DX
*
* NEGATIVE ZERO AT 4 MHZ
*
R6
11 12 1E6
R7
12 98 1
C4
11 12 39.8E-15
E2
11 98 9
24 1E6
*
* POLE AT 15 MHZ
*
R8
13 98 1E6
C5
13 98 10.6E-15
G2
98 13 12
24 1E-6
*
* POLE AT 15 MHZ
*
R9
14 98 1E6
C6
14 98 10.6E-15
G3
98 14 13
24 1E-6
*
* POLE AT 15 MHZ
*
R19
19 98 1E6
C13
19 98 10.6E-15
G11
98 19 14
24 1E-6
REV. B
–7–
OP282/OP482
0
80
35
70
20
135
0
180
25
20
15
10
5
10k
100k
1M
10M
100M
POSITIVE EDGE
30
20
25
60
20
SLEW RATE – V/µs
30
AVCL = +10
20
10
AVCL = +1
500
VS = ±15V
– SR
40
100
200
300
400
LOAD CAPACITANCE – pF
Figure 11. Small Signal Overshoot
vs. Load Capacitance
INPUT BIAS CURRENT – pA
AVCL= +100
0
1000
TA = +25°C
VS = ±15V
50
CLOSED-LOOP GAIN – dB
100 125
Figure 8. Open-Loop Gain (V/mV)
Figure 5. Open-Loop Gain, Phase
vs. Frequency
AVCL = +1
40
10
0
25
50 75
–75 –50 –25
TEMPERATURE – °C
FREQUENCY – Hz
AVCL = +1
NEGATIVE EDGE
50
0
1k
RL =
L 2kΩ
VIN = 100mV p-p
60
OVERSHOOT – %
40
90
OPEN-LOOP GAIN – V/MV
60
VS = ±15V
VS = ±15V
RL= 10k
30
45
PHASE – Degrees
OPEN-LOOP GAIN – dB
TA = +25°C
VS = ±15V
VS= ±15V
RL= 10k
L
CL= 50pF
15
10
+ SR
0
5
VCM = 0
100
10
1.0
–10
0.1
10k
100k
1M
10M
–75
100M
FREQUENCY – Hz
Figure 6. Closed-Loop Gain vs.
Frequency
ØM
GBW
50
4.0
45
3.5
40
3.0
0
–75 –50 –25
25 50
75
TEMPERATURE – °C
100 125
Figure 7. OP482 Phase Margin and
Gain Bandwidth Product vs.
Temperature
Hz
VOLTAGE NOISE DENSITY – nV/
4.5
80
GAIN BANDWIDTH PRODUCT – MH Z
PHASE MARGIN – Degrees
VS = ±15V
RL = 10k
55
100 125
Figure 9. OP282/OP482 Slew Rate
vs. Temperature
50
60
–50 –25 0
25
50 75
TEMPERATURE –°C
25
50 75
–50 –25 0
TEMPERATURE – °C
100 125
Figure 12. OP282 Input Bias Current
vs. Temperature
1000
VS = ±15V
TA = +25°C
70
INPUT BIAS CURRENT – pA
–20
1k
60
50
40
30
20
VS = ±15V
TA = +25°C
100
10
1
10
0
10
100
1k
FREQUENCY – Hz
10k
Figure 10. Voltage Noise Density
vs. Frequency
–8–
0.1
–15
–10
–5
5
10
0
COMMON - MODE VOLTAGE – V
15
Figure 13. OP282 Input Bias Current
vs. Common-Mode Voltage
REV. B
OP282/OP482
20
1.10
TA = +25°C
1.05
1.00
0.95
0.90
0.85
±10
±5
±15
SUPPLY VOLTAGE – Volts
5
0
–5
±5
±10
±15
0
100
±20
AVCL = 100
AVCL= +10
AVCL= 1
1k
100k
100
1.00
0.95
0.90
0.85
TA = +25°C
VS = ±15V
14
80
POSITIVE
SWING
10
8
NEGATIVE
SWING
6
+ PSRR
60
– PSRR
40
20
4
0
2
–20
100
0
100
1k
10k
1k
10k
Figure 18. Maximum Output Voltage
vs. Load Resistance
10
SOURCE
5
100
TA = +25°C
VS = ±15V
AVCL = +1
RL = 10k Ω
25
80
20
60
CMRR – dB
15
MAXIMUM OUTPUT SWING – Volts
VS = ±15V
15
20
5
0
Figure 16. OP282/OP482 Short
Circuit Current vs. Temperature
1k
10k
100k
1M
FREQUENCY – Hz
Figure 19. Maximum Output Swing
vs. Frequency
–9–
VS = ±15V
VCM = 100mV
TA = +25°C
40
10
0
100 125
1M
Figure 21. OP282 Power Supply
Rejection Ratio (PSRR) vs. Frequency
30
SINK
100k
FREQUENCY – Hz
LOAD RESISTANCE – Ω
20
VS = ±15V
∆V = 100mV
TA = +25°C
12
100 125
Figure 15. Relative Supply Current
vs. Temperature
1M
Figure 20. OP482 Closed-Loop Output Impedance vs. Frequency
PSRR – dB
1.05
10k
FREQUENCY – Hz
Figure 17. Output Voltage Swing
vs. Supply Voltage
ABSOLUTE OUTPUT VOLTAGE – Volts
1.10
REV. B
200
SUPPLY VOLTAGE – Volts
VSUP = ±15
0
–75 –50 –25
25
50 75
TEMPERATURE – °C
300
100
–15
16
0.80
0
–75 –50 –25
25 50 75
TEMPERATURE – °C
AVCL = 1000
400
–10
0
1.20
1.15
TA = +25°C
VS = ±15V
500
10
±20
Figure 14. Relative Supply Current
vs. Supply Voltage
RELATIVE SUPPLY CURRENT – ISY
15
–20
0
SHORT CIRCUIT CURRENT – mA
600
TA = +25°C
RL = 10k Ω
IMPEDANCE – Ω
OUTPUT VOLTAGE SWING – Volts
RELATIVE SUPPLY CURRENT – ISY
1.15
–20
100
1k
10k
100k
1M
FREQUENCY – Hz
Figure 22. OP282 Common-Mode
Rejection Ratio (CMRR) vs. Frequency
OP282/OP482
320
280
VS = ±15V
TA= +25°C
315 × OP282
(630 OP AMPS )
240
200
700
280
VS = ±15V
-40°C ≤ TA ≤ +125°C
300 × OP482
1200 OP AMPS
600
240
500
160
UNITS
UNITS
UNITS
200
160
120
400
300
120
80
200
80
40
100
40
0
-2000 -1600 -1200 -800 -400
0
0
0
0
400 800 1200 1600 2000
4
8
VOS – µV
280
VS = ±15V
TA = +25°C
320 × OP282
(640 OP AMPS)
200
24
28
32
0
4
8
12
16
20
24
28
32
TCVOS – µV/°C
Figure 25. OP282 TCVOS (µ V/°C)
Distribution "P" Package
Figure 23. VOS Distribution "P"
Package
240
12 16 20
TCVOS – µV/°C
Figure 27. OP482 TCVOS Distribution
"Z" Package
320
700
280
600
240
VS = ±15V
-40°C ≤ TA ≤ +85°C
300 × OP482
1200 OP AMPS
500
120
UNITS
UNITS
160
160
400
300
120
80
200
80
40
100
40
0
–2000 –1600 –1200 –800 –400
0
0
0
0
400 800 1200 1600 2000
VOS – µV
4
8
12 16
20
TCVOS – µV/°C
24
28
32
0
4
8
12
16
20
24
28
32
TCVOS – µV/°C
Figure 26. OP282 TCVOS (µ V/°C)
Distribution "Z" Package
Figure 24. VOS Distribution "Z"
Package
Figure 28. TCVOS Distribution "P"
Package
700
700
TA = +25°C
VS = ±15V
300 3 OP482
1200 OP AMPS
600
500
TA = +25°C
VS = ±15V
300 3 OP482
1200 OP AMPS
600
500
400
UNITS
UNITS
UNITS
200
300
400
300
200
200
100
100
0
0
–2000 –1600 –1200 –800 –400
0
–2000 –1600 –1200 –800 –400
400 800 1200 1600 2000
0
400 800 1200 1600 2000
VOS – µV
V OS – µV
Figure 29. OP482 VOS Distribution “Z”
Package
Figure 30. OP482 VOS Distribution “P”
Package
–10–
REV. B
OP282/OP482
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Narrow-Body SOIC
(S Suffix)
8-Lead Epoxy DIP
(P Suffix)
14-Lead Narrow-Body SOIC
(S Suffix)
14-Lead Epoxy DIP
(P Suffix)
20-Position Chip Carrier
(RC Suffix)
REV. B
–11–
–12–
REV. B
PRINTED IN U.S.A.
C1597–24–11/91
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