OPA2694 SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 Dual, Wideband, Low-Power, Current Feedback Operational Amplifier FEATURES D D D D D D DESCRIPTION UNITY GAIN STABLE BANDWIDTH: 1500MHz HIGH GAIN OF 2V/V BANDWIDTH: 690MHz The OPA2694 is a dual, ultra-wideband, low-power, current feedback operational amplifier f eaturing high slew rate and low differential gain/phase errors. An improved output stage provides ±70mA output drive with < 1.5V output voltage headroom. Low supply current with > 500MHz bandwidth meets the requirements of high density video routers. Being a current feedback design, the OPA2694 holds its bandwidth to very high gains—at a gain of 10, the OPA2694 will still provide > 200MHz bandwidth. LOW SUPPLY CURRENT: 5.8mA/ch HIGH SLEW RATE: 1700V/μs HIGH FULL-POWER BANDWIDTH: 670MHz LOW DIFFERENTIAL GAIN/PHASE: 0.03%/0.0155 RF applications can use the OPA2694 as a low-power SAW pre-amplifier. Extremely high 3rd-order intercept is provided through 70MHz at much lower quiescent power than many typical RF amplifiers. APPLICATIONS D D D D D D D MEDICAL IMAGING WIDEBAND VIDEO LINE DRIVER DIFFERENTIAL RECEIVER ADC DRIVER HIGH-SPEED SIGNAL PROCESSING PULSE AMPLIFIER IMPROVED REPLACEMENT FOR OPA2658 The OPA2694 is available in an industry-standard pinout in an SO-8 package. 100pF 50Ω 232Ω +5V 20Ω 1/2 OPA2694 RELATED PRODUCTS SINGLES DUALS TRIPLES QUADS OPA694 — — — FEATURES OPA683 OPA2683 — — Low-Power, CFBPLUS OPA684 OPA2684 OPA3684 OPA4684 Low-Power, CFBPLUS OPA691 OPA2691 OPA3691 — High Output Current OPA695 OPA2695 OPA3695 — High Intercept VI 75pF 50Ω 232Ω 400Ω 20Ω 100pF 800Ω 357Ω 800Ω 357Ω 22pF VO 1/2 OPA2694 −5V Low-Power, Differential I/O, 3rd-Order Butterworth Active Filter Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2004−2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS(1) Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6.5VDC Internal Power Dissipation . . . . . . . . . See Thermal Characteristics Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2V Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS Storage Temperature Range: D, DBV . . . . . . . . . −65°C to +125°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C ESD Rating: Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 3000V Charge Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . 1000V Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V (1) This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR OPA2694 SO 8 SO-8 D (1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING −40°C 40°C tto +85°C 85°C OPA2694 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA2694ID Rails, 100 OPA2694IDR Tape and Reel, 2500 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. PIN CONFIGURATION TOP VIEW 2 SO-8 Out A 1 8 +VS −In A 2 7 Out B +In A 3 6 −In B −VS 4 5 +In B OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. OPA2694ID TYP MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C(2) −40°C to +85°C(2) 690 340 330 320 G = +5, VO = 0.5VPP, RF = 330Ω 250 190 170 G = +10, VO = 0.5VPP, RF = 180Ω 200 140 120 G = +1, VO = 0.5VPP, RF = 430Ω Peaking at a Gain of +1 VO ≤ 0.1VPP, RF = 430Ω Large-Signal Bandwidth G = +2, VO = 2VPP 670 G = +2, 2V Step 1700 G = +2, VO = 0.2V Step MIN/ MAX TEST LEVEL(3) MHz typ C MHz min B 150 MHz min B 110 MHz min B 90 MHz min B 2 dB typ C MHz typ C V/μs min B 0.8 ns typ C G = +2, VO = 2V Step 20 ns typ C G = +2, VO = 2V Step 13 ns typ C G = +2, f = 5MHz, VO = 2VPP — — — — RL = 100Ω −85 −78 −72 −70 dBc max B RL ≥ 500Ω −92 −87 −85 −83 dBc max B RL = 100Ω −72 −68 −66 −65 dBc max B RL ≥ 500Ω −93 −87 −85 −83 dBc max B Input Voltage Noise f > 1MHz 2.1 2.5 2.9 3.1 nV/√Hz max B Inverting Input Current Noise f > 1MHz 22 25 26 29 pA/√Hz max B Non-inverting Input Current Noise f > 1MHz 24 27 28 30 pA/√Hz max B VO = 1.4VPP, RL = 150Ω 0.03 % max C PARAMETER CONDITIONS +25°C G = +1, VO = 0.5VPP, RF = 430Ω 1500 G = +2, VO = 0.5VPP, RF =390Ω UNITS AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth Bandwidth for 0.1dB Gain Flatness Slew Rate Rise Time and Fall Time Settling Time to 0.01% to 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic NTSC Differential Gain NTSC Differential Phase Channel-to-Channel Crosstalk 1300 1275 1250 VO = 1.4VPP, RL = 37.5Ω 0.05 % max C G = +2, VO − 1.4VPP, RL = 150Ω 0.015 ° typ C VO − 1.4VPP, RL = 37.5Ω 0.15 ° typ C f = 5MHz 63 dB typ C DC PERFORMANCE(4) Open-Loop Transimpedance VO = 0V, RL = 100Ω 145 88 63 58 kΩ min A Input Offset Voltage VCM = 0V ±0.7 ±3.2 ±3.9 ±4.3 mV max A Average Input Offset Voltage Drift VCM = 0V — 12 15 μV/°C max B Channel to Channel ΔVIO VCM = 0V ±0.5 mV typ C Noninverting Input Bias Current VCM = 0V ±5 A Average Input Bias Current Drift VCM = 0V — Channel to Channel ΔIBI VCM = 0V ±5 Inverting Input Bias Current VCM = 0V ±4 Average Input Bias Current Drift VCM = 0V — Channel to Channel ΔIBN VCM = 0V ±4 ±22 ±20 ±28 ±33 μA max ±100 ±150 nA/°C max B μA typ C A ±28 ±40 μA max ±150 ±200 nA/°C max B μA typ C A INPUT Common-Mode Input Voltage(5) (CMIR) Common-Mode Rejection Ratio (CMRR) VCM = 0V Noninverting Input Impedance Inverting Input Resistance Open-Loop ±2.5 ±2.3 ±2.2 ±2.1 V min 60 54 52 50 dB min A 280 || 1.2 kΩ || pF typ C 30 Ω typ C OUTPUT Voltage Output Voltage No Load ±4 ±3.8 ±3.7 ±3.6 V min A RL = 100Ω ±3.4 ±3.1 ±3.1 ±3.0 V min A Output Current VO = 0V ±70 ±55 ±53 ±45 mA min A Short-Circuit Output Current VO = 0V ±200 mA typ C G = +2, f =100kHz 0.02 Ω typ C Closed-Loop Output Impedance (1) (2) (3) (4) (5) Junction temperature = ambient for +25°C specifications. Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over temperature specifications. Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Current is considered positive out of node. VCM is the input common-mode voltage. Tested < 3dB below minimum specified CMRR at ±CMIR limits. 3 OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS: VS = ±5V (continued) Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. OPA2694ID TYP PARAMETER CONDITIONS +25°C MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C(2) −40°C to +85°C(2) UNITS MIN/ MAX TEST LEVEL(3) POWER SUPPLY Specified Operating Voltage ±5 V typ C Maximum Operating Voltage Range — ±6.3 ±6.3 ±6.3 V max A Minimum Operating Voltage Range — ±3.5 ±3.5 ±3.5 mA max B Maximum Quiescent Current VS = ±5V, Both Channels 11.6 12.1 12.5 12.7 mA max A Minimum Quiescent Current VS = ±5V, Both Channels 11.6 11.1 10.5 9.9 mA min A Input-Referred 58 53 51 49 dB min A −40 to +85 °C typ C — — — — 125 °C/W typ C Power-Supply Rejection Ratio (PSRR) THERMAL CHARACTERISTICS Specification: ID Thermal Resistance qJA D (1) (2) (3) (4) (5) 4 SO-8 Junction-to-Ambient Junction temperature = ambient for +25°C specifications. Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over temperature specifications. Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Current is considered positive out of node. VCM is the input common-mode voltage. Tested < 3dB below minimum specified CMRR at ±CMIR limits. OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 TYPICAL CHARACTERISTICS: VS = ±5V RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE −3 −6 G = +10V/V RF = 178Ω −9 G = +5V/V RF = 318Ω −3 −9 0 200 400 600 800 1000 0 VO = 4VPP Gain (dB) VO = 2VPP 0 −3 −6 VO = 7VPP VO = 4VPP See Figure 1 0 200 400 600 800 1000 1200 1400 VO = 1VPP See Figure 2 −12 0 200 400 600 800 1000 Frequency (MHz) Frequency (MHz) NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE 3 Large Signal, 5VPP Left Scale Small Signal, 0.5VPP Right Scale 0.2 0 −1 −0.2 −2 −0.4 Time (5ns/div) −0.6 1400 0.6 G = −2V/V 0.4 1200 3 0.6 See Figure 1 G = +2V/V Output Voltage (200mV/div) −12 VO = 7VPP −9 2 Output Voltage (1V/div) Gain (dB) −3 1200 G = −2V/V RF = 402Ω VO = 2VPP 6 3 −9 1000 9 G = +2V/V RF = 402Ω VO = 1VPP −6 800 600 INVERTING LARGE−SIGNAL FREQUENCY RESPONSE 0 Output Voltage (1V/div) 400 NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE 3 −3 200 Frequency (MHz) 6 0 G = −5V/V RF = 318Ω See Figure 2 Frequency (MHz) 9 1 G = −10V/V R F = 500Ω −12 −18 −12 2 G = −2V/V RF = 402Ω −6 −15 See Figure 1 VO = 0.5VPP RL = 100Ω G = −1V/V RF = 430Ω 0 Normalized Gain (dB) Normalized Gain (dB) 0 3 VO = 0.5VPP RL = 100Ω G = +2V/V RF = 402Ω 1 0 See Figure 2 Large Signal, 5VPP Left Scale Small Signal, 0.5VPP Right Scale 0.4 0.2 0 −1 −0.2 −2 −0.4 −3 Time (5ns/div) Output Voltage (200mV/div) 3 INVERTING SMALL−SIGNAL FREQUENCY RESPONSE −0.6 5 OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 TYPICAL CHARACTERISTICS: VS = ±5V (continued) RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted HARMONIC DISTORTION vs SUPPLY VOLTAGE HARMONIC DISTORTION vs LOAD RESISTANCE G = +2V/V f = 5MHz VO = 2VPP −70 −75 −80 3rd Harmonic −85 2nd Harmonic −90 See Figure 1 −95 100 −80 −85 G = +2V/V f = 5MHz VO = 2VPP RL = 100Ω −90 2.5 1000 2nd Harmonic See Figure 1 3.0 3.5 4.0 4.5 5.0 Supply Voltage (±VS) HARMONIC DISTORTION vs FREQUENCY 5MHz HARMONIC DISTORTION vs OUTPUT VOLTAGE −65 3rd Harmonic −75 −80 −85 −90 2nd Harmonic See Figure 1 G = +2V/V RL = 100Ω f = 5MHz −70 1 6.0 3rd Harmonic −80 2nd Harmonic −85 −90 See Figure 1 0.1 10 1 Frequency (MHz) Output Voltage Swing (VPP) HARMONIC DISTORTION vs NONINVERTING GAIN HARMONIC DISTORTION vs INVERTING GAIN −60 5.5 −75 −95 −95 0.1 3rd Harmonic −75 Resistance (Ω ) G = +2V/V RL = 100Ω VO = 2VPP −70 −70 −95 Harmonic Distortion (dBc) Harmonic Distortion (dBc) −65 −65 Harmonic Distortion (dBc) Harmonic Distortion (dBc) −65 10 −60 −65 −70 3rd Harmonic −75 −80 2nd Harmonic −85 RL = 100Ω f = 5MHz VO = 2VPP −90 −65 3rd Harmonic −70 −75 2nd Harmonic −80 RL = 100Ω f = 5MHz VO = 2VPP −85 See Figure 2 −90 1 10 Gain (V/V) 6 Harmonic Distortion (dBc) Harmonic Distortion (dBc) See Figure 1 1 10 Gain (|V/V|) OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 TYPICAL CHARACTERISTICS: VS = ±5V (continued) RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted INPUT VOLTAGE AND CURRENT NOISE 2−TONE, 3rd−ORDER INTERMODULATION INTERCEPT 1k 55 Inverting Current Noise (22pA/√Hz) 10 Intercept Point (+dBm) Current Noise (pA/√Hz) Voltage Noise (nV/√Hz) Noninverting Current Noise (24pA/√Hz) 100 Voltage Noise (2.1nV/√Hz) PO 50Ω 50Ω 390Ω 45 390Ω 40 35 30 25 20 1 10 100 1k 10k 100k 1M 10M 100M 10 0 20 30 40 60 50 70 Frequency (Hz) Frequency (MHz) RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 60 80 90 100 3 0dB Peaking Targeted Normalized Gain (dB) 40 30 20 CL = 10pF 0 50 RS (Ω) 50Ω PI 50 CL = 47pF −6 VI −9 −15 0 −18 RS 1/2 OPA2694 50Ω VO CL 390Ω −12 10 CL = 22pF CL = 100pF −3 1kΩ(1) 390Ω NOTE: (1) 1kΩ load is optional 100 COMMON−MODE REJECTION RATIO AND POWER−SUPPLY REJECTION RATIO vs FREQUENCY OPEN−LOOP ZOL GAIN AND PHASE +PSRR PSRR (dB) 50 40 −PSRR 30 20 10 1K 10K 100K Frequency (Hz) 1M 10M 100M Open−Loop ZOL Gain (dBΩ) CMRR 60 CMRR (dB) 100M Frequency (Hz) 70 0 100 10M 1M Capacitive Load (pF) 1G 120 30 110 0 100 −30 90 < ZOL 80 −90 −120 70 20 log |ZOL| 60 −150 −180 50 40 100 −60 Open−Loop ZOL Phase (_ ) 10 −210 1K 10K 100K 1M 10M 100M 1G Frequency (Hz) 7 OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 TYPICAL CHARACTERISTICS: VS = ±5V (continued) RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted VIDEO DIFFERENTIAL GAIN/DIFFERNTIAL PHASE (No Pulldown) TYPICAL DC DRIFT OVER TEMPERATURE 0.08 0.04 dG Negative Video 0.04 0.02 dP Negative Video 0 2 1 4 Input Offset Voltage (mV) dG Positive Video Differential Phase (_ ) Differential Gain (%) 0.12 0.06 0.5 0 4 Input Offset Voltage (VOS) Left Scale Inverting Input Bias Current (I BI) Right Scale Right Scale −5 −25 0 +25 +50 +75 Video Loads Ambient Temperature (_ C) OUTPUT VOLTAGE AND CURRENT LIMITATIONS SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 1W Internal Power Limit 5 0 Noninverting Input Bias Current (IBN) −0.5 −1.0 −50 0 3 10 1.0 dP Positive Video Input Bias and Offset Current (μA) 0.16 0.08 +100 −10 +125 75.0 18 72.5 16 1 0 −1 −2 Output Current Limit RL = 25Ω Output Current Limit Sinking, Sourcing Output Current Left Scale 70.0 12 67.5 Supply Current Right Scale −3 −4 −200 1W Internal Power Limit −100 0 100 65.0 −50 200 −25 0 +25 NONINVERTING OVERDRIVE RECOVERY INVERTING OVERDRIVE RECOVERY 4 4 −2 −4 Output Voltage (V) 0 Input Voltage (V) Output Voltage (V) Output (Left Scale) 0 10 +125 4 2 2 Input Right Scale 0 0 Output Left Scale −2 −2 Input (Right Scale) See Figure 2 −4 Time (10ns/div) +100 RL = 100Ω G = −1V/V 2 4 −8 8 +75 Ambient Temperature (_ C) RL = 100Ω G = +2V/V See Figure 1 +50 Output Current (mA) 8 14 −4 −4 Time (10ns/div) Input Voltage (V) RL = 50Ω Supply Current (mA) RL = 100Ω 2 Output Current (mA) Output Voltage (V) 3 OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 TYPICAL CHARACTERISTICS: VS = ±5V (continued) RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted CHANNEL−TO−CHANNEL CROSSTALK Input Referred Crosstalk (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 1 10 100 Frequency (MHz) 9 OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 TYPICAL CHARACTERISTICS: VS = ±5V (continued) RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted Differential Performance Test Circuit DIFFERENTIAL SMALL−SIGNAL FREQUENCY RESPONSE +5V 3 VI RT RF RG RF RL 400Ω VO Normalized Gain (dB) 0 1/2 OPA2694 RG GD = 10V/V RF = 250Ω −3 −6 GD = 2V/V RF = 402Ω −9 GD = 1V/V RF = 430Ω −12 1/2 OPA2694 VO VI = RF RG = GD RL = 400Ω VO = 200mVPP −15 0 50 100 150 200 250 300 350 400 450 500 550 600 Frequency (MHz) −5V DIFFERENTIAL LARGE−SIGNAL FREQUENCY RESPONSE 9 VO = 2VPP 3 VO = 1VPP 0 −60 VO = 8VPP −3 GD = 2V/V f = 5MHz VO = 4VPP −65 Harmonic Distortion (dBc) Normalized Gain (dB) DIFFERENTIAL DISTORTION vs LOAD RESISTANCE GD = 2V/V RL = 400Ω VO = 4VPP 6 −70 0 −75 −80 −85 2nd Harmonic −90 50 100 150 200 250 300 350 400 450 500 100 10 DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE DIFFERENTIAL DISTORTION vs FREQUENCY −65 −60 GD = +2V/V RL = 400Ω VO = 4VPP −75 3rd Harmonic −80 G D = +2V/V f = 5MHz R L = 400Ω −65 Harmonic Distortion (dBc) −70 1k Resistance (Ω) Frequency (MHz) Harmonic Distortion (dBc) 3rd Harmonic −95 −6 2nd Harmonic −85 −90 −70 −75 3rd Harmonic −80 −85 −90 −95 2nd Harmonic −100 −105 −95 1 10 Frequency (MHz) 10 GD = 5V/V RF = 330Ω 100 0.1 1 Output Voltage Swing (VPP) 10 20 OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 WIDEBAND CURRENT FEEDBACK OPERATION The OPA2694 provides exceptional AC performance for a wideband, low-power, current-feedback operational amplifier. Requiring only 5.8mA/ch quiescent current, the OPA2694 offers a 690MHz bandwidth at a gain of +2, along with a 1700V/μs slew rate. An improved output stage provides ±70mA output drive, along with < 1.5V output voltage headroom. This combination of low power and high bandwidth can benefit high-resolution video applications. Figure 1 shows the DC-coupled, gain of +2, dual powersupply circuit configuration used as the basis of the ±5V Electrical Characteristic tables and Typical Characteristic curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the Electrical Charateristics are taken directly at the input and output pins, while load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 1, the total effective load will be 100Ω || 804Ω = 89Ω. One optional component is included in Figure 1. In addition to the usual power-supply decoupling capacitors to ground, a 0.01μF capacitor is included between the two power-supply pins. In practical PCB layouts, this optional added capacitor will typically improve the 2nd-harmonic distortion performance by 3dB to 6dB. Figure 2 shows the DC-coupled, gain of −2V/V, dual power-supply circuit used as the basis of the inverting Typical Characteristic curves. Inverting operation offers several performance benefits. Since there is no common-mode signal across the input stage, the slew rate for inverting operation is higher and the distortion performance is slightly improved. An additional input resistor, RT, is included in Figure 2 to set the input impedance equal to 50Ω. The parallel combination of RT and RG sets the input impedance. Both the noninverting and inverting applications of Figure 1 and Figure 2 will benefit from optimizing the feedback resistor (RF) value for bandwidth (see the discussion in Setting Resistor Values to Optimize Bandwidth). The typical design sequence is to select the RF value for best bandwidth, set RG for the gain, then set RT for the desired input impedance. As the gain increases for the inverting configuration, a point will be reached where RG will equal 50Ω, where RT is removed and the input match is set by RG only. With RG fixed to achieve an input match to 50Ω, RF is simply increased, to increase gain. This will, however, quickly reduce the achievable bandwidth, as shown by the inverting gain of –10 frequency response in the Typical Characteristic curves. For gains > 10V/V (14dB at the matched load), noninverting operation is recommended to maintain broader bandwidth. +5V +VS 0.1μF +5V +VS 20Ω −VS −5V 50ΩLoad 1/2 OPA2694 VO 50Ω 50Ω Load Optional 0.01μF 50Ω Source RG 200Ω RF 402Ω VI RF 402Ω RT 66.5Ω 6.8μF 0.1μF + Optional 0.01μF RG 402Ω VO 50Ω 1/2 OPA2694 6.8μF 6.8μF Figure 1. DC-Coupled, G = +2, Bipolar-Supply Specification and Test Circuit 0.1μF −VS −5V 6.8μF + 50Ω + 0.1μF 50ΩSource VI + APPLICATION INFORMATION Figure 2. DC-Coupled, G = −2V/V, Bipolar-Supply Specification and Test Circuit 11 OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 ADC DRIVER gain), wideband inverting summing stages may be implemented using the OPA2694. The circuit in Figure 4 shows an example inverting summing amplifier, where the resistor values have been adjusted to maintain both maximum bandwidth and input impedance matching. If each RF signal is assumed to be driven from a 50Ω source, the NG for this circuit will be (1 + 100Ω/(100Ω/5)) = 6. The total feedback impedance (from VO to the inverting error current) is the sum of RF + (RI • NG). where RI is the impedance looking into the inverting input from the summing junction (see the Setting Resistor Values to Optimize Performance section). Using 100Ω feedback (to get a signal gain of –2 from each input to the output pin) requires an additional 30Ω in series with the inverting input to increase the feedback impedance. With this resistor added to the typical internal RI = 30Ω, the total feedback impedance is 100Ω + (60Ω • 6) = 460Ω, which is equal to the required value to get a maximum bandwidth flat frequency response for NG = 6. Most modern, high-performance analog-to-digital converters (ADCs), such as Texas Instruments ADS522x series, require a low-noise, low-distortion driver. The OPA2694 combines low-voltage noise (2.1nV/√Hz) with low harmonic distortion. Figure 3 shows an example of a wideband, AC-coupled, 12-bit ADC driver. One OPA2694 is used in the circuit of Figure 3 to form a differential driver for the ADS5220. The OPA2694 offers > 150MHz bandwidth at a differential gain of 5V/V, with a 2VPP output swing. A 2nd-order RLC filter is used in order to limit the noise from the amplifier and provide some attenuation for higher-frequency harmonic distortion. WIDEBAND INVERTING SUMMING AMPLIFIER Since the signal bandwidth for a current-feedback op amp can be controlled independently of the noise gain (NG), which is normally the same as the noninverting signal +5V Power−supply decoupling not shown. 25Ω 100Ω 1:2 VI C1 1/2 OPA2694 R1 L V+ 500Ω C R2 50Ω 100Ω 500Ω 0.1μF 12−Bit 40MSPS ADS5220 VCM R2 Single−to−Differential Gain of 10 C1 1/2 OPA2694 25Ω R1 L V− −5V Figure 3. Wideband, AC-Coupled, Low-Power ADC Driver +5V DIS 50Ω V1 1/2 OPA2694 50Ω V2 50Ω V3 RG−58 100Ω 100MHz, −1dB Compression = 15dBm V4 50Ω VO = −(V1 + V2 + V3 + V4 + V5) 50Ω 30Ω 50Ω V5 50Ω −5V Figure 4. 200MHz RF Summing Amplifier 12 OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 SAW FILTER BUFFER +VCC One common requirement in an IF strip is to buffer the output of a mixer with enough gain to recover the insertion loss of a narrowband SAW filter. Figure 5 shows one possible configuration driving a SAW filter. The 2-Tone, 3rd-Order Intermodulation Intercept plot is shown in the Typical Characteritics curves. Operating in the inverting mode at a voltage gain of –8V/V, this circuit provides a 50Ω input match using the gain set resistor, has the feedback optimized for maximum bandwidth (250MHz in this case), and drives through a 50Ω output resistor into the matching network at the input of the SAW filter. If the SAW filter gives a 12dB insertion loss, a net gain of 0dB to the 50Ω load at the output of the SAW (which could be the input impedance of the next IF amplifier or mixer) will be delivered in the passband of the SAW filter. Using the OPA2694 in this application will isolate the first mixer from the impedance of the SAW filter and provide very low two-tone, 3rd-order spurious levels in the SAW filter bandwidth. 1/2 OPA2694 RF VI 1000pF 0.1μF 50Ω PO Matching Network 50Ω 50Ω Source 1000pF PI SAW Filter 50Ω VO 1/2 OPA2694 −VCC Figure 6. Noninverting Differential I/O Amplifier 5kΩ 1/2 RF This approach provides for a source termination impedance that is independent of the signal gain. For instance, simple differential filters may be included in the signal path right up to the noninverting inputs without interacting with the gain setting. The differential signal gain for the circuit of Figure 6 is shown in Equation (1): +12V 5kΩ OPA2694 RG 400Ω PO = 12dB − (SAW Loss) PI Figure 5. IF Amplifier Driving SAW Filter DIFFERENTIAL INTERFACE APPLICATIONS Dual op amps are particularly suitable to differential input to differential output applications. Typically, these fall into either ADC input interface or line driver applications. Two basic approaches to differential I/O are noninverting or inverting configurations. Since the output is differential, the signal polarity is somewhat meaningless—the noninverting and inverting terminology applies here to where the input is brought into the OPA2694. Each has its advantages and disadvantages. Figure 6 shows a basic starting point for noninverting differential I/O applications. AD + 1 ) 2 RF RG (1) The differential gain, however, may be adjusted with considerable freedom using just the RG resistor. In fact, RG may be a reactive network providing a very isolated shaping to the differential frequency response. Since the inverting inputs of the OPA2694 are low-impedance closed-loop buffer outputs, the RG element does not interact with the amplifier bandwidth. Wide ranges of resistor values and/or filter elements may be inserted here with minimal amplifier bandwidth interaction. Various combinations of single-supply or AC-coupled gain can also be delivered using the basic circuit of Figure 6. Common-mode bias voltages on the two noninverting inputs pass on to the output with a gain of 1, since an equal DC voltage at each inverting node creates no current through RG. This circuit does show a common-mode gain of 1 from input to output. The source connection should either remove this common-mode signal if undesired (using an input transformer can provide this function), or the common-mode voltage at the inputs can be used to set the output common-mode bias. If the low common-mode rejection of this circuit is a problem, the output interface may also be used to reject that common-mode. For instance, most modern differential input ADCs reject 13 OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 common-mode signals very well, while a line driver application through a transformer also attenuates the common-mode signal through to the line. Figure 7 shows a differential I/O stage configured as an inverting amplifier. In this case, the gain resistors (RG) become part of the input resistance for the source. This provides a better noise performance than the noninverting configuration, but does limit the flexibility in setting the input impedance separately from the gain. +VCC VCM VI DC-COUPLED SINGLE-TO-DIFFERENTIAL CONVERSION The previous differential output circuits were set up to receive a differential input as well. A simple way to provide a DC-coupled single-to-differential conversion using a dual op amp is shown in Figure 8. Here, the output of the first stage is simply inverted by the second to provide an inverting version of a single amplifier design. This approach works well for lower frequencies, but will start to depart from ideal differential outputs as the propagation delay and distortion of the inverting stage adds significantly to that present at the noninverting output pin. 1/2 OPA2694 RG RF RG RF +5V VO 1VPP 50Ω 1/2 OPA2694 402Ω 1/2 OPA2694 VCM 80.6Ω −VCC Figure 7. Inverting Differential I/O Amplifier The two noninverting inputs provide an easy common-mode control input. This is particularly easy if the source is AC-coupled through either blocking caps or a transformer. In either case, the common-mode input voltages on the two noninverting inputs again have a gain of 1 to the output pins, giving particularly easy common-mode control for single-supply operation. Once RF is fixed, the input resistors can be adjusted to the desired gain, but will also be changing the input impedance as well. The high-frequency, common-mode gain for this circuit from input to output is the same as for the signal gain. Again, if the source includes an undesired common-mode signal, it can be rejected at the input using blocking caps (for low-frequency and DC common-mode) or a transformer coupling. 14 402Ω 12VPP Differential 402Ω 1/2 OPA2694 −5V Figure 8. Single-to-Differential Conversion The circuit of Figure 8 is set up for a single-ended gain of 6 to the output of the first amplifier, then an inverting gain of –1 through the second stage to provide a total differential gain of 12. OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 DIFFERENTIAL ACTIVE FILTER The OPA2694 can provide a very capable gain block for low-noise active filters. The dual design lends itself very well to differential active filters. Where the filter topology is looking for a simple gain function to implement the filter, the noninverting configuration is preferred to isolate the filter elements from the gain elements in the design. Figure 9 shows an example of a very low power, 10MHz 3rd-order Butterworth low-pass, Sallen-Key filter. The example of Figure 9 designs the filter for a differential gain of 1 using the OPA2694. The resistor values have been adjusted slightly to account for the amplifier bandwidth effects. While this circuit is bipolar (using ±5V supplies), it can easily be adapted to single-supply operation. This is typically done by providing a supply midpoint reference at the noninverting inputs, and then adding DC blocking caps at each input and in series with the amplifier gain resistor, RG. This will add two real zeroes in the response, transforming the circuit into a bandpass. DESIGN-IN TOOLS DEMONSTRATION FIXTURES Two printed circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the OPA2694 in either of two possible configurations: inverting or noninverting. Both of these are offered free of charge as unpopulated PCBs, delivered with a user’s guide. The summary information for these fixtures is shown in Table 1. Table 1. Demonstration Fixtures by Package PRODUCT PACKAGE ORDERING NUMBER LITERATURE NUMBER OPA2694ID SO-8 DEM-OPA-SO-2B (noninverting) SBOU030 SO-8 DEM-OPA-SO-2C (inverting) SBOU029 OPA2694ID The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the OPA2694 product folder. 100pF 50Ω 232Ω MACROMODELS AND APPLICATIONS SUPPORT +5V 20Ω 1/2 OPA2694 VI 75pF 50Ω 232Ω 400Ω 20Ω 100pF 800Ω 357Ω 800Ω 357Ω 22pF VO 1/2 OPA2694 Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA2694 is available through the TI web site (www.ti.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dφ characteristics. These models do not attempt to distinguish between package types in their small-signal AC performance. −5V Figure 9. Low-Power, Differential I/O, 3rd-Order Butterworth Active Filter 15 OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 OPERATING SUGGESTIONS SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH A current-feedback op amp like the OPA2694 can hold an almost constant bandwidth over signal gain settings with the proper adjustment of the external resistor values. This is shown in the Typical Characteristic curves; the small-signal bandwidth decreases only slightly with increasing gain. Those curves also show that the feedback resistor has been changed for each gain setting. The resistor values on the inverting side of the circuit for a current-feedback op amp can be treated as frequency response compensation elements while their ratios set the signal gain. Figure 10 shows the small-signal frequency response analysis circuit for the OPA2694. A current-feedback op amp senses an error current in the inverting node (as opposed to a differential input error voltage for a voltage-feedback op amp) and passes this on to the output through an internal frequency dependent transimpedance gain. The Typical Characteristics show this open-loop transimpedance response. This is analogous to the open-loop voltage gain curve for a voltage-feedback op amp. Developing the transfer function for the circuit of Figure 10 gives Equation (2): ǒ VO + VI 1) VO RI iERR Z(S) iERR RF RG Figure 10. Recommended Feedback Resistor Versus Noise Gain The key elements of this current-feedback op amp model are: α → Buffer gain from the noninverting input to the inverting input RI → Buffer output impedance iERR → Feedback error current signal Z(s) → Frequency dependent open-loop transimpedance gain from iERR to VO The buffer gain is typically very close to 1.00 and is normally neglected from signal gain considerations. It will, however, set the CMRR for a single op amp differential amplifier configuration. For a buffer gain α < 1.0, the CMRR = –20 × log (1– α) dB. RI, the buffer output impedance, is a critical portion of the bandwidth control equation. RI for the OPA2694 is typically about 30Ω. 16 Ǔ + Z (S) aNG R )R I NG 1) F Z (S) (2) where: ǒ α ǒ R R F)RI 1) F RG NG + 1 ) VI Ǔ RF RG a 1) Ǔ RF RG This is written in a loop-gain analysis format, where the errors arising from a noninfinite open-loop gain are shown in the denominator. If Z(S) were infinite over all frequencies, the denominator of Equation (2) would reduce to 1 and the ideal desired signal gain shown in the numerator would be achieved. The fraction in the denominator of Equation (2) determines the frequency response. Equation (3) shows this as the loop-gain equation: Z (S) + Loop Gain R F ) R I NG (3) If 20 × log(RF + NG × RI) were drawn on top of the open-loop transimpedance plot, the difference between the two would be the loop gain at a given frequency. Eventually, Z(S) rolls off to equal the denominator of Equation (3), at which point the loop gain reduces to 1 (and the curves intersect). This point of equality is where the amplifier closed-loop frequency response given by Equation (2) starts to roll off, and is exactly analogous to the frequency at which the noise gain equals the open-loop voltage gain for a voltage-feedback op amp. The difference here is that the total impedance in the denominator of Equation (3) may be controlled somewhat separately from the desired signal gain (or NG). The OPA2694 is internally compensated to give a maximally flat frequency response for RF = 402Ω at NG = 2 on ±5V supplies. Evaluating the denominator of Equation (3) (which is the feedback transimpedance) gives an optimal target of 462Ω. As the signal gain changes, the contribution of the NG × RI term in the feedback transimpedance will change, but the total can be held constant by adjusting RF. Equation (4) gives an approximate equation for optimum RF over signal gain: R F + 462W * NG @ RI (4) OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 As the desired signal gain increases, this equation will eventually predict a negative RF. A somewhat subjective limit to this adjustment can also be set by holding RG to a minimum value of 20Ω. Lower values will load both the buffer stage at the input and the output stage, if RF gets too low, actually decreasing the bandwidth. Figure 11 shows the recommended RF versus NG for ±5V operation. The values for RF versus gain shown here are approximately equal to the values used to generate the Typical Characteristics. They differ in that the optimized values used in the Typical Characteristics are also correcting for board parasitics not considered in the simplified analysis leading to Equation (3). The values shown in Figure 11 give a good starting point for design where bandwidth optimization is desired. 450 Feedback Resistor (Ω ) 400 350 300 250 200 150 0 5 10 15 20 Noise Gain The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage × current, or V−I product, which is more relevant to circuit operation. Refer to the Output Voltage and Current Limitations plot in the Typical Characteristics. The X and Y axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA2694 output drive capabilities, noting that the graph is bounded by a Safe Operating Area of 1W maximum internal power dissipation. Superimposing resistor load lines onto the plot shows that the OPA2694 can drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±3.4V output swing capability, as shown in the Electrical Charateristics. The minimum specified output voltage and current over-temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the Electrical Characteristic tables. As the output transistors deliver power, the junction temperatures will increase, decreasing both VBE (increasing the available output voltage swing) and increasing the current gains (increasing the available output current). In steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications, since the output stage junction temperatures will be higher than the minimum specified operating ambient. Figure 11. Feedback Resistor vs Noise Gain The total impedance going into the inverting input may be used to adjust the closed-loop signal bandwidth. Inserting a series resistor between the inverting input and the summing junction will increase the feedback impedance (denominator of Equation (2)), decreasing the bandwidth. This approach to bandwidth control is used for the inverting summing circuit of Figure 4. The internal buffer output impedance for the OPA2694 is slightly influenced by the source impedance looking out of the noninverting input terminal. High source resistors will have the effect of increasing RI, decreasing the bandwidth. OUTPUT CURRENT AND VOLTAGE The OPA2694 provides output voltage and current capabilities that are not usually found in wideband amplifiers. Under no-load conditions at 25°C, the output voltage typically swings closer than 1.2V to either supply rail; the +25°C swing limit is within 1.2V of either rail. Into a 15Ω load (the minimum tested load), it is tested to deliver more than ±55mA. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance that may be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA2694 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds 17 OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS vs Capacitive Load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA2694. Long PCB traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA2694 output pin (see the Board Layout Guidelines section). significantly lower than earlier solutions, while the input voltage noise (2.1nV/√Hz) is lower than most unity-gain stable, wideband, voltage-feedback op amps. This low input voltage noise was achieved at the price of higher noninverting input current noise (22pA/√Hz). As long as the AC source impedance looking out of the noninverting node is less than 100Ω, this current noise will not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. Figure 12 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. DISTORTION PERFORMANCE The OPA2694 provides good distortion performance into a 100Ω load on ±5V supplies. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic will dominate the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration (see Figure 1), this is the sum of RF + RG, while in the inverting configuration it is just RF. Also, providing an additional supply decoupling capacitor (0.1μF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Characteristics show the 2nd-harmonic increasing at a little less than the expected 2x rate, while the 3rd-harmonic increases at a little less than the expected 3x rate. Where the test power doubles, the 2nd-harmonic increases by less than the expected 6dB, while the 3rd-harmonic increases by less than the expected 12dB. This also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. ENI RS Wideband, current-feedback op amps generally have a higher output noise than comparable voltage-feedback op amps. The OPA2694 offers an excellent balance between voltage and current noise terms to achieve low output noise. The inverting current noise (24pA/√Hz) is 18 IBN ERS EO RF √4kTRS √4kTRF IBI RG 4kT RG 4kT = 1.6 × 10−20 J at 290K Figure 12. Op Amp Noise Analysis Model The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation (5) shows the general form for the output noise voltage using the terms shown in Figure 12. EO + Ǹǒ 2 ENI ) ǒI BNRSǓ ) 4kTRS 2 Ǔ 2 NG2 ) ǒI BIRFǓ ) 4kTRFNG (5) Dividing this expression by the noise gain (NG = (1 + RF/RG)) will give the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 6. EN + NOISE PERFORMANCE 1/2 OPA2694 Ǹ 2 ENI ) ǒI BNR SǓ ) 4kTR S ) 2 ǒ Ǔ I BIR F NG 2 ) 4kTR F NG (6) Evaluating these two equations for the OPA2694 circuit and component values (see Figure 1) gives a total output spot noise voltage of 11.2nV/√Hz and a total equivalent input spot noise voltage of 5.6nV/√Hz. This total input-referred spot noise voltage is higher than the 2.1nV/√Hz specification for the op amp voltage noise OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. If the feedback resistor is reduced in high-gain configurations (as suggested previously), the total input-referred voltage noise given by Equation (5) will approach just the 2.1nV/√Hz of the op amp itself. For example, going to a gain of +10 using RF = 178Ω will give a total input-referred noise of 2.36nV/√Hz. Power−supply decoupling not shown. VI A current-feedback op amp like the OPA2694 provides exceptional bandwidth in high gains, giving fast pulse settling, but only moderate DC accuracy. The Electrical Characteristics show an input offset voltage comparable to high-speed, voltage-feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Whereas bias current cancellation techniques are very effective with most voltage-feedback op amps, they do not generally reduce the output DC offset for wideband, current-feedback op amps. Since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: ± (NG × VOS) ± (IBN × RS/2 × NG) ± (IBI × RF) where NG = noninverting signal gain = ± (2 × 3.2mV) ± (22μA × 25Ω × 2) ± (402Ω × 20μA) = ±6.4mV + 1.1mV ± 8.04mV = ±15.54mV A fine-scale, output offset null, or DC operating point adjustment, is sometimes required. Numerous techniques are available for introducing DC offset control into an op amp circuit. Most simple adjustment techniques do not correct for temperature drift. It is possible to combine a lower speed, precision op amp with the OPA2694 to get the DC accuracy of the precision op amp along with the signal bandwidth of the OPA2694. Figure 13 shows a noninverting G = +10 circuit that holds an output offset voltage less than ±7.5mV over-temperature with > 150MHz signal bandwidth. DIS 1/2 OPA2694 1.8kΩ VO +5V 2.86kΩ DC ACCURACY AND OFFSET CONTROL +5V −5V 180Ω OPA237 20Ω −5V 18kΩ 2kΩ Figure 13. Wideband, DC-Connected Composite Circuit This DC-coupled circuit provides very high signal bandwidth using the OPA2694. At lower frequencies, the output voltage is attenuated by the signal gain and compared to the original input voltage at the inputs of the OPA237 (this is a low-cost, precision voltage-feedback op amp with 1.5MHz gain bandwidth product). If these two do not agree (due to DC offsets introduced by the OPA2694), the OPA237 sums in a correction current through the 2.86kΩ inverting summing path. Several design considerations will allow this circuit to be optimized. First, the feedback to the OPA237 noninverting input must be precisely matched to the high-speed signal gain. Making the 2kΩ resistor to ground an adjustable resistor would allow the low- and high-frequency gains to be precisely matched. Second, the crossover frequency region where the OPA237 passes control to the OPA2694 must occur with exceptional phase linearity. These two issues reduce to designing for pole/zero cancellation in the overall transfer function. Using the 2.86kΩ resistor will nominally satisfy this requirement for the circuit in Figure 13. Perfect cancellation over process and temperature is not possible. However, this initial resistor setting and precise gain matching will minimize long-term pulse settling tails. 19 OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 THERMAL ANALYSIS Due to the high output power capability of the OPA2694, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation, as described below. In no case should the maximum junction temperature be allowed to exceed 150°C. Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 × RL) where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA2694ID (SO-8 package) in the circuit of Figure 1, with both amplifiers operating at the maximum specified ambient temperature of +85°C and driving a grounded 20Ω load to +2.5V DC: PD = 10V × 12.7mA + 2 × [52/(4 × (20Ω || 804Ω))] = 768mW Maximum TJ = +85°C + (0.45W × (125°C/W)) = 180°C This absolute worst-case condition exceeds the specified maximum junction temperature. Remember, this is a worst-case internal power dissipation—use your actual signal and load to compute PDL. The highest possible internal dissipation will occur if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. The Output Voltage and Current Limitations plot shown in the Typical Characteristics includes a boundary for 1W maximum internal power dissipation under these conditions. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier like the OPA2694 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted 20 capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25”) from the power-supply pins to high-frequency 0.1μF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections (on pins 4 and 7) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2μF to 6.8μF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA2694. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC-board trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. The frequency response is primarily determined by the feedback resistor value, as described previously. Increasing its value will reduce the bandwidth, while decreasing it will give a more peaked frequency response. The 402Ω feedback resistor used in the Electrical Characteristic tables at a gain of +2 on ±5V supplies is a good starting point for design. Note that a 430Ω feedback resistor, rather than a direct short, is recommended for the unity-gain follower application. A current-feedback op amp requires a feedback resistor even in the unity-gain follower configuration to control stability. d) Connections to other wideband devices on the board may be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 and set RS from the plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS, since the OPA2694 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary onboard, and in fact, a higher impedance environment will improve distortion, as shown in the Distortion versus Load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA2694 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA2694 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Recommended RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. INPUT AND ESD PROTECTION The OPA2694 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies, as shown in Figure 14. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the OPA2694), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible, since high values degrade both noise performance and frequency response. +VCC External Pin Internal Circuitry −VCC Figure 14. Internal ESD Protection e) Socketing a high-speed part like the OPA2694 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2694 directly onto the board. 21 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) OPA2694ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 2694 OPA2694IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 2694 OPA2694IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 2694 OPA2694IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 2694 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device OPA2694IDR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA2694IDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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