P89LPC9102/9103/9107 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable flash with 8-bit A/D converter Rev. 03 — 10 July 2007 Product data sheet 1. General description The P89LPC9102/9103/9107 are single-chip microcontrollers in low-cost 10-pin and 14-pin packages based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9102/9103/9107 in order to reduce component count, board space, and system cost. 2. Features 2.1 Principal features n 1 kB byte-erasable flash code memory organized into 256-byte sectors and 16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. n 128-byte RAM data memory. n Two 16-bit timer/counters (P89LPC9102/9107). Two 16-bit timers (P89LPC9103) n 23-bit system timer that can also be used as a RTC. n Four input multiplexed 8-bit A/D converter/single DAC output. One analog comparator with selectable reference. n Enhanced UART with fractional baud rate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities (P89LPC9103/9107). n High-accuracy internal RC oscillator option, factory calibrated to 1 %, allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. n VDD operating range of 2.4 V to 3.6 V with 5 V tolerant I/O pins (may be pulled up or driven to 5.5 V). n Up to 10 (P89LPC9107) or eight (P89LPC9102/9103) I/O pins when using internal oscillator and reset options. n Ultra-small 10-pin HVSON package (P89LPC9102/9103). 14-pin TSSOP and DIP packages (P89LPC9107). 2.2 Additional features n A high performance 80C51 CPU provides instruction cycle times of 136 ns to 272 ns for all instructions except multiply and divide when using the internal 7.3728 MHz RC oscillator in clock doubling mode (111 ns to 222 ns when using an external 18 MHz clock). A lower clock frequency for the same performance results in power savings and reduced EMI. P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core n In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage. n Serial flash ICP allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. n Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values. n Low voltage reset (Brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt. n Idle mode and two different reduced power Power-down modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical Power-down mode current is less than 1 µA (total Power-down mode with voltage comparators disabled). n Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available. n Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. n Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. n LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip. n Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. n Only power and ground connections are required to operate the P89LPC9102/9103/9107 when internal reset option is selected. n Four interrupt priority levels. n Two keypad interrupt inputs. n Second data pointer. n External clock input. n Clock output (P89LPC9102/9107). n Schmitt trigger port inputs. n Emulation support. 3. Product comparison overview Table 1 highlights the differences between these two devices. For a complete list of device features, please see Section 2 “Features”. Table 1. Product comparison overview Type number UART T0 toggle/PWM T1 toggle/PWM CLKOUT P89LPC9102 - X X X P89LPC9103 X - - - P89LPC9107 X X X X P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 2 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 4. Ordering information Table 2. Ordering information Type number Package Name Description HVSON10 plastic thermal enhanced very thin small outline package; no leads; SOT650-1 10 terminals; body 3 × 3 × 0.85 mm P89LPC9107FDH TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 P89LPC9107FN DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 P89LPC9102FTK P89LPC9103FTK Version 4.1 Ordering options Table 3. Ordering options Type number Temperature range Frequency P89LPC9102FTK −40 °C to +85 °C internal RC or watchdog timer P89LPC9103FTK P89LPC9107FDH P89LPC9107FN P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 3 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 5. Block diagram P89LPC9102 ACCELERATED 2-CLOCK 80C51 CPU 1 kB FLASH 128 BYTE RAM internal bus AD10 AD11 AD12 AD13 DAC1 P1.2, P1.5 PORT 1 CONFIGURABLE I/Os ADC1/DAC1 P0[1:5], P0.7 PORT 0 CONFIGURABLE I/Os REAL-TIME CLOCK/ SYSTEM TIMER KEYPAD INTERRUPT TIMER 0 TIMER 1 WATCHDOG TIMER AND OSCILLATOR ANALOG COMPARATORS KBI1 KBI2 PROGRAMMABLE OSCILLATOR DIVIDER CLKOUT CLKIN CONFIGURABLE OSCILLATOR T0 T1 CIN1A CIN1B CPU clock ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER OPTION POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) 002aaa967 Fig 1. Block diagram of P89LPC9102 P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 4 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core P89LPC9103 ACCELERATED 2-CLOCK 80C51 CPU TXD 1 kB FLASH UART RXD internal bus P1.0, P1.1, P1.5 PORT 1 CONFIGURABLE I/Os 128 BYTE RAM P0[1:5] PORT 0 CONFIGURABLE I/Os ADC1/DAC1 KEYPAD INTERRUPT REAL-TIME CLOCK/ SYSTEM TIMER WATCHDOG TIMER AND OSCILLATOR TIMER 0 TIMER 1 KBI1 KBI2 PROGRAMMABLE OSCILLATOR DIVIDER CLKIN CONFIGURABLE OSCILLATOR CPU clock ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER OPTION AD10 AD11 AD12 AD13 DAC1 CIN1A ANALOG COMPARATORS CIN1B POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) 002aaa968 Fig 2. Block diagram of P89LPC9103 P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 5 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core P89LPC9107 ACCELERATED 2-CLOCK 80C51 CPU TXD 1 kB FLASH UART RXD internal bus P1[0:2], P1.5 PORT 1 CONFIGURABLE I/Os 128 BYTE RAM P0[1:5], P0.7 PORT 0 CONFIGURABLE I/Os ADC1/DAC1 KBI1 KEYPAD INTERRUPT KBI2 REAL-TIME CLOCK/ SYSTEM TIMER WATCHDOG TIMER AND OSCILLATOR CONFIGURABLE OSCILLATOR CLKIN T0 TIMER 0 TIMER 1 PROGRAMMABLE OSCILLATOR DIVIDER CLKOUT AD10 AD11 AD12 AD13 DAC1 T1 CIN1A ANALOG COMPARATORS CPU clock ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER OPTION CIN1B POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) 002aab100 Fig 3. Block diagram of P89LPC9107 6. Functional diagram VDD DAC1 AD13 CLKIN AD11 AD12 AD10 CLKOUT CIN1A CMPREF KBI2 CIN1B KBI1 T1 VSS PORT 1 PORT 0 RST T0 P89LPC9102 002aaa971 Fig 4. Functional diagram of P89LPC9102 P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 6 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core VDD DAC1 AD13 CLKIN AD11 AD12 AD10 CIN1A CMPREF KBI2 CIN1B KBI1 PORT 0 VSS PORT 1 RST RXD TXD PORT 1 RST RXD TXD T0 P89LPC9103 002aaa972 Fig 5. Functional diagram of P89LPC9103 VDD DAC1 AD13 CLKIN AD11 AD12 AD10 CLKOUT CIN1A CMPREF KBI2 CIN1B KBI1 T1 PORT 0 VSS P89LPC9107 002aab084 Fig 6. Functional diagram of P89LPC9107 P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 7 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 7. Pinning information 7.1 Pinning terminal 1 index area P0.2/KBI2/AD11 1 10 P0.3/CIN1B/AD12 P1.5/RST 2 9 P0.4/CIN1A/AD13/DAC1 VSS 3 8 P0.5/CMPREF/CLKIN P0.1/KBI1/AD10 4 7 VDD P1.2/T0 5 6 P0.7/T1/CLKOUT LPC9102 002aaa969 Transparent top view Fig 7. P89LPC9102 pinning (HVSON10) terminal 1 index area P0.2/KBI2/AD11 1 10 P0.3/CIN1B/AD12 P1.5/RST 2 9 P0.4/CIN1A/AD13/DAC1 VSS 3 8 P0.5/CMPREF/CLKIN P0.1/KBI1/AD10 4 7 VDD P1.0/TXD 5 6 P1.1/RXD LPC9103 002aaa970 Transparent top view Fig 8. P89LPC9103 pinning (HVSON10) P0.2/KBI2/AD11 1 14 P0.3/CIN1B/AD12 n.c. 2 13 n.c. P1.5/RST 3 VSS 4 P0.1/KBI1/AD10 5 10 VDD P1.0/TXD 6 9 P1.1/RXD P1.2/T0 7 8 P0.7/T1/CLKOUT 12 P0.4/CIN1A/AD13/DAC1 LPC9107 11 P0.5/CMPREF/CLKIN 002aab083 Fig 9. P89LPC9107 pinning (TSSOP14) P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 8 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core P0.2/KBI2/AD11 1 14 P0.3/CIN1B/AD12 n.c. 2 13 n.c. P1.5/RST 3 12 P0.4/CIN1A/AD13/DAC1 VSS 4 P0.1/KBI1/AD10 5 P1.0/TXD 6 9 P1.1/RXD P1.2/T0 7 8 P0.7/T1/CLKOUT LPC9107 11 P0.5/CMPREF/CLKIN 10 VDD 002aac987 Fig 10. P89LPC9107 pinning (DIP14) P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 9 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 7.2 Pin description Table 4. P89LPC9102 pin description Symbol Pin P0.1 to P0.5, P0.7 Type Description I/O Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input-only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 “Port configurations” and Table 12 “Static characteristics” for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: P0.1/KBI1/ AD10 P0.2/KBI2/ AD11 P0.3/CIN1B/ AD12 P0.4/CIN1A/ AD13/DAC1 4 1 10 9 P0.5/CMPRE F/CLKIN 8 P0.7/T1/ CLKOUT 6 P1.2, P1.5 I/O P0.1 — Port 0 bit 1. I KBI1 — Keyboard input 1. I AD10 — ADC1 channel 0 analog input. I/O P0.2 — Port 0 bit 2. I KBI2 — Keyboard input 2. I AD11 — ADC1 channel 1 analog input. I/O P0.3 — Port 0 bit 3. I CIN1B — Comparator 1 positive input. I AD12 — ADC1 channel 2 analog input. I/O P0.4 — Port 0 bit 4. I CIN1A — Comparator 1 positive input. I AD13 — ADC1 channel 3 analog input. O DAC1 — Digital to analog converter output. I/O P0.5 — Port 0 bit 5. I CMPREF — Comparator reference (negative) input. I CLKIN — External clock input. I/O P0.7 — Port 0 bit 7. I/O T1 — Timer/counter 1 external count input or overflow/PWM output. I CLKOUT — Clock output. I/O Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1 latches are configured in the input-only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.12.1 “Port configurations” and Table 12 “Static characteristics” for details. P1.5 is input-only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: P1.2/T0 5 I/O P1.2 — Port 1 bit 2. I/O T0 — Timer/counter 0 external count input or overflow/PWM output. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 10 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core Table 4. P89LPC9102 pin description …continued Symbol Pin Type Description P1.5/RST 2 I P1.5 — Port 1 bit 5 (input-only). I RST — External Reset input during power-on or if selected via User Configuration Register 1 (UCFG1). When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. VSS 3 I Ground: 0 V reference. VDD 7 I Power supply: This is the power supply voltage for normal operation as well as Idle mode and Power-down mode. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 11 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core Table 5. P89LPC9103 pin description Symbol Pin P0.1 to P0.5 Type Description I/O Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input-only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 “Port configurations” and Table 12 “Static characteristics” for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: P0.1/KBI1/ AD10 4 P0.2/KBI2/ AD11 1 P0.3/CIN1B/ AD12 P0.4/CIN1A/ AD13/DAC1 10 9 P0.5/CMPREF/ 6 CLKIN P1.0 to P1.5 I/O P0.1 — Port 0 bit 1. I KBI1 — Keyboard input 1. I AD10 — ADC1 channel 0 analog input. I/O P0.2 — Port 0 bit 2. I KBI2 — Keyboard input 2. I AD11 — ADC1 channel 1 analog input. I/O P0.3 — Port 0 bit 3. I CIN1B — Comparator 1 positive input. I AD12 — ADC1 channel 2 analog input. I/O P0.4 — Port 0 bit 4. I CIN1A — Comparator 1 positive input. I AD13 — ADC1 channel 3 analog input. O DAC1 — Digital to analog converter output. I/O P0.5 — Port 0 bit 5. I CMPREF — Comparator reference (negative) input. I CLKIN — External clock input. I/O Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1 latches are configured in the input-only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.12.1 “Port configurations” and Table 12 “Static characteristics” for details. P1.5 is input-only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: P1.0/TXD P1.1/RXD 5 6 I/O P1.0 — Port 1 bit 0. O TXD — Serial port transmitter data. I/O P1.1 — Port 1 bit 1. I RXD — Serial port receiver data. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 12 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core Table 5. P89LPC9103 pin description …continued Symbol Pin Type Description P1.5/RST 2 I P1.5 — Port 1 bit 5 (input-only). I RST — External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. VSS 3 I Ground: 0 V reference. VDD 7 I Power supply: This is the power supply voltage for normal operation as well as Idle mode and Power-down mode. Table 6. P89LPC9107 pin description Symbol Pin P0.1 to P0.5, P0.7 Type Description I/O Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input-only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 “Port configurations” and Table 12 “Static characteristics” for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: P0.1/KBI1/ AD10 P0.2/KBI2/ AD11 5 1 P0.3/CIN1B/ AD12 14 P0.4/CIN1A/ AD13/DAC1 12 P0.5/CMPREF/ 11 CLKIN P0.7/T1/ CLKOUT 8 I/O P0.1 — Port 0 bit 1. I KBI1 — Keyboard input 1. I AD10 — ADC1 channel 0 analog input. I/O P0.2 — Port 0 bit 2. I KBI2 — Keyboard input 2. I AD11 — ADC1 channel 1 analog input. I/O P0.3 — Port 0 bit 3. I CIN1B — Comparator 1 positive input. I AD12 — ADC1 channel 2 analog input. I/O P0.4 — Port 0 bit 4. I CIN1A — Comparator 1 positive input. I AD13 — ADC1 channel 3 analog input. O DAC1 — Digital to analog converter output. I/O P0.5 — Port 0 bit 5. I CMPREF — Comparator reference (negative) input. I CLKIN — External clock input. I/O P0.7 — Port 0 bit 7. I/O T1 — Timer/counter 1 external count input or overflow/PWM output. I CLKOUT — Clock output. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 13 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core Table 6. P89LPC9107 pin description …continued Symbol Pin P1.0 to P1.2, P1.5 Type Description I/O Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1 latches are configured in the input-only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.12.1 “Port configurations” and Table 12 “Static characteristics” for details. P1.5 is input-only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: P1.0/TXD 6 P1.1/RXD 9 P1.2/T0 7 P1.5/RST 3 I/O P1.0 — Port 1 bit 0. O TXD — Serial port transmitter data. I/O P1.1 — Port 1 bit 1. I RXD — Serial port receiver data. I/O P1.2 — Port 1 bit 2. I/O T0 — Timer/counter 0 external count input or overflow/PWM output. I P1.5 — Port 1 bit 5 (input-only). I RST — External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. VSS 4 I Ground: 0 V reference. VDD 10 I Power supply: This is the power supply voltage for normal operation as well as Idle mode and Power-down mode. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 14 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 8. Functional description Remark: Please refer to the P89LPC9102/9103/9107 User manual UM10112 for a more detailed functional description. 8.1 Special function registers Remark: Special Function Registers (SFRs) accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. • SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows: – ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives. – ‘0’ must be written with ‘0’, and will return a ‘0’ when read. – ‘1’ must be written with ‘1’, and will return a ‘1’ when read. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 15 of 61 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors P89LPC9102_9103_9107_3 Product data sheet Table 7. P89LPC9102 special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 E6 E5 Reset value LSB E4 E3 E2 E1 Hex Binary 00 0000 0000 ADCS10 00 0000 0000 E0 E0H ADCON1 A/D control register 1 97H ENBI1 ENADCI 1 TMM1 - ADCI1 ENADC1 ADCS11 ADINS A/D input select A3H AD13 AD12 AD11 AD10 - - - - 00 0000 0000 ADMODA A/D mode register A C0H BNDI1 BURST1 SCC1 SCAN1 - - - - 00 0000 0000 ADMODB A/D mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 - BSA1 - 00 000x 0000 AD1BH A/D_1 boundary high register C4H FF 1111 1111 AD1BL A/D_1 boundary low register BCH 00 0000 0000 AD1DAT0 A/D_1 data register 0 D5H 00 0000 0000 AD1DAT1 A/D_1 data register 1 D6H 00 0000 0000 AD1DAT2 A/D_1 data register 2 D7H 00 0000 0000 AD1DAT3 A/D_1 data register 3 F5H 00 0000 0000 A2H 00[1] 0000 00x0 00 0000 0000 00 xx00 0000 AUXR1 Auxiliary function register B* B register F0H CMP1 Comparator 1 control register ACH DIVM CPU clock divide-by-M control 95H 00 0000 0000 DPTR Data pointer (2 bytes) Bit address CLKLP EBRR ENT1 ENT0 SRST 0 - DPS F7 F6 F5 F4 F3 F2 F1 F0 - - CE1 CP1 CN1 - CO1 CMF1 16 of 61 © NXP B.V. 2007. All rights reserved. DPH Data pointer high 83H 00 0000 0000 DPL Data pointer low 82H 00 0000 0000 FMADRH Program flash address high E7H 00 0000 0000 FMADRL Program flash address low E6H 00 0000 0000 FMCON Program flash Control (Read) E4H 70 0111 0000 E5H 00 0000 0000 A8H 00[1] 0000 0000 Program flash Control (Write) FMDATA IEN0* Program flash data Interrupt enable 0 BUSY - - - HVA HVE SV OI FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 FMCMD. 3 FMCMD. 2 FMCMD. 1 FMCMD. 0 EA EWDRT EBO - ET1 - ET0 - P89LPC9102/9103/9107 Accumulator 8-bit microcontrollers with two-clock accelerated 80C51 core Rev. 03 — 10 July 2007 ACC* xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR Bit functions and addresses addr. MSB Bit address IEN1* Interrupt enable 1 E8H Bit address IP0* IP0H Interrupt priority 0 B8H Interrupt priority 0 high B7H Bit address IP1* Interrupt priority 1 F8H Reset value LSB Hex Binary 00[1] 00x0 0000 EF EE ED EC EB EA E9 E8 EAD - - - - EC EKBI - BF BE BD BC BB BA B9 B8 - PWDRT PBO - PT1 - PT0 - 00[1] x000 0000 00[1] x000 0000 - PWDRT H PBOH - PT1H - PT0H - FF FE FD FC FB FA F9 F8 PAD - - - - PC PKBI - 00[1] 00x0 0000 00x0 0000 F7H PADH - - - - PCH PKBIH - Keypad control register 94H - - - - - - PATN _SEL KBIF 00[1] xxxx xx00 KBMASK Keypad interrupt mask register 86H - - - KBMASK KBMASK .2 .1 - - 00 xxxx x00x KBPATN Keypad pattern register 93H - - - - KBPATN. KBPATN. 2 1 - - FF xxxx x11x 87 86 85 84 83 82 81 80 CLKOUT/ T1 - CMPREF /CLKIN CIN1A CIN1B CIN2A /KBI2 KBI1 - 97 96 95 94 93 92 91 90 RST - - T0 - - P0* Port 0 80H Bit address [2] P1* Port 1 90H - - P0M1 Port 0 output mode 1 84H (P0M1.7) - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) - FF 1111 1111 P0M2 Port 0 output mode 2 85H (P0M2.7) - (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) - 00 0000 0000 - FF[1] 1111 1111 00[1] 0000 0000 P1M1 Port 1 output mode 1 91H 92H - 17 of 61 © NXP B.V. 2007. All rights reserved. P1M2 Port 1 output mode 2 PCON Power control register PCONA Power control register A PCONB reserved for Power control register B B6H - PSW* Program status word D0H PT0AD Port 0 digital input disable F6H - - - - - - 87H - - B5H RTCPD Bit address - - (P1M1.2) - - - (P1M2.2) - - BOPD BOI GF1 GF0 PMOD1 PMOD0 VCPD ADPD - - - - - - - - D7 D6 D5 D4 D3 D2 D1 D0 CY AC F0 RS1 RS0 OV F1 - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 0000 0000 00[1] 0000 0000 00[1] xxxx xxxx P 00 0000 0000 - 00 xx00 000x P89LPC9102/9103/9107 Interrupt priority 1 high KBCON 8-bit microcontrollers with two-clock accelerated 80C51 core Rev. 03 — 10 July 2007 IP1H 00[1] Bit address NXP Semiconductors P89LPC9102_9103_9107_3 Product data sheet Table 7. P89LPC9102 special function registers …continued * indicates SFRs that are bit addressable. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR Bit functions and addresses addr. MSB Reset value LSB RSTSRC Reset source register DFH - - BOF POF - R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN RTCH Real-time clock register high Hex Binary [3] 60[4] 011x xx00 D2H 00[4] 0000 0000 D3H 00[4] 0000 0000 07 0000 0111 00 xxx0 xxx0 00 0000 0000 RTCL Real-time clock register low SP Stack pointer 81H TAMOD Timer 0 and 1 auxiliary mode 8FH Bit address NXP Semiconductors P89LPC9102_9103_9107_3 Product data sheet Table 7. P89LPC9102 special function registers …continued * indicates SFRs that are bit addressable. - - - T1M2 - - - T0M2 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 - - - - 88H TH0 Timer 0 high 8CH 00 0000 0000 TH1 Timer 1 high 8DH 00 0000 0000 TL0 Timer 0 low 8AH 00 0000 0000 TL1 Timer 1 low 8BH 00 0000 0000 TMOD Timer 0 and 1 mode 89H - - T1M1 T1M0 - - T0M1 T0M0 00 0000 0000 TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 [4][5] WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK [4][6] WDL Watchdog load C1H WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H FF 1111 1111 18 of 61 © NXP B.V. 2007. All rights reserved. [1] Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read. [2] All ports are in input-only (high-impedance) state after power-up. [3] The RSTSRC register reflects the cause of the P89LPC9102/9103/9107 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. [4] The only reset source that affects these SFRs is power-on reset. [5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1s, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog timer reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. P89LPC9102/9103/9107 Timer 0 and 1 control 8-bit microcontrollers with two-clock accelerated 80C51 core Rev. 03 — 10 July 2007 TCON* xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors P89LPC9102_9103_9107_3 Product data sheet Table 8. P89LPC9103 special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 E6 E5 Reset value LSB E4 E3 E2 E1 Hex Binary 00 0000 0000 ADCS10 00 0000 0000 E0 Accumulator E0H ADCON1 A/D control register 1 97H ENBI1 ENADCI 1 TMM1 - ADCI1 ENADC1 ADCS11 ADINS A/D input select A3H AD13 AD12 AD11 AD10 - - - - 00 0000 0000 ADMODA A/D mode register A C0H BNDI1 BURST1 SCC1 SCAN1 - - - - 00 0000 0000 ADMODB A/D mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 - BSA1 - 00 000x 0000 AD1BH A/D_1 boundary high register C4H FF 1111 1111 AD1BL A/D_1 boundary low register BCH 00 0000 0000 AD1DAT0 A/D_1 data register 0 D5H 00 0000 0000 AD1DAT1 A/D_1 data register 1 D6H 00 0000 0000 AD1DAT2 A/D_1 data register 2 D7H 00 0000 0000 AD1DAT3 A/D_1 data register 3 F5H 00 0000 0000 A2H 00[1] 0000 00x0 Auxiliary function register B* B register F0H 00 0000 0000 BRGR0[2] Baud rate generator rate low BEH 00 0000 0000 BRGR1[2] Baud rate generator rate high BFH 00 0000 0000 xxxx xx00 Bit address CLKLP EBRR - - SRST 0 - DPS F7 F6 F5 F4 F3 F2 F1 F0 BRGCON Baud rate generator control BDH - - - - - - SBRGS BRGEN 00[2] CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 - CO1 CMF1 00[1] xx00 0000 DIVM CPU clock divide-by-M control 95H 00 0000 0000 DPTR Data pointer (2 bytes) 19 of 61 © NXP B.V. 2007. All rights reserved. DPH Data pointer high 83H 00 0000 0000 DPL Data pointer low 82H 00 0000 0000 FMADRH Program flash address high E7H 00 0000 0000 FMADRL Program flash address low E6H 00 0000 0000 FMCON Program flash Control (Read) E4H 70 0111 0000 Program flash Control (Write) BUSY - - - HVA HVE SV OI FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 FMCMD. 3 FMCMD. 2 FMCMD. 1 FMCMD. 0 P89LPC9102/9103/9107 AUXR1 8-bit microcontrollers with two-clock accelerated 80C51 core Rev. 03 — 10 July 2007 ACC* xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR Bit functions and addresses addr. MSB FMDATA Program flash data E5H IEN0* Interrupt enable 0 A8H Bit address IEN1* Interrupt enable 1 IP0* Interrupt priority 0 E8H Bit address IP0H Interrupt priority 0 high IP1* Interrupt priority 1 B8H B7H Bit address Interrupt priority 1 high F7H Keypad control register 94H KBMASK Keypad interrupt mask register 86H KBPATN Keypad pattern register 93H Bit address 80H EWDRT EBO ES/ESR ET1 - ET0 - EF EE ED EC EB EA E9 E8 EAD EST - - - EC EKBI - Hex Binary 00 0000 0000 00 0000 0000 00[1] 00x0 0000 BF BE BD BC BB BA B9 B8 - PWDRT PBO PS/PSR PT1 - PT0 - 00[1] x000 0000 PT0H - 00[1] x000 0000 PWDRT H PBOH PSH /PSRH PT1H FF FE FD FC FB FA F9 F8 PAD PST - - - PC PKBI - 00[1] 00x0 0000 - 00[1] 00x0 0000 KBIF 00[1] xxxx xx00 PADH - PSTH - - - - PCH - PKBIH - - - - PATN _SEL - - - - KBMASK KBMASK .2 .1 - 00 xxxx x00x - - - - - KBPATN. KBPATN. 2 1 - FF xxxx x11x 87 86 85 84 83 82 81 80 - - CMPREF /CLKIN CIN1A CIN1B KBI2 KBI1 - [3] P0* Port 0 97 96 95 94 93 92 91 90 P1* Port 1 90H - - RST - - - RXD TXD P0M1 Port 0 output mode 1 84H - - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) - FF 1111 1111 P0M2 Port 0 output mode 2 85H - - (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) - 00 0000 0000 FF[1] 1111 1111 Bit address 20 of 61 © NXP B.V. 2007. All rights reserved. P1M1 Port 1 output mode 1 91H - - - - - - (P1M1.1) (P1M1.0) P1M2 Port 1 output mode 2 92H - - - - - - (P1M2.1) (P1M2.0) 00[1] 0000 0000 PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 00 0000 0000 SPD 00[1] 0000 0000 - 00[1] xxxx xxxx PCONA PCONB Power control register A reserved for Power control register B B5H B6H RTCPD - VCPD - - ADPD - - - PMOD0 - P89LPC9102/9103/9107 KBCON LSB 8-bit microcontrollers with two-clock accelerated 80C51 core Rev. 03 — 10 July 2007 IP1H F8H Reset value EA - NXP Semiconductors P89LPC9102_9103_9107_3 Product data sheet Table 8. P89LPC9103 special function registers …continued * indicates SFRs that are bit addressable. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR Bit functions and addresses addr. MSB Bit address Reset value LSB Hex Binary 00 0000 0000 xx00 000x D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 [4] RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN RTCH Real-time clock register high 60[5] 011x xx00 D2H 00[5] 0000 0000 0000 0000 0000 0000 RTCL Real-time clock register low D3H 00[5] SADDR Serial port address register A9H 00 SADEN Serial port address enable B9H 00 0000 0000 SBUF Serial port data buffer register 99H xx xxxx xxxx 9F 9E 9D 9C 9B 9A 99 98 SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000 SSTAT Serial port extended status register BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 SP Stack pointer 81H 07 0000 0111 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 - - - - TCON* Timer 0 and 1 control 88H 00 0000 0000 TH0 Timer 0 high 8CH 00 0000 0000 TH1 Timer 1 high 8DH 00 0000 0000 TL0 Timer 0 low 8AH 00 0000 0000 TL1 Timer 1 low 8BH 00 0000 0000 TMOD Timer 0 and 1 mode 89H 00 0000 0000 - - T1M1 T1M0 - - T0M1 T0M0 21 of 61 © NXP B.V. 2007. All rights reserved. TRIM Internal oscillator trim register 96H RCCLK - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 [5][6] WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK [5][7] WDL Watchdog load C1H WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H FF 1111 1111 [1] Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. P89LPC9102/9103/9107 Bit address 8-bit microcontrollers with two-clock accelerated 80C51 core Rev. 03 — 10 July 2007 Bit address NXP Semiconductors P89LPC9102_9103_9107_3 Product data sheet Table 8. P89LPC9103 special function registers …continued * indicates SFRs that are bit addressable. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx All ports are in input-only (high-impedance) state after power-up. [4] The RSTSRC register reflects the cause of the P89LPC9102/9103/9107 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. [5] The only reset source that affects these SFRs is power-on reset. [6] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [7] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1s, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog timer reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. NXP Semiconductors P89LPC9102_9103_9107_3 Product data sheet [3] P89LPC9102/9103/9107 22 of 61 © NXP B.V. 2007. All rights reserved. 8-bit microcontrollers with two-clock accelerated 80C51 core Rev. 03 — 10 July 2007 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors P89LPC9102_9103_9107_3 Product data sheet Table 9. P89LPC9107 special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 E6 E5 Reset value LSB E4 E3 E2 E1 Hex Binary 00 0000 0000 ADCS10 00 0000 0000 E0 Accumulator E0H ADCON1 A/D control register 1 97H ENBI1 ENADCI 1 TMM1 - ADCI1 ENADC1 ADCS11 ADINS A/D input select A3H AD13 AD12 AD11 AD10 - - - - 00 0000 0000 ADMODA A/D mode register A C0H BNDI1 BURST1 SCC1 SCAN1 - - - - 00 0000 0000 ADMODB A/D mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 - BSA1 - 00 000x 0000 AD1BH A/D_1 boundary high register C4H FF 1111 1111 AD1BL A/D_1 boundary low register BCH 00 0000 0000 AD1DAT0 A/D_1 data register 0 D5H 00 0000 0000 AD1DAT1 A/D_1 data register 1 D6H 00 0000 0000 AD1DAT2 A/D_1 data register 2 D7H 00 0000 0000 AD1DAT3 A/D_1 data register 3 F5H 00 0000 0000 A2H 00[1] 0000 00x0 Auxiliary function register B* B register F0H 00 0000 0000 BRGR0[2] Baud rate generator rate low BEH 00 0000 0000 BRGR1[2] Baud rate generator rate high BFH 00 0000 0000 xxxx xx00 Bit address CLKLP EBRR ENT1 ENT0 SRST 0 - DPS F7 F6 F5 F4 F3 F2 F1 F0 BRGCON Baud rate generator control BDH - - - - - - SBRGS BRGEN 00[2] CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 - CO1 CMF1 00[1] xx00 0000 DIVM CPU clock divide-by-M control 95H 00 0000 0000 DPTR Data pointer (2 bytes) 23 of 61 © NXP B.V. 2007. All rights reserved. DPH Data pointer high 83H 00 0000 0000 DPL Data pointer low 82H 00 0000 0000 FMADRH Program flash address high E7H 00 0000 0000 FMADRL Program flash address low E6H 00 0000 0000 FMCON Program flash Control (Read) E4H 70 0111 0000 Program flash Control (Write) BUSY - - - HVA HVE SV OI FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 FMCMD. 3 FMCMD. 2 FMCMD. 1 FMCMD. 0 P89LPC9102/9103/9107 AUXR1 8-bit microcontrollers with two-clock accelerated 80C51 core Rev. 03 — 10 July 2007 ACC* xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR Bit functions and addresses addr. MSB FMDATA Program flash data E5H IEN0* Interrupt enable 0 A8H Bit address IEN1* Interrupt enable 1 IP0* Interrupt priority 0 E8H Bit address IP0H Interrupt priority 0 high IP1* Interrupt priority 1 B8H B7H Bit address Interrupt priority 1 high F7H Keypad control register 94H KBMASK Keypad interrupt mask register 86H KBPATN Keypad pattern register 93H Bit address 80H EWDRT EBO ES/ESR ET1 - ET0 - EF EE ED EC EB EA E9 E8 EAD EST - - - EC EKBI - Hex Binary 00 0000 0000 00 0000 0000 00[1] 00x0 0000 BF BE BD BC BB BA B9 B8 - PWDRT PBO PS/PSR PT1 - PT0 - 00[1] x000 0000 PT0H - 00[1] x000 0000 PWDRT H PBOH PSH /PSRH PT1H FF FE FD FC FB FA F9 F8 PAD PST - - - PC PKBI - 00[1] 00x0 0000 - 00[1] 00x0 0000 KBIF 00[1] xxxx xx00 PADH - PSTH - - - - PCH - PKBIH - - - - PATN _SEL - - - - KBMASK KBMASK .2 .1 - 00 xxxx x00x - - - - - KBPATN. KBPATN. 2 1 - FF xxxx x11x 87 86 85 84 83 82 81 80 - - CMPREF /CLKIN CIN1A CIN1B KBI2 KBI1 - [3] P0* Port 0 97 96 95 94 93 92 91 90 P1* Port 1 90H - - RST - - - RXD TXD P0M1 Port 0 output mode 1 84H - - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) - FF 1111 1111 P0M2 Port 0 output mode 2 85H - - (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) - 00 0000 0000 FF[1] 1111 1111 Bit address 24 of 61 © NXP B.V. 2007. All rights reserved. P1M1 Port 1 output mode 1 91H - - - - - - (P1M1.1) (P1M1.0) P1M2 Port 1 output mode 2 92H - - - - - - (P1M2.1) (P1M2.0) 00[1] 0000 0000 PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 00 0000 0000 SPD 00[1] 0000 0000 - 00[1] xxxx xxxx PCONA PCONB Power control register A reserved for Power control register B B5H B6H RTCPD - VCPD - - ADPD - - - PMOD0 - P89LPC9102/9103/9107 KBCON LSB 8-bit microcontrollers with two-clock accelerated 80C51 core Rev. 03 — 10 July 2007 IP1H F8H Reset value EA - NXP Semiconductors P89LPC9102_9103_9107_3 Product data sheet Table 9. P89LPC9107 special function registers …continued * indicates SFRs that are bit addressable. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR Bit functions and addresses addr. MSB Bit address Reset value LSB Hex Binary 00 0000 0000 xx00 000x D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 [4] RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN RTCH Real-time clock register high 60[5] 011x xx00 D2H 00[5] 0000 0000 0000 0000 0000 0000 RTCL Real-time clock register low D3H 00[5] SADDR Serial port address register A9H 00 SADEN Serial port address enable B9H 00 0000 0000 SBUF Serial port data buffer register 99H xx xxxx xxxx 9F 9E 9D 9C 9B 9A 99 98 SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000 SSTAT Serial port extended status register BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 SP Stack pointer 81H 07 0000 0111 P89LPC9102/9103/9107 25 of 61 © NXP B.V. 2007. All rights reserved. 8-bit microcontrollers with two-clock accelerated 80C51 core Rev. 03 — 10 July 2007 Bit address NXP Semiconductors P89LPC9102_9103_9107_3 Product data sheet Table 9. P89LPC9107 special function registers …continued * indicates SFRs that are bit addressable. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description SFR Bit functions and addresses addr. MSB Bit address Reset value LSB 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 - - - - Hex Binary 00 0000 0000 TCON* Timer 0 and 1 control 88H TH0 Timer 0 high 8CH 00 0000 0000 TH1 Timer 1 high 8DH 00 0000 0000 TL0 Timer 0 low 8AH 00 0000 0000 TL1 Timer 1 low 8BH 00 0000 0000 TMOD Timer 0 and 1 mode 89H 00 0000 0000 - - T1M1 NXP Semiconductors P89LPC9102_9103_9107_3 Product data sheet Table 9. P89LPC9107 special function registers …continued * indicates SFRs that are bit addressable. T1M0 - - T0M1 T0M0 Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK [5][7] WDL Watchdog load C1H WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H FF 1111 1111 Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] All ports are in input-only (high-impedance) state after power-up. [4] The RSTSRC register reflects the cause of the P89LPC9102/9103/9107 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. [5] The only reset source that affects these SFRs is power-on reset. [6] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [7] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1s, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog timer reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. 26 of 61 © NXP B.V. 2007. All rights reserved. P89LPC9102/9103/9107 [1] 8-bit microcontrollers with two-clock accelerated 80C51 core Rev. 03 — 10 July 2007 TRIM [5][6] P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 8.2 Enhanced CPU The P89LPC9102/9103/9107 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 8.3 Clocks 8.3.1 Clock definitions The P89LPC9102/9103/9107 device has internal clocks as defined below: OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of the clock sources (see Figure 11 “Block diagram of P89LPC9102 oscillator control”) and can also be optionally divided to a slower frequency (see Section 8.8 “CCLK modification: DIVM register”). Note: fosc is defined as the OSCCLK frequency. CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when enabled, provides an output frequency of 14.746 MHz. PCLK — Clock for the various peripheral devices and is CCLK⁄2. 8.3.2 CPU clock (CCLK) The P89LPC9102/9103/9107 provides user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash memory is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, and an external clock input. 8.4 On-chip RC oscillator option The P89LPC9102/9103/9107 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature. End-user applications can write to the Trim register to adjust the on-chip RC oscillator to other frequencies. When the clock doubler option is enabled (UCFG1.3 = 1) the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower. The RCCLK bit (TRIM.7) can be used to switch between the clock source selected by UCFG1 and the internal RC oscillator. This allows a low frequency source such as the WDT or low speed external source to clock the device in order to save power and then switch to the higher speed internal RC oscillator to perform processing. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 27 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 8.5 Watchdog oscillator option The watchdog timer has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed. RTC ADC1/ DAC1 CLKIN RC OSCILLATOR WITH CLOCK DOUBLER OPTION OSCCLK CCLK DIVM CPU ÷2 (7.3728 MHz or 14.7456 MHz) WDT WATCHDOG OSCILLATOR (400 kHz) PCLK TIMER 0 TIMER 1 002aaa973 Fig 11. Block diagram of P89LPC9102 oscillator control RTC ADC1/ DAC1 CLKIN RC OSCILLATOR WITH CLOCK DOUBLER OPTION OSCCLK DIVM CCLK CPU ÷2 (7.3728 MHz or 14.7456 MHz) WDT WATCHDOG OSCILLATOR (400 kHz) PCLK BAUD RATE GENERATOR TIMER 0 TIMER 1 UART 002aaa974 Fig 12. Block diagram of P89LPC9103/9107 oscillator control 8.6 External clock input option In this configuration, the processor clock is derived from an external source driving the P0.5/CMPREF/CLKIN pin. The rate may be from 0 Hz up to 18 MHz. The P0.5/CMPREF/CLKIN pin may also be used as a standard port pin. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 28 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. 8.7 CCLK wake-up delay The P89LPC9102/9103/9107 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. 8.8 CCLK modification: DIVM register The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution. 8.9 Low power select If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0. 8.10 Memory organization The various P89LPC9102/9103/9107 memory spaces are as follows: • DATA 128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instruction other than MOVX and MOVC. All or part of the stack may be in this area. • SFR Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing. • CODE 1 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. 8.11 Interrupts The P89LPC9102 supports nine interrupt sources: timers 0 and 1, brownout detect, watchdog timer/RTC, keyboard, comparator 1, and the A/D converter. The P89LPC9103/9107 support nine interrupt sources: timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect, watchdog timer/RTC, keyboard, comparator, and the A/D converter. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 29 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level. 8.11.1 External interrupt inputs The P89LPC9102/9103/9107 has a Keypad Interrupt function. This can be used as an external interrupt input. If enabled when the P89LPC9102/9103/9107 is put into Power-down mode or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 8.14 “Power reduction modes” for details. BOF EBO RTCF ERTC (RTCCON.1) WDOVF wake-up (if in power-down) KBIF EKBI EWDRT CMF EC EA (IE0.7) TF1 ET1 interrupt to CPU TF0 ET0 ENADCI1 ADCI1 ENBI1 BNDI1 EAD 002aaa976 Fig 13. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC9102) P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 30 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core BOF EBO RTCF ERTC (RTCCON.1) WDOVF wake-up (if in power-down) KBIF EKBI EWDRT CMF EC EA (IE0.7) TF1 ET1 TI and RI/RI ES/ESR interrupt to CPU TI EST TF0 ET0 ENADCI1 ADCI1 ENBI1 BNDI1 EAD 002aaa977 Fig 14. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC9103/9107) 8.12 I/O ports The P89LPC9102/9103/9107 has either 6, 7, or 8 I/O pins depending on the reset pin option and clock source option chosen. Refer to Table 10. Table 10. Number of I/O pins available Clock source Reset option Number of I/O pins (10-pin package) Number of I/O pins (14-pin package) On-chip oscillator or watchdog oscillator No external reset (except during power-up) 8 10 External RST pin supported 7 9 No external reset (except during power-up) 7 9 External RST pin supported[1] 6 8 External clock input [1] Required for operation above 12 MHz. 8.12.1 Port configurations All but one I/O port pin on the P89LPC9102/9103/9107 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. P1.5 (RST) can only be an input and cannot be configured. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 31 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 8.12.2 Quasi-bidirectional output configuration Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. The P89LPC9102/9103/9107 is a 3 V device, however, the pins are 5 V-tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged. A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit. 8.12.3 Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. An open-drain port pin has a Schmitt triggered input that also has a glitch suppression circuit. 8.12.4 Input-only configuration The input-only port configuration has no output drivers. It is a Schmitt triggered input that also has a glitch suppression circuit. 8.12.5 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt triggered input that also has a glitch suppression circuit. 8.12.6 Port 0 analog functions The P89LPC9102/9103/9107 incorporates an Analog Comparator. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-only (high-impedance) mode as described in Section 8.12.4 “Input-only configuration”. Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On any reset, the PT0AD bits default to logic 0s to enable digital functions. 8.12.7 Additional port features After power-up, all pins are in Input-only mode. Please note that this is different from the LPC76x series of devices. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 32 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core • After power-up all I/O pins, except P1.5, may be configured by software. • Pin P1.5 is input-only. Every output on the P89LPC9102/9103/9107 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 12 “Static characteristics” for detailed specifications. All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times. 8.13 Power monitoring functions The P89LPC9102/9103/9107 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout detect. 8.13.1 Brownout detection The Brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a Brownout detection to cause a processor reset, however, it may alternatively be configured to generate an interrupt. Brownout detection may be enabled or disabled in software. If Brownout detection is enabled, the brownout condition occurs when VDD falls below the brownout trip voltage, Vbo (see Table 12 “Static characteristics”), and is negated when VDD rises above Vbo. If the P89LPC9102/9103/9107 device is to operate with a power supply that can be below 2.7 V, Brownout detect Enable (BOE) should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating. For correct activation of Brownout detect, the VDD rise and fall times must be observed. Please see Table 12 “Static characteristics” for specifications. 8.13.2 Power-on detection The Power-on Detect has a function similar to the Brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where Brownout detect can work. The Power-on detect flag (POF) in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software. 8.14 Power reduction modes The P89LPC9102/9103/9107 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and Total Power-down mode. 8.14.1 Idle mode Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 33 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 8.14.2 Slow-down mode using the DIVM register Slow-down mode is achieved by dividing down the OSCCLK frequency to generate CCLK. This division is accomplished by configuring the DIVM register to divide OSCCLK by up to 510 times. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution. 8.14.3 Power-down mode The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC9102/9103/9107 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the data retention voltage VDDR. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VDDR, therefore it is highly recommended to wake-up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited. Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during Power-down mode. These include: Brownout detect, watchdog timer, comparators (note that comparator can be powered-down separately), and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. 8.14.4 Total Power-down mode This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during Power-down mode, there will be high power consumption. Please use an external low frequency clock to achieve low power with the RTC running during Power-down mode. 8.15 Reset The P1.5/RST pin can function as either an active-LOW reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to logic 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. Remark: During a power-up sequence, the RPE selection is overridden and this pin will always function as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this input will function either as an external reset input or as a digital input as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit. Remark: During a power cycle, VDD must fall below VPOR (see Table 12 “Static characteristics”) before power is reapplied, in order to ensure a power-on reset. Reset can be triggered from the following sources: • External reset pin (during power-up or if user configured via UCFG1) P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 34 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core • • • • • Power-on detect Brownout detect Watchdog timer Software reset UART break character detect reset (P89LPC9103/9107). For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a logic 0 to the corresponding bit. More than one flag bit may be set: • During a power-on reset, both POF and BOF are set but the other flag bits are cleared. • For any other reset, previously set flag bits that have not been cleared will remain set. 8.16 Timers 0 and 1 The P89LPC9102 has two general purpose timer/counters which are similar to the standard 80C51 Timer 0 and Timer 1. These timers have five operating modes (modes 0, 1, 2, 3, and 6). Modes 0, 1, and 2 are the same for both Timers. Mode 3 is different. The P89LPC9103/9107 has two general purpose timers which are similar to the standard 80C51 Timer 0 and Timer 1. These timers have four operating modes (modes 0, 1, 2, and 3). Modes 0, 1, and 2 are the same for both Timers. Mode 3 is different. 8.16.1 Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1. 8.16.2 Mode 1 Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used. 8.16.3 Mode 2 Mode 2 configures the Timer register as an 8-bit counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1. 8.16.4 Mode 3 When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator. 8.16.5 Mode 6 (P89LPC9102/9107) In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 35 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 8.16.6 Timer overflow toggle output (P89LPC9102/9107) Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. 8.17 RTC/system timer The P89LPC9102/9103/9107 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered-down. The RTC can be a wake-up or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded again and the RTCF flag will be set. The clock source for this counter is the CCLK. Only power-on reset will reset the RTC and its associated SFRs to the default state. 8.18 UART (P89LPC9103/9107) The P89LPC9103/9107 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC9103/9107 does include an independent Baud Rate Generator. The baud rate can be selected from CCLK (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART, and CCLK⁄32 or CCLK⁄16. 8.18.1 Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. Eight bits are transmitted or received, LSB first. The baud rate is fixed at 1⁄16 of the CPU clock frequency. 8.18.2 Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 8.18.5 “Baud rate generator and selection”). 8.18.3 Mode 2 11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is not saved. The baud rate is programmable to either 1⁄16 or 1⁄32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 36 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 8.18.4 Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in section Section 8.18.5 “Baud rate generator and selection”). 8.18.5 Baud rate generator and selection The P89LPC9103/9107 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or the baud rate generator output (see Figure 15). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent Baud Rate Generator uses CCLK. timer 1 overflow (PCLK-based) SMOD1 = 1 SBRGS = 0 ÷2 SMOD1 = 0 baud rate generator (CCLK-based) baud rate modes 1 and 3 SBRGS = 1 002aaa978 Fig 15. Baud rate sources for UART (Modes 1, 3) 8.18.6 Framing error Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is logic 1, framing errors can be made available in SCON.7, respectively. If SMOD0 is logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON[7:6]) are set up when SMOD0 is logic 0. 8.18.7 Break detect Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device. 8.18.8 Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SnBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0). P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 37 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 8.18.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3) Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated when the double buffer is ready to receive new data. 8.18.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3) If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the Tx interrupt. If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. 8.19 Analog comparators One analog comparator is provided on the P89LPC9102/9103/9107. Comparator operation is such that the output is a logic 1 (which may be read in a register) when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. The comparator may be configured to cause an interrupt when the output value changes. The connections to the comparator are shown in Figure 16. The comparator functions to VDD = 2.4 V. When the comparator is first enabled, the comparator’s interrupt flag is not guaranteed to be stable for 10 microseconds. The comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. When a comparator is disabled the comparator’s output, COx, goes HIGH. If the comparator output was LOW and then is disabled, the resulting transition of the comparator output from a LOW to HIGH state will set the comparator flag, CMFx. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator flag, CMFx, after disabling the comparator. CP1 comparator (P0.4) CIN1A (P0.3) CIN1B change detect CO1 CMF1 interrupt (P0.5) CMPREF VREF EC CN1 002aaa979 Fig 16. Comparator input and output connections 8.20 Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as Vref(bg), is 1.23 V ± 3 %. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 38 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 8.21 Comparator interrupt The comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. 8.22 Comparator and power reduction modes The comparator may remain enabled when Power-down mode or Idle mode is activated, but the comparator is disabled automatically in Total Power-down mode. If the comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. The comparator consumes power in Power-down mode and Idle mode, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparator via PCONA.5 or put the device in Total Power-down mode. 8.23 Keypad interrupt (KBI) The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison. In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake-up the CPU from Idle mode or Power-down mode. This feature is particularly useful in handheld, battery powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs. 8.24 Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 39 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog timer feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 17 shows the watchdog timer in Watchdog mode. Feeding the watchdog timer requires a two-byte sequence. If PCLK is selected as the watchdog timer clock and the CPU is powered-down, the watchdog timer is disabled. The watchdog timer has a time-out period that ranges from a few µs to a few seconds. Please refer to the P89LPC9102/9103/9107 User manual UM10112 for more details. WDL (C1H) MOV WFEED1, #0A5H MOV WFEED2, #05AH watchdog oscillator PCLK ÷32 8-BIT DOWN COUNTER PRESCALER reset (1) SHADOW REGISTER WDCON (A7H) PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK 002aaa980 (1) Watchdog timer reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence. Fig 17. Watchdog timer in Watchdog mode (WDTE = 1) 8.25 Additional features 8.25.1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog timer reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets. 8.25.2 Dual data pointers The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 40 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 8.26 Flash program memory 8.26.1 General description The P89LPC9102/9103/9107 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (256 bytes) or page (16 bytes). The Chip Erase operation will erase the entire program memory. In-Circuit Programming using standard commercial programmers is available. In addition, In-Application Programming Lite (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC9102/9103/9107 flash reliably stores memory contents even after more than 400000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC9102/9103/9107 uses VDD as the supply voltage to perform the Program/Erase algorithms. 8.26.2 Features • • • • • • • • Programming and erase over the full operating voltage range. Byte-erase allowing code memory to be used for data storage. Read/Programming/Erase using ICP. Any flash program/erase operation in 2 ms. Programming with industry-standard commercial programmers. Programmable security for the code in the flash for each sector. More than 400000 minimum erase/program cycles for each byte. 20-year minimum data retention. 8.26.3 Flash organization The P89LPC9102/9103/9107 program memory consists of four 256 byte sectors. Each sector can be further divided into 16-byte pages. In addition to sector erase, page erase, and byte erase, a 16-byte page register is included which allows from 1 byte to 16 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. In addition, erasing and reprogramming of user-programmable configuration bytes including UCFG1, the Boot Status Bit, and the Boot Vector is supported. 8.26.4 Flash programming and erasing Different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IAP-Lite) under control of the application’s firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock- serial data interface. Third, the flash may be programmed or erased using a commercially available EPROM programmer which supports this device. This device does not provide for direct verification of code memory contents. Instead this device provides a 32-bit CRC result on either a sector or the entire 1 kB of user code space. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 41 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 8.26.5 In-circuit programming In-Circuit Programming is performed without removing the microcontroller from the system. The In-Circuit Programming facility consists of internal hardware resources to facilitate remote programming of the P89LPC9102/9103/9107 through a two-wire serial interface. The NXP In-Circuit Programming facility has made in-circuit programming in an embedded application, using commercially available programmers, possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC9102/9103/9107 User manual UM10112. 8.26.6 In-application programming (IAP-Lite) In-Application Programming is performed in the application under the control of the microcontroller’s firmware. The IAP facility consists of internal hardware resources to facilitate programming and erasing. The NXP In-Application Programming (IAP-Lite) has made in-application programming in an embedded application possible without additional components. This is accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC9102/9103/9107 User manual UM10112. 8.26.7 Using flash as data storage The flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage. 8.26.8 User configuration bytes Some user-configurable features of the P89LPC9102/9103/9107 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the flash byte UCFG1. Please see the P89LPC9102/9103/9107 User manual UM10112 for additional details. 8.26.9 User sector security bytes There are four user sector security bytes, each corresponding to one sector. Please see the P89LPC9102/9103/9107 User manual UM10112 for additional details. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 42 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 9. A/D Converter 9.1 General description The P89LPC9102/9103/9107 has an 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter. The A/D consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the Successive Approximation Register (SAR) drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR. A block diagram of the A/D converter is shown in Figure 18. 9.2 Features n 8-bit, 4-channel multiplexed input, successive approximation A/D converter n Four result registers n Six operating modes u Fixed channel, single conversion mode u Fixed channel, continuous conversion mode u Auto scan, single conversion mode u Auto scan, continuous conversion mode u Dual channel, continuous conversion mode u Single step mode n Two conversion start modes u Timer triggered start u Start immediately n 8-bit conversion time of ≥ 3.9 µs at an ADC clock of 3.3 MHz n Interrupt or polled operation n Boundary limits interrupt n DAC output to a port pin with high output impedance n Clock divider n Power-down mode P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 43 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 9.3 Block diagram comp + INPUT MUX SAR – 8 DAC1 CONTROL LOGIC CCLK 002aaa975 Fig 18. ADC block diagram 9.4 A/D operating modes 9.4.1 Fixed channel, single conversion mode A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after the conversion completes. 9.4.2 Fixed channel, continuous conversion mode A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result registers. An interrupt, if enabled, will be generated after every four conversions. Additional conversion results will again cycle through the four result registers, overwriting the previous results. Continuous conversions continue until terminated by the user. 9.4.3 Auto scan, single conversion mode Any combination of the four input channels can be selected for conversion. A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode. 9.4.4 Auto scan, continuous conversion mode Any combination of the four input channels can be selected for conversion. A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. The process will repeat starting with the first selected channel. Additional conversion results will again cycle through the four result registers, overwriting the previous results. Continuous conversions continue until terminated by the user. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 44 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 9.4.5 Dual channel, continuous conversion mode This is a variation of the auto scan continuous conversion mode where conversion occurs on two user-selectable inputs. The result of the conversion of the first channel is placed in result register, AD1DAT0. The result of the conversion of the second channel is placed in result register, AD1DAT1. The first channel is again converted and its result stored in AD1DAT2. The second channel is again converted and its result placed in AD1DAT3. An interrupt is generated, if enabled, after every set of four conversions (two conversions per channel). 9.4.6 Single step mode This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any combination of the four input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the A/D waits for the next start condition. May be used with any of the start modes. 9.5 Conversion start modes 9.5.1 Timer triggered start An A/D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all A/D operating modes. 9.5.2 Start immediately Programming this mode immediately starts a conversion. This start mode is available in all A/D operating modes. 9.6 Boundary limits interrupt The A/D converter has both a high and low boundary limit register. After the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary high and low registers. If the four MSBs of the conversion are outside the limit an interrupt will be generated, if enabled. If the conversion result is within the limits, the boundary limits will again be compared after all 8 bits have been converted. An interrupt will be generated, if enabled, if the result is outside the boundary limits. The boundary limit may be disabled by clearing the boundary limit interrupt enable. 9.7 DAC output to a port pin with high output impedance The A/D converter’s DAC block can be output to a port pin. In this mode, the AD1DAT3 register is used to hold the value fed to the DAC. After a value has been written to the DAC (written to AD1DAT3), the DAC output will appear on the channel 3 pin. 9.8 Clock divider The A/D converter requires that its internal clock source be in the range of 500 kHz to 3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 45 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 9.9 Power-down and Idle mode In Idle mode the A/D converter, if enabled, will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is enabled, it will consume power. Power can be reduced by disabling the A/D. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 46 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 10. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Tamb(bias) Min Max Unit bias ambient temperature −55 +125 °C Tstg storage temperature −65 +150 °C IOH(I/O) HIGH-level output current per input/output pin - 8 mA IOL(I/O) LOW-level output current per input/output pin - 20 mA II/Otot(max) maximum total input/output current - 120 mA Vn voltage on any other pin except VSS, with respect to VDD −0.5 +5.5 V Ptot(pack) total power dissipation per package based on package heat transfer, not device power consumption - 1.5 W [1] Conditions The following applies to Table 11 “Limiting values”: a) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in Table 12 “Static characteristics” and Table 13 “Dynamic characteristics (12 MHz)” section of this specification are not implied. b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 47 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 11. Static characteristics Table 12. Static characteristics VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified. Symbol IDD(oper) IDD(idle) Parameter operating supply current Idle mode supply current Min Typ[1] Max 3.6 V; 12 MHz [2] - 7 11 mA 3.6 V; 7.373 MHz [3] - 4 7 mA 3.6 V; 12 MHz [2] - 3 5 mA 3.6 V; 7.373 MHz [3] - 2 4 mA - 55 80 µA - 0.5 5 µA Conditions Unit IDD(pd) Power-down mode supply current 3.6 V; voltage comparators powered-down [2] IDD(tpd) total Power-down mode supply current 3.6 V [4] (dV/dt)r rise rate of VDD - - 2 mV/µs (dV/dt)f fall rate of VDD - - 50 mV/µs VPOR power-on reset voltage - - 0.2 V VDDR data retention supply voltage 1.5 - - V Vth(HL) HIGH-LOW threshold voltage 0.22VDD 0.4VDD - V Vth(LH) LOW-HIGH threshold voltage - 0.6VDD 0.7VDD V Vhys hysteresis voltage VOL VOH Ciss IIL LOW-level output voltage HIGH-level output voltage - 0.2VDD - V IOL = 20 mA [5] - 0.6 1.0 V IOL = 10 mA [5] - 0.3 0.5 V IOL = 3.2 mA [5] - 0.2 0.3 V IOH = −8 mA; push-pull mode, all ports VDD − 1.0 - - V IOH = −3.2 mA; push-pull mode, all ports VDD − 0.7 VDD − 0.4 - V IOH = −20 µA; quasi-bidirectional mode, all ports VDD − 0.3 VDD − 0.2 - V input capacitance [6] - - 15 pF LOW-level input current VI = 0.4 V; all ports [7] - - −80 µA [8] - - ±1 µA −30 - −450 µA 10 - 30 kΩ ILI input leakage current VI = VIL or VIH; all ports ITHL HIGH-LOW transition current VI = 2.0 V at VDD = 3.6 V; all ports [9][10] RRST_N(int) internal pull-up resistance on pin RST P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 48 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core Table 12. Static characteristics …continued VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Vbo brownout trip voltage 2.4 V < VDD < 3.6 V; with BOV = 1, BOPD = 0 2.40 - 2.70 V Vref(bg) band gap reference voltage 1.19 1.23 1.27 V TCbg band gap temperature coefficient - 10 20 ppm/°C [1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. [2] The IDD(oper), IDD(idle), and IDD(pd) specifications are measured using an external clock with the following functions disabled: comparators, real-time clock, and watchdog timer. [3] The IDD(oper) and IDD(idle) specifications are measured using with the following functions disabled: comparators, real-time clock, and watchdog timer. [4] The IDD(tpd) specification is measured using an external clock with the following functions disabled: comparators, real-time clock, brownout detect, and watchdog timer. [5] Applies to all ports, in all modes except Hi-Z. [6] Pin capacitance is characterized but not tested. [7] Measured with port in quasi-bidirectional mode. [8] Measured with port in high-impedance mode. [9] Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups) [10] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when VI is approximately 2 V. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 49 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 12. Dynamic characteristics Table 13. Dynamic characteristics (12 MHz) VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1] Symbol Parameter Conditions Variable clock fext = 12 MHz Unit Min Max Min Max fosc(RC) internal RC oscillator frequency clock doubler option = OFF (default); nominal f = 7.3728 MHz; trimmed to ±1 % at Tamb = 25 °C 7.189 7.557 7.189 7.557 MHz clock doubler option = ON; nominal f = 14.7456 MHz; VDD = 2.7 V to 3.6 V 14.378 15.114 14.378 15.114 MHz 520 320 520 kHz fosc(WD) internal watchdog oscillator frequency nominal f = 400 kHz 320 Tcy(clk) clock cycle time see Figure 20 83 - - - ns fCLKLP low-power select clock frequency 0 8 - - MHz - - 0 12 MHz 33 Tcy(clk) − tCLCX 33 - ns 33 Tcy(clk) − tCHCX 33 - ns External clock fext external clock frequency tCHCX clock HIGH time tCLCX clock LOW time tCLCH clock rise time - 8 - 8 ns tCHCL clock fall time - 8 - 8 ns - 50 - 50 ns VDD = 2.7 V to 3.6 V; see Figure 20 Glitch filter tgr glitch rejection P1.5/RST pin - 15 - 15 ns tsa signal acceptance P1.5/RST pin 125 - 125 - ns any pin except P1.5/RST 50 - 50 - ns any pin except P1.5/RST Shift register (UART mode 0 - P89LPC9103) TXLXL serial port clock cycle time see Figure 19 16Tcy(clk) - 1333 - ns tQVXH output data set-up to clock rising edge see Figure 19 13Tcy(clk) - 1083 - ns tXHQX output data hold after clock rising edge see Figure 19 - Tcy(clk) + 20 - 103 ns tXHDX input data hold after clock rising edge see Figure 19 - 0 - 0 ns tXHDV input data valid to clock see Figure 19 rising edge 150 - 150 - ns [1] Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 50 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core Table 14. Dynamic characteristics (18 MHz) VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1] Symbol fosc(RC) Parameter internal RC oscillator frequency Conditions Variable clock fext = 18 MHz Unit Min Max Min Max clock doubler option = OFF (default); nominal f = 7.3728 MHz; trimmed to ±1 % at Tamb = 25 °C 7.189 7.557 7.189 7.557 MHz clock doubler option = ON; nominal f = 14.7456 MHz 14.378 15.114 14.378 15.114 MHz 520 320 520 kHz fosc(WD) internal watchdog oscillator frequency nominal f = 400 kHz 320 Tcy(clk) clock cycle time see Figure 20 83 - - - ns fCLKLP low-power select clock frequency 0 8 - - MHz - - 0 18 MHz 22 Tcy(clk) − tCLCX 22 - ns 22 Tcy(clk) − tCHCX 22 - ns External clock fext external clock frequency tCHCX clock HIGH time tCLCX clock LOW time tCLCH clock rise time - 5 - 5 ns tCHCL clock fall time - 5 - 5 ns - 50 - 50 ns see Figure 20 Glitch filter tgr glitch rejection P1.5/RST pin - 15 - 15 ns tsa signal acceptance P1.5/RST pin 125 - 125 - ns any pin except P1.5/RST 50 - 50 - ns any pin except P1.5/RST Shift register (UART mode 0 - P89LPC9103) TXLXL serial port clock cycle time see Figure 19 16Tcy(clk) - 888 - ns tQVXH output data set-up to clock rising edge see Figure 19 13Tcy(clk) - 722 - ns tXHQX output data hold after clock rising edge see Figure 19 - Tcy(clk) + 20 - 75 ns tXHDX input data hold after clock rising edge see Figure 19 - 0 - 0 ns tXHDV input data valid to clock see Figure 19 rising edge 150 - 150 - ns [1] Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 51 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 12.1 Waveforms TXLXL clock tXHQX tQVXH output data 0 write to SBUF input data 1 2 3 4 5 6 7 tXHDX set TI tXHDV valid valid valid valid valid valid valid valid clear RI set RI 002aaa906 Fig 19. Shift register mode timing (P89LPC9103/9107) VDD − 0.5 V 0.45 V 0.2VDD + 0.9 V 0.2VDD − 0.1 V tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 20. External clock timing P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 52 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 13. Other characteristics 13.1 Comparator electrical characteristics Table 15. Comparator electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified. Symbol Parameter VIO input offset voltage VIC common-mode input voltage CMRR common-mode rejection ratio Conditions [1] Min Typ Max Unit - - ±10 mV 0 - VDD − 0.3 V - - −50 dB tres(tot) total response time - 250 500 ns t(CE-OV) chip enable to output valid time - - 10 µs ILI input leakage current - - ±1 µA [1] 0 V < VI < VDD This parameter is characterized, but not tested in production. 13.2 A/D converter electrical characteristics Table 16. A/D converter electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified. All limits valid for an external source impedance of less than 10 kΩ. Symbol Parameter VIA analog input voltage Ciss input capacitance ED differential linearity error EL(adj) integral non-linearity EO offset error EG gain error Eu(tot) total unadjusted error MCTC channel-to-channel matching αct(port) crosstalk between port inputs SRin input slew rate Tcy(ADC) ADC clock cycle tADC ADC conversion time Conditions 0 kHz to 100 kHz A/D enabled P89LPC9102_9103_9107_3 Product data sheet Min Typ Max Unit VSS − 0.2 - VSS + 0.2 V - - 15 pF - - ±1 LSB - - ±1 LSB - - ±2 LSB - - ±1 % - - ±2 LSB - - ±1 LSB - - −60 dB - - 100 V/ms 111 - 2000 ns - - 13tCLK(ADC) µs © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 53 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 14. Package outline HVSON10: plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 3 x 3 x 0.85 mm SOT650-1 0 1 2 mm scale X A B D A A1 E c detail X terminal 1 index area C e1 terminal 1 index area e 5 y y1 C v M C A B w M C b 1 L Eh 6 10 Dh DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D(1) Dh E(1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 2.55 2.15 3.1 2.9 1.75 1.45 0.5 2 0.55 0.30 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT650-1 --- MO-229 --- EUROPEAN PROJECTION ISSUE DATE 01-01-22 02-02-08 Fig 21. Package outline SOT650-1 (HVSON10) P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 54 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 22. Package outline SOT402-1 (TSSOP14) P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 55 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 23. Package outline SOT27-1 (DIP14) P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 56 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 15. Abbreviations Table 17. Acronym list Acronym Description A/D Analog-to-Digital BOE Brownout Enable CMRR Common-Mode Rejection Ratio DAC Digital-to-Analog Converter EMI Electromagnetic Interference IAP In-Application Programming ICP In-Circuit Programming LSB Least Significant Bit MSB Most Significant Bit PWM Pulse Width Modulator RTC Real-Time Clock SAR Successive Approximation Register UART Universal Asynchronous Receiver/Transmitter P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 57 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 16. Revision history Table 18. Revision history Document ID Release date Data sheet status Change notice Supersedes P89LPC9102_9103_ 9107_3 20070710 Product data sheet - P89LPC9102_9103_9107_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Added new device P89LPC9107FN. P89LPC9102_9103_ 9107_2 20050411 Product data sheet - P89LPC9102_9103_9107_1 P89LPC9102_9103_ 9107_1 20050111 Product data sheet - - P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 58 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 59 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 19. Contents 1 2 2.1 2.2 3 4 4.1 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.11.1 8.12 8.12.1 8.12.2 8.12.3 8.12.4 8.12.5 8.12.6 8.12.7 8.13 8.13.1 8.13.2 8.14 8.14.1 8.14.2 8.14.3 8.14.4 8.15 8.16 8.16.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 Product comparison overview . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 8 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional description . . . . . . . . . . . . . . . . . . 15 Special function registers . . . . . . . . . . . . . . . . 15 Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 27 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 27 CPU clock (CCLK) . . . . . . . . . . . . . . . . . . . . . 27 On-chip RC oscillator option . . . . . . . . . . . . . . 27 Watchdog oscillator option . . . . . . . . . . . . . . . 28 External clock input option . . . . . . . . . . . . . . . 28 CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 29 CCLK modification: DIVM register . . . . . . . . . 29 Low power select . . . . . . . . . . . . . . . . . . . . . . 29 Memory organization . . . . . . . . . . . . . . . . . . . 29 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 External interrupt inputs . . . . . . . . . . . . . . . . . 30 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Port configurations . . . . . . . . . . . . . . . . . . . . . 31 Quasi-bidirectional output configuration . . . . . 32 Open-drain output configuration . . . . . . . . . . . 32 Input-only configuration . . . . . . . . . . . . . . . . . 32 Push-pull output configuration . . . . . . . . . . . . 32 Port 0 analog functions . . . . . . . . . . . . . . . . . . 32 Additional port features. . . . . . . . . . . . . . . . . . 32 Power monitoring functions. . . . . . . . . . . . . . . 33 Brownout detection . . . . . . . . . . . . . . . . . . . . . 33 Power-on detection . . . . . . . . . . . . . . . . . . . . . 33 Power reduction modes . . . . . . . . . . . . . . . . . 33 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Slow-down mode using the DIVM register . . . 34 Power-down mode . . . . . . . . . . . . . . . . . . . . . 34 Total Power-down mode . . . . . . . . . . . . . . . . . 34 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Timers 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . 35 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.16.2 8.16.3 8.16.4 8.16.5 8.16.6 8.17 8.18 8.18.1 8.18.2 8.18.3 8.18.4 8.18.5 8.18.6 8.18.7 8.18.8 8.18.9 8.18.10 8.19 8.20 8.21 8.22 8.23 8.24 8.25 8.25.1 8.25.2 8.26 8.26.1 8.26.2 8.26.3 8.26.4 8.26.5 8.26.6 8.26.7 8.26.8 8.26.9 9 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 6 (P89LPC9102/9107) . . . . . . . . . . . . . Timer overflow toggle output (P89LPC9102/9107) . . . . . . . . . . . . . . . . . . . RTC/system timer. . . . . . . . . . . . . . . . . . . . . . UART (P89LPC9103/9107) . . . . . . . . . . . . . . Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud rate generator and selection . . . . . . . . . Framing error . . . . . . . . . . . . . . . . . . . . . . . . . Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . Double buffering . . . . . . . . . . . . . . . . . . . . . . . Transmit interrupts with double buffering enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . Analog comparators . . . . . . . . . . . . . . . . . . . . Internal reference voltage. . . . . . . . . . . . . . . . Comparator interrupt . . . . . . . . . . . . . . . . . . . Comparator and power reduction modes . . . . Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . Additional features . . . . . . . . . . . . . . . . . . . . . Software reset . . . . . . . . . . . . . . . . . . . . . . . . Dual data pointers . . . . . . . . . . . . . . . . . . . . . Flash program memory . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash organization . . . . . . . . . . . . . . . . . . . . . Flash programming and erasing. . . . . . . . . . . In-circuit programming . . . . . . . . . . . . . . . . . . In-application programming (IAP-Lite) . . . . . . Using flash as data storage . . . . . . . . . . . . . . User configuration bytes. . . . . . . . . . . . . . . . . User sector security bytes . . . . . . . . . . . . . . . A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . A/D operating modes . . . . . . . . . . . . . . . . . . . Fixed channel, single conversion mode . . . . . Fixed channel, continuous conversion mode . Auto scan, single conversion mode . . . . . . . . Auto scan, continuous conversion mode . . . . 35 35 35 35 36 36 36 36 36 36 37 37 37 37 37 38 38 38 38 39 39 39 39 40 40 40 41 41 41 41 41 42 42 42 42 42 43 43 43 44 44 44 44 44 44 continued >> P89LPC9102_9103_9107_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 10 July 2007 60 of 61 P89LPC9102/9103/9107 NXP Semiconductors 8-bit microcontrollers with two-clock accelerated 80C51 core 9.4.5 9.4.6 9.5 9.5.1 9.5.2 9.6 9.7 9.8 9.9 10 11 12 12.1 13 13.1 13.2 14 15 16 17 17.1 17.2 17.3 17.4 18 19 Dual channel, continuous conversion mode . . Single step mode . . . . . . . . . . . . . . . . . . . . . . Conversion start modes . . . . . . . . . . . . . . . . . Timer triggered start . . . . . . . . . . . . . . . . . . . . Start immediately . . . . . . . . . . . . . . . . . . . . . . Boundary limits interrupt. . . . . . . . . . . . . . . . . DAC output to a port pin with high output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . Power-down and Idle mode . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics. . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . Other characteristics . . . . . . . . . . . . . . . . . . . . Comparator electrical characteristics . . . . . . . A/D converter electrical characteristics. . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 45 45 45 45 45 45 45 46 47 48 50 52 53 53 53 54 57 58 59 59 59 59 59 59 60 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 July 2007 Document identifier: P89LPC9102_9103_9107_3