PIC16F610/16HV610 PIC16F616/16HV616 Data Sheet 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers © 2007 Microchip Technology Inc. Preliminary DS41288C Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41288C-page ii © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers High-Performance RISC CPU: Peripheral Features: • Only 35 instructions to learn: - All single-cycle instructions except branches • Operating speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt capability • 8-level deep hardware stack • Direct, Indirect and Relative Addressing modes • Shunt Voltage Regulator (PIC16HV610/616 only): - 5 volt regulation - 4 mA to 50 mA shunt range • 11 I/O pins and 1 input only - High current source/sink for direct LED drive - Interrupt-on-Change pins - Individually programmable weak pull-ups • Analog Comparator module with: - Two analog comparators - Programmable on-chip voltage reference (CVREF) module (% of VDD) - Fixed Voltage Reference - Comparator inputs and outputs externally accessible - SR Latch - Built-In Hysteresis (user selectable) • Timer0: 8-bit timer/counter with 8-bit programmable prescaler • Enhanced Timer1: - 16-bit timer/counter with prescaler - External Timer1 Gate (count enable) - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator if INTOSC mode selected - Timer1 oscillator • In-Circuit Serial ProgrammingTM (ICSPTM) via two pins Special Microcontroller Features: • Precision Internal Oscillator: - Factory calibrated to ±1%, typical - User selectable frequency: 4 MHz or 8 MHz • Power-Saving Sleep mode • Voltage range: - PIC16F610/616: 2.0V to 5.5V - PIC16HV610/616: 2.0V to user defined maximum (see note) • Industrial and Extended Temperature range • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Brown-out Reset (BOR) • Watchdog Timer (WDT) with independent oscillator for reliable operation • Multiplexed Master Clear with pull-up/input pin • Programmable code protection • High Endurance Flash: - 100,000 write Flash endurance - Flash retention: > 40 years PIC16F616/16HV616 only: • A/D Converter: - 10-bit resolution - 8 external input channels - 2 internal reference channels • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Enhanced Capture, Compare, PWM module: - 16-bit Capture, max. resolution 12.5 ns - 16-bit Compare, max. resolution 200 ns - 10-bit PWM with 1, 2 or 4 output channels, programmable “dead time”, max. frequency 20 kHz Low-Power Features: • Standby Current: - 50 nA @ 2.0V, typical • Operating Current: - 20 μA @ 32 kHz, 2.0V, typical - 220 μA @ 4 MHz, 2.0V, typical • Watchdog Timer Current: - 1 μA @ 2.0V, typical Note: Voltage across internal shunt regulator cannot exceed 5V. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 1 PIC16F610/616/16HV610/616 Program Memory Data Memory Flash (words) SRAM (bytes) PIC16F610 1024 PIC16HV610 1024 PIC16F616 PIC16HV616 Device I/O 10-bit A/D (ch) Comparators Timers 8/16-bit 64 11 — 2 1/1 2.0-5.5V 64 11 — 2 1/1 2.0-user defined 2048 128 11 8 2 2/1 2.0-5.5V 2048 128 11 8 2 2/1 2.0-user defined Voltage Range VDD 1 RA5/T1CKI/OSC1/CLKIN 2 RA4/T1G/OSC2/CLKOUT 3 RA3/MCLR/VPP 4 5 RC4/C2OUT 6 RC3/C12IN3- 7 14 VSS 13 RA0/C1IN+/ICSPDAT 12 RA1/C12IN0-/ICSPCLK 11 RA2/T0CKI/INT/C1OUT 10 RC0/C2IN+ 9 RC1/C12IN1- 8 RC2/C12IN2- PIC16F610/16HV610 14-PIN SUMMARY TABLE 1: I/O RC5 PIC16F610/16HV610 PIC16F610/16HV610 14-Pin Diagram (PDIP, SOIC, TSSOP) Pin Comparators Timer Interrupts Pull-ups Basic RA0 13 C1IN+ — IOC Y ICSPDAT RA1 12 C12IN0- — IOC Y ICSPCLK RA2 11 C1OUT T0CKI INT/IOC Y — — IOC Y(2) MCLR/VPP RA3(1) 4 — RA4 3 — T1G IOC Y OSC2/CLKOUT RA5 2 — T1CKI IOC Y OSC1/CLKIN RC0 10 C2IN+ — — — — RC1 9 C12IN1- — — — — RC2 8 C12IN2- — — — — RC3 7 C12IN3- — — — — RC4 6 C2OUT — — — — RC5 5 — — — — — — 1 — — — — VDD — 14 — — — — VSS Note 1: 2: Input only. Only when pin is configured for external MCLR. DS41288C-page 2 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 VDD 1 RA5/T1CKI/OSC1/CLKIN 2 RA4/AN3/T1G/OSC2/CLKOUT 3 RA3/MCLR/VPP 4 RC5/CCP1/P1A 5 RC4/C2OUT/P1B RC3/AN7/C12IN3-/P1C 6 7 PIC16F616/16HV616 PIC16F616/16HV616 14-Pin Diagram (PDIP, SOIC, TSSOP) 14 VSS 13 RA0/AN0/C1IN+/ICSPDAT 12 RA1/AN1/C12IN0-/VREF/ICSPCLK 11 RA2/AN2/T0CKI/INT/C1OUT 10 RC0/AN4/C2IN+ 9 RC1/AN5/C12IN1- 8 RC2/AN6/C12IN2-/P1D PIC16F616/16HV616 14-PIN SUMMARY TABLE 2: I/O Pin Analog Comparators Timer CCP Interrupts Pull-ups Basic RA0 13 AN0 C1IN+ — — IOC Y ICSPDAT RA1 12 AN1/VREF C12IN0- — — IOC Y ICSPCLK RA2 11 AN2 C1OUT T0CKI — INT/IOC Y — IOC Y(2) MCLR/VPP RA3(1) 4 — — RA4 3 AN3 — T1G — IOC Y OSC2/CLKOUT RA5 2 — — T1CKI — IOC Y OSC1/CLKIN — — RC0 10 AN4 C2IN+ — — — — — RC1 9 AN5 C12IN1- — — — — — RC2 8 AN6 C12IN2- — P1D — — — RC3 7 AN7 C12IN3- — P1C — — — RC4 6 — C2OUT — P1B — — — RC5 5 — — — CCP1/P1A — — — — 1 — — — — — — VDD — 14 — — — — — — VSS Note 1: 2: Input only. Only when pin is configured for external MCLR. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 3 PIC16F610/616/16HV610/616 VDD NC NC VSS 15 14 13 11 RA1/C12IN0-/ICSPCLK 10 RA2/T0CKI/INT/C1OUT 8 9 7 4 RA0/C1IN+/ICSPDAT RC1/C12IN1- RC5 6 3 12 RC2/C12IN2- RA3/MCLR/VPP PIC16F610/ PIC16HV610 RC3/C12IN3- 2 5 RA4/T1G/OSC2/CLKOUT RC4/C2OUT 1 RC0/C2IN1+ PIC16F610/16HV610 16-PIN SUMMARY TABLE 3: I/O RA5/T1CKI/OSC1/CLKIN 16 PIC16F610/16HV610 16-Pin Diagram (QFN) Pin Comparators Timers Interrupts Pull-ups Basic 12 C1IN+ — IOC Y ICSPDAT RA1 11 C12IN0- — IOC Y ICSPCLK RA2 10 C1OUT T0CKI INT/IOC Y — — IOC Y(2) MCLR/VPP RA0 RA3 (1) 3 — RA4 2 — T1G IOC Y OSC2/CLKOUT RA5 1 — T1CKI IOC Y OSC1/CLKIN RC0 9 C2IN+ — — — — RC1 8 C12IN1- — — — — RC2 7 C12IN2- — — — — RC3 6 C12IN3- — — — — RC4 5 C2OUT — — — — RC5 4 — — — — — — 16 — — — — VDD — 13 — — — — VSS Note 1: 2: Input only. Only when pin is configured for external MCLR. DS41288C-page 4 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 VDD NC NC VSS 15 14 13 RA2/AN2/T0CKI/INT/C1OUT 9 8 4 10 RC1/AN5/C12IN1- RC5/CCP/P1A RA1/AN1/C12IN0-/VREF/ICSPCLK 7 3 11 RC2/AN6/C12IN2-/P1D RA3/MCLR/VPP PIC16F616/ PIC16HV616 6 2 RA0/AN0/C1IN+/ICSPDAT RC3/AN7/C12IN3-/P1C RA4/AN3/T1G/OSC2/CLKOUT 12 5 1 RC4/C2OUT/P1B RA5/T1CKI/OSC1/CLKIN 16 PIC16F616/16HV616 16-Pin Diagram (QFN) RC0/AN4/C2IN1+ PIC16F616/16HV616 16-PIN SUMMARY TABLE 4: I/O Pin Analog Comparators Timers CCP Interrupts Pull-ups Basic RA0 12 AN0 C1IN+ — — IOC Y ICSPDAT RA1 11 AN1/VREF C12IN0- — — IOC Y ICSPCLK RA2 10 AN2 C1OUT T0CKI — INT/IOC Y — IOC Y(2) MCLR/VPP RA3 (1) 3 — — — — RA4 2 AN3 — T1G — IOC Y OSC2/CLKOUT RA5 1 — — T1CKI — IOC Y OSC1/CLKIN RC0 9 AN4 C2IN+ — — — — — RC1 8 AN5 C12IN1- — — — — — RC2 7 AN6 C12IN2- — P1D — — — RC3 6 AN7 C12IN3- — P1C — — — RC4 5 — C2OUT — P1B — — — RC5 4 — — — CCP1/P1A — — — — 16 — — — — — — VDD — 13 — — — — — — VSS Note 1: 2: Input only. Only when pin is configured for external MCLR. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 5 PIC16F610/616/16HV610/616 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Memory Organization ................................................................................................................................................................. 11 3.0 Oscillator Module........................................................................................................................................................................ 25 4.0 I/O Ports ..................................................................................................................................................................................... 31 5.0 Timer0 Module ........................................................................................................................................................................... 43 6.0 Timer1 Module with Gate Control............................................................................................................................................... 47 7.0 Timer2 Module ........................................................................................................................................................................... 53 8.0 Comparator Module.................................................................................................................................................................... 55 9.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 71 10.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module ................................................................. 83 11.0 Voltage Regulator..................................................................................................................................................................... 105 12.0 Special Features of the CPU .................................................................................................................................................... 106 13.0 Instruction Set Summary .......................................................................................................................................................... 125 14.0 Development Support............................................................................................................................................................... 135 15.0 Electrical Specifications............................................................................................................................................................ 139 16.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 161 17.0 Packaging Information.............................................................................................................................................................. 163 Appendix A: Data Sheet Revision History.......................................................................................................................................... 169 Appendix B: Migrating from other PIC® Devices................................................................................................................................ 169 Index .................................................................................................................................................................................................. 171 The Microchip Web Site ..................................................................................................................................................................... 175 Customer Change Notification Service .............................................................................................................................................. 175 Customer Support .............................................................................................................................................................................. 175 Reader Response .............................................................................................................................................................................. 176 Product Identification System............................................................................................................................................................. 177 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS41288C-page 6 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 1.0 DEVICE OVERVIEW The PIC16F610/616/16HV610/616 is covered by this data sheet. It is available in 14-pin PDIP, SOIC, TSSOP and 16-pin QFN packages. Block Diagrams and pinout descriptions of the devices are as follows: • PIC16F610/16HV610 (Figure 1-1, Table 1-1) • PIC16F616/16HV616 (Figure 1-2, Table 1-2) FIGURE 1-1: PIC16F610/16HV610 BLOCK DIAGRAM INT Configuration 13 Flash 1K X 14 Program Memory Program Bus PORTA RA0 RA1 RA2 RA3 RA4 RA5 RAM 64 Bytes File Registers 8-Level Stack (13-Bit) 14 8 Data Bus Program Counter RAM Addr 9 Addr MUX Instruction Reg 7 Direct Addr 8 Indirect Addr PORTC FSR Reg STATUS Reg 8 3 Power-up Timer OSC1/CLKIN Instruction Decode and Control Oscillator Start-up Timer Timing Generation Watchdog Timer Brown-out Reset OSC2/CLKOUT Power-on Reset RC0 RC1 RC2 RC3 RC4 RC5 MUX ALU 8 W Reg Internal Oscillator Block Shunt Regulator (PIC16HV610 only) MCLR VDD VSS T1G T1CKI Timer0 Timer1 T0CKI Comparator Voltage Reference 2 Analog Comparators Fixed Voltage Reference C1IN+ C12IN0C12IN1C12IN2C12IN3C1OUT C2IN+ C2OUT © 2007 Microchip Technology Inc. Preliminary DS41288C-page 7 PIC16F610/616/16HV610/616 FIGURE 1-2: PIC16F616/16HV616 BLOCK DIAGRAM INT Configuration 13 Flash 2K X 14 Program Memory Program Bus PORTA RA0 RA1 RA2 RA3 RA4 RA5 RAM 128 Bytes File Registers 8-Level Stack (13-Bit) 14 8 Data Bus Program Counter RAM Addr 9 Addr MUX Instruction Reg 7 Direct Addr Indirect Addr 8 PORTC RC0 RC1 RC2 RC3 RC4 RC5 FSR Reg STATUS Reg 8 3 Power-up Timer Instruction Decode and Control OSC1/CLKIN Timing Generation OSC2/CLKOUT MUX Oscillator Start-up Timer Power-on Reset ALU 8 Watchdog Timer Brown-out Reset W Reg Internal Oscillator Block Shunt Regulator (PIC16HV616 only) MCLR VDD T1G VSS T1CKI Timer0 Timer1 Timer2 T0CKI Comparator Voltage Reference Analog-To-Digital Converter 2 Analog Comparators ECCP Fixed Voltage Reference Preliminary CCP1/P1A P1B P1C P1D C1IN+ C12IN0C12IN1C12IN2C12IN3C1OUT C2IN+ C2OUT AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 VREF DS41288C-page 8 © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 1-1: PIC16F610/16HV610 PINOUT DESCRIPTION Name RA0/C1IN+/ICSPDAT RA1/C12IN0-/ICSPCLK RA2/T0CKI/INT/C1OUT RA3/MCLR/VPP RA4/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RC0/C2IN+ RC1/C12IN1RC2/C12IN2RC3/C12IN3RC4/C2OUT Function Input Type Output Type Description RA0 TTL CMOS C1IN+ AN — PORTA I/O with prog. pull-up and interrupt-on-change ICSPDAT ST CMOS Serial Programming Data I/O PORTA I/O with prog. pull-up and interrupt-on-change Comparator C1 non-inverting input RA1 TTL CMOS C12IN0- AN — Comparators C1 and C2 inverting input ICSPCLK ST — Serial Programming Clock RA2 ST CMOS T0CKI ST — Timer0 clock input INT ST — External Interrupt C1OUT — CMOS RA3 TTL — PORTA input with interrupt-on-change MCLR ST — Master Clear w/internal pull-up VPP HV — RA4 TTL CMOS T1G ST — OSC2 — XTAL PORTA I/O with prog. pull-up and interrupt-on-change Comparator C1 output Programming voltage PORTA I/O with prog. pull-up and interrupt-on-change Timer1 gate (count enable) Crystal/Resonator CLKOUT — CMOS FOSC/4 output RA5 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change T1CKI ST — OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection RC0 TTL CMOS C2IN+ AN — RC1 TTL CMOS C12IN1- AN — RC2 TTL CMOS C12IN2- AN — RC3 TTL CMOS C12IN3- AN — RC4 TTL CMOS Timer1 clock input PORTC I/O Comparator C2 non-inverting input PORTC I/O Comparators C1 and C2 inverting input PORTC I/O Comparators C1 and C2 inverting input PORTC I/O Comparators C1 and C2 inverting input PORTC I/O C2OUT — CMOS Comparator C2 output RC5 RC5 TTL CMOS PORTC I/O VDD VDD Power — Positive supply VSS VSS Power — Ground reference Legend: AN = Analog input or output ST = Schmitt Trigger input with CMOS levels © 2007 Microchip Technology Inc. CMOS = CMOS compatible input or output TTL = TTL compatible input Preliminary HV = High Voltage XTAL = Crystal DS41288C-page 9 PIC16F610/616/16HV610/616 TABLE 1-2: PIC16F616/16HV616 PINOUT DESCRIPTION Name RA0/AN0/C1IN+/ICSPDAT RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA3/MCLR/VPP RA4/AN3/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RC0/AN4/C2IN+ RC1/AN5/C12IN1- RC2/AN6/C12IN2-/P1D RC3/AN7/C12IN3-/P1C RC4/C2OUT/P1B Function Input Type Output Type RA0 TTL CMOS AN0 AN — Description PORTA I/O with prog. pull-up and interrupt-on-change A/D Channel 0 input C1IN+ AN — ICSPDAT ST CMOS RA1 TTL CMOS AN1 AN — A/D Channel 1 input C12IN0- AN — Comparators C1 and C2 inverting input VREF AN — External Voltage Reference for A/D ICSPCLK ST — Serial Programming Clock RA2 ST CMOS AN2 AN — T0CKI ST — Timer0 clock input INT ST — External Interrupt C1OUT — CMOS RA3 TTL — PORTA input with interrupt-on-change MCLR ST — Master Clear w/internal pull-up VPP HV — RA4 TTL CMOS AN3 AN — T1G ST — OSC2 — XTAL Comparator C1 non-inverting input Serial Programming Data I/O PORTA I/O with prog. pull-up and interrupt-on-change PORTA I/O with prog. pull-up and interrupt-on-change A/D Channel 2 input Comparator C1 output Programming voltage PORTA I/O with prog. pull-up and interrupt-on-change A/D Channel 3 input Timer1 gate (count enable) Crystal/Resonator CLKOUT — CMOS FOSC/4 output RA5 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change T1CKI ST — OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection RC0 TTL CMOS AN4 AN — C2IN+ AN — RC1 TTL CMOS AN5 AN — C12IN1- AN — RC2 TTL CMOS Timer1 clock input PORTC I/O A/D Channel 4 input Comparator C2 non-inverting input PORTC I/O A/D Channel 5 input Comparators C1 and C2 inverting input PORTC I/O AN6 AN — A/D Channel 6 input C12IN2- AN — Comparators C1 and C2 inverting input P1D — CMOS PWM output RC3 TTL CMOS PORTC I/O AN7 AN — A/D Channel 7 input C12IN3- AN — Comparators C1 and C2 inverting input P1C — CMOS PWM output RC4 TTL CMOS PORTC I/O Comparator C2 output C2OUT — CMOS P1B — CMOS PWM output RC5 TTL CMOS PORTC I/O CCP1 ST CMOS Capture input/Compare output P1A — CMOS PWM output VDD VDD Power — Positive supply VSS VSS Power — Ground reference RC5/CCP1/P1A Legend: AN = Analog input or output ST = Schmitt Trigger input with CMOS levels DS41288C-page 10 CMOS = CMOS compatible input or output TTL = TTL compatible input Preliminary HV = High Voltage XTAL = Crystal © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization FIGURE 2-2: The PIC16F610/616/16HV610/616 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. Only the first 1K x 14 (0000h-3FF) for the PIC16F610/16HV610 and the first 2K x 14 (0000h-07FFh) for the PIC16F616/16HV616 is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first 1K x 14 space (PIC16F610/16HV610) and 2K x 14 space (PIC16F616/16HV616). The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1). FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F610/16HV610 PROGRAM MEMORY MAP AND STACK FOR THE PIC16F616/16HV616 PC<12:0> CALL, RETURN RETFIE, RETLW 13 Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h 0005h PC<12:0> CALL, RETURN RETFIE, RETLW On-chip Program 13 Memory 07FFh Stack Level 1 0800h Stack Level 2 1FFFh Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h 0005h On-chip Program Memory 03FFh 0400h 1FFFh © 2007 Microchip Technology Inc. Preliminary DS41288C-page 11 PIC16F610/616/16HV610/616 2.2 2.2.1 Data Memory Organization The data memory (see Figure 2-4) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. PIC16F610/16HV610 Register locations 40h-7Fh in Bank 0 are General Purpose Registers, implemented as static RAM. PIC16F616/16HV616 Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are General Purpose Registers, implemented as static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. The RP0 bit of the STATUS register is the bank select bit. RP0 0 → Bank 0 is selected 1 → Bank 1 is selected Note: GENERAL PURPOSE REGISTER FILE The register file is organized as 64 x 8 in the PIC16F610/16HV610 and 128 x 8 in the PIC16F616/16HV616. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. The IRP and RP1 bits of the STATUS register are reserved and should always be maintained as ‘0’s. DS41288C-page 12 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 2-3: DATA MEMORY MAP OF THE PIC16F610/16HV610 File Address FIGURE 2-4: File Address DATA MEMORY MAP OF THE PIC16F616/16HV616 File Address File Address Indirect Addr.(1) 00h Indirect Addr.(1) 80h Indirect Addr.(1) 00h Indirect Addr.(1) 80h TMR0 01h OPTION_REG 81h TMR0 01h OPTION_REG 81h PCL 02h PCL 82h PCL 02h PCL 82h STATUS 03h STATUS 83h STATUS 03h STATUS 83h FSR 04h FSR 84h FSR 04h FSR 84h PORTA 05h TRISA 85h PORTA 05h TRISA 85h 06h PORTC 06h 86h TRISC 07h PORTC 87h 86h TRISC 07h 08h 88h 08h 09h 89h 09h 87h 88h 89h PCLATH 0Ah PCLATH 8Ah PCLATH 0Ah PCLATH 8Ah INTCON 0Bh INTCON 8Bh INTCON 0Bh INTCON 8Bh PIR1 0Ch PIE1 8Ch PIR1 0Ch PIE1 8Ch 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h 11h 0Dh 8Dh PCON 8Dh PCON 8Eh TMR1L 0Eh 8Fh TMR1H 0Fh OSCTUNE 90h T1CON 10h OSCTUNE 90h ANSEL 91h TMR2 11h ANSEL 91h 12h 92h T2CON 12h PR2 92h 13h 93h CCPR1L 13h 14h 94h CCPR1H 14h 8Eh 8Fh 93h 94h 15h WPUA 95h CCP1CON 15h WPUA 95h 16h IOCA 96h PWM1CON 16h IOCA 96h 17h 97h ECCPAS 17h 18h 98h 97h 18h 98h VRCON 19h SRCON0 99h VRCON 19h SRCON0 99h CM1CON0 1Ah SRCON1 9Ah CM1CON0 1Ah SRCON1 9Ah CM2CON0 1Bh 9Bh CM2CON0 1Bh 9Bh CM2CON1 1Ch 9Ch CM2CON1 1Ch 9Ch 1Dh 9Dh 1Eh 9Eh ADRESH 1Eh ADRESL 9Eh 1Fh 9Fh A0h ADCON0 1Fh ADCON1 General Purpose Registers 32 Bytes 9Fh A0h 20h 1Dh 9Dh 20h General Purpose Registers 3Fh 40h BFh C0h 96 Bytes General Purpose Registers 64 Bytes 6Fh Accesses 70h-7Fh 7Fh Bank 0 F0h 70h FFh 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Note 1: F0h FFh Bank 1 Unimplemented data memory locations, read as ‘0’. Not a physical register. © 2007 Microchip Technology Inc. Accesses 70h-7Fh Note Preliminary 1: Not a physical register. DS41288C-page 13 PIC16F610/616/16HV610/616 TABLE 2-1: Addr Name PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 113 01h TMR0 Timer0 Module’s Register xxxx xxxx 43, 113 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 113 03h STATUS 16, 113 04h FSR 05h PORTA IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx Indirect Data Memory Address Pointer — xxxx xxxx 22, 113 — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 31, 113 — — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 00xx 40, 113 — 06h — 07h PORTC Unimplemented 08h — Unimplemented — 09h — Unimplemented — — ---0 0000 22, 113 — 0Ah PCLATH — 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 18, 113 0Ch PIR1 — ADIF(2) CCP1IF(2) C2IF C1IF — TMR2IF(2) TMR1IF -000 0-00 20, 113 — — Write Buffer for upper 5 bits of Program Counter 0Dh — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 10h T1CON 11h TMR2(2) 12h T2CON(2) 13h CCPR1L(2) 14h CCPR1H(2) 15h CCP1CON(2) 16h PWM1CON(2) 17h ECCPAS(2) 18h — 19h VRCON Unimplemented T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON Timer2 Module Register — — xxxx xxxx 47, 113 xxxx xxxx 47, 113 0000 0000 50, 113 0000 0000 53, 113 -000 0000 54, 113 Capture/Compare/PWM Register 1 Low Byte XXXX XXXX 84, 113 Capture/Compare/PWM Register 1 High Byte XXXX XXXX 84, 113 0000 0000 83, 113 0000 0000 83, 113 — TOUTPS3 P1M1 P1M0 PRSEN PDC6 TOUTPS2 DC1B1 TOUTPS1 DC1B0 TOUTPS0 CCP1M3 TMR2ON CCP1M2 T2CKPS1 CCP1M1 T2CKPS0 CCP1M0 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 — — C2VREN VRR FVREN VR3 VR2 VR1 VR0 0000 0000 70, 113 ECCPASE ECCPAS2 Unimplemented C1VREN 0000 0000 100, 113 1Ah CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 60, 113 1Bh CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 61, 113 1Ch CM2CON1 MC1OUT MC2OUT — T1ACS C1HYS C2HYS T1GSS C2SYNC 00-0 0010 63, 113 1Dh — 1Eh ADRESH(2) 1Fh ADCON0(2) Legend: Note 1: 2: Unimplemented Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON — — xxxx xxxx 78, 113 0000 0000 76, 113 – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented IRP and RP1 bits are reserved, always maintain these bits clear. PIC16F616/16HV616 only. DS41288C-page 14 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 2-2: Addr PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 1 80h INDF 81h OPTION_REG Addressing this location uses contents of FSR to address data memory (not a physical register) 82h PCL 83h STATUS FSR 85h TRISA 86h INTEDG T0CS T0SE IRP(1) RP1(1) RP0 PS2 PS1 PS0 1111 1111 17, 113 TO PD Z DC C 0001 1xxx 16, 113 0000 0000 22, 113 Indirect Data Memory Address Pointer — TRISC — xxxx xxxx 22, 113 — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 31, 113 — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 40, 113 Unimplemented — xxxx xxxx 22, 113 PSA Program Counter’s (PC) Least Significant Byte 84h 87h RAPU — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH — 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 18, 113 8Ch PIE1 — ADIE(3) CCP1IE(3) C2IE C1IE — TMR2IE(3) TMR1IE -000 0-00 19, 113 — — — — — POR BOR ---- --qq 21, 113 — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 29, 113 ANS7 ANS6 ANS5 ANS4 ANS3(3) ANS2(3) ANS1 ANS0 1111 1111 32, 114 8Dh 8Eh — PCON 8Fh 90h — OSCTUNE 91h ANSEL 92h PR2(3) — — Write Buffer for upper 5 bits of Program Counter Unimplemented — ---0 0000 22, 113 — Unimplemented — Timer2 Module Period Register — — 1111 1111 53, 114 93h — Unimplemented — — 94h — Unimplemented — — 95h WPUA 96h IOCA — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 33, 114 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 33, 114 97h — Unimplemented — — 98h — Unimplemented — — 99h SRCON0 9Ah SRCON1 SR1 SR0 C1SEN C2REN PULSS PULSR — SRCS1 SRCS0 — — — — — SRCLKEN 0000 00-0 67, 114 — 00-- ---- 67, 114 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh ADRESL(3) 9Fh ADCON1(3) Legend: Note 1: 2: 3: Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result — ADCS2 ADCS1 ADCS0 — — xxxx xxxx 78, 114 — — -000 ---- 77, 114 – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented IRP and RP1 bits are reserved, always maintain these bits clear. RA3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 15 PIC16F610/616/16HV610/616 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (RAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see the Section 13.0 “Instruction Set Summary”. Note 1: Bits IRP and RP1 of the STATUS register are not used by the PIC16F610/616/16HV610/616 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). REGISTER 2-1: STATUS: STATUS REGISTER Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRP: This bit is reserved and should be maintained as ‘0’ bit 6 RP1: This bit is reserved and should be maintained as ‘0’ bit 5 RP0: Register Bank Select bit (used for direct addressing) 1 = Bank 1 (80h – FFh) 0 = Bank 0 (00h – 7Fh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is reversed. 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. DS41288C-page 16 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 2.2.2.2 OPTION Register Note: The OPTION register is a readable and writable register, which contains various control bits to configure: • • • • Timer0/WDT prescaler External RA2/INT interrupt Timer0 Weak pull-ups on PORTA REGISTER 2-2: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ of the OPTION register. See Section 5.1.3 “Software Programmable Prescaler”. OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on RA2/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits BIT VALUE 000 001 010 011 100 101 110 111 © 2007 Microchip Technology Inc. x = Bit is unknown TIMER0 RATE WDT RATE 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 Preliminary DS41288C-page 17 PIC16F610/616/16HV610/616 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GIE PEIE T0IE INTE RAIE T0IF INTF RAIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: RA2/INT External Interrupt Enable bit 1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt bit 3 RAIE: PORTA Change Interrupt Enable bit(1) 1 = Enables the PORTA change interrupt 0 = Disables the PORTA change interrupt bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = Timer0 register has overflowed (must be cleared in software) 0 = Timer0 register did not overflow bit 1 INTF: RA2/INT External Interrupt Flag bit 1 = The RA2/INT external interrupt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur bit 0 RAIF: PORTA Change Interrupt Flag bit 1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software) 0 = None of the PORTA <5:0> pins have changed state Note 1: 2: IOCA register must also be enabled. T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit. DS41288C-page 18 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 2.2.2.4 PIE1 Register The PIE1 register contains the peripheral interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit(1) 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 CCP1IE: CCP1 Interrupt Enable bit(1) 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 4 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 3 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit(1) 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: x = Bit is unknown PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 19 PIC16F610/616/16HV610/616 2.2.2.5 PIR1 Register The PIR1 register contains the peripheral interrupt flag bits, as shown in Register 2-5. REGISTER 2-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ADIF: A/D Interrupt Flag bit(1) 1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started bit 5 CCP1IF: CCP1 Interrupt Flag bit(1) Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 4 C2IF: Comparator C2 Interrupt Flag bit 1 = Comparator C2 output has changed (must be cleared in software) 0 = Comparator C2 output has not changed bit 3 C1IF: Comparator C1 Interrupt Flag bit 1 = Comparator C1 output has changed (must be cleared in software) 0 = Comparator C1 output has not changed bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit(1) 1 = Timer2 to PR2 match occurred (must be cleared in software) 0 = Timer2 to PR2 match has not occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software) 0 = Timer1 has not overflowed Note 1: PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’. DS41288C-page 20 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 2.2.2.6 PCON Register The Power Control (PCON) register (see Table 12-2) contains flag bits to differentiate between a: • • • • Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-6. REGISTER 2-6: PCON: POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0(1) — — — — — — POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: Reads as ‘0’ if Brown-out Reset is disabled. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 21 PIC16F610/616/16HV610/616 2.3 PCL and PCLATH 2.3.2 The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in Figure 2-5 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH). FIGURE 2-5: LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 12 8 7 0 PC The PIC16F610/616/16HV610/616 Family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. 8 PCLATH<4:0> 5 Instruction with PCL as Destination ALU Result PCLATH PCH 12 11 10 PCL 8 0 7 PC 2.4 GOTO, CALL 2 PCLATH<4:3> 11 OPCODE <10:0> Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. PCLATH 2.3.1 STACK MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 5 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program branch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit of the STATUS register, as shown in Figure 2-7. A simple program to clear RAM location 40h-4Fh using indirect addressing is shown in Example 2-1. EXAMPLE 2-1: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE INDIRECT ADDRESSING 0x40 FSR INDF FSR, F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue For more information refer to Application Note AN556, “Implementing a Table Read” (DS00556). DS41288C-page 22 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC16F610/16HV610 Direct Addressing (1) RP1 RP0 6 Bank Select From Opcode Indirect Addressing IRP(1) 0 File Select Register Bank Select Location Select 00 01 10 0 Location Select 11 00h Data Memory 7 180h NOT USED(2) 20h 40h 70h 1FFh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail, see Figure 2-3. Unimplemented data memory locations, read as ‘0’. Note 1: 2: The RP1 and IRP bits are reserved; always maintain these bits clear. Accesses in Bank 2 and Bank 3 are mirrored back into Bank 0 and Bank 1, respectively. FIGURE 2-7: DIRECT/INDIRECT ADDRESSING PIC16F616/16HV616 Direct Addressing RP1(1) RP0 Bank Select 6 From Opcode Indirect Addressing IRP(1) 0 7 File Select Register Bank Select Location Select 00 01 10 0 Location Select 11 00h 180h NOT USED(2) Data Memory 40h 70h 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail, see Figure 2-4. Unimplemented data memory locations, read as ‘0’. Note 1: 2: The RP1 and IRP bits are reserved; always maintain these bits clear. Accesses in Bank 2 and Bank 3 are mirrored back into Bank 0 and Bank 1, respectively. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 23 PIC16F610/616/16HV610/616 NOTES: DS41288C-page 24 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 3.0 OSCILLATOR MODULE The Oscillator module can be configured in one of eight clock modes. 3.1 Overview 1. 2. 3. The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the Oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured with a choice of two selectable speeds: internal or external system clock source. 4. 5. 6. 7. 8. EC – External clock with I/O on OSC2/CLKOUT. LP – 32 kHz Low-Power Crystal mode. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode. HS – High Gain Crystal or Ceramic Resonator mode. RC – External Resistor-Capacitor (RC) with FOSC/4 output on OSC2/CLKOUT. RCIO – External Resistor-Capacitor (RC) with I/O on OSC2/CLKOUT. INTOSC – Internal oscillator with FOSC/4 output on OSC2 and I/O on OSC1/CLKIN. INTOSCIO – Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT. Clock Source modes are configured by the FOSC<2:0> bits in the Configuration Word register (CONFIG). The Internal Oscillator module provides a selectable system clock mode of either 4 MHz (Postscaler) or 8 MHz (INTOSC). FIGURE 3-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FOSC<2:0> IOSCFS (Configuration Word Register) External Oscillator OSC2 Sleep INTOSC Internal Oscillator MUX LP, XT, HS, RC, RCIO, EC OSC1 System Clock (CPU and Peripherals) INTOSC 8 MHz Postscaler 4 MHz © 2007 Microchip Technology Inc. Preliminary DS41288C-page 25 PIC16F610/616/16HV610/616 3.2 3.3.2 Clock Source Modes Clock Source modes can be classified as external or internal. • External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. • Internal clock sources are contained internally within the Oscillator module. The Oscillator module has two selectable clock frequencies: 4 MHz and 8 MHz The system clock can be selected between external or internal clock sources via the FOSC<2:0> bits of the Configuration Word register. 3.3 OSCILLATOR START-UP TIMER (OST) If the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the Oscillator module. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 3-1. External Clock Modes 3.3.1 EC MODE The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure 3-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 3-2: EXTERNAL CLOCK (EC) MODE OPERATION OSC1/CLKIN Clock from Ext. System PIC® MCU I/O Note 1: OSC2/CLKOUT(1) Alternate pin functions are listed in the Section 1.0 “Device Overview”. TABLE 3-1: OSCILLATOR DELAY EXAMPLES Switch From Switch To Frequency Oscillator Delay Sleep/POR INTOSC 4 MHz to 8 MHz Oscillator Warm-Up Delay (TWARM) Sleep/POR EC, RC DC – 20 MHz 2 Instruction Cycles Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST) DS41288C-page 26 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 3.3.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-3). The mode selects a low, medium or high gain setting of the internal inverteramplifier to support various resonator types and speed. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). 3: For oscillator design assistance, reference the following Microchip Applications Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 3-3 and Figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively. FIGURE 3-3: FIGURE 3-4: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) PIC® MCU OSC1/CLKIN C1 PIC® MCU OSC1/CLKIN C1 To Internal Logic RP(3) RF(2) Sleep To Internal Logic Quartz Crystal C2 CERAMIC RESONATOR OPERATION (XT OR HS MODE) RS(1) RF(2) C2 Ceramic RS(1) Resonator Sleep Note 1: OSC2/CLKOUT Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 MΩ to 10 MΩ). © 2007 Microchip Technology Inc. Preliminary OSC2/CLKOUT A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 MΩ to 10 MΩ). 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. DS41288C-page 27 PIC16F610/616/16HV610/616 3.3.4 EXTERNAL RC MODES 3.4 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 3-5 shows the external RC mode connections. FIGURE 3-5: EXTERNAL RC MODES VDD PIC® MCU REXT OSC1/CLKIN Internal Clock CEXT VSS FOSC/4 or I/O(2) Internal Clock Modes The Oscillator module provides a selectable system clock source of either 4 MHz or 8 MHz. The selectable frequency is configured through the IOSCFS bit of the Configuration Word. The frequency of the internal oscillator can be can be user-adjusted via software using the OSCTUNE register. 3.4.1 INTOSC AND INTOSCIO MODES The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the FOSC<2:0> bits in the Configuration Word register (CONFIG). See Section 12.0 “Special Features of the CPU” for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O. OSC2/CLKOUT(1) Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V 3 kΩ ≤ REXT ≤ 100 kΩ, 3-5V CEXT > 20 pF, 2-5V Note 1: 2: Alternate pin functions are listed in Section 1.0 “Device Overview”. Output depends upon RC or RCIO Clock mode. In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes an additional general purpose I/O pin. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: • threshold voltage variation • component tolerances • packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used. DS41288C-page 28 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 3.4.1.1 OSCTUNE Register The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. The oscillator is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-1). REGISTER 3-1: When the OSCTUNE register is modified, the frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = • • • 00001 = 00000 = Oscillator module is running at the manufacturer calibrated frequency. 11111 = • • • 10000 = Minimum frequency TABLE 3-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Value on POR, BOR Value on all other Resets(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CONFIG(2) IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu Legend: Note 1: 2: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. See Configuration Word register (Register 12-1) for operation of all register bits. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 29 PIC16F610/616/16HV610/616 NOTES: DS41288C-page 30 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 4.0 I/O PORTS port pins are read, this value is modified and then written to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1. There are as many as eleven general purpose I/O pins and an input pin available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. 4.1 The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. PORTA and the TRISA Registers Note: PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 4-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as ‘1’. Example 4-1 shows how to initialize PORTA. EXAMPLE 4-1: Reading the PORTA register (Register 4-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the REGISTER 4-1: The ANSEL register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’ and cannot generate an interrupt. BCF CLRF BSF CLRF MOVLW MOVWF STATUS,RP0 PORTA STATUS,RP0 ANSEL 0Ch TRISA BCF STATUS,RP0 INITIALIZING PORTA ;Bank 0 ;Init PORTA ;Bank 1 ;digital I/O ;Set RA<3:2> as inputs ;and set RA<5:4,1:0> ;as outputs ;Bank 0 PORTA: PORTA REGISTER U-0 U-0 R/W-x R/W-0 R-x R/W-0 R/W-0 R/W-0 — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Pin bit 1 = PORTA pin is > VIH 0 = PORTA pin is < VIL REGISTER 4-2: x = Bit is unknown TRISA: PORTA TRI-STATE REGISTER U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISA<5:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note 1: 2: x = Bit is unknown TRISA<3> always reads ‘1’. TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 31 PIC16F610/616/16HV610/616 4.2 4.2.3 Additional Pin Functions INTERRUPT-ON-CHANGE Every PORTA pin on the PIC16F610/616/16HV610/ 616 has an interrupt-on-change option and a weak pullup option. The next three sections describe these functions. Each PORTA pin is individually configurable as an interrupt-on-change pin. Control bits IOCAx enable or disable the interrupt function for each pin. Refer to Register 4-5. The interrupt-on-change is disabled on a Power-on Reset. 4.2.1 For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTA. The ‘mismatch’ outputs of the last read are OR’d together to set the PORTA Change Interrupt Flag bit (RAIF) in the INTCON register (Register 2-3). ANSEL REGISTER The ANSEL register is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSEL bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. 4.2.2 WEAK PULL-UPS Each of the PORTA pins, except RA3, has an individually configurable internal weak pull-up. Control bits WPUAx enable or disable each pull-up. Refer to Register 4-4. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the RAPU bit of the OPTION register). A weak pull-up is automatically enabled for RA3 when configured as MCLR and disabled when RA3 is an I/O. There is no software control of the MCLR pull-up. REGISTER 4-3: This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) Any read or write of PORTA. This will end the mismatch condition, then, Clear the flag bit RAIF. b) A mismatch condition will continue to set flag bit RAIF. Reading PORTA will end the mismatch condition and allow flag bit RAIF to be cleared. The latch holding the last read value is not affected by a MCLR nor BOR Reset. After these resets, the RAIF flag will continue to be set if a mismatch is present. Note: If a change on the I/O pin should occur when any PORTA operation is being executed, then the RAIF interrupt flag may not get set. ANSEL: ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown ANS<7:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS41288C-page 32 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 REGISTER 4-4: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPUA<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPUA<2:0>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: 2: 3: 4: x = Bit is unknown Global RAPU must be enabled for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0). The RA3 pull-up is enabled when configured as MCLR and disabled as an input in the Configuration Word. WPUA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. REGISTER 4-5: IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCA<5:0>: Interrupt-on-change PORTA Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: 2: x = Bit is unknown Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. IOCA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 33 PIC16F610/616/16HV610/616 4.2.4 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the Comparator or the ADC, refer to the appropriate section in this data sheet. RA0/AN0(1)/C1IN+/ICSPDAT 4.2.4.1 Figure 4-1 shows the diagram for this pin. The RA0 pin is configurable to function as one of the following: • • • • RA1/AN1(1)/C12IN0-/VREF(1)/ ICSPCLK 4.2.4.2 Figure 4-1 shows the diagram for this pin. The RA1 pin is configurable to function as one of the following: • • • • • a general purpose I/O an analog input for the ADC(1) an analog inverting input to the comparator a voltage reference input for the ADC(1) In-Circuit Serial Programming clock Note 1: PIC16F616/16HV616 only. a general purpose I/O an analog input for the ADC(1) an analog non-inverting input to the comparator In-Circuit Serial Programming data FIGURE 4-1: BLOCK DIAGRAM OF RA<1:0> Analog(1) Input Mode VDD Data Bus D WR WPUA Q Weak CK Q RAPU VDD RD WPUA D WR PORTA Q I/O Pin CK Q VSS D WR TRISA Q CK Q RD TRISA Analog(1) Input Mode RD PORTA D WR IOCA Q Q CK Q D EN RD IOCA Q Interrupt-onChange S(2) R From other RA<5:1> pins (RA0) RA<5:2, 0> pins (RA1) RD PORTA To Comparator To A/D Converter(3) 1: Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC16F616/16HV616 only. DS41288C-page 34 D EN Write ‘0’ to RAIF Note Q Q1 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 RA2/AN2(1)/T0CKI/INT/C1OUT 4.2.4.3 Figure 4-2 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following: • • • • • a general purpose I/O an analog input for the ADC(1) the clock input for TMR0 an external edge triggered interrupt a digital output from Comparator C1 Note 1: PIC16F616/16HV616 only. FIGURE 4-2: BLOCK DIAGRAM OF RA2 Analog(1) Input Mode VDD Data Bus D WR WPUA Q Weak CK Q C1OE Enable RAPU VDD RD WPUA C1OE D WR PORTA Q 0 I/O Pin CK Q D WR TRISA 1 VSS Q CK Q RD TRISA Analog(1) Input Mode RD PORTA D WR IOAC Q Q CK Q D EN RD IOAC Q Interrupt-onChange Q S(2) R Q1 D EN From other RA<5:3, 1:0> pins Write ‘0’ to RAIF RD PORTA To Timer0 To INT To A/D Converter(3) Note 1: Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 35 PIC16F610/616/16HV610/616 4.2.4.4 RA3/MCLR/VPP Figure 4-3 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset with weak pull-up FIGURE 4-3: BLOCK DIAGRAM OF RA3 VDD MCLRE Weak Data Bus MCLRE Reset RD TRISA Input Pin VSS MCLRE RD PORTA D WR IOCA CK Q Q D Q Q1 EN RD IOCA Q Interrupt-onChange Q S(1) R VSS D EN From other RA<5:4, 2:0> pins RD PORTA Write ‘0’ to RAIF Note 1: DS41288C-page 36 Set has priority over Reset Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 4.2.4.5 RA4/AN3(1)/T1G/OSC2/CLKOUT • a Timer1 gate (count enable) • a crystal/resonator connection • a clock output Figure 4-4 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: Note 1: PIC16F616/16HV616 only. • a general purpose I/O • an analog input for the ADC(1) FIGURE 4-4: BLOCK DIAGRAM OF RA4 Analog(3) Input Mode Data Bus D WR WPUA CLK(1) Modes Q VDD CK Q Weak RAPU RD WPUA Oscillator Circuit OSC1 VDD CLKOUT Enable D WR PORTA Q FOSC/4 CK Q 1 0 I/O Pin CLKOUT Enable D WR TRISA Q CK Q VSS INTOSC/ RC/EC(2) CLKOUT Enable RD TRISA Analog Input Mode RD PORTA D Q CK Q WR IOCA Q D EN RD IOCA Q Interrupt-onChange Q S(4) R Q1 D EN From other RA<5, 3:0> pins RD PORTA To T1G Write ‘0’ to RAIF To A/D Converter(5) Note 1: CLK modes are XT, HS, LP, TMR1 LP and CLKOUT Enable. 2: With CLKOUT option. 3: Analog Input mode comes from ANSEL. 4: Set has priority over Reset. 5: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 37 PIC16F610/616/16HV610/616 4.2.4.6 RA5/T1CKI/OSC1/CLKIN • • • • Figure 4-5 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: FIGURE 4-5: a general purpose I/O a Timer1 clock input a crystal/resonator connection a clock input BLOCK DIAGRAM OF RA5 INTOSC Mode TMR1LPEN(1) Data Bus D WR WPUA CK VDD Q Weak Q RAPU RD WPUA Oscillator Circuit OSC2 D WR PORTA CK VDD Q Q I/O Pin D WR TRISA CK Q Q VSS INTOSC Mode RD TRISA RD PORTA D WR IOCA CK Q Q D Q EN Q1 RD IOCA Q Q Interrupt-onChange S(2) R D EN From other RA<4:0> pins RD PORTA Write ‘0’ to RAIF To Timer1 Note 1: 2: Timer1 LP Oscillator enabled. Set has priority over Reset. DS41288C-page 38 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 4-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000 GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 INTCON IOCA OPTION_REG PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 --u0 u000 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 WPUA — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 --11 -111 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 39 PIC16F610/616/16HV610/616 4.3 PORTC and the TRISC Registers PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to A/D Converter (ADC) or Comparator. For specific information about individual functions such as the Enhanced CCP or the ADC, refer to the appropriate section in this data sheet. Note: The ANSEL register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’ and cannot generate an interrupt. REGISTER 4-6: EXAMPLE 4-2: BCF CLRF BSF CLRF MOVLW MOVWF STATUS,RP0 PORTC STATUS,RP0 ANSEL 0Ch TRISC BCF STATUS,RP0 INITIALIZING PORTC ;Bank 0 ;Init PORTC ;Bank 1 ;digital I/O ;Set RC<3:2> as inputs ;and set RC<5:4,1:0> ;as outputs ;Bank 0 PORTC: PORTC REGISTER U-0 U-0 R/W-x R/W-x R/W-0 R/W-0 R/W-x R/W-x — — RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RC<5:0>: PORTC I/O Pin bit 1 = PORTC pin is > VIH 0 = PORTC pin is < VIL REGISTER 4-7: x = Bit is unknown TRISC: PORTC TRI-STATE REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISC<5:0>: PORTC Tri-State Control bit 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output DS41288C-page 40 Preliminary x = Bit is unknown © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 RC0/AN4(1)/C2IN+ 4.3.1 RC2/AN6(1)/C12IN2-/P1D(1) 4.3.3 The RC0 is configurable to function as one of the following: The RC2 is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC(1) • an analog non-inverting input to Comparator C2 • • • • RC1/AN5(1)/C12IN1- 4.3.2 The RC1 is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC(1) • an analog inverting input to the comparator FIGURE 4-6: BLOCK DIAGRAM OF RC0 AND RC1 D CK a general purpose I/O an analog input for the ADC(1) an analog inverting input to Comparators C1 and C2 a digital output from the Enhanced CCP(1) Note 1: PIC16F616/16HV616 only. VDD Q CCPOUT(2) Enable Q I/O Pin CK BLOCK DIAGRAM OF RC2 AND RC3 Data Bus D D WR TRISC The RC3 is configurable to function as one of the following: FIGURE 4-7: Data Bus WR PORTC RC3/AN7(1)/C12IN3-/P1C(1) 4.3.4 • • • • Note 1: PIC16F616/16HV616 only. a general purpose I/O an analog input for the ADC(1) an analog input to Comparators C1 and C2 a digital output from the Enhanced CCP(1) Q CK Q CCPOUT 1 0 Q VSS D Analog Input Mode(1) RD TRISC WR PORTC VDD Q WR TRISC CK Q VSS Analog Input Mode(1) RD TRISC RD PORTC I/O Pin Q To Comparators RD PORTC To A/D Converter To A/D Converter Note 1: Analog Input mode comes from ANSEL or Comparator mode. © 2007 Microchip Technology Inc. Preliminary Note 1: Analog Input mode comes from ANSEL. 2: PIC16F616/16HV616 only. DS41288C-page 41 PIC16F610/616/16HV610/616 RC4/C2OUT/P1B(1) 4.3.5 RC5/CCP1(1)/P1A(1) 4.3.6 The RC4 is configurable to function as one of the following: The RC5 is configurable to function as one of the following: • a general purpose I/O • a digital output from Comparator C2 • a digital output from the Enhanced CCP(1) • a general purpose I/O • a digital input/output for the Enhanced CCP(1) Note 1: PIC16F616/16HV616 only. Note 1: PIC16F616/16HV616 only. 2: Enabling both C2OUT and P1B will cause a conflict on RC4 and create unpredictable results. Therefore, if C2OUT is enabled, the ECCP can not be used in Half-Bridge or Full-Bridge mode and vice-versa. FIGURE 4-8: BLOCK DIAGRAM OF RC4 FIGURE 4-9: Data bus D WR PORTC C2OE CCP1M<3:0> VDD CCP1M<3:0> CCPOUT/P1B 1 Data Bus WR PORTC D Q CCP1OUT(1)/ 1 P1A 0 I/O Pin Q CK Q VSS I/O Pin Q RD PORTC CK Q WR TRISC CK VDD RD TRISC 0 D WR TRISC CCP1OUT(1) Enable Q D C2OE C2OUT BLOCK DIAGRAM OF RC5 PIN VSS To Enhanced CCP Note Q 1: PIC16F616/16HV616 only. CK Q RD TRISC RD PORTC Note 1: Port/Peripheral Select signals selects between PORT data and peripheral output. TABLE 4-2: Name ANSEL SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000 PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 00xx --uu 00uu TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. DS41288C-page 42 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 5.0 TIMER0 MODULE 5.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the following features: When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. • • • • • 5.1.1 8-bit timer/counter register (TMR0) 8-bit prescaler (shared with Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow 8-BIT TIMER MODE When used as a timer, the Timer0 module will increment every instruction cycle (without prescaler). Timer mode is selected by clearing the T0CS bit of the OPTION register to ‘0’. Figure 5-1 is a block diagram of the Timer0 module. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: 5.1.2 The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. 8-BIT COUNTER MODE When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’. FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER FOSC/4 Data Bus 0 8 1 Sync 2 Tcy 1 T0CKI pin T0SE TMR0 0 0 T0CS Set Flag bit T0IF on Overflow 8-bit Prescaler PSA 1 PSA 8 3 PS<2:0> WDT Time-out Watchdog Timer WDTE 1 0 PSA Note 1: 2: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. WDTE bit is in the Configuration Word register. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 43 PIC16F610/616/16HV610/616 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. 5.1.3.1 Switching Prescaler Between Timer0 and WDT Modules As a result of having the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changing the prescaler assignment from Timer0 to the WDT module, the instruction sequence shown in Example 5-1 must be executed. EXAMPLE 5-1: BANKSEL CLRWDT CLRF TMR0 CHANGING PRESCALER (TIMER0 → WDT) ; ;Clear WDT TMR0 ;Clear TMR0 and ;prescaler BANKSEL OPTION_REG ; BSF OPTION_REG,PSA ;Select WDT CLRWDT ; ; MOVLW b’11111000’ ;Mask prescaler ANDWF OPTION_REG,W ;bits IORLW b’00000101’ ;Set WDT prescaler MOVWF OPTION_REG ;to 1:32 DS41288C-page 44 When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 5-2). EXAMPLE 5-2: CHANGING PRESCALER (WDT → TIMER0) CLRWDT ;Clear WDT and ;prescaler BANKSEL OPTION_REG ; MOVLW b’11110000’ ;Mask TMR0 select and ANDWF OPTION_REG,W ;prescaler bits IORLW b’00000011’ ;Set prescale to 1:16 MOVWF OPTION_REG ; 5.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register. Note: 5.1.5 The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. USING TIMER0 WITH AN EXTERNAL CLOCK When Timer0 is in Counter mode, the synchronization of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in Section 15.0 “Electrical Specifications”. Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits BIT VALUE 000 001 010 011 100 101 110 111 TABLE 5-1: Name TMR0 INTCON OPTION_REG TRISA TMR0 RATE WDT RATE 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 x = Bit is unknown SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Timer0 Modules Register GIE PEIE RAPU INTEDG — — Value on all other Resets Bit 4 Bit 5 xxxx xxxx uuuu uuuu TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 45 PIC16F610/616/16HV610/616 NOTES: DS41288C-page 46 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 6.0 TIMER1 MODULE WITH GATE CONTROL 6.1 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. The Timer1 module is a 16-bit timer/counter with the following features: • • • • • • • • • • • 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 3-bit prescaler Optional LP oscillator Synchronous or asynchronous operation Timer1 gate (count enable) via comparator or T1G pin Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) Time base for the Capture/Compare function Special Event Trigger (with ECCP) Comparator output synchronization to Timer1 clock When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter. 6.2 Clock Source Selection The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS = 0, the clock source is FOSC/4. When TMR1CS = 1, the clock source is supplied externally. Clock Source Figure 6-1 is a block diagram of the Timer1 module. FIGURE 6-1: Timer1 Operation TMR1CS T1ACS FOSC/4 0 0 FOSC 0 1 T1CKI pin 1 x TIMER1 BLOCK DIAGRAM TMR1GE T1GINV TMR1ON Set flag bit TMR1IF on Overflow TMR1 TMR1H To C2 Comparator Module Timer1 Clock (2) TMR1L Synchronized clock input 0 EN 1 Oscillator (1) T1SYNC OSC1/T1CKI 1 Prescaler 1, 2, 4, 8 Synchronize(3) det 0 OSC2/T1G 2 T1CKPS<1:0> TMR1CS 1 INTOSC Without CLKOUT T1OSCEN FOSC FOSC/4 Internal Clock 1 0 C2OUT 0 T1GSS T1ACS Note 1: 2: 3: ST Buffer is low power type when using LP osc, or high speed type when using T1CKI. Timer1 register increments on rising edge. Synchronize does not operate while in Sleep. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 47 PIC16F610/616/16HV610/616 6.2.1 INTERNAL CLOCK SOURCE 6.5 When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler. 6.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 6.5.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”). Note: If an external clock oscillator is needed (and the microcontroller is using the INTOSC without CLKOUT), Timer1 can use the LP oscillator as a clock source. Note: 6.3 In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge. 6.4 Timer1 Oscillator A low-power 32.768 kHz crystal oscillator is built-in between pins OSC1 (input) and OSC2 (output). The oscillator is enabled by setting the T1OSCEN control bit of the T1CON register. The oscillator will continue to run during Sleep. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is derived from the internal oscillator or when the oscillator is in the LP Oscillator mode. The user must provide a software time delay to ensure proper oscillator start-up. TRISA5 and TRISA4 bits are set when the Timer1 oscillator is enabled. RA5 and RA4 bits read as ‘0’ and TRISA5 and TRISA4 bits read as ‘1’. Note: 6.5.1 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. Timer1 Operation in Asynchronous Counter Mode When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 6.6 Timer1 Gate Timer1 gate source is software configurable to be the T1G pin or the output of Comparator C2. This allows the device to directly time external events using T1G or analog events using Comparator C2. See the CM2CON1 register (Register 8-3) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many other applications. For more information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com). Note: TMR1GE bit of the T1CON register must be set to use either T1G or C2OUT as the Timer1 gate source. See the CM2CON1 register (Register 8-3) for more information on selecting the Timer1 gate source. Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or Comparator C2 output. This configures Timer1 to measure either the active-high or active-low time between events. DS41288C-page 48 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 6.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • • • TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register T1SYNC bit of the T1CON register TMR1CS bit of the T1CON register T1OSCEN bit of the T1CON register (can be set) The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: 6.8 The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see Section 10.0 “Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC16F616/16HV616 Only)”. 6.10 ECCP Special Event Trigger (PIC16F616/16HV616 Only) When the ECCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The ECCP module may still be configured to generate a ECCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer1. Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: • TMR1ON bit of the T1CON register must be set • TMR1IE bit of the PIE1 register must be set • PEIE bit of the INTCON register must be set The device will wake-up on an overflow and execute the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h). 6.9 In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. ECCP Capture/Compare Time Base (PIC16F616/16HV616 Only) The ECCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. Timer1 should be synchronized to the FOSC to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the ECCP, the write will take precedence. For more information, see Section 10.2.4 “Special Event Trigger”. 6.11 Comparator Synchronization The same clock used to increment Timer1 can also be used to synchronize the comparator output. This feature is enabled in the Comparator module. When using the comparator for Timer1 gate, the comparator output should be synchronized to Timer1. This ensures Timer1 does not miss an increment if the comparator changes. For more information, see Section 8.8.2 “Synchronizing Comparator C2 Output to Timer1”. FIGURE 6-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 49 PIC16F610/616/16HV610/616 6.12 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 6-1: R/W-0 R/W-0 (1) T1GINV T1CON: TIMER1 CONTROL REGISTER (2) TMR1GE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 6 TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 Gate function 0 = Timer1 is always counting bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value bit 3 T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock If TMR1ACS = 0: FOSC/4 If TMR1ACS = 1: FOSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: 2: x = Bit is unknown T1GINV bit inverts the Timer1 gate logic, regardless of source. TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1 register, as a Timer1 gate source. DS41288C-page 50 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 6-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 0000 -000 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 CM2CON1 MC1OUT MC2OUT — T1ACS C1HYS C2HYS T1GSS C2SYNC 00-0 0010 00-0 0010 GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 -000 0-00 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 -000 0-00 INTCON TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0000 0000 uuuu uuuu T1CON Legend: Note 1: T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 51 PIC16F610/616/16HV610/616 NOTES: DS41288C-page 52 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 7.0 TIMER2 MODULE (PIC16F616/16HV616 ONLY) The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. The Timer2 module is an 8-bit timer with the following features: • • • • • 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register. The Timer2 postscaler is controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared when: See Figure 7-1 for a block diagram of Timer2. 7.1 Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by setting the TMR2ON bit to a ‘0’. Timer2 Operation The clock input to the Timer2 module is the system instruction clock (FOSC/4). The clock is fed into the Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. • A write to TMR2 occurs. • A write to T2CON occurs. • Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset). Note: TMR2 is not cleared when T2CON is written. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: • TMR2 is reset to 00h on the next increment cycle. • The Timer2 postscaler is incremented The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register. FIGURE 7-1: TIMER2 BLOCK DIAGRAM TMR2 Output FOSC/4 Prescaler 1:1, 1:4, 1:16 2 TMR2 Sets Flag bit TMR2IF Reset Comparator EQ Postscaler 1:1 to 1:16 T2CKPS<1:0> PR2 4 TOUTPS<3:0> © 2007 Microchip Technology Inc. Preliminary DS41288C-page 53 PIC16F610/616/16HV610/616 REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 TABLE 7-1: x = Bit is unknown SUMMARY OF ASSOCIATED TIMER2 REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 -000 0-00 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 -000 0-00 PR2 Timer2 Module Period Register 1111 1111 1111 1111 TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000 -000 0000 -000 0000 T2CON — Legend: Note 1: x = unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. PIC16F616/16HV616 only. TOUTPS3 DS41288C-page 54 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON Preliminary T2CKPS1 T2CKPS0 © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.0 COMPARATOR MODULE FIGURE 8-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the device. The Analog Comparator module includes the following features: • • • • • • • • • • • • Independent comparator control Programmable input selection Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep PWM shutdown Timer1 gate (count enable) Output synchronization to Timer1 clock input SR Latch Programmable and fixed voltage reference User-enable Comparator Hysteresis Note: 8.1 SINGLE COMPARATOR VIN+ + VIN- – Output VINVIN+ Output Note: The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. Only Comparator C2 can be linked to Timer1. Comparator Overview A single comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 55 PIC16F610/616/16HV610/616 FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> C1POL 2 D C12IN0- 0 C12IN1C12IN2- 1 MUX 2 C12IN3- 3 Q1 To Data Bus Q EN RD_CM1CON0 Set C1IF D Q3*RD_CM1CON0 Q EN CL To PWM Logic Reset C1ON(1) C1R C1IN+ C1OE 0 MUX 1 C1VREF C1VIN- C1 C1VIN+ + C1OUT C1OUT pin(2) C1POL Note 1: 2: FIGURE 8-3: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. Output shown for reference only. See I/O port pin block diagram for more detail. COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM C2POL D Q1 To Data Bus Q EN RD_CM2CON0 C2CH<1:0> Set C2IF 2 C12IN0- 0 C12IN1C2IN2- 1 MUX 2 C2IN3- 3 C2R D Q3*RD_CM2CON0 C2ON(1) C2VREF Note 1: 2: DS41288C-page 56 0 MUX 1 EN CL Reset C2VINC2VIN+ To other peripherals C2OUT C2 C2SYNC C2POL D C2IN+ Q Q C2OE 0 MUX 1 C2OUT pin(2) From Timer1 Clock SYNCC2OUT To Timer1 Gate To SR Latch When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate. Output shown for reference only. See I/O port pin block diagram for more detail. Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.2 8.2.4 Comparator Control Each comparator has a separate control and Configuration register: CM1CON0 for Comparator C1 and CM2CON0 for Comparator C2. In addition, Comparator C2 has a second control register, CM2CON1, for controlling the interaction with Timer1 and simultaneous reading of both comparator outputs. The CM1CON0 and CM2CON0 registers (see Registers 8-1 and 8-2, respectively) contain the control and Status bits for the following: • • • • • Enable Input selection Reference selection Output selection Output polarity 8.2.1 COMPARATOR ENABLE COMPARATOR INPUT SELECTION The CxCH<1:0> bits of the CMxCON0 register direct one of four analog input pins to the comparator inverting input. Note: 8.2.3 To use CxIN+ and CxIN- pins as analog inputs, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. COMPARATOR REFERENCE SELECTION Setting the CxR bit of the CMxCON0 register directs an internal voltage reference or an analog input pin to the non-inverting input of the comparator. See Section 8.11 “Comparator Voltage Reference” for more information on the internal voltage reference module. © 2007 Microchip Technology Inc. The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CM2CON1 register. In order to make the output available for an external connection, the following conditions must be true: • CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set. Note 1: The CxOE bit overrides the PORT data latch. Setting the CxON has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator for minimum current consumption. 8.2.2 COMPARATOR OUTPUT SELECTION 8.2.5 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 8-1 shows the output state versus input conditions, including polarity control. TABLE 8-1: COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS Input Condition CxPOL CxOUT CxVIN- > CxVIN+ 0 0 CxVIN- < CxVIN+ 0 1 CxVIN- > CxVIN+ 1 1 CxVIN- < CxVIN+ 1 0 8.3 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 15.0 “Electrical Specifications” for more details. Preliminary DS41288C-page 57 PIC16F610/616/16HV610/616 8.4 FIGURE 8-4: Comparator Interrupt Operation The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusive-or gate (see Figure 8-2 and Figure 8-3). One latch is updated with the comparator output level when the CMxCON0 register is read. This latch retains the value until the next read of the CMxCON0 register or the occurrence of a Reset. The other latch of the mismatch circuit is updated on every Q1 system clock. A mismatch condition will occur when a comparator output change is clocked through the second latch on the Q1 clock cycle. At this point the two mismatch latches have opposite output levels which is detected by the exclusive-or gate and fed to the interrupt circuitry. The mismatch condition persists until either the CMxCON0 register is read or the comparator output returns to the previous state. Note 1: A write operation to the CMxCON0 register will also clear the mismatch condition because all writes include a read operation at the beginning of the write cycle. COMPARATOR INTERRUPT TIMING W/O CMxCON0 READ Q1 Q3 CxIN+ TRT CxOUT Set CxIF (edge) CxIF reset by software FIGURE 8-5: COMPARATOR INTERRUPT TIMING WITH CMxCON0 READ Q1 Q3 CxIN+ TRT CxOUT Set CxIF (edge) CxIF cleared by CMxCON0 read reset by software 2: Comparator interrupts will operate correctly regardless of the state of CxOE. The comparator interrupt is set by the mismatch edge and not the mismatch level. This means that the interrupt flag can be reset without the additional step of reading or writing the CMxCON0 register to clear the mismatch registers. When the mismatch registers are cleared, an interrupt will occur upon the comparator’s return to the previous state, otherwise no interrupt will be generated. Note 1: If a change in the CMxCON0 register (CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CxIF of the PIR1 register interrupt flag may not get set. Software will need to maintain information about the status of the comparator output, as read from the CMxCON0 register, or CM2CON1 register, to determine the actual change that has occurred. 2: When either comparator is first enabled, bias circuitry in the comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 μs for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. The CxIF bit of the PIR1 register is the comparator interrupt flag. This bit must be reset in software by clearing it to ‘0’. Since it is also possible to write a ‘1’ to this register, an interrupt can be generated. The CxIE bit of the PIE1 register and the PEIE and GIE bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabled, although the CxIF bit of the PIR1 register will still be set if an interrupt condition occurs. DS41288C-page 58 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.5 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in Section 15.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off by clearing the CxON bit of the CMxCON0 register. A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CxIE bit of the PIE1 register and the PEIE bit of the INTCON register must be set. The instruction following the Sleep instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the interrupt service routine. 8.6 Effects of a Reset A device Reset forces the CMxCON0 and CM2CON1 registers to their Reset states. This forces both comparators and the voltage references to their OFF states. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 59 PIC16F610/616/16HV610/616 REGISTER 8-1: CM1CON0: COMPARATOR 1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity): C1OUT = 0 when C1VIN+ > C1VINC1OUT = 1 when C1VIN+ < C1VINIf C1POL = 0 (non-inverted polarity): C1OUT = 1 when C1VIN+ > C1VINC1OUT = 0 when C1VIN+ < C1VIN- bit 5 C1OE: Comparator C1 Output Enable bit 1 = C1OUT is present on the C1OUT pin(1) 0 = C1OUT is internal only bit 4 C1POL: Comparator C1 Output Polarity Select bit 1 = C1OUT logic is inverted 0 = C1OUT logic is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 C1R: Comparator C1 Reference Select bit (non-inverting input) 1 = C1VIN+ connects to C1VREF output 0 = C1VIN+ connects to C1IN+ pin bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bit 00 = C12IN0- pin of C1 connects to C1VIN01 = C12IN1- pin of C1 connects to C1VIN10 = C12IN2- pin of C1 connects to C1VIN11 = C12IN3- pin of C1 connects to C1VIN- Note 1: x = Bit is unknown Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port TRIS bit = 0. DS41288C-page 60 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 REGISTER 8-2: CM2CON0: COMPARATOR 2 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2ON: Comparator C2 Enable bit 1 = Comparator C2 is enabled 0 = Comparator C2 is disabled bit 6 C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity): C2OUT = 0 when C2VIN+ > C2VINC2OUT = 1 when C2VIN+ < C2VINIf C2POL = 0 (non-inverted polarity): C2OUT = 1 when C2VIN+ > C2VINC2OUT = 0 when C2VIN+ < C2VIN- bit 5 C2OE: Comparator C2 Output Enable bit 1 = C2OUT is present on C2OUT pin(1) 0 = C2OUT is internal only bit 4 C2POL: Comparator C2 Output Polarity Select bit 1 = C2OUT logic is inverted 0 = C2OUT logic is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input) 1 = C2VIN+ connects to C2VREF 0 = C2VIN+ connects to C2IN+ pin bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits 00 = C2VIN- pin of C2 connects to C12IN001 = C2VIN- pin of C2 connects to C12IN110 = C2VIN- pin of C2 connects to C12IN211 = C2VIN- pin of C2 connects to C12IN3- Note 1: x = Bit is unknown Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port TRIS bit = 0. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 61 PIC16F610/616/16HV610/616 8.7 Comparator Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 8-6. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. A maximum source impedance of 10 kΩ is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. FIGURE 8-6: ANALOG INPUT MODEL VDD VT ≈ 0.6V Rs < 10K RIC To ADC Input AIN VA CPIN 5 pF VT ≈ 0.6V ILEAKAGE ±500 nA Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance = Source Impedance RS = Analog Voltage VA VT = Threshold Voltage DS41288C-page 62 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.8 8.8.2 Additional Comparator Features There are three additional comparator features: The Comparator C2 output can be synchronized with Timer1 by setting the C2SYNC bit of the CM2CON1 register. When enabled, the C2 output is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 8-3) and the Timer1 Block Diagram (Figure 6-1) for more information. • Timer1 count enable (gate) • Synchronizing output with Timer1 • Simultaneous read of comparator outputs 8.8.1 SYNCHRONIZING COMPARATOR C2 OUTPUT TO TIMER1 COMPARATOR C2 GATING TIMER1 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CM2CON1 register will enable Timer1 to increment based on the output of Comparator C2. This requires that Timer1 is on and gating is enabled. See Section 6.0 “Timer1 Module with Gate Control” for details. 8.8.3 It is recommended to synchronize the comparator with Timer1 by setting the C2SYNC bit when the comparator is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if the comparator changes during an increment. SIMULTANEOUS COMPARATOR OUTPUT READ The MC1OUT and MC2OUT bits of the CM2CON1 register are mirror copies of both comparator outputs. The ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers. Note 1: Obtaining the status of C1OUT or C2OUT by reading CM2CON1 does not affect the comparator interrupt mismatch registers. REGISTER 8-3: CM2CON1: COMPARATOR 2 CONTROL REGISTER 1 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 MC1OUT MC2OUT — T1ACS C1HYS C2HYS T1GSS C2SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MC1OUT: Mirror Copy of C1OUT bit bit 6 MC2OUT: Mirror Copy of C2OUT bit bit 5 Unimplemented: Read as ‘0’ bit 4 T1ACS: Timer1 Alternate Clock Select bit 1 = Timer1 clock source is the system clock (FOSC) 0 = Timer1 clock source is the internal clock FOSC/4) bit 3 C1HYS: Comparator C1 Hysteresis Enable bit 1 = Comparator C1 Hysteresis enabled 0 = Comparator C1 Hysteresis disabled bit 2 C2HYS: Comparator C2 Hysteresis Enable bit 1 = Comparator C2 Hysteresis enabled 0 = Comparator C2 Hysteresis disabled bit 1 T1GSS: Timer1 Gate Source Select bit 1 = Timer1 gate source is T1G 0 = Timer1 gate source is SYNCC2OUT. bit 0 C2SYNC: Comparator C2 Output Synchronization bit 1 = C2 Output is synchronous to falling edge of Timer1 clock 0 = C2 Output is asynchronous © 2007 Microchip Technology Inc. Preliminary x = Bit is unknown DS41288C-page 63 PIC16F610/616/16HV610/616 8.9 Comparator Hysteresis Each comparator has built-in hysteresis that is user enabled by setting the C1HYS or C2HYS bits of the CM2CON1 register. The hysteresis feature can help filter noise and reduce multiple comparator output transitions when the output is changing state. FIGURE 8-7: Figure 8-9 shows the relationship between the analog input levels and digital output of a comparator with and without hysteresis. The output of the comparator changes from a low state to a high state only when the analog voltage at VIN+ rises above the upper hysteresis threshold (VH+). The output of the comparator changes from a high state to a low state only when the analog voltage at VIN+ falls below the lower hysteresis threshold (VH-). COMPARATOR HYSTERESIS VIN+ + VIN- – Output V+ VH+ VINVHVIN+ Output (Without Hysteresis) Output (With Hysteresis) Note: The black areas of the comparator output represents the uncertainty due to input offsets and response time. DS41288C-page 64 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 8-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 0000 0000 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 0000 0000 0000 CM2CON1 MC1OUT MC2OUT — T1ACS C1HYS C2HYS T1GSS C2SYNC 00-0 0010 00-0 0010 0000 000x GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x PIE1 INTCON — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 -000 0-00 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 -000 0-00 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 --x0 x000 PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 00xx --uu 00uu SRCON0 SR1 SR0 C1SEN C2REN PULSS PULSR — SRCLKEN 0000 00-0 0000 00-0 SRCON1 SRCS1 SRCS0 — — — — — — 00-- ---- 00-- ---- — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 VRR FVREN VR3 VR2 VR1 VR0 0000 0000 0000 0000 TRISA TRISC VRCON Legend: Note 1: C1VREN C2VREN x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator. PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 65 PIC16F610/616/16HV610/616 8.10 Comparator SR Latch inputs are high the latch will go to the Reset state. Both the PULSS and PULSR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset operation. The SR latch module provides additional control of the comparator outputs. The module consists of a single SR latch and output multiplexers. The SR latch can be set, reset or toggled by the comparator outputs. The SR latch may also be set or reset, independent of comparator output, by control bits in the SRCON0 control register. The SR latch output multiplexers select whether the latch outputs or the comparator outputs are directed to the I/O port logic for eventual output to a pin. 8.10.2 The SR<1:0> bits of the SRCON0 register control the latch output multiplexers and determine four possible output configurations. In these four configurations, the CxOUT I/O port logic is connected to: • • • • The SR latch also has a variable clock, which is connected to the set input of the latch. The SRCLKEN bit of SRCON0 enables the SR latch set clock. The clock will periodically pulse the set input of the latch. Control over the frequency of the SR latch set clock is provided by the SRCS<1:0> bits of SRCON1 register. 8.10.1 C1OUT and C2OUT C1OUT and SR latch Q C2OUT and SR latch Q SR latch Q and Q After any Reset, the default output configuration is the unlatched C1OUT and C2OUT mode. This maintains compatibility with devices that do not have the SR latch feature. LATCH OPERATION The latch is a Set-Reset latch that does not depend on a clock source. Each of the Set and Reset inputs are active-high. Each latch input is connected to a comparator output and a software controlled pulse generator. The latch can be set by C1OUT or the PULSS bit of the SRCON0 register. The latch can be reset by C2OUT or the PULSR bit of the SRCON0 register. The latch is reset-dominant, therefore, if both Set and Reset FIGURE 8-8: LATCH OUTPUT The applicable TRIS bits of the corresponding ports must be cleared to enable the port pin output drivers. Additionally, the CxOE comparator output enable bits of the CMxCON0 registers must be set in order to make the comparator or latch outputs available on the output pins. The latch configuration enable states are completely independent of the enable states for the comparators. SR LATCH SIMPLIFIED BLOCK DIAGRAM SRCLKEN SRCLK SR0 C1OE PULSS Pulse Gen(2) C1OUT (from comparator) S 0 MUX 1 Q C1OUT pin(3) C1SEN SR Latch(1) C2OE SYNCC2OUT (from comparator) R C2REN PULSR Note 1: 2: 3: 1 MUX 0 Q Pulse Gen(2) C2OUT pin(3) SR1 If R = 1 and S = 1 simultaneously, Q = 0, Q = 1 Pulse generator causes a 1 TOSC pulse width. Output shown for reference only. See I/O port pin block diagram for more detail. DS41288C-page 66 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 REGISTER 8-4: SRCON0: SR LATCH CONTROL 0 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/S-0 R/S-0 U-0 R/W-0 SR1(2) SR0(2) C1SEN C2REN PULSS PULSR — SRCLKEN bit 7 bit 0 Legend: S = Bit is set only - R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SR1: SR Latch Configuration bit(2) 1= C2OUT pin is the latch Q output 0= C2OUT pin is the C2 comparator output bit 6 SR0: SR Latch Configuration bits(2) 1= C1OUT pin is the latch Q output 0= C1OUT pin is the C1 Comparator output bit 5 C1SEN: C1 Set Enable bit 1 = C1 comparator output sets SR latch 0 = C1 comparator output has no effect on SR latch bit 4 C2REN: C2 Reset Enable bit 1 = C2 comparator output resets SR latch 0 = C2 comparator output has no effect on SR latch bit 3 PULSS: Pulse the SET Input of the SR Latch bit 1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware. 0 = Does not trigger pulse generator bit 2 PULSR: Pulse the Reset Input of the SR Latch bit 1 = Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware. 0 = Does not trigger pulse generator bit 1 Unimplemented: Read as ‘0’ bit 0 SRCLKEN: SR Latch Set Clock Enable bit 1 = Set input of SR latch is pulsed with SRCLK 0 = Set input of SR latch is not pulsed with the SRCLK Note 1: 2: The C1OUT and C2OUT bits in the CMxCON0 register will always reflect the actual comparator output (not the level on the pin), regardless of the SR latch operation. To enable an SR Latch output to the pin, the appropriate CxOE, and TRIS bits must be properly configured. REGISTER 8-5: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 SRCS1 SRCS0 — — — — — — bit 7 bit 0 Legend: S = Bit is set only - R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 SRCS<1:0>: SR Latch Clock Prescale bits 00 = FOSC/16 01 = FOSC/32 10 = FOSC/64 11 = FOSC/128 bit 5-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. Preliminary x = Bit is unknown DS41288C-page 67 PIC16F610/616/16HV610/616 8.11 8.11.3 Comparator Voltage Reference The comparator voltage reference module provides an internally generated voltage reference for the comparators. The following features are available: • • • • • Independent from Comparator operation Two 16-level voltage ranges Output clamped to VSS Ratiometric with VDD Fixed Reference (0.6V) 8.11.1 The fixed voltage reference output voltage can be set to Vss with no power consumption by clearing the FVREN bit of the VRCON register (FVREN = 0). This allows the comparator to detect a zero-crossing while not consuming additional module current. 8.11.4 The VRCON register (Register 8-6) controls the voltage reference module shown in Figure 8-9. OUTPUT CLAMPED TO VSS OUTPUT RATIOMETRIC TO VDD The comparator voltage reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the Comparator Voltage Reference can be found in Section 15.0 “Electrical Specifications”. INDEPENDENT OPERATION The comparator voltage reference is independent of the comparator configuration. Setting the FVREN bit of the VRCON register will enable the voltage reference. 8.11.2 OUTPUT VOLTAGE SELECTION The CVREF voltage reference has 2 ranges with 16 voltage levels in each range. Range selection is controlled by the VRR bit of the VRCON register. The 16 levels are set with the VR<3:0> bits of the VRCON register. The CVREF output voltage is determined by the following equations: EQUATION 8-1: CVREF OUTPUT VOLTAGE V RR = 1 (low range): CVREF = (VR<3:0>/24) × V DD V RR = 0 (high range): CV REF = (VDD/4) + (VR<3:0> × VDD/32) The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure 8-9. DS41288C-page 68 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.11.5 FIXED VOLTAGE REFERENCE 8.11.7 The fixed voltage reference is independent of VDD, with a nominal output voltage of 0.6V. This reference can be enabled by setting the FVREN bit of the VRCON register to ‘1’. This reference is always enabled when the HFINTOSC oscillator is active. 8.11.6 Multiplexers on the output of the voltage reference module enable selection of either the CVREF or fixed voltage reference for use by the comparators. Setting the C1VREN bit of the VRCON register enables current to flow in the CVREF voltage divider and selects the CVREF voltage for use by C1. Clearing the C1VREN bit selects the fixed voltage for use by C1. FIXED VOLTAGE REFERENCE STABILIZATION PERIOD When the fixed voltage reference module is enabled, it will require some time for the reference and its amplifier circuits to stabilize. The user program must include a small delay routine to allow the module to settle. See the electrical specifications section for the minimum delay requirement. FIGURE 8-9: VOLTAGE REFERENCE SELECTION Setting the C2VREN bit of the VRCON register enables current to flow in the CVREF voltage divider and selects the CVREF voltage for use by C2. Clearing the C2VREN bit selects the fixed voltage for use by C2. When both the C1VREN and C2VREN bits are cleared, current flow in the CVREF voltage divider is disabled minimizing the power drain of the voltage reference peripheral. COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR Analog MUX 15 CVREF To Comparators and ADC Module 0 VR<3:0>(1) C1VREN 4 C2VREN To ADC Module Fixed Ref To Comparators and ADC Module 1.2V 0.6V FVREN EN Fixed Voltage Reference Note 1: © 2007 Microchip Technology Inc. Preliminary Care should be taken to ensure VREF remains within the comparator common mode input range. See Section 15.0 “Electrical Specifications” for more detail. DS41288C-page 69 PIC16F610/616/16HV610/616 REGISTER 8-6: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C1VREN C2VREN VRR FVREN VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1VREN: Comparator 1 Voltage Reference Enable bit 1 = CVREF circuit powered on and routed to C1VREF input of Comparator C1 0 = 0.6 Volt constant reference routed to C1VREF input of Comparator C1 bit 6 C2VREN: Comparator 2 Voltage Reference Enable bit 1 = CVREF circuit powered on and routed to C2VREF input of Comparator C2 0 = 0.6 Volt constant reference routed to C2VREF input of Comparator C2 bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 FVREN: Fixed Voltage Reference (0.6V) Enable bit 1 = Enabled 0 = Disabled bit 3-0 VR<3:0>: Comparator Voltage Reference CVREF Value Selection bits (0 ≤ VR<3:0> ≤ 15) When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD DS41288C-page 70 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE (PIC16F616/16HV616 ONLY) The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). The ADC voltage reference is software selectable to either VDD or a voltage applied to the external reference pins. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. Figure 9-1 shows the block diagram of the ADC. FIGURE 9-1: ADC BLOCK DIAGRAM VDD VCFG = 0 VREF VCFG = 1 RA0/AN0 RA1/AN1/VREF RA2/AN2 RA4/AN3 RC0/AN4 RC1/AN5 RC2/AN6 ADC RC3/AN7 10 GO/DONE CVREF 0.6V Reference ADFM 1.2V Reference 4 CHS <3:0> © 2007 Microchip Technology Inc. 0 = Left Justify 1 = Right Justify ADON 10 VSS Preliminary ADRESH ADRESL DS41288C-page 71 PIC16F610/616/16HV610/616 9.1 9.1.4 ADC Configuration When configuring and using the ADC, the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 9.1.1 The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. See the corresponding Port section for more information. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. 9.1.2 The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: • • • • • • • PORT CONFIGURATION CONVERSION CLOCK FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods as shown in Figure 9-3. For correct conversion, the appropriate TAD specification must be met. See A/D conversion requirements in Section 15.0 “Electrical Specifications” for more information. Table 9-1 gives examples of appropriate ADC clock selections. Note: CHANNEL SELECTION The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. When changing channels, a delay is required before starting the next conversion. Refer to Section 9.2 “ADC Operation” for more information. ADC VOLTAGE REFERENCE 9.1.3 The VCFG bit of the ADCON0 register provides control of the positive voltage reference. The positive voltage reference can be either VDD or an external voltage source. The negative voltage reference is always connected to the ground reference. TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V) ADC Clock Period (TAD) ADC Clock Source FOSC/2 ADCS<2:0> 000 Device Frequency (FOSC) 20 MHz 100 ns(2) ns(2) 8 MHz 250 ns(2) 500 ns(2) 4 MHz 500 ns(2) 1.0 μs(2) 1 MHz 2.0 μs 4.0 μs FOSC/4 100 200 FOSC/8 001 400 ns(2) 1.0 μs(2) 2.0 μs 8.0 μs(3) FOSC/16 101 800 ns(2) 2.0 μs 4.0 μs 16.0 μs(3) FOSC/32 010 1.6 μs 4.0 μs FOSC/64 110 3.2 μs 8.0 μs(3) FRC Legend: Note 1: 2: 3: 4: x11 2-6 μs(1,4) 2-6 μs(1,4) μs(3) 32.0 μs(3) 16.0 μs(3) 64.0 μs(3) μs(1,4) 2-6 μs(1,4) 8.0 2-6 Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 4 μs for VDD > 3.0V. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. DS41288C-page 72 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit 9.1.5 ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input INTERRUPTS 9.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note: RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 9-4 shows the two output formats. The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the interrupt service routine. Please see Section 9.1.5 “Interrupts” for more information. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 10-bit A/D Result (ADFM = 1) bit 0 Unimplemented: Read as ‘0’ MSB bit 7 LSB bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. bit 7 bit 0 10-bit A/D Result Preliminary DS41288C-page 73 PIC16F610/616/16HV610/616 9.2 9.2.1 9.2.5 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the analog-to-digital conversion. Note: 9.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 9.2.6 “A/D Conversion Procedure”. COMPLETION OF A CONVERSION SPECIAL EVENT TRIGGER The ECCP Special Event Trigger allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. Using the Special Event Trigger does not ensure proper ADC timing. It is the user’s responsibility to ensure that the ADC timing requirements are met. See Section 10.0 “Enhanced Capture/Compare/ PWM (With Auto-Shutdown and Dead Band) Module (PIC16F616/16HV616 Only)” for more information. When the conversion is complete, the ADC module will: 9.2.6 • Clear the GO/DONE bit • Set the ADIF flag bit • Update the ADRESH:ADRESL registers with new conversion result This is an example procedure for using the ADC to perform an analog-to-digital conversion: 9.2.3 TERMINATING A CONVERSION 9.2.4 Configure Port: • Disable pin output driver (See TRIS register) • Configure pin as analog Configure the ADC module: • Select ADC conversion clock • Configure voltage reference • Select ADC input channel • Select result format • Turn on ADC module Configure ADC interrupt (optional): • Clear ADC interrupt flag • Enable ADC interrupt • Enable peripheral interrupt • Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) Read ADC Result Clear the ADC interrupt flag (required if interrupt is enabled). 2. If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete analog-to-digital conversion sample. Instead, the ADRESH:ADRESL register pair will retain the value of the previous conversion. Additionally, a 2 TAD delay is required before another acquisition can be initiated. Following this delay, an input acquisition is automatically started on the selected channel. Note: 1. A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 3. 4. 5. 6. ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. 7. 8. Note 1: The global interrupt may be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. DS41288C-page 74 A/D CONVERSION PROCEDURE Preliminary 2: See Section 9.3 Requirements”. “A/D Acquisition © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 EXAMPLE 9-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B’01110000’ ;ADC Frc clock MOVWF ADCON1 ; BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B’10000001’ ;Right justify, MOVWF ADCON0 ;Vdd Vref, AN0, On CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space © 2007 Microchip Technology Inc. Preliminary DS41288C-page 75 PIC16F610/616/16HV610/616 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = Channel 00 (AN0) 0001 = Channel 01 (AN1) 0010 = Channel 02 (AN2) 0011 = Channel 03 (AN3) 0100 = Channel 04 (AN4) 0101 = Channel 05 (AN5) 0110 = Channel 06 (AN6) 0111 = Channel 07 (AN7) 1000 = Reserved – do not use 1001 = Reserved – do not use 1010 = Reserved – do not use 1011 = Reserved – do not use 1100 = CVREF 1101 = 0.6V Fixed Voltage Reference(1) 1110 = 1.2V Fixed Voltage Reference(1) 1111 = Reserved – do not use bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: When the CHS<3:0> bits change to select the 1.2V or 0.6V Fixed Voltage Reference, the reference output voltage will have a transient. If the Comparator module uses this VP6 reference voltage, the comparator output may momentarily change state due to the transient. DS41288C-page 76 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — ADCS2 ADCS1 ADCS0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. Preliminary x = Bit is unknown DS41288C-page 77 PIC16F610/616/16HV610/616 REGISTER 9-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY) R-x R-x R-x R-x R-x R-x R-x R-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 9-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 (READ-ONLY) R-x R-x U-0 U-0 U-0 U-0 U-0 U-0 ADRES1 ADRES0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. REGISTER 9-5: x = Bit is unknown ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 (READ-ONLY) U-0 U-0 U-0 U-0 U-0 U-0 R-x R-x — — — — — — ADRES9 ADRES8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result REGISTER 9-6: x = Bit is unknown ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 (READ-ONLY) R-x R-x R-x R-x R-x R-x R-x R-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result DS41288C-page 78 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 9-4. The maximum recommended impedance for analog sources is 10 kΩ. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 9-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. EQUATION 9-1: ACQUISITION TIME EXAMPLE Temperature = 50°C and external impedance of 10k Ω 5.0V V DD Assumptions: T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 5µs + T C + [ ( Temperature - 25°C ) ( 0.05µs/°C ) ] The value for TC can be approximated with the following equations: 1 V AP PLIE D ⎛⎝ 1 – ------------⎞⎠ = V CHOLD 2047 ;[1] VCHOLD charged to within 1/2 lsb –TC ----------⎞ ⎛ RC V AP P LI ED ⎜ 1 – e ⎟ = V CHOLD ⎝ ⎠ ;[2] VCHOLD charge response to VAPPLIED – Tc ---------⎞ ⎛ 1 RC V AP P LIED ⎜ 1 – e ⎟ = V A P PLIE D ⎛⎝ 1 – ------------⎞⎠ 2047 ⎝ ⎠ ;combining [1] and [2] Solving for TC: T C = – C HOLD ( R IC + R SS + R S ) ln(1/2047) = – 10pF ( 1k Ω + 7k Ω + 10k Ω ) ln(0.0004885) = 1.37 µs Therefore: T ACQ = 5µ S + 1.37µ S + [ ( 50°C- 25°C ) ( 0.05µ S /°C ) ] = 7.67µ S Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 79 PIC16F610/616/16HV610/616 FIGURE 9-4: ANALOG INPUT MODEL VDD ANx Rs CPIN 5 pF VA VT = 0.6V VT = 0.6V RIC ≤ 1k Sampling Switch SS Rss I LEAKAGE ± 500 nA CHOLD = 10 pF VSS/VREF- Legend: CPIN = Input Capacitance = Threshold Voltage VT I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance FIGURE 9-5: 6V 5V VDD 4V 3V 2V RSS 5 6 7 8 9 10 11 Sampling Switch (kΩ) ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh ADC Output Code 3FDh 3FCh 1 LSB ideal 3FBh Full-Scale Transition 004h 003h 002h 001h 000h Analog Input Voltage 1 LSB ideal VSS/VREF- DS41288C-page 80 Zero-Scale Transition Preliminary VDD/VREF+ © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 9-2: Name ADCON0(1) ADCON1 (1) ANSEL SUMMARY OF ASSOCIATED ADC REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ---- ANS ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 uuuu uuuu ADRESH A/D Result Register High Byte xxxx xxxx ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu 0000 0000 0000 0000 INTCON GIE PEIE T0IE — ADIE(1) PIR1 — (1) ADIF PIE1 INTE RAIE T0IF INTF RAIF CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 -000 0-00 (1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 -000 0-00 --u0 u000 CCP1IF PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 00xx --uu 00uu TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 TRISC Legend: Note 1: x = unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for ADC module. PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 81 PIC16F610/616/16HV610/616 NOTES: DS41288C-page 82 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 10.0 ENHANCED CAPTURE/ COMPARE/PWM (WITH AUTOSHUTDOWN AND DEAD BAND) MODULE (PIC16F616/16HV616 ONLY) The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external REGISTER 10-1: event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. Table 10-1 shows the timer resources required by the ECCP module. TABLE 10-1: ECCP MODE – TIMER RESOURCES REQUIRED ECCP Mode Timer Resource Capture Timer1 Compare Timer1 PWM Timer2 CCP1CON: ENHANCED CCP1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 P1M<1:0>: PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 = Half-Bridge output; P1A, P1B modulated with dead-time control; P1C, P1D assigned as port pins 11 = Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M<3:0>: ECCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (CCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D conversion, if the ADC module is enabled) 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2007 Microchip Technology Inc. Preliminary DS41288C-page 83 PIC16F610/616/16HV610/616 10.1 10.1.2 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new captured value (see Figure 10-1). 10.1.1 CCP1 PIN CONFIGURATION In Capture mode, the CCP1 pin should be configured as an input by setting the associated TRIS control bit. Note: If the CCP1 pin is configured as an output, a write to the port can cause a capture condition. FIGURE 10-1: Prescaler ÷ 1, 4, 16 CAPTURE MODE OPERATION BLOCK DIAGRAM CCPR1H and Edge Detect 10.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt enable bit of the PIE1 register clear to avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register following any change in operating mode. 10.1.4 CCP PRESCALER There are four prescaler settings specified by the CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCP1CON register before changing the prescaler (see Example 10-1). CHANGING BETWEEN CAPTURE PRESCALERS BANKSEL CCP1CON CLRF MOVLW CCPR1L Capture Enable TMR1H Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. EXAMPLE 10-1: Set Flag bit CCP1IF (PIR1 register) CCP1 pin TIMER1 MODE SELECTION MOVWF ;Set Bank bits to point ;to CCP1CON CCP1CON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; move value and CCP ON CCP1CON ;Load CCP1CON with this ; value TMR1L CCP1CON<3:0> System Clock (FOSC) DS41288C-page 84 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 10-2: Name CCP1CON(1) SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 CCPR1L(1) Capture/Compare/PWM Register 1 Low Byte CCPR1H(1) Capture/Compare/PWM Register 1 High Byte INTCON Value on POR, BOR Value on all other Resets 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 0000 0-00 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 0000 0-00 T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu T1CON TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 85 PIC16F610/616/16HV610/616 10.2 10.2.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: • • • • • Toggle the CCP1 output Set the CCP1 output Clear the CCP1 output Generate a Special Event Trigger Generate a Software Interrupt All Compare modes can generate an interrupt. FIGURE 10-2: S Output Logic Match TRIS Output Enable Comparator TMR1H TMR1L Special Event Trigger • Clear TMR1H and TMR1L registers. • NOT set interrupt flag bit TMR1IF of the PIR1 register. • Set the GO/DONE bit to start the ADC conversion. The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPR1H, CCPR1L register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. This allows the CCPR1H, CCPR1L register pair to effectively provide a 16-bit programmable period register for Timer1. CCP1 PIN CONFIGURATION The user must configure the CCP1 pin as an output by clearing the associated TRIS bit. Note: SPECIAL EVENT TRIGGER Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register. Special Event Trigger will: 10.2.1 10.2.4 The CCP1 module does not assert control of the CCP1 pin in this mode (see the CCP1CON register). Set CCP1IF Interrupt Flag (PIR1) 4 CCPR1H CCPR1L R When Generate Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the CCP1 module does not assert control of the CCP1 pin (see the CCP1CON register). • Resets Timer1 • Starts an ADC conversion if ADC is enabled CCP1CON<3:0> Mode Select Q SOFTWARE INTERRUPT MODE When Special Event Trigger mode is chosen (CCP1M<3:0> = 1011), the CCP1 module does the following: COMPARE MODE OPERATION BLOCK DIAGRAM CCP1 Pin In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. 10.2.3 The action on the pin is based on the value of the CCP1M<3:0> control bits of the CCP1CON register. TIMER1 MODE SELECTION 2: Removing the match condition by changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the PORT I/O data latch. DS41288C-page 86 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 10-3: Name CCP1CON(1) SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 CCPR1L(1) Capture/Compare/PWM Register 1 Low Byte CCPR1H(1) Capture/Compare/PWM Register 1 High Byte INTCON Value on POR, BOR Value on all other Resets 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 0000 0-00 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 0000 0-00 T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu T1CON TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 87 PIC16F610/616/16HV610/616 10.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • • • • The PWM output (Figure 10-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 10-4: PR2 T2CON CCPR1L CCP1CON Period Pulse Width In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCP1 pin. Since the CCP1 pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to make the CCP1 pin an output. Note: CCP PWM OUTPUT TMR2 = PR2 TMR2 = CCPR1L:CCP1CON<5:4> TMR2 = 0 Clearing the CCP1CON register will relinquish CCP1 control of the CCP1 pin. Figure 10-3 shows a simplified block diagram of PWM operation. Figure 10-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 10.3.7 “Setup for PWM Operation”. FIGURE 10-3: SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty Cycle Registers CCPR1L CCPR1H(2) (Slave) CCP1 R Comparator TMR2 (1) Q S TRIS Comparator PR2 Note 1: 2: Clear Timer2, toggle CCP1 pin and latch duty cycle The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPR1H is a read-only register. DS41288C-page 88 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 10.3.1 PWM PERIOD EQUATION 10-2: The PWM period is specified by writing to the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 10-1. EQUATION 10-1: T OSC • (TMR2 Prescale Value) EQUATION 10-3: (TMR2 Prescale Value) DUTY CYCLE RATIO CCPR1L:CCP1CON<5:4> -) Duty Cycle Ratio = (---------------------------------------------------------------------4 ( PR2 + 1 ) When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is latched from CCPR1L into CCPR1H. 10.3.2 Pulse Width = ( CCPR1L:CCP1CON<5:4> ) • PWM PERIOD PWM Period = [ ( PR2 ) + 1 ] • 4 • T OSC • Note: PULSE WIDTH The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. The Timer2 postscaler (see Section 7.1 “Timer2 Operation”) is not used in the determination of the PWM frequency. When the 10-bit time base matches the CCPR1H and 2-bit latch, then the CCP1 pin is cleared (see Figure 10-3). PWM DUTY CYCLE 10.3.3 PWM RESOLUTION The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPR1L register and CCP1<1:0> bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the CCP1<1:0> bits of the CCP1CON register contain the two LSbs. CCPR1L and CCP1<1:0> bits of the CCP1CON register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H register is read-only. The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. Equation 10-2 is used to calculate the PWM pulse width. [ 4 ( PR2 + 1 ) ]- bits Resolution = log ----------------------------------------log ( 2 ) Equation 10-3 is used to calculate the PWM duty cycle ratio. TABLE 10-4: EQUATION 10-4: Note: PWM RESOLUTION If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 10-5: The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 10-4. 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits) © 2007 Microchip Technology Inc. 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Preliminary DS41288C-page 89 PIC16F610/616/16HV610/616 10.3.4 OPERATION IN SLEEP MODE 10.3.7 In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 10.3.5 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 3.0 “Oscillator Module” for additional details. 10.3.6 The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 6. DS41288C-page 90 SETUP FOR PWM OPERATION Preliminary Configure the PWM pin (CCP1) as an input by setting the associated TRIS bit. Set the PWM period by loading the PR2 register. Configure the CCP module for the PWM mode by loading the CCP1CON register with the appropriate values. Set the PWM duty cycle by loading the CCPR1L register and CCP1 bits of the CCP1CON register. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register. • Set the Timer2 prescale value by loading the T2CKPS bits of the T2CON register. • Enable Timer2 by setting the TMR2ON bit of the T2CON register. Enable PWM output after a new PWM cycle has started: • Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCP1 pin output by clearing the associated TRIS bit. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 10.4 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. The Enhanced PWM Mode can generate a PWM signal on up to four different output pins with up to 10-bits of resolution. It can do this through four different PWM Output modes: • • • • Table 10-6 shows the pin assignments for each Enhanced PWM mode. Single PWM Half-Bridge PWM Full-Bridge PWM, Forward mode Full-Bridge PWM, Reverse mode Figure 10-5 shows an example of a simplified block diagram of the Enhanced PWM module. Note: To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal. To select an Enhanced PWM mode, the P1M bits of the CCP1CON register must be set appropriately. FIGURE 10-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE CCP1<1:0> CCP1M<3:0> 4 P1M<1:0> Duty Cycle Registers 2 CCPR1L CCP1/P1A CCP1/P1A TRISC<5> CCPR1H (Slave) P1B R Comparator Output Controller Q P1B TRISC<4> P1C P1C TMR2 (1) TRISC<3> S P1D Comparator Clear Timer2, toggle PWM pin and latch duty cycle PR2 Note 1: P1D TRISC<2> PWM1CON The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. Note 1: The TRIS register value for each PWM output must be configured appropriately. 2: Clearing the CCP1CON register will relinquish ECCP control of all PWM output pins. 3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions TABLE 10-6: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode P1M CCP1/P1A P1B P1C P1D Single 00 Half-Bridge 10 Yes No No No Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes © 2007 Microchip Technology Inc. Preliminary DS41288C-page 91 PIC16F610/616/16HV610/616 FIGURE 10-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) P1M<1:0> Signal PR2+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section 10.4.6 “Programmable Dead-Band Delay mode”). DS41288C-page 92 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 10-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal P1M<1:0> PR2+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) 10 (Half-Bridge) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section 10.4.6 “Programmable Dead-Band Delay mode”). © 2007 Microchip Technology Inc. Preliminary DS41288C-page 93 PIC16F610/616/16HV610/616 10.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 10-8). This mode can be used for half-bridge applications, as shown in Figure 10-9, or for full-bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in halfbridge power devices. The value of the PDC<6:0> bits of the PWM1CON register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See 10.4.6 “Programmable Dead-Band Delay mode” for more details of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs. FIGURE 10-8: Period Period Pulse Width P1A(2) td td P1B(2) (1) (1) (1) td = Dead-Band Delay Note 1: 2: FIGURE 10-9: EXAMPLE OF HALFBRIDGE PWM OUTPUT At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high. EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A Load FET Driver + P1B - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET Driver FET Driver P1A FET Driver Load FET Driver P1B DS41288C-page 94 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 10.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of full-bridge application is shown in Figure 10-10. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure 10-11. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure 10-11. P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 10-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D © 2007 Microchip Technology Inc. Preliminary DS41288C-page 95 PIC16F610/616/16HV610/616 FIGURE 10-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A (2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) Note 1: 2: (1) At this time, the TMR2 register is equal to the PR2 register. Output signal is shown as active-high. DS41288C-page 96 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 10.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the P1M1 bit of the CCP1CON register. The following sequence occurs four Timer2 cycles prior to the end of the current PWM period: • The modulated outputs (P1B and P1D) are placed in their inactive state. • The associated unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. • PWM modulation resumes at the beginning of the next period. See Figure 10-12 for an illustration of this sequence. The Full-Bridge mode does not provide dead-band delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation where dead-band delay is required. This situation occurs when both of the following conditions are true: 1. 2. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn off time of the power switch, including the power device and driver circuit, is greater than the turn on time. Figure 10-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty cycle. In this example, at time t1, the output P1A and P1D become inactive, while output P1C becomes active. Since the turn off time of the power devices is longer than the turn on time, a shoot-through current will flow through power devices QC and QD (see Figure 10-10) for the duration of ‘t’. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. 2. Reduce PWM duty cycle for one PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 10-12: EXAMPLE OF PWM DIRECTION CHANGE Period(1) Signal Period P1A (Active-High) P1B (Active-High) Pulse Width P1C (Active-High) (2) P1D (Active-High) Pulse Width Note 1: 2: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle. When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is four Timer2 counts. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 97 PIC16F610/616/16HV610/616 FIGURE 10-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B DC P1C P1D PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: T = TOFF – TON All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver. DS41288C-page 98 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 10.4.3 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the highimpedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). The CCP1M<1:0> bits of the CCP1CON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 99 PIC16F610/616/16HV610/616 10.4.4 ENHANCED PWM AUTOSHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the ECCPASx bits of the ECCPAS register. A shutdown event may be generated by: • • • • A logic ‘0’ on the INT pin Comparator C1 Comparator C2 Setting the ECCPASE bit in firmware REGISTER 10-2: A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state. When a shutdown event occurs, two things happen: The ECCPASE bit is set to ‘1’. The ECCPASE will remain set until cleared in firmware or an auto-restart occurs (see Section 10.4.5 “Auto-Restart Mode”). The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [P1A/P1C] and [P1B/P1D]. The state of each pin pair is determined by the PSSAC and PSSBD bits of the ECCPAS register. Each pin pair may be placed into one of three states: • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits 000 = Auto-Shutdown is disabled 001 = Comparator C1 output high 010 = Comparator C2 output high(1) 011 = Either Comparators output is high 100 = VIL on INT pin 101 = VIL on INT pin or Comparator C1 output high 110 = VIL on INT pin or Comparator C2 output high 111 = VIL on INT pin or either Comparators output is high bit 3-2 PSSACn: Pins P1A and P1C Shutdown State Control bits 00 = Drive pins P1A and P1C to ‘0’ 01 = Drive pins P1A and P1C to ‘1’ 1x = Pins P1A and P1C tri-state bit 1-0 PSSBDn: Pins P1B and P1D Shutdown State Control bits 00 = Drive pins P1B and P1D to ‘0’ 01 = Drive pins P1B and P1D to ‘1’ 1x = Pins P1B and P1D tri-state DS41288C-page 100 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Note 1: The auto-shutdown condition is a levelbased signal, not an edge-based signal. As long as the level is present, the autoshutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart), the PWM signal will always restart at the beginning of the next PWM period. FIGURE 10-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0) PWM Period Shutdown Event ECCPASE bit PWM Activity Normal PWM ECCPASE Cleared by Shutdown Shutdown Firmware PWM Event Occurs Event Clears Resumes Start of PWM Period 10.4.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register. If auto-restart is enabled, the ECCPASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPASE bit will be cleared via hardware and normal operation will resume. FIGURE 10-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1) PWM Period Shutdown Event ECCPASE bit PWM Activity Normal PWM Start of PWM Period © 2007 Microchip Technology Inc. Shutdown Shutdown Event Occurs Event Clears Preliminary PWM Resumes DS41288C-page 101 PIC16F610/616/16HV610/616 10.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 10-16: In half-bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shoot-through current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shootthrough current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. Period Period Pulse Width P1A(2) td td P1B(2) (1) (1) (1) td = Dead-Band Delay Note 1: In Half-Bridge mode, a digitally programmable deadband delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 10-16 for illustration. The lower seven bits of the associated PWM1CON register (Register 10-3) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 10-17: EXAMPLE OF HALFBRIDGE PWM OUTPUT 2: At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high. EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + V - P1A Load FET Driver + V - P1B V- DS41288C-page 102 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 REGISTER 10-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits PDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active TABLE 10-7: Name CCP1CON(1) SUMMARY OF REGISTERS ASSOCIATED WITH PWM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 CCPR1L(1) Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H(1) Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000 CM2CON1 MC1OUT MC2OUT — T1ACS C1HYS C2HYS T1GSS C2SYNC 00-0 0010 00-0 0010 ECCPAS(1) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000 GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 0000 0-00 — (1) (1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 0000 0-00 0000 0000 INTCON PIE1 PIR1 PWM1CON(1) T2CON(1) TMR2(1) ADIF CCP1IF PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 0000 0000 0000 0000 Timer2 Module Register TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 103 PIC16F610/616/16HV610/616 NOTES: DS41288C-page 104 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 11.0 VOLTAGE REGULATOR The PIC16HV616 includes a permanent internal 5 volt (nominal) shunt regulator in parallel with the VDD pin. This eliminates the need for an external voltage regulator in systems sourced by an unregulated supply. All external devices connected directly to the VDD pin will share the regulated supply voltage and contribute to the total VDD supply current (ILOAD). An external current limiting resistor, RSER, located between the unregulated supply, VUNREG, and the VDD pin, drops the difference in voltage between VUNREG and VDD. RSER must be between RMAX and RMIN as defined by Equation 11-1. EQUATION 11-1: RMAX = 11.1 Regulator Operation A shunt regulator generates a specific supply voltage by creating a voltage drop across a pass resistor RSER. The voltage at the VDD pin of the microcontroller is monitored and compared to an internal voltage reference. The current through the resistor is then adjusted, based on the result of the comparison, to produce a voltage drop equal to the difference between the supply voltage VUNREG and the VDD of the microcontroller. See Figure 11-1 for voltage regulator schematic. FIGURE 11-1: VOLTAGE REGULATOR VUNREG ISUPPLY RSER ISHUNT (VUMIN - 5V) 1.05 • (4 MA + ILOAD) (VUMAX - 5V) 0.95 • (50 MA) Where: RMAX = maximum value of RSER (ohms) RMIN = minimum value of RSER (ohms) VUMIN = minimum value of VUNREG VUMAX = maximum value of VUNREG VDD = regulated voltage (5V nominal) ILOAD = maximum expected load current in mA including I/O pin currents and external circuits connected to VDD. ILOAD VDD CBYPASS RMIN = RSER LIMITING RESISTOR 1.05 = compensation for +5% tolerance of RSER 0.95 = compensation for -5% tolerance of RSER Feedback VSS 11.2 Regulator Considerations The supply voltage VUNREG and load current are not constant. Therefore, the current range of the regulator is limited. Selecting a value for RSER must take these three factors into consideration. Since the regulator uses the band gap voltage as the regulated voltage reference, this voltage reference is permanently enabled in the PIC16F610/16HV610 devices. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 105 PIC16F610/616/16HV610/616 12.0 SPECIAL FEATURES OF THE CPU The PIC16F610/616/16HV610/616 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. 12.1 The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 12-1. These bits are mapped in program memory location 2007h. Note: These features are: Configuration Bits • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Oscillator selection • Sleep • Code protection • ID Locations • In-Circuit Serial Programming Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h3FFFh), which can be accessed only during programming. See “PIC12F60X/12F61X/ 16F61X Memory Programming Specification” (DS41284) for more information. The PIC16F610/616/16HV610/616 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Powerup Timer to provide at least a 64 ms Reset. With these three functions-on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through: • External Reset • Watchdog Timer Wake-up • An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 12-1). DS41288C-page 106 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 REGISTER 12-1: — CONFIG: CONFIGURATION WORD REGISTER — — — — — BOREN1(1) BOREN0(1) bit 15 bit 8 CP(2) IOSCFS MCLRE(3) PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘1’ bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 0x = BOR disabled bit 7 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz 0 = 4 MHz bit 6 CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 5 MCLRE: MCLR Pin Function Select bit(3) 1 = MCLR pin function is MCLR 0 = MCLR pin function is digital input, MCLR internally tied to VDD bit 4 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN 110 = RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 011 = EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN Note 1: 2: 3: Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire program memory will be erased when the code protection is turned off. When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 107 PIC16F610/616/16HV610/616 12.2 Calibration Bits The 8 MHz internal oscillator is factory calibrated. These calibration values are stored in fuses located in the Calibration Word (2009h). The Calibration Word is not erased when using the specified bulk erase sequence in the “PIC12F60X/12F61X/16F61X Memory Programming Specification” (DS41284) and thus, does not require reprogramming. 12.3 Reset The PIC16F610/616/16HV610/616 between various kinds of Reset: a) b) c) d) e) f) differentiates Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” on: • • • • • Power-on Reset MCLR Reset MCLR Reset during Sleep WDT Reset Brown-out Reset (BOR) WDT wake-up does not cause register resets in the same manner as a WDT Reset since wake-up is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 12-2. Software can use these bits to determine the nature of the Reset. See Table 12-4 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 12-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 15.0 “Electrical Specifications” for pulse-width specifications. FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR/VPP pin Sleep WDT Module WDT Time-out Reset POR Detect Power-on Reset VDD Brown-out(1) Reset BOREN S OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1/ CLKI pin PWRT On-Chip RC OSC 11-bit Ripple Counter Enable PWRT Enable OST Note 1: Refer to the Configuration Word register (Register 12-1). DS41288C-page 108 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 12.3.1 POWER-ON RESET (POR) FIGURE 12-2: The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 15.0 “Electrical Specifications” for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section 12.3.4 “Brown-out Reset (BOR)”). Note: VDD PIC® MCU R1 1 kΩ (or greater) R2 MCLR SW1 (optional) 100 Ω (needed with capacitor) C1 0.1 μF (optional, not critical) The POR circuit does not produce an internal Reset when VDD declines. To reenable the POR, VDD must reach Vss for a minimum of 100 μs. When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure proper operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. RECOMMENDED MCLR CIRCUIT 12.3.3 POWER-UP TIMER (PWRT) PIC16F610/616/16HV610/616 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from an internal RC oscillator. For more information, see Section 3.4 “Internal Clock Modes”. The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. It should be noted that a WDT Reset does not drive MCLR pin low. The Power-up Timer delay will vary from chip-to-chip due to: Voltages applied to the MCLR pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 12-2, is suggested. • VDD variation • Temperature variation • Process variation For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 12.3.2 MCLR An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the RA3/MCLR pin becomes an external Reset input. In this mode, the RA3/MCLR pin has a weak pull-up to VDD. © 2007 Microchip Technology Inc. See DC parameters for details “Electrical Specifications”). Note: Preliminary (Section 15.0 Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 Ω should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to VSS. DS41288C-page 109 PIC16F610/616/16HV610/616 12.3.4 BROWN-OUT RESET (BOR) On any Reset (Power-on, Brown-out Reset, Watchdog timer, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 12-3). If enabled, the Powerup Timer will be invoked by the Reset and keep the chip in Reset an additional 64 ms. The BOREN0 and BOREN1 bits in the Configuration Word register select one of three BOR modes. Selecting BOREN<1:0> = 10, the BOR is automatically disabled in Sleep to conserve power and enabled on wake-up. See Register 12-1 for the Configuration Word definition. Note: A brown-out occurs when VDD falls below VBOR for greater than parameter TBOR (see Section 15.0 “Electrical Specifications”). The brown-out condition will reset the device. This will occur regardless of VDD slew rate. A Brown-out Reset may not occur if VDD falls below VBOR for less than parameter TBOR. FIGURE 12-3: If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 64 ms Reset. BROWN-OUT SITUATIONS VDD Internal Reset VBOR 64 ms(1) VDD Internal Reset VBOR < 64 ms 64 ms(1) VDD VBOR Internal Reset Note 1: The Power-up Timer is enabled by the PWRTE bit in the Configuration Word register. 64 ms(1) 64 ms delay only if PWRTE bit is programmed to ‘0’. DS41288C-page 110 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 12.3.5 TIME-OUT SEQUENCE 12.3.6 On power-up, the time-out sequence is as follows: The Power Control register PCON (address 8Eh) has two Status bits to indicate what type of Reset occurred last. • PWRT time-out is invoked after POR has expired. • OST is activated after the PWRT time-out has expired. Bit 0 is BOR (Brown-out). BOR is unknown on Poweron Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a “don’t care” and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word register). The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 12-4, Figure 12-5 and Figure 12-6 depict time-out sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC16F610/616/ 16HV610/616 device operating in parallel. Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on Reset and unaffected otherwise. The user must write a ‘1’ to this bit following a Power-on Reset. On a subsequent Reset, if POR is ‘0’, it will indicate that a Poweron Reset has occurred (i.e., VDD may have gone too low). Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers. TABLE 12-1: POWER CONTROL (PCON) REGISTER For more information, see Section 12.3.4 “Brown-out Reset (BOR)”. TIME-OUT IN VARIOUS SITUATIONS Power-up Brown-out Reset PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 Wake-up from Sleep TPWRT + 1024 • TOSC 1024 • TOSC TPWRT + 1024 • TOSC 1024 • TOSC 1024 • TOSC TPWRT — TPWRT — — Oscillator Configuration XT, HS, LP RC, EC, INTOSC TABLE 12-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 x 1 1 Power-on Reset u 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x = unknown TABLE 12-3: Name PCON STATUS SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET Value on all other Resets(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR — — — — — — POR BOR ---- --qq ---- --uu IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 111 PIC16F610/616/16HV610/616 FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 FIGURE 12-5: VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset DS41288C-page 112 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 12-4: Register W INDF TMR0 INITIALIZATION CONDITION FOR REGISTERS Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out — xxxx xxxx uuuu uuuu uuuu uuuu 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu PORTA 05h --x0 x000 --u0 u000 --uu uuuu PORTC 07h --xx xx00 --uu 00uu --uu uuuu PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh/8Bh 0000 0000 0000 0000 uuuu uuuu(2) PIR1 0Ch -000 0-00 -000 0-00 -uuu u-uu(2) TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu (6) 11h 0000 0000 0000 0000 uuuu uuuu 12h -000 0000 -000 0000 -uuu uuuu (6) CCPR1L 13h xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H(6) 14h xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON(6) 15h 0000 0000 0000 0000 uuuu uuuu PWM1CON(6) 16h 0000 0000 0000 0000 uuuu uuuu ECCPAS(6) 17h 0000 0000 0000 0000 uuuu uuuu VRCON 19h 0000 0000 0000 0000 uuuu uuuu CM1CON0 1Ah 0000 -000 0000 -000 uuuu -uuu CM2CON0 1Bh 0000 -000 0000 -000 uuuu -uuu CM2CON1 1Ch 00-0 0000 00-0 0000 uu-u uuuu ADRESH(6) 1Eh xxxx xxxx uuuu uuuu uuuu uuuu (6) TMR2 T2CON(6) 1Fh 0000 0000 0000 0000 uuuu uuuu OPTION_REG ADCON0 81h 1111 1111 1111 1111 uuuu uuuu TRISA 85h --11 1111 --11 1111 --uu uuuu TRISC 87h --11 1111 --11 1111 --uu uuuu PIE1 8Ch -000 0-00 -000 0-00 -uuu u-uu PCON 8Eh ---- --0x ---- --uu(1, 5) ---- --uu 90h ---0 0000 ---u uuuu ---u uuuu OSCTUNE Legend: Note 1: 2: 3: 4: 5: 6: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 12-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 113 PIC16F610/616/16HV610/616 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Register Address Power-on Reset MCLR Reset WDT Reset (Continued) Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out (Continued) ANSEL 91h 1111 1111 1111 1111 uuuu uuuu PR2(6) 92h 1111 1111 1111 1111 1111 1111 WPUA 95h --11 -111 --11 -111 --uu -uuu IOCA 96h --00 0000 --00 0000 --uu uuuu SRCON0 99h 0000 00-0 0000 00-0 uuuu uu-u SRCON1 9Ah 00-- ---- 00-- ---- uu-- ---- (6) 9Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON1(6) 9Fh -000 ---- -000 ---- -uuu ---- ADRESL Legend: Note 1: 2: 3: 4: 5: 6: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 12-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. PIC16F616/16HV616 only. TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Counter Status Register PCON Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during Sleep 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 uuuu ---- --uu PC + 1 uuu0 0uuu ---- --uu 000h 0001 1uuu ---- --10 uuu1 0uuu ---- --uu Condition WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep PC + 1 (1) Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. DS41288C-page 114 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 12.4 Interrupts The PIC16F610/616/16HV610/616 sources of interrupt: • • • • • • • • has multiple External Interrupt RA2/INT Timer0 Overflow Interrupt PORTA Change Interrupts 2 Comparator Interrupts A/D Interrupt (PIC16F616/16HV616 only) Timer1 Overflow Interrupt Timer2 Match Interrupt (PIC16F616/16HV616 only) Enhanced CCP Interrupt (PIC16F616/16HV616 only) For external interrupt events, such as the INT pin or PORTA change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 12-8). The latency is the same for one or twocycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. The Interrupt Control register (INTCON) and Peripheral Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. The Global Interrupt Enable bit, GIE of the INTCON register, enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register and PIE1 register. GIE is cleared on Reset. When an interrupt is serviced, the following actions occur automatically: • The GIE is cleared to disable any further interrupt. • The return address is pushed onto the stack. • The PC is loaded with 0004h. The Return from Interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables unmasked interrupts. The following interrupt flags are contained in the INTCON register: • INT Pin Interrupt • PORTA Change Interrupt • Timer0 Overflow Interrupt The peripheral interrupt flags are contained in the special register, PIR1. The corresponding interrupt enable bit is contained in special register, PIE1. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again. For additional information on Timer1, Timer2, comparators, ADC, Enhanced CCP modules, refer to the respective peripheral section. 12.4.1 The external interrupt on the RA2/INT pin is edgetriggered; either on the rising edge if the INTEDG bit of the OPTION register is set, or the falling edge, if the INTEDG bit is clear. When a valid edge appears on the RA2/INT pin, the INTF bit of the INTCON register is set. This interrupt can be disabled by clearing the INTE control bit of the INTCON register. The INTF bit must be cleared by software in the Interrupt Service Routine before re-enabling this interrupt. The RA2/INT interrupt can wake-up the processor from Sleep, if the INTE bit was set prior to going into Sleep. See Section 12.7 “Power-Down Mode (Sleep)” for details on Sleep and Figure 12-9 for timing of wake-up from Sleep through RA2/INT interrupt. Note: The following interrupt flags are contained in the PIR1 register: • • • • • RA2/INT INTERRUPT The ANSEL register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’ and cannot generate an interrupt. A/D Interrupt 2 Comparator Interrupts Timer1 Overflow Interrupt Timer2 Match Interrupt Enhanced CCP Interrupt © 2007 Microchip Technology Inc. Preliminary DS41288C-page 115 PIC16F610/616/16HV610/616 12.4.2 TIMER0 INTERRUPT 12.4.3 An overflow (FFh → 00h) in the TMR0 register will set the T0IF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 5.0 “Timer0 Module” for operation of the Timer0 module. An input change on PORTA sets the RAIF bit of the INTCON register. The interrupt can be enabled/ disabled by setting/clearing the RAIE bit of the INTCON register. Plus, individual pins can be configured through the IOCA register. Note: FIGURE 12-7: PORTA INTERRUPT-ON-CHANGE If a change on the I/O pin should occur when any PORTA operation is being executed, then the RAIF interrupt flag may not get set. INTERRUPT LOGIC IOC-RA0 IOCA0 IOC-RA1 IOCA1 IOC-RA2 IOCA2 IOC-RA3 IOCA3 IOC-RA4 IOCA4 IOC-RA5 IOCA5 T0IF T0IE TMR2IF(2) (2) INTF INTE RAIF RAIE TMR2IE TMR1IF TMR1IE C1IF C1IE PEIE C2IF C2IE GIE Wake-up (If in Sleep mode)(1) Interrupt to CPU ADIF(2) ADIE(2) CCP1IF(2) CCP1IE(2) Note 1: 2: DS41288C-page 116 Some peripherals depend upon the system clock for operation. Since the system clock is suspended during Sleep, only those peripherals which do not depend upon the system clock will wake the part from Sleep. See Section 12.7.1 “Wake-up from Sleep”. PIC16F616/16HV616 only. Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 12-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF flag (INTCON reg.) Interrupt Latency (2) (5) GIE bit (INTCON reg.) INSTRUCTION FLOW PC Instruction Fetched INTCON Dummy Cycle Inst (PC) 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. TABLE 12-6: Name — Inst (PC + 1) Inst (PC – 1) 0004h PC + 1 PC + 1 Inst (PC) Instruction Executed Note 1: PC SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 0000 0000 GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 IOCA — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 -000 0-00 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 -000 0-00 PIE1 Legend: Note 1: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by the interrupt module. PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 117 PIC16F610/616/16HV610/616 12.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Temporary holding registers W_TEMP and STATUS_TEMP should be placed in the last 16 bytes of GPR (see Figure 2-4). These 16 locations are common to all banks and do not require banking. This makes context save and restore operations simpler. The code shown in Example 12-1 can be used to: • • • • • Store the W register Store the STATUS register Execute the ISR code Restore the Status (and Bank Select Bit register) Restore the W register Note: The PIC16F610/616/16HV610/616 does not require saving the PCLATH. However, if computed GOTO’s are used in both the ISR and the main code, the PCLATH must be saved and restored in the ISR. EXAMPLE 12-1: MOVWF SWAPF SAVING STATUS AND W REGISTERS IN RAM W_TEMP STATUS,W MOVWF STATUS_TEMP : :(ISR) : SWAPF STATUS_TEMP,W MOVWF SWAPF SWAPF STATUS W_TEMP,F W_TEMP,W DS41288C-page 118 ;Copy W to TEMP ;Swap status to ;Swaps are used ;Save status to register be saved into W because they do not affect the status bits bank zero STATUS_TEMP register ;Insert user code here ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 12.6 12.6.1 Watchdog Timer (WDT) WDT PERIOD The WDT has a nominal time-out period of 18 ms (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see Table 15-4, Parameter 31). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The Watchdog Timer is a free running, on-chip RC oscillator, which requires no external components. This RC oscillator is separate from the external RC oscillator of the CLKIN pin and INTOSC. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped (for example, by execution of a SLEEP instruction). During normal operation, a WDT time out generates a device Reset. If the device is in Sleep mode, a WDT time out causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming the Configuration bit, WDTE, as clear (Section 12.1 “Configuration Bits”). The CLRWDT and SLEEP instructions clear the WDT and the prescaler, if assigned to the WDT, and prevent it from timing out and generating a device Reset. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time out. 12.6.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worstcase conditions (i.e., VDD = Min., Temperature = Max., Max. WDT prescaler) it may take several seconds before a WDT time out occurs. FIGURE 12-2: WATCHDOG TIMER BLOCK DIAGRAM CLKOUT (= FOSC/4) Data Bus 0 8 1 SYNC 2 Cycles 1 T0CKI pin TMR0 0 0 T0SE T0CS Set Flag bit T0IF on Overflow 8-bit Prescaler PSA 1 PSA 8 3 PS<2:0> 1 WDT Time-Out Watchdog Timer 0 PSA WDTE Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. TABLE 12-7: WDT STATUS Conditions WDT WDTE = 0 CLRWDT Command Cleared Exit Sleep + System Clock = EXTRC, INTRC, EC Exit Sleep + System Clock = XT, HS, LP © 2007 Microchip Technology Inc. Cleared until the end of OST Preliminary DS41288C-page 119 PIC16F610/616/16HV610/616 TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — (1) CONFIG Legend: Note 1: Shaded cells are not used by the Watchdog Timer. See Register 12-1 for operation of all Configuration Word register bits. DS41288C-page 120 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 12.7 Power-Down Mode (Sleep) The Power-Down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • • • • • WDT will be cleared but keeps running. PD bit in the STATUS register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin and the comparators and CVREF should be disabled. I/O pins that are highimpedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pullups on PORTA should be considered. The MCLR pin must be at a logic high level. Note: 12.7.1 It should be noted that a Reset generated by a WDT time-out does not drive MCLR pin low. WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from RA2/INT pin, PORTA change or a peripheral interrupt. The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. 4. 5. 6. Timer1 interrupt. Timer1 must be operating as an asynchronous counter. ECCP Capture mode interrupt. A/D conversion (when A/D clock source is RC). Comparator output changes state. Interrupt-on-change. External Interrupt from INT pin. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared) and any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. 12.7.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. • If the interrupt occurs during or after the execution of a SLEEP instruction, the device will Immediately wake-up from Sleep. The SLEEP instruction is executed. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. See Figure 12-9 for more details. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 121 PIC16F610/616/16HV610/616 FIGURE 12-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON reg.) Interrupt Latency (3) GIE bit (INTCON reg.) Processor in Sleep Instruction Flow PC Instruction Fetched Instruction Executed Note 12.8 PC Inst(PC) = Sleep Inst(PC – 1) PC + 1 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Dummy Cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC, INTOSC and RC Oscillator modes. 3: GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = ‘0’, execution will continue in-line. 4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference. Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP™ for verification purposes. Note: 12.9 The entire Flash program memory will be erased when the code protection is turned off. See the “PIC12F60X/12F61X/16F61X Memory Programming Specification” (DS41284) for more information. ID Locations Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. DS41288C-page 122 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 12.10 In-Circuit Serial Programming™ 12.11 In-Circuit Debugger The PIC16F610/616/16HV610/616 microcontrollers can be serially programmed while in the end application circuit. This is simply done with five connections for: Since in-circuit debugging requires access to three pins, MPLAB® ICD 2 development with an 14-pin device is not practical. A special 28-pin PIC16F610/ 616/16HV610/616 ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user. clock data power ground programming voltage A special debugging adapter allows the ICD device to be used in place of a PIC16F610/616/16HV610/616 device. The debugging adapter is the only source of the ICD device. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the RA0 and RA1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See the “PIC12F60X/ 12F61X/16F61X Memory Programming Specification” (DS41284) for more information. RA0 becomes the programming data and RA1 becomes the programming clock. Both RA0 and RA1 are Schmitt Trigger inputs in Program/Verify mode. A typical In-Circuit Serial Programming connection is shown in Figure 12-10. FIGURE 12-10: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections External Connector Signals * PIC16F610/16HV610 PIC16F616/16HV616 VDD 0V VSS VPP MCLR/VPP/RA3 CLK RA1 Data I/O RA0 * TABLE 12-9: Resource Description I/O pins ICDCLK, ICDDATA Stack 1 level Program Memory Address 0h must be NOP 700h-7FFh For more information, see “MPLAB® ICD 2 In-Circuit Debugger User’s Guide” (DS51331), available on Microchip’s web site (www.microchip.com). 28-PIN ICD PINOUT 28-Pin PDIP In-Circuit Debug Device VDD CS0 CS1 CS2 RA5 RA4 RA3 RC5 RC4 RC3 NC ICDCLK ICDMCLR ICDDATA * To Normal Connections * Isolation devices (as required) Note: DEBUGGER RESOURCES FIGURE 12-11: +5V * When the ICD pin on the PIC16F610/616/16HV610/ 616 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 12-9 shows which features are consumed by the background debugger. 1 2 3 28 27 26 4 5 25 24 6 7 8 9 10 11 PIC16F616-ICD • • • • • 23 22 21 20 19 18 12 17 13 14 16 15 GND RA0 RA1 SHUNTEN RA2 RC0 RC1 RC2 NC NC NC NC NC ICD To erase, the device VDD must be above the Bulk Erase VDD minimum given in the “PIC12F615/12HV615/16F616/16HV616 Memory Programming Specification” (DS41284) © 2007 Microchip Technology Inc. Preliminary DS41288C-page 123 PIC16F610/616/16HV610/616 NOTES: DS41288C-page 124 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 13.0 INSTRUCTION SET SUMMARY The PIC16F610/616/16HV610/616 instruction set is highly orthogonal and is comprised of three basic categories: TABLE 13-1: OPCODE FIELD DESCRIPTIONS Field Description Register file address (0x00 to 0x7F) f • Byte-oriented operations • Bit-oriented operations • Literal and control operations W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 13-1, while the various opcode fields are summarized in Table 13-1. x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Table 13-2 lists the instructions recognized by the MPASMTM assembler. For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is placed in the W register. If ‘d’ is one, the result is placed in the file register specified in the instruction. PC Program Counter TO Time-out bit Carry bit C DC Digit carry bit Zero bit Z PD Power-down bit FIGURE 13-1: For bit-oriented instructions, ‘b’ represents a bit field designator, which selects the bit affected by the operation, while ‘f’ represents the address of the file in which the bit is located. For literal and control operations, ‘k’ represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 μs. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) Literal and control operations General 8 7 OPCODE Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (RMW) operation. The register is read, the data is modified, and the result is stored according to either the instruction or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. 0 b = 3-bit bit address f = 7-bit file register address 13 13.1 0 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 0 k (literal) k = 11-bit immediate value For example, a CLRF PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the RAIF flag. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 125 PIC16F610/616/16HV610/616 TABLE 13-2: PIC16F610/616/16HV610/616 INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 C, DC, Z Z Z Z Z Z Z Z Z C C C, DC, Z Z 1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS 1 1 1 (2) 1 (2) 01 01 01 01 1, 2 1, 2 3 3 LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: 2: 3: k k k – k k k – k – – k k Add literal and W AND literal with W Call Subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 C, DC, Z Z TO, PD Z TO, PD C, DC, Z Z When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS41288C-page 126 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 13.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. k BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. BSF Bit Set f Syntax: [ label ] BSF f,b ADDWF Add W and f Syntax: [ label ] ADDWF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: (W) + (f) → (destination) Operation: 1 → (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: Bit ‘b’ in register ‘f’ is set. ANDLW AND literal with W BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDLW Syntax: [ label ] BTFSC f,b Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) .AND. (k) → (W) 0 ≤ f ≤ 127 0≤b≤7 Status Affected: Z Operation: skip if (f<b>) = 0 Description: The contents of W register are AND’ed with the eight-bit literal ‘k’. The result is placed in the W register. Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a two-cycle instruction. ANDWF f,d k AND W with f Syntax: [ label ] ANDWF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .AND. (f) → (destination) f,d Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2007 Microchip Technology Inc. f,b Preliminary DS41288C-page 127 PIC16F610/616/16HV610/616 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: None Operation: 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. Operation: skip if (f<b>) = 1 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. CALL Call Subroutine COMF Complement f Syntax: [ label ] CALL k Syntax: [ label ] COMF Operands: 0 ≤ k ≤ 2047 Operands: Operation: (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (destination) Status Affected: Z Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DECF Decrement f Syntax: [ label ] DECF f,d f,d Status Affected: None Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. CLRF Clear f Syntax: [ label ] CLRF Operands: 0 ≤ f ≤ 127 Operands: Operation: 00h → (f) 1→Z 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are cleared and the Z bit is set. Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW f Operands: None Operation: 00h → (W) 1→Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. DS41288C-page 128 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a NOP is executed instead, making it a two-cycle instruction. Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, a NOP is executed instead, making it a two-cycle instruction. GOTO Unconditional Branch IORLW Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 2047 Operands: 0 ≤ k ≤ 255 Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> Operation: (W) .OR. k → (W) Status Affected: Z Status Affected: None Description: Description: GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. The contents of the W register are OR’ed with the eight-bit literal ‘k’. The result is placed in the W register. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (destination) Operation: (W) .OR. (f) → (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. GOTO k INCF f,d © 2007 Microchip Technology Inc. Preliminary INCFSZ f,d Inclusive OR literal with W IORLW k IORWF f,d DS41288C-page 129 PIC16F610/616/16HV610/616 MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] MOVF f,d MOVWF Move W to f Syntax: [ label ] MOVWF Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) f Operation: (f) → (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’. If d = 0, destination is W register. If d = 1, the destination is file register ‘f’ itself. d = 1 is useful to test a file register since status flag Z is affected. Move data from W register to register ‘f’. Words: 1 Cycles: 1 Words: 1 Cycles: 1 Example: MOVF Example: MOVW F OPTION Before Instruction OPTION = W = After Instruction OPTION = W = FSR, 0 0xFF 0x4F 0x4F 0x4F After Instruction W = value in FSR register Z = 1 MOVLW Move literal to W NOP No Operation Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W) Operation: No operation Status Affected: None Status Affected: None Description: The eight-bit literal ‘k’ is loaded into W register. The “don’t cares” will assemble as ‘0’s. Description: No operation. Words: 1 Cycles: 1 Words: 1 Cycles: 1 Example: MOVLW k Example: MOVLW NOP 0x5A After Instruction W = DS41288C-page 130 NOP 0x5A Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC, 1 → GIE Operation: k → (W); TOS → PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Description: The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = GIE = TOS 1 TABLE RETLW k CALL TABLE;W contains ;table offset ;value GOTO DONE • • ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ;End of table DONE Before Instruction W = 0x07 After Instruction W = value of k8 © 2007 Microchip Technology Inc. RETURN Return from Subroutine Syntax: [ label ] Operands: None Operation: TOS → PC RETURN Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Preliminary DS41288C-page 131 PIC16F610/616/16HV610/616 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 00h → WDT, 0 → WDT prescaler, 1 → TO, 0 → PD RLF f,d C Words: 1 Cycles: 1 Example: Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Register f RLF REG1,0 Before Instruction REG1 C = = 1110 0110 0 = = = 1110 0110 1100 1100 1 After Instruction REG1 W C RRF Rotate Right f through Carry SUBLW Syntax: [ label ] Syntax: [ label ] SUBLW k Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. RRF f,d C DS41288C-page 132 Register f Preliminary Subtract W from literal The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. Result Condition C=0 W>k C=1 W≤k DC = 0 W<3:0> > k<3:0> DC = 1 W<3:0> ≤ k<3:0> © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 SUBWF Subtract W from f XORWF Exclusive OR W with f Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORWF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (destination) Operation: (W) .XOR. (f) → (destination) Status Affected: C, DC, Z Status Affected: Z Description: Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. C=0 W>f C=1 W≤f DC = 0 W<3:0> > f<3:0> DC = 1 W<3:0> ≤ f<3:0> SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. XORLW f,d Exclusive OR literal with W Syntax: [ label ] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 133 PIC16F610/616/16HV610/616 NOTES: DS41288C-page 134 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 14.0 DEVELOPMENT SUPPORT 14.1 The PIC® microcontrollers are supported with a full range of hardware and software development tools: • Integrated Development Environment - MPLAB® IDE Software • Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debugger - MPLAB ICD 2 • Device Programmers - PICSTART® Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Visual device initializer for easy register initialization • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 135 PIC16F610/616/16HV610/616 14.2 MPASM Assembler 14.5 The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 14.6 14.3 MPLAB C18 and MPLAB C30 C Compilers The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip’s PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 14.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. MPLAB ASM30 Assembler, Linker and Librarian MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS41288C-page 136 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 14.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 14.9 The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were chosen to best make these features available in a simple, unified application. 14.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC® and MCU devices. It debugs and programs PIC® and dsPIC® Flash microcontrollers with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, lowvoltage differential signal (LVDS) interconnection (CAT5). MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. 14.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 137 PIC16F610/616/16HV610/616 14.11 PICSTART Plus Development Programmer 14.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. 14.12 PICkit 2 Development Programmer The PICkit™ 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip’s baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH’s PICC™ Lite C compiler, and is designed to help get up to speed quickly using PIC® microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip’s powerful, mid-range Flash memory family of microcontrollers. DS41288C-page 138 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart® battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 15.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ...................................................................................................................... 95 mA Maximum current into VDD pin ......................................................................................................................... 95 mA Input clamp current, IIK (VI < 0 or VI > VDD)...............................................................................................................± 20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD).........................................................................................................± 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by PORTA and PORTC (combined) ........................................................................... 90 mA Maximum current sourced PORTA and PORTC (combined) ........................................................................... 90 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 139 PIC16F610/616/16HV610/616 FIGURE 15-1: PIC16F610/616 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.5 5.0 VDD (V) 4.5 4.0 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: PIC16HV610/616 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.0 VDD (V) 4.5 4.0 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41288C-page 140 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 15-3: PIC16F610/616 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 125 ± 5% Temperature (°C) 85 ± 2% 60 ± 1% 25 0 2.5 2.0 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-4: PIC16HV610/616 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 125 ± 5% Temperature (°C) 85 ± 2% 60 ± 1% 25 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (V) © 2007 Microchip Technology Inc. Preliminary DS41288C-page 141 PIC16F610/616/16HV610/616 15.1 DC Characteristics: PIC16F610/616/16HV610/616-I (Industrial) PIC16F610/616/16HV610/616-E (Extended) DC CHARACTERISTICS Param No. Sym VDD D001 Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min Typ† Max Units Conditions Supply Voltage PIC16F610/616 2.0 — 5.5 V FOSC < = 4 MHz D001 PIC16HV610/616 2.0 — 5.0 V FOSC < = 4 MHz D001B PIC16F610/616 2.0 — 5.5 V FOSC < = 8 MHz D001B PIC16HV610/616 2.0 — 5.0 V FOSC < = 8 MHz D001C PIC16F610/616 3.0 — 5.5 V FOSC < = 10 MHz D001C PIC16HV610/616 3.0 — 5.0 V FOSC < = 10 MHz D001D PIC16F610/616 4.5 — 5.5 V FOSC < = 20 MHz D001D PIC16HV610/616 4.5 — 5.0 V FOSC < = 20 MHz D002* VDR RAM Data Retention Voltage(1) 1.5 — — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal — VSS — V See Section 12.3.1 “Power-on Reset (POR)” for details. D004* SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 — — V/ms See Section 12.3.1 “Power-on Reset (POR)” for details. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. DS41288C-page 142 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 15.2 DC Characteristics: PIC16F610/616/16HV610/616-I (Industrial) PIC16F610/616/16HV610/616-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. D010 Conditions Device Characteristics Min Typ† Max Units Note VDD Supply Current (IDD) D011* D012 D013* D014 D016* D017 D018 D019 (1, 2) — 11 16 μA 2.0 — 18 28 μA 3.0 — 35 54 μA 5.0 — 140 240 μA 2.0 — 220 380 μA 3.0 — 380 550 μA 5.0 — 260 360 μA 2.0 — 420 650 μA 3.0 — 0.8 1.1 mA 5.0 — 130 220 μA 2.0 — 215 360 μA 3.0 — 360 520 μA 5.0 — 220 340 μA 2.0 — 375 550 μA 3.0 — 0.65 1.0 mA 5.0 — 340 450 μA 2.0 — 500 700 μA 3.0 — 0.8 1.2 mA 5.0 — 410 650 μA 2.0 — 700 950 μA 3.0 — 1.30 1.65 mA 5.0 — 230 400 μA 2.0 — 400 680 μA 3.0 — 0.63 1.1 mA 5.0 — 2.6 3.25 mA 4.5 — 2.8 3.35 mA 5.0 FOSC = 32 kHz LP Oscillator mode FOSC = 1 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz EC Oscillator mode FOSC = 4 MHz INTOSC mode FOSC = 8 MHz INTOSC mode FOSC = 4 MHz EXTRC mode(3) FOSC = 20 MHz HS Oscillator mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in kΩ. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 143 PIC16F610/616/16HV610/616 15.3 DC Characteristics: PIC16F616/16HV616- I (Industrial) DC CHARACTERISTICS Param No. D020 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Device Characteristics Min Typ† 0.15 1.5 μA 3.0 1.8 μA 5.0 500 nA 3.0 — 150 D024 D025* D026 D027 WDT, BOR, Comparators, VREF and T1OSC disabled 0.35 — — D023 Note 2.0 PIC16F610/616 D022 VDD μA — D021 Units 1.2 Power-down Base Current(IPD)(2) PIC16HV610/616 Max 0.05 — 350 — μA 2.0 — 350 — μA 3.0 -40°C ≤ TA ≤ +25°C 4 — 50 mA 5.0 NOTE 3 — 1 TBD μA 2.0 WDT Current(1) — 2 TBD μA 3.0 — 8 TBD μA 5.0 — 3 TBD μA 3.0 — 4 TBD μA 5.0 — 32 TBD μA 2.0 — 60 TBD μA 3.0 — 120 TBD μA 5.0 — 30 30 μA 2.0 — 45 55 μA 3.0 — 75 95 μA 5.0 — 39 47 μA 2.0 — 59 72 μA 3.0 — 98 124 μA 5.0 — 45 7.0 μA 2.0 — 5.0 8.0 μA 3.0 — 6.0 12 μA 5.0 — 0.30 1.6 μA 3.0 — 0.36 1.9 μA 5.0 BOR Current(1) Comparator Current(1), both comparators enabled CVREF Current(1) (high range) CVREF Current(1) (low range) T1OSC Current(1), 32.768 kHz A/D Current(1), no conversion in progress Legend: TBD = To Be Determined * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: Shunt regulator is always enabled and always draws operating current. DS41288C-page 144 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 15.4 DC Characteristics: PIC16F610/616/16HV610/616-E (Extended) DC CHARACTERISTICS Param No. D020E Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Device Characteristics Power-down Base Current (IPD)(2) Min Typ† — 0.05 Max Units VDD Note WDT, BOR, Comparators, VREF and T1OSC disabled 9 μA 2.0 — 0.15 11 μA 3.0 PIC16F610/616 — 0.35 15 μA 5.0 — 350 — μA 2.0 PIC16HV610/616 — 350 — μA 3.0 D021E 4 — 200 nA 5.0 Note 3 — 1 TBD μA 2.0 WDT Current(1) — 2 TBD μA 3.0 — 8 TBD μA 5.0 D022E — 3 TBD μA 3.0 — 4 TBD μA 5.0 D023E — 32 TBD μA 2.0 — 60 TBD μA 3.0 — 120 TBD μA 5.0 — 30 70 μA 2.0 — 45 90 μA 3.0 — 75 120 μA 5.0 — 39 91 μA 2.0 D024E D025E* D026E D027E — 59 117 μA 3.0 — 98 156 μA 5.0 — 4.5 25 μA 2.0 — 5 30 μA 3.0 — 6 40 μA 5.0 — 0.30 12 μA 3.0 — 0.36 16 μA 5.0 BOR Current(1) Comparator Current(1), both comparators enabled CVREF Current(1) (high range) CVREF Current(1) (low range) T1OSC Current(1), 32.768 kHz A/D Current(1), no conversion in progress * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: Shunt regulator is always enabled and always draws operating current. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 145 PIC16F610/616/16HV610/616 15.5 DC Characteristics: PIC16F610/616/16HV610/616-I (Industrial) PIC16F610/616/16HV610/616-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ† Max Units Vss Vss Conditions — 0.8 V 4.5V ≤ VDD ≤ 5.5V — 0.15 VDD V 2.0V ≤ VDD ≤ 4.5V Vss — 0.2 VDD V 2.0V ≤ VDD ≤ 5.5V VSS — 0.2 VDD V Input Low Voltage I/O port: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (RC mode)(1) D033 OSC1 (XT and LP modes) VSS — 0.3 V D033A OSC1 (HS mode) VSS — 0.3 VDD V VIH Input High Voltage I/O ports: D040 — with TTL buffer D040A D041 with Schmitt Trigger buffer 2.0 — VDD V 4.5V ≤ VDD ≤ 5.5V 0.25 VDD + 0.8 — VDD V 2.0V ≤ VDD ≤ 4.5V 0.8 VDD — VDD V 2.0V ≤ VDD ≤ 5.5V 0.8 VDD — VDD V D042 MCLR D043 OSC1 (XT and LP modes) 1.6 — VDD V D043A OSC1 (HS mode) 0.7 VDD — VDD V D043B OSC1 (RC mode) 0.9 VDD — VDD V (Note 1) Input Leakage Current(2) IIL D060 I/O ports — ± 0.1 ±1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR(3) — ± 0.1 ±5 μA VSS ≤ VPIN ≤ VDD D063 OSC1 — ± 0.1 ±5 μA VSS ≤ VPIN ≤ VDD, XT, HS and LP oscillator configuration 50 250 400 μA VDD = 5.0V, VPIN = VSS — — 0.6 V VDD – 0.7 — — V D070* IPUR VOL D080 PORTA Weak Pull-up Current Output Low Voltage (4) I/O ports VOH D090 I/O ports * † Note 1: 2: 3: 4: IOL = 8.5 mA, VDD = 4.5V (Ind.) Output High Voltage(4) IOH = -3.0 mA, VDD = 4.5V (Ind.) These parameters are characterized but not tested. Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode. DS41288C-page 146 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 15.5 DC Characteristics: PIC16F610/616/16HV610/616-I (Industrial) PIC16F610/616/16HV610/616-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units OSC2 pin — — 15 pF All I/O pins — — 50 pF Conditions Capacitive Loading Specs on Output Pins D101* COSC2 D101A* CIO In XT, HS and LP modes when external clock is used to drive OSC1 Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W D130A ED Cell Endurance 1K 10K — E/W D131 VPR VDD for Read VMIN — 5.5 V D132 VPEW VDD for Erase/Write 4.5 — 5.5 V D133 TPEW Erase/Write cycle time — 2 2.5 ms D134 TRETD Characteristic Retention 40 — — * † Note 1: 2: 3: 4: -40°C ≤ TA ≤ +85°C +85°C ≤ TA ≤ +125°C VMIN = Minimum operating voltage Year Provided no other specifications are violated These parameters are characterized but not tested. Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 147 PIC16F610/616/16HV610/616 15.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic TH01 θJA Thermal Resistance Junction to Ambient TH02 θJC Thermal Resistance Junction to Case TH03 TH04 TH05 TDIE Die Temperature PD Power Dissipation PINTERNAL Internal Power Dissipation TH06 TH07 Note 1: 2: Typ Units 70 85.0 100 46.3 32.5 31.0 31.7 2.6 150 — — C/W C/W C/W C/W C/W C/W C/W C/W C W W Conditions 14-pin PDIP package 14-pin SOIC package 14-pin TSSOP package 16-pin QFN 4x4mm package 14-pin PDIP package 14-pin SOIC package 14-pin TSSOP package 16-pin QFN 4x4mm package PD = PINTERNAL + PI/O PINTERNAL = IDD x VDD (NOTE 1) PI/O I/O Power Dissipation — W PI/O = Σ (IOL * VOL) + Σ (IOH * (VDD - VOH)) PDER Derated Power — W PDER = PDMAX (TDIE - TA)/θJA (NOTE 2) IDD is current to run the chip alone without driving any load on the output pins. TA = Ambient Temperature. DS41288C-page 148 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 15.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O Port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 15-5: T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins 15 pF for OSC2 output © 2007 Microchip Technology Inc. Preliminary DS41288C-page 149 PIC16F610/616/16HV610/616 15.8 AC Characteristics: PIC16F610/616/16HV610/616 (Industrial, Extended) FIGURE 15-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 15-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym OS01 FOSC Characteristic External CLKIN Frequency(1) (1) Oscillator Frequency OS02 TOSC External CLKIN Period(1) Oscillator Period(1) OS03 TCY Instruction Cycle Time(1) OS04* TOSH, TOSL External CLKIN High, External CLKIN Low TOSR, TOSF External CLKIN Rise, External CLKIN Fall OS05* * † Note 1: Min Typ† Max Units Conditions DC — 37 kHz DC — 4 MHz XT Oscillator mode DC — 20 MHz HS Oscillator mode DC — 20 MHz EC Oscillator mode LP Oscillator mode — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 20 MHz HS Oscillator mode DC — 4 MHz RC Oscillator mode 27 — ∞ μs LP Oscillator mode 250 — ∞ ns XT Oscillator mode 50 — ∞ ns HS Oscillator mode 50 — ∞ ns EC Oscillator mode — 30.5 — μs LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode 200 TCY DC ns TCY = 4/FOSC 2 — — μs LP oscillator 100 — — ns XT oscillator 20 — — ns HS oscillator 0 — ∞ ns LP oscillator 0 — ∞ ns XT oscillator 0 — ∞ ns HS oscillator These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. DS41288C-page 150 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 15-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic OS06 TWARM Internal Oscillator Switch when running(3) OS08 INTOSC Internal Calibrated INTOSC Frequency(2) OS10* TIOSC ST INTOSC Oscillator Wakeup from Sleep Start-up Time * † Note 1: 2: 3: Freq. Tolerance Min Typ† Max Units — — — 2 TOSC Slowest clock ±1% 7.92 8.0 8.08 MHz VDD = 3.5V, 25°C ±2% 7.84 8.0 8.16 MHz 2.5V ≤ VDD ≤ 5.5V, 0°C ≤ TA ≤ +85°C ±5% 7.60 8.0 8.40 MHz 2.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ +85°C (Ind.), -40°C ≤ TA ≤ +125°C (Ext.) — 5.5 12 24 μs VDD = 2.0V, -40°C to +85°C — 3.5 7 14 μs VDD = 3.0V, -40°C to +85°C — 3 6 11 μs VDD = 5.0V, -40°C to +85°C Conditions These parameters are characterized but not tested. Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. By design. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 151 PIC16F610/616/16HV610/616 FIGURE 15-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 15-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic TOSH2CKL FOSC↑ to CLKOUT↓ (1) OS12 TOSH2CKH FOSC↑ to CLKOUT↑ (1) OS13 TCKL2IOV CLKOUT↓ to Port out valid(1) OS14 TIOV2CKH Port input valid before CLKOUT↑(1) OS15 TOSH2IOV OS16 OS11 Min Typ† Max Units Conditions — — 70 ns VDD = 5.0V VDD = 5.0V — — 72 ns — — 20 ns TOSC + 200 ns — — ns FOSC↑ (Q1 cycle) to Port out valid — 50 70* ns VDD = 5.0V TOSH2IOI FOSC↑ (Q2 cycle) to Port input invalid (I/O in hold time) 50 — — ns VDD = 5.0V OS17 TIOV2OSH Port input valid to FOSC↑ (Q2 cycle) (I/O in setup time) 20 — — ns OS18 TIOR Port output rise time(2) — — 15 40 72 32 ns VDD = 2.0V VDD = 5.0V OS19 TIOF Port output fall time(2) — — 28 15 55 30 ns VDD = 2.0V VDD = 5.0V OS20* TINP INT pin input high or low time 25 — — ns OS21* TRAP PORTA interrupt-on-change new input level time TCY — — ns * † Note 1: 2: These parameters are characterized but not tested. Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. Includes OSC2 in CLKOUT mode. DS41288C-page 152 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 15-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: FIGURE 15-9: Asserted low. BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR + VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset (due to BOR) * 33* 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 153 PIC16F610/616/16HV610/616 TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions 30 TMCL MCLR Pulse Width (low) 2 5 — — — — μs μs VDD = 5V, -40°C to +85°C VDD = 5V, +85°C to +125°C 31 TWDT Watchdog Timer Time-out Period (No Prescaler) 7 TBD 18 18 33 TBD ms ms VDD = 5V, -40°C to +85°C VDD = 5V, +85°C to +125°C 32 TOST Oscillation Start-up Timer Period(1, 2) — 1024 — 33* TPWRT Power-up Timer Period 40 65 140 ms 34* TIOZ I/O High-impedance from MCLR Low or Watchdog Timer Reset — — 2.0 μs 35* VBOR Brown-out Reset Voltage TBD 2.1 TBD V 36* VHYST Brown-out Reset Hysteresis — 50 — mV 37* TBOR Brown-out Reset Minimum Detection Period 100 — — μs TOSC (NOTE 3) (NOTE 4) VDD ≤ VBOR Legend: TBD = To Be Determined * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. DS41288C-page 154 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 15-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. 40* Sym TT0H Characteristic T0CKI High Pulse Width No Prescaler Min Typ† Max Units 0.5 TCY + 20 — — ns 10 — — ns 0.5 TCY + 20 — — ns With Prescaler 41* TT0L T0CKI Low Pulse Width No Prescaler 42* TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler With Prescaler 10 — — ns Greater of: 20 or TCY + 40 N — — ns 0.5 TCY + 20 — — ns 15 — — ns Asynchronous 46* TT1L T1CKI Low Time Synchronous, No Prescaler 30 — — ns 0.5 TCY + 20 — — ns 15 — — ns Synchronous, with Prescaler Asynchronous 47* TT1P T1CKI Input Synchronous Period 48 FT1 Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment 30 — — ns Greater of: 30 or TCY + 40 N — — ns Asynchronous * † 60 — — ns — 32.768 — kHz 2 TOSC — 7 TOSC — Conditions N = prescale value (2, 4, ..., 256) N = prescale value (1, 2, 4, 8) Timers in Sync mode These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 155 PIC16F610/616/16HV610/616 FIGURE 15-11: CAPTURE/COMPARE/PWM TIMINGS (ECCP) CCP1 (Capture mode) CC01 CC02 CC03 Note: TABLE 15-6: Refer to Figure 15-5 for load conditions. CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. CC01* CC02* CC03* Sym TccL TccH TccP Characteristic CCP1 Input Low Time CCP1 Input High Time CCP1 Input Period Min Typ† Max Units No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns 3TCY + 40 N — — ns Conditions N = prescale value (1, 4 or 16) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41288C-page 156 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 15-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristics CM01 VOS Input Offset Voltage CM02 VCM Input Common Mode Voltage CM03* CMRR Common Mode Rejection Ratio CM04* TRT Response Time Min Typ† Max Units — ± 5.0 ± 10 mV 0 — VDD – 1.5 V +55 — — dB Falling — 150 600 ns Rising — 200 1000 ns CM05* TMC2COV Comparator Mode Change to Output Valid — — 10 μs CM06* VHYS — 45 — mV Input Hysteresis Voltage Comments (VDD - 1.5)/2 (NOTE 1) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV. TABLE 15-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristics Min Typ† Max Units Comments CV01 CLSB Step Size(2) — — VDD/24 VDD/32 — — V V Low Range (VRR = 1) High Range (VRR = 0) CV02 CACC Absolute Accuracy — — — — ± 1/2 ± 1/2 LSb LSb Low Range (VRR = 1) High Range (VRR = 0) CV03 CR Unit Resistor Value (R) — 2k — Ω CV04 CST Settling Time(1) — — 10 μs † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. 2: See Section 8.11 “Comparator Voltage Reference” for more information. TABLE 15-9: VOLTAGE REFERENCE SPECIFICATIONS VR Voltage Reference Specifications Param No. Symbol Characteristics Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Min Typ Max Units VR01 VP6OUT VP6 voltage output 0.55 0.6 0.65 V VR02 V1P2OUT V1P2 voltage output 1.1 1.200 1.3 V VR03 TSTABLE Settling Time — 10 — μs * Comments These parameters are characterized but not tested. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 157 PIC16F610/616/16HV610/616 TABLE 15-10: SHUNT REGULATOR SPECIFICATIONS (PIC16HV610/616 only) SHUNT REGULATOR CHARACTERISTICS Param No. Symbol Characteristics SR01 VSHUNT Shunt Voltage SR02 ISHUNT SR03* TSETTLE Settling Time SR04 CLOAD Load Capacitance SR05 ΔISNT Regulator operating current * Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Min Typ Max Units 4.75 5 5.25 V Shunt Current Comments 4 — 50 mA — — 150 ns To 1% of final value 0.01 — 10 μF Bypass capacitor on VDD pin — — 180 μA Includes band gap reference current These parameters are characterized but not tested. TABLE 15-11: PIC16F616/16HV616 A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym No. Characteristic Min Typ† Max Units Conditions AD01 NR Resolution — — 10 bits AD02 EIL Integral Error — — ±1 LSb VREF = 5.12V AD03 EDL Differential Error — — ±1 LSb No missing codes to 10 bits VREF = 5.12V AD04 EOFF Offset Error — 1.5 — LSb VREF = 5.12V AD07 EGN LSb VREF = 5.12V bit Gain Error — — ±1 AD06 VREF AD06A Reference Voltage(3) 2.2 2.5 — — VDD V AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended Impedance of Analog Voltage Source — — 10 kΩ AD09* IREF VREF Input Current(3) 10 — 1000 μA During VAIN acquisition. Based on differential of VHOLD to VAIN. — — 50 μA During A/D conversion cycle. Absolute minimum to ensure 1 LSb accuracy * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input. 4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. DS41288C-page 158 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 15-12: PIC16F616/16HV616 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym AD130* TAD Characteristic A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Min Typ† 1.6 — 9.0 μs TOSC-based, VREF ≥ 3.0V 3.0 — 9.0 μs TOSC-based, VREF full range 3.0 6.0 9.0 μs ADCS<1:0> = 11 (ADRC mode) At VDD = 2.5V 1.6 4.0 6.0 μs At VDD = 5.0V — 11 — TAD Set GO/DONE bit to new data in A/D Result register 11.5 — μs Amplifier Settling Time — — 5 μs Q4 to A/D Clock Start — TOSC/2 — — — TOSC/2 + TCY — — AD132* TACQ Acquisition Time AD133* TAMP AD134 TGO Max Units Conditions If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Section 9.3 “A/D Acquisition Requirements” for minimum conditions. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 159 PIC16F610/616/16HV610/616 FIGURE 15-12: PIC16F616/16HV616 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 9 A/D Data 8 7 6 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO DONE Note 1: Sampling Stopped AD132 Sample If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. FIGURE 15-13: PIC16F616/16HV616 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK 9 A/D Data 8 7 6 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample Note 1: AD132 Sampling Stopped If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. DS41288C-page 160 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs are not available at this time. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 161 PIC16F610/616/16HV610/616 NOTES: DS41288C-page 162 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 14-Lead PDIP Example PIC16F616 -I/P e3 0610017 XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (.150”) Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16F616-E 0610017 14-Lead TSSOP Example XXXXXXXX YYWW NNN XXXX/ST 0610 017 16-Lead QFN Example XXXXXXX XXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: * 16F616 -I/ML 0610017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability code. For PIC® device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 163 PIC16F610/616/16HV610/616 17.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 8 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 b1 .040 .060 .070 b .014 .018 .022 eB – – Upper Lead Width Lower Lead Width Overall Row Spacing § .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-018B DS41288C-page 164 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 14-Lead Plastic Small Outline (SL or OD) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e h b A c φ A2 L A1 β L1 Units Dimension Limits Number of Pins α h MILLIMETERS MIN N NOM MAX 14 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E Molded Package Width E1 3.90 BSC Overall Length D 8.65 BSC 1.75 6.00 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-065B © 2007 Microchip Technology Inc. Preliminary DS41288C-page 165 PIC16F610/616/16HV610/616 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b A2 A c A1 φ Units Dimension Limits Number of Pins L L1 MILLIMETERS MIN N NOM MAX 14 Pitch e Overall Height A – 0.65 BSC – Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 1.20 Overall Width E Molded Package Width E1 4.30 6.40 BSC 4.40 Molded Package Length D 4.90 5.00 5.10 Foot Length L 0.45 0.60 0.75 Footprint L1 4.50 1.00 REF Foot Angle φ 0° – 8° Lead Thickness c 0.09 – 0.20 Lead Width b 0.19 – 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-087B DS41288C-page 166 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 16-Lead Plastic Quad Flat, No Lead Package (ML) – 4x4x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D2 D EXPOSED PAD e E E2 2 2 1 b 1 TOP VIEW K N N NOTE 1 L BOTTOM VIEW A3 A A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 16 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E Exposed Pad Width E2 Overall Length D Exposed Pad Length D2 2.50 2.65 2.80 b 0.25 0.30 0.35 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Contact Width 4.00 BSC 2.50 2.65 2.80 4.00 BSC Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-127B © 2007 Microchip Technology Inc. Preliminary DS41288C-page 167 PIC16F610/616/16HV610/616 NOTES: DS41288C-page 168 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 APPENDIX A: DATA SHEET REVISION HISTORY APPENDIX B: Revision A MIGRATING FROM OTHER PIC® DEVICES This discusses some of the issues in migrating from other PIC® devices to the PIC16F6XX Family of devices. This is a new data sheet. Revision B (12/06) Added PIC16F610/16HV610 parts. Replaced Package Drawings. Revision C (03/2007) Replaced Package Drawings (Rev. AM); Replaced Development Support Section; Revised Product ID System. B.1 PIC16F676 to PIC16F610/616/16HV610/616 TABLE B-1: FEATURE COMPARISON Feature Max Operating Speed Max Program Memory (Words) PIC16F676 PIC16F610/16HV610 PIC16F616/16HV616 20 MHz 20 MHz 20 MHz 1024 1024 2048 SRAM (bytes) 64 64 128 A/D Resolution 10-bit None 10-bit Timers (8/16-bit) 1/1 1/1 2/1 Oscillator Modes 8 8 8 Brown-out Reset Y Y Y Internal Pull-ups RA0/1/2/4/5 RA0/1/2/4/5, MCLR RA0/1/2/4/5, MCLR RA0/1/2/3/4/5 RA0/1/2/3/4/5 RA0/1/2/3/4/5 1 2 2 Interrupt-on-change Comparator ECCP INTOSC Frequencies Internal Shunt Regulator Note: N N Y 4 MHz 8 MHz 8 MHz N Y (PIC16HV610) Y (PIC16HV616) This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 169 PIC16F610/616/16HV610/616 NOTES: DS41288C-page 170 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 INDEX A A/D Specifications.................................................... 158, 159 Absolute Maximum Ratings .............................................. 139 AC Characteristics Industrial and Extended ............................................ 150 Load Conditions ........................................................ 149 ADC .................................................................................... 71 Acquisition Requirements ........................................... 79 Associated registers.................................................... 81 Block Diagram............................................................. 71 Calculating Acquisition Time....................................... 79 Channel Selection....................................................... 72 Configuration............................................................... 72 Configuring Interrupt ................................................... 74 Conversion Clock........................................................ 72 Conversion Procedure ................................................ 74 Internal Sampling Switch (RSS) Impedance................ 79 Interrupts..................................................................... 73 Operation .................................................................... 74 Operation During Sleep .............................................. 74 Port Configuration ....................................................... 72 Reference Voltage (VREF)........................................... 72 Result Formatting........................................................ 73 Source Impedance...................................................... 79 Special Event Trigger.................................................. 74 Starting an A/D Conversion ........................................ 73 ADCON0 Register............................................................... 76 ADCON1 Register............................................................... 77 ADRESH Register (ADFM = 0) ........................................... 78 ADRESH Register (ADFM = 1) ........................................... 78 ADRESL Register (ADFM = 0)............................................ 78 ADRESL Register (ADFM = 1)............................................ 78 Analog-to-Digital Converter. See ADC ANSEL Register .................................................................. 32 Assembler MPASM Assembler................................................... 136 B Block Diagrams (CCP) Capture Mode Operation ................................. 84 ADC ............................................................................ 71 ADC Transfer Function ............................................... 80 Analog Input Model ............................................... 62, 80 CCP PWM................................................................... 88 Clock Source............................................................... 25 Comparator C1 ........................................................... 56 Comparator C2 ........................................................... 56 Compare ..................................................................... 86 Crystal Operation ........................................................ 27 External RC Mode....................................................... 28 In-Circuit Serial Programming Connections.............. 123 Interrupt Logic ........................................................... 116 MCLR Circuit............................................................. 109 On-Chip Reset Circuit ............................................... 108 PIC16F610/16HV610.................................................... 7 PIC16F616/16HV616.................................................... 8 PWM (Enhanced)........................................................ 91 RA0 and RA1 Pins ...................................................... 34 RA2 Pins ..................................................................... 35 RA3 Pin....................................................................... 36 RA4 Pin....................................................................... 37 RA5 Pin....................................................................... 38 RC0 and RC1 Pins...................................................... 41 © 2007 Microchip Technology Inc. RC2 and RC3 Pins ..................................................... 41 RC4 Pin ...................................................................... 42 RC5 Pin ...................................................................... 42 Resonator Operation .................................................. 27 Timer1 ........................................................................ 47 Timer2 ........................................................................ 53 TMR0/WDT Prescaler ................................................ 43 Watchdog Timer ....................................................... 119 Brown-out Reset (BOR).................................................... 110 Associated Registers................................................ 111 Specifications ........................................................... 154 Timing and Characteristics ....................................... 153 C C Compilers MPLAB C18.............................................................. 136 MPLAB C30.............................................................. 136 Calibration Bits.................................................................. 108 Capture Module. See Enhanced Capture/ Compare/PWM (ECCP) Capture/Compare/PWM (CCP) Associated registers w/ Capture/Compare/ PWM..................................................... 85, 87, 103 Capture Mode............................................................. 84 CCP1 Pin Configuration ............................................. 84 Compare Mode........................................................... 86 CCP1 Pin Configuration ..................................... 86 Software Interrupt Mode ............................... 84, 86 Special Event Trigger ......................................... 86 Timer1 Mode Selection................................. 84, 86 Prescaler .................................................................... 84 PWM Mode................................................................. 88 Duty Cycle .......................................................... 89 Effects of Reset .................................................. 90 Example PWM Frequencies and Resolutions, 20 MHz .................................. 89 Example PWM Frequencies and Resolutions, 8 MHz .................................... 89 Operation in Sleep Mode.................................... 90 Setup for Operation ............................................ 90 System Clock Frequency Changes .................... 90 PWM Period ............................................................... 89 Setup for PWM Operation .......................................... 90 CCP1CON (Enhanced) Register ........................................ 83 Clock Sources External Modes........................................................... 26 EC ...................................................................... 26 HS ...................................................................... 27 LP ....................................................................... 27 OST .................................................................... 26 RC ...................................................................... 28 XT ....................................................................... 27 Internal Modes............................................................ 28 INTOSC .............................................................. 28 INTOSCIO .......................................................... 28 CM1CON0 Register............................................................ 60 CM2CON0 Register............................................................ 61 CM2CON1 Register............................................................ 63 Code Examples A/D Conversion .......................................................... 75 Assigning Prescaler to Timer0.................................... 44 Assigning Prescaler to WDT....................................... 44 Changing Between Capture Prescalers ..................... 84 Indirect Addressing..................................................... 22 Preliminary DS41288C-page 171 PIC16F610/616/16HV610/616 Initializing PORTA ....................................................... 31 Initializing PORTC....................................................... 40 Saving Status and W Registers in RAM ................... 118 Code Protection ................................................................ 122 Comparator C2OUT as T1 Gate ..................................................... 63 Operation .................................................................... 55 Operation During Sleep .............................................. 59 Response Time ........................................................... 57 Synchronizing COUT w/Timer1 .................................. 63 Comparator Analog Input Connection Considerations........ 62 Comparator Hysteresis ....................................................... 64 Comparator Module ............................................................ 55 Associated registers.................................................... 65 C1 Output State Versus Input Conditions ................... 57 Comparator Voltage Reference (CVREF) Response Time ........................................................... 57 Comparator Voltage Reference (CVREF) ............................ 68 Effects of a Reset........................................................ 59 Specifications ............................................................ 157 Comparators C2OUT as T1 Gate ..................................................... 48 Effects of a Reset........................................................ 59 Specifications ............................................................ 157 Compare Module. See Enhanced Capture/ Compare/PWM (ECCP) CONFIG Register.............................................................. 107 Configuration Bits.............................................................. 106 CPU Features ................................................................... 106 Customer Change Notification Service ............................. 175 Customer Notification Service........................................... 175 Customer Support ............................................................. 175 D Data Memory....................................................................... 12 DC Characteristics Extended and Industrial ............................................ 146 Industrial and Extended ............................................ 142 Development Support ....................................................... 135 Device Overview ................................................................... 7 E ECCP. See Enhanced Capture/Compare/PWM ECCPAS Register ............................................................. 100 Effects of Reset PWM mode ................................................................. 90 Electrical Specifications .................................................... 139 Enhanced Capture/Compare/PWM..................................... 83 Enhanced Capture/Compare/PWM (ECCP) Enhanced PWM Mode ................................................ 91 Auto-Restart...................................................... 101 Auto-shutdown .................................................. 100 Direction Change in Full-Bridge Output Mode .... 97 Full-Bridge Application ........................................ 95 Full-Bridge Mode................................................. 95 Half-Bridge Application ....................................... 94 Half-Bridge Application Examples..................... 102 Half-Bridge Mode ................................................ 94 Output Relationships (Active-High and Active-Low) ................................................. 92 Output Relationships Diagram ............................ 93 Programmable Dead Band Delay ..................... 102 Shoot-through Current ...................................... 102 Start-up Considerations ...................................... 99 Specifications ............................................................ 156 Timer Resources......................................................... 83 DS41288C-page 172 Errata .................................................................................... 6 F Firmware Instructions ....................................................... 125 Fuses. See Configuration Bits G General Purpose Register File ........................................... 12 I ID Locations...................................................................... 122 In-Circuit Debugger........................................................... 123 In-Circuit Serial Programming (ICSP)............................... 123 Indirect Addressing, INDF and FSR registers..................... 22 Instruction Format............................................................. 125 Instruction Set................................................................... 125 ADDLW..................................................................... 127 ADDWF..................................................................... 127 ANDLW..................................................................... 127 ANDWF..................................................................... 127 BCF .......................................................................... 127 BSF........................................................................... 127 BTFSC ...................................................................... 127 BTFSS ...................................................................... 128 CALL......................................................................... 128 CLRF ........................................................................ 128 CLRW ....................................................................... 128 CLRWDT .................................................................. 128 COMF ....................................................................... 128 DECF ........................................................................ 128 DECFSZ ................................................................... 129 GOTO ....................................................................... 129 INCF ......................................................................... 129 INCFSZ..................................................................... 129 IORLW ...................................................................... 129 IORWF...................................................................... 129 MOVF ....................................................................... 130 MOVLW .................................................................... 130 MOVWF .................................................................... 130 NOP .......................................................................... 130 RETFIE ..................................................................... 131 RETLW ..................................................................... 131 RETURN................................................................... 131 RLF ........................................................................... 132 RRF .......................................................................... 132 SLEEP ...................................................................... 132 SUBLW ..................................................................... 132 SUBWF..................................................................... 133 SWAPF ..................................................................... 133 XORLW .................................................................... 133 XORWF .................................................................... 133 Summary Table ........................................................ 126 INTCON Register................................................................ 18 Internal Oscillator Block INTOSC Specifications ........................................... 151, 152 Internal Sampling Switch (RSS) Impedance........................ 79 Internet Address ............................................................... 175 Interrupts........................................................................... 115 ADC ............................................................................ 74 Associated Registers ................................................ 117 Context Saving ......................................................... 118 Interrupt-on-Change ................................................... 32 PORTA Interrupt-on-Change .................................... 116 RA2/INT .................................................................... 115 Timer0 ...................................................................... 116 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TMR1 .......................................................................... 49 INTOSC Specifications ............................................. 151, 152 IOCA Register ..................................................................... 33 L Load Conditions ................................................................ 149 M MCLR ................................................................................ 109 Internal ...................................................................... 109 Memory Organization.......................................................... 11 Data ............................................................................ 12 Program ...................................................................... 11 Microchip Internet Web Site .............................................. 175 Migrating from other PIC Devices ..................................... 169 MPLAB ASM30 Assembler, Linker, Librarian ................... 136 MPLAB ICD 2 In-Circuit Debugger ................................... 137 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................................... 137 MPLAB Integrated Development Environment Software .. 135 MPLAB PM3 Device Programmer .................................... 137 MPLAB REAL ICE In-Circuit Emulator System................. 137 MPLINK Object Linker/MPLIB Object Librarian ................ 136 O OPCODE Field Descriptions ............................................. 125 Operational Amplifier (OPA) Module AC Specifications...................................................... 158 OPTION Register .......................................................... 17, 45 Oscillator Associated registers.............................................. 29, 51 Oscillator Module ................................................................ 25 EC ............................................................................... 25 HS ............................................................................... 25 INTOSC ...................................................................... 25 INTOSCIO................................................................... 25 LP................................................................................ 25 RC............................................................................... 25 RCIO ........................................................................... 25 XT ............................................................................... 25 Oscillator Parameters ....................................................... 151 Oscillator Specifications .................................................... 150 Oscillator Start-up Timer (OST) Specifications............................................................ 154 OSCTUNE Register ............................................................ 29 P P1A/P1B/P1C/P1D.See Enhanced Capture/ Compare/PWM (ECCP) .............................................. 91 Packaging ......................................................................... 163 Marking ..................................................................... 163 PDIP Details.............................................................. 164 PCL and PCLATH ............................................................... 22 Stack ........................................................................... 22 PCON Register ........................................................... 21, 111 PICSTART Plus Development Programmer ..................... 138 PIE1 Register ...................................................................... 19 Pin Diagram PDIP, SOIC, TSSOP................................................. 2, 3 QFN .......................................................................... 4, 5 Pinout Descriptions PIC16F610/16HV610.................................................... 9 PIC16F616/16HV616.................................................. 10 PIR1 Register...................................................................... 20 PORTA................................................................................ 31 Additional Pin Functions ............................................. 32 © 2007 Microchip Technology Inc. ANSEL Register ................................................. 32 Interrupt-on-Change ........................................... 32 Weak Pull-Ups.................................................... 32 Associated registers ................................................... 39 Pin Descriptions and Diagrams .................................. 34 RA0............................................................................. 34 RA1............................................................................. 34 RA2............................................................................. 35 RA3............................................................................. 36 RA4............................................................................. 37 RA5............................................................................. 38 Specifications ........................................................... 152 PORTA Register ................................................................. 31 PORTC ............................................................................... 40 Associated registers ................................................... 42 P1A/P1B/P1C/P1D.See Enhanced Capture/ Compare/PWM (ECCP)...................................... 40 Specifications ........................................................... 152 PORTC Register................................................................. 40 Power-Down Mode (Sleep)............................................... 121 Power-on Reset (POR)..................................................... 109 Power-up Timer (PWRT) .................................................. 109 Specifications ........................................................... 154 Precision Internal Oscillator Parameters .......................... 152 Prescaler Shared WDT/Timer0................................................... 44 Switching Prescaler Assignment ................................ 44 Program Memory ................................................................ 11 Map and Stack (PIC16F610/16HV610) ...................... 11 Map and Stack (PIC16F616/16HV616) ...................... 11 Programming, Device Instructions.................................... 125 PWM Mode. See Enhanced Capture/Compare/PWM ........ 91 PWM1CON Register......................................................... 103 R Reader Response............................................................. 176 Read-Modify-Write Operations ......................................... 125 Registers ADCON0 (ADC Control 0) .......................................... 76 ADCON1 (ADC Control 1) .......................................... 77 ADRESH (ADC Result High) with ADFM = 0) ............ 78 ADRESH (ADC Result High) with ADFM = 1) ............ 78 ADRESL (ADC Result Low) with ADFM = 0).............. 78 ADRESL (ADC Result Low) with ADFM = 1).............. 78 ANSEL (Analog Select) .............................................. 32 CCP1CON (Enhanced CCP1 Control) ....................... 83 CM1CON0 (C1 Control) ............................................. 60 CM2CON0 (C2 Control) ............................................. 61 CM2CON1 (C2 Control) ............................................. 63 CONFIG (Configuration Word) ................................. 107 Data Memory Map (PIC16F610/16HV610) ................ 13 Data Memory Map (PIC16F616/16HV616) ................ 13 ECCPAS (Enhanced CCP Auto-shutdown Control) . 100 INTCON (Interrupt Control) ........................................ 18 IOCA (Interrupt-on-Change PORTA).......................... 33 OPTION_REG (OPTION)..................................... 17, 45 OSCTUNE (Oscillator Tuning).................................... 29 PCON (Power Control Register)................................. 21 PCON (Power Control) ............................................. 111 PIE1 (Peripheral Interrupt Enable 1) .......................... 19 PIR1 (Peripheral Interrupt Register 1) ........................ 20 PORTA ....................................................................... 31 PORTC ....................................................................... 40 PWM1CON (Enhanced PWM Control) ..................... 103 Reset Values ............................................................ 113 Reset Values (special registers)............................... 114 Preliminary DS41288C-page 173 PIC16F610/616/16HV610/616 Special Function Registers ......................................... 12 Special Register Summary ......................................... 15 SRCON0 (SR Latch Control 0) ................................... 67 SRCON1 (SR Latch Control 1) ................................... 67 STATUS ...................................................................... 16 T1CON ........................................................................ 50 T2CON ........................................................................ 54 TRISA (Tri-State PORTA) ........................................... 31 TRISC (Tri-State PORTC) .......................................... 40 VRCON (Voltage Reference Control) ......................... 70 WPUA (Weak Pull Up PORTA)................................... 33 Reset................................................................................. 108 Revision History ................................................................ 169 S Shoot-through Current ...................................................... 102 Sleep Power-Down Mode ................................................... 121 Wake-up.................................................................... 121 Wake-up using Interrupts .......................................... 121 Software Simulator (MPLAB SIM)..................................... 136 Special Event Trigger.......................................................... 74 Special Function Registers ................................................. 12 SRCON0 Register............................................................... 67 SRCON1 Register............................................................... 67 STATUS Register................................................................ 16 T T1CON Register.................................................................. 50 T2CON Register.................................................................. 54 Thermal Considerations .................................................... 148 Time-out Sequence........................................................... 111 Timer0 ................................................................................. 43 Associated Registers .................................................. 45 External Clock ............................................................. 44 Interrupt....................................................................... 45 Operation .................................................................... 43 Specifications ............................................................ 155 T0CKI .......................................................................... 44 Timer1 ................................................................................. 47 Associated registers.................................................... 51 Asynchronous Counter Mode ..................................... 48 Reading and Writing ........................................... 48 Interrupt....................................................................... 49 Modes of Operation .................................................... 47 Operation .................................................................... 47 Operation During Sleep .............................................. 49 Oscillator ..................................................................... 48 Prescaler ..................................................................... 48 Specifications ............................................................ 155 Timer1 Gate Inverting Gate ..................................................... 48 Selecting Source........................................... 48, 63 SR Latch ............................................................. 66 Synchronizing COUT w/Timer1 .......................... 63 TMR1H Register ......................................................... 47 TMR1L Register .......................................................... 47 Timer2 Associated registers.................................................... 54 Timers Timer1 T1CON................................................................ 50 Timer2 T2CON................................................................ 54 Timing Diagrams A/D Conversion ......................................................... 160 DS41288C-page 174 A/D Conversion (Sleep Mode) .................................. 160 Brown-out Reset (BOR)............................................ 153 Brown-out Reset Situations ...................................... 110 CLKOUT and I/O ...................................................... 152 Clock Timing ............................................................. 150 Comparator Output ..................................................... 55 Enhanced Capture/Compare/PWM (ECCP)............. 156 Full-Bridge PWM Output............................................. 96 Half-Bridge PWM Output .................................... 94, 102 INT Pin Interrupt ....................................................... 117 PWM Auto-shutdown Auto-restart Enabled......................................... 101 Firmware Restart .............................................. 101 PWM Direction Change .............................................. 97 PWM Direction Change at Near 100% Duty Cycle..... 98 PWM Output (Active-High) ......................................... 92 PWM Output (Active-Low) .......................................... 93 Reset, WDT, OST and Power-up Timer ................... 153 Time-out Sequence Case 1 .............................................................. 112 Case 2 .............................................................. 112 Case 3 .............................................................. 112 Timer0 and Timer1 External Clock ........................... 155 Timer1 Incrementing Edge ......................................... 49 Wake-up from Interrupt............................................. 122 Timing Parameter Symbology .......................................... 149 TRISA ................................................................................. 31 TRISA Register................................................................... 31 TRISC ................................................................................. 40 TRISC Register................................................................... 40 V Voltage Reference (VR) Specifications ........................................................... 157 Voltage Reference. See Comparator Voltage Reference (CVREF) Voltage References Associated registers ................................................... 65 VP6 Stabilization ........................................................ 69 VREF. SEE ADC Reference Voltage W Wake-up Using Interrupts ................................................. 121 Watchdog Timer (WDT).................................................... 119 Associated registers ................................................. 120 Specifications ........................................................... 154 WPUA Register................................................................... 33 WWW Address ................................................................. 175 WWW, On-Line Support ....................................................... 6 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2007 Microchip Technology Inc. Preliminary DS41288C-page 175 PIC16F610/616/16HV610/616 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16F610/616/16HV610/616 Literature Number: DS41288C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41288C-page 176 Preliminary © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device: PIC16F610/616/16HV610/616, PIC16F610/616/16HV610/ 616T(1) Temperature Range: I E Package: ML P SL ST = -40°C to +85°C = -40°C to +125°C = = = = PIC16F610/616/16HV610/616-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 PIC16F610/616/16HV610/616-I/SL = Industrial Temp., SOIC package, 20 MHz (Industrial) (Extended) Quad Flat No Leads (QFN) Plastic DIP 14-lead Small Outline (3.90 mm) Thin Shrink Small Outline (4.4 mm) Note 1: Pattern: T = in tape and reel TSSOP and SOIC packages only. QTP, SQTP or ROM Code; Special Requirements (blank otherwise) © 2007 Microchip Technology Inc. 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