PMC PRELIMINARY Pm29F004 4 Megabit (512K X 8) 5.0 Volt-only CMOS Flash Memory FEATURES • Data# Polling and Toggle Bit Features • Single Power Supply Operation - 5.0 V ± 10% Read/Program/Erase • High Performance Read - 70/90 ns access time • Low Power Consumption - Typical 15 mA active read current - Typical 40 mA program/erase current - Typical 0.1 µA CMOS standby current • Memory Blocks Architecture - One 16 Kbytes top or bottom Boot Block with software lockout - Two 8 Kbytes Parameter Blocks - One 96 Kbytes Main Block - Three 128 Kbytes Main Blocks • High Product Endurance - Guarantee 10,000 program/erase cycles - Typical 50,000 program/erase cycles - Minimum 10 years data retention • Industrial Standard Pin-out and Packaging - 32-pin Plastic DIP - 32-pin PLCC • Automatic Block Erase and Byte Program - Typical 12 µs/byte programming - Typical 50 ms block or chip erase • Manufactured on 0.30 µm process • Hardware Data Protection GENERAL DESCRIPTION The Pm29F004 is a 4 Megabit, 5 Volt-only Flash Memory organized as 524,288 bytes of 8 bits each. This device is designed to use a 5.0 Volt power supply to perform in-system programming, 12.0 Volt VPP power supply for program and erase operation is not required. The device can be programmed in standard EPROM programmers as well. The 4 Megabit memory array is divided into seven blocks of one 16 Kbytes, two 8 Kbytes, one 96 Kbytes, and three 128 Kbytes for BIOS and parameters storage. The seven blocks allow users to flexibly make chip erase or block erase operation. The block erase feature allows a particular block to be erased and reprogrammed without affecting the data in other blocks. After the device performed chip erase or block erase operation, it can be reprogrammed on a byte-by-byte basis. The device has a standard microprocessor interface as well as JEDEC single-power-supply Flash compatible pin-out and command set. The program operation of Pm29F004 is executed by issuing the program command code into command register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase operation of Pm29F004 is executed by issuing the chip erase or block erase command code into command register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not been programmed is not required before the erase operation. The device also features Data# Polling and Toggle Bit function, the end of program or erase operation can be detected by Data# Polling of I/O7 or Toggle Bit of I/O6. The device has an optional 16 Kbytes top or bottom boot block with a software lockout feature for data security. The boot block can be used to store user secure code. When the lockout feature is enabled, the boot block is permanently protected from being reprogrammed. The Pm29F004 is manufactured on PMC’s advanced 0.30 µm, P-FLASH™, nonvolatile memory process. The device is packaged in a 32-pin DIP and PLCC with access time of 70 and 90 ns. Programmable Microelectronics Corp. 1 Issue Date: November, 2000 Rev:1. 0 Pm29F004 Preliminary PMC A16 A18 V CC WE# A17 3 2 1 32 31 30 A14 6 28 A13 A5 7 27 A8 A4 8 26 A9 A3 9 25 A11 A2 10 24 OE# A1 11 23 A10 A0 12 22 CE# I/O0 13 21 I/O7 14 15 16 17 18 19 20 I/O6 29 I/O5 32-Pin PDIP A6 4 I/O4 17 5 I/O3 12 13 14 15 16 A7 GND 7 8 9 10 11 V CC WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# I/O7 I/O6 I/O5 I/O4 I/O3 A15 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 I/O2 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 I/O1 A18 A16 A15 A12 A7 A6 A5 A4 A3 A12 CONNECTION DIAGRAMS 32-Pin PLCC LOGIC SYMBOL 19 A0-A18 8 I/O0-I/O7 CE# OE# WE# Programmable Microelectronics Corp. 2 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC PRODUCT ORDERING INFORMATION Pm29F004 T -70 P C Temperature Range C = Commercial (0°C to +70°C) Package Type P = 32-pin Plastic DIP (32P) J = 32-pin Plastic J-Leaded Chip Carrier (32J) Speed Option Boot Block Location T = Top Boot Block B = Bottom Boot Block PMC Device Number Part Number tACC (ns) B oot Location Pm29F004T-70JC P ackag e 32J Top Pm29F004T-70PC 32P 70 Pm29F004B-70JC 32J Bottom Pm29F004B-70PC Pm29F004T-90JC 32P 32P 90 Pm29F004B-90JC Programmable Microelectronics Corp. Commercial (0°C to +70°C) 32J Top Pm29F004T-90PC Pm29F004B-90PC Temperature R an g e 32J Bottom 3 Commercial (0°C to +70°C) 32P Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION INPUT Address Inputs: For memory addresses and command register. Addresses are internally latched during a write cycle. C E# INPUT Chip Enable: CE# low activates the device's internal circuitries for device operation. CE# high deselects the device and switches into standby mode to reduce the power consumption. Please refer to DC characteristics table. WE# INPUT Write Enable: Activate the device for write operation. WE# is active low. OE# INPUT Output Enable: Control the device's data buffers during a read cycle. OE# is active low. INPUT/ OUTPUT Data Inputs/Outputs: Inputs array data during program operation, when CE# and WE# are active. Data is internally latched during the write and program cycles. When CE# and OE# are active, the output sends array data, manufacturer code or device code. The data pins float to tri-state when the chip is deselected or the outputs are disabled. A 0 - A 18 I/O0 - I/O7 V CC Device Power Supply GND Ground NC No Connection Programmable Microelectronics Corp. 4 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC BLOCK DIAGRAM ERASE/PROGRAM VOLTAGE GENERATOR I/O0-I/O7 I/O BUFFERS HIGH VOLTAGE SWITCH WE# COMMAND REGISTER CE,OE LOGIC DATA LATCH SENSE AMP A0-A18 ADDRESS LATCH CE# OE# Y-DECODER X-DECODER MEMORY ARRAY BOOT BLOCK LOCKOUT DETECTION DEVICE OPERATION The state of the Boot Block lockout can be detected by software product identification entry. After entry, selects Boot Block address with A0 = “0” and A1 = “1” and then read I/O0. A data of “0” means the lockout feature is disabled and the Boot Block can be erased or programmed. A data of “1” means the lockout feature is enabled and the Boot Block is protected. Product identification exit must be executed before the device returns to read mode. READ OPERATION The access of Pm29F004 is similar as that of EPROM. To obtain data at the outputs, three control functions must be satisfied: • CE# is the chip enable and should be pulled low ( VIL ). • OE# is the output enable and should be pulled low ( VIL). • WE# is the write enable and should remains high ( VIH ). PRODUCT IDENTIFICATION The product identification mode can be used to identify the device and the manufacturer by hardware or software operation. The hardware operation mode is activated by applying a 12.0 Volt on A9 pin, typically used by an external programmer to select the right programming algorithm for the device. For detail, please see Bus Operation Modes in Table 3. The software operation mode is activated by three-bus-cycle command. Please see Software Command Definition in Table 4. BOOT BLOCK LOCKOUT The device has a software lockout feature to prevent the data in the boot block from being erased or reprogrammed. The boot block can be located at the top or bottom of the address location. The block size is 16 Kbytes. Once the lockout feature is enable, the boot block can not be erased or reprogrammed. Data in the main memory block can still be updated through the regular programming method. The boot block lockout feature can be turned on by issuing a six-bus-cycle command sequence. Please refer to Table 4 and Chart 4. Programmable Microelectronics Corp. Y-GATING 5 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC DEVICE OPERATION (CONTINUED) BYTE PROGRAMMING I/O7 DATA# POLLING The programming is a four-bus-cycle operation and the data is programmed into the device (to a logical “0”) on a byte-by-byte basis. Please see Software Command Definition in Table 4. A program operation is activated by writing the three-byte command sequence followed by one byte of data into the device. The address are latched on the falling edge of WE# or CE# whichever occurs later, and the data is latched on the rising edge of WE# or CE#, whichever occurs first. The internal control logic automatically handles the internal programming voltages and timing. A data “0” can not be programmed back to a “1”. Only erase operation can convert “0”s to “1”s. The Data# Polling of I/O7 or Toggle Bit of I/O6 can be used to detect when the programming operation is completed. The Pm29F004 provides Data# Polling feature to indicate the process or the completion of a program or erase cycle. During a program cycle, an attempt to read the device will result in the complement of the last loaded data on I/O7. Once the program cycle is completed, the true data of the last loaded data is valid on all outputs. During a block or chip erase operation, an attempt to read the device will result a “0” on I/O7. After the erase cycle is completed, an attempt to read the device will result a “1” on I/O7. I/O6 TOGGLE BIT The Pm29F004 also provides Toggle Bit feature as a method to detect the process or the end of a program or erase cycle. During a program or erase operation, an attempt to read data from the device will result in I/O6 toggling between “1” and “0”. When the program or erase operation is complete, I/O6 will stop toggling and valid data will be read. Toggle bit may be accessed at any time during a program or erase cycle. CHIP ERASE The entire memory array can be erased through a chip erase operation. Pre-programs the device is not required prior to chip erase operation. Chip erase starts after a six-bus-cycle chip erase command sequence. All commands will be ignored once the chip erase operation has started. The device will return back to read mode after the completion of chip erase. When the boot block lockout feature is enabled, the boot block will not be erased during a chip erase operation. Only the parameter blocks and the main blocks will be erased. HARDWARE DATA PROTECTION Hardware data protection protects the device from unintentional erase or program operation. It is performed in the following ways: (a) VCC sense: if VCC is below 3.8 V (typical), the program function is inhibited. (b) Write inhibit: holding any of the signal OE# low, CE# high or WE# high inhibits a write cycle. (c) Noise filter: pulses of less than 20 ns (typical) on the WE# or CE# inputs will not initiate a write cycle. BLOCK ERASE The memory array is organized into seven blocks: one 16 Kbytes boot block, two 8 Kbytes parameter blocks, one 96 Kbytes and three 128 Kbytes main blocks. A block erase operation allows to erase any individual block. Pre-programs the block is not required prior to block erase operation. If the boot block lockout feature is enable, the block erase command attempts to erase the boot block will be ignored. The block erase command is similar to chip erase command except for the last bus cycle command where the block addresses are used to select the block for erasure and the input data to the I/Os is 30h. Each block erase operation erases one block. Block erase and chip erase are both internally controlled and timed. Programmable Microelectronics Corp. 6 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC MEMORY BLOCKS AND ADDRESSES Table 1. Top Boot Block Address Table (Pm29F004T) Block Block Siz e Address Range Main Block 4 128 Kbytes 00000h-1FFFFh Main Block 3 128 Kbytes 20000h-3FFFFh Main Block 2 128 Kbytes 40000h-5FFFFh Main Block 1 96 Kbytes 60000h-77FFFh Parameter Block 2 8 Kbytes 78000h-79FFFh Parameter Block 1 8 Kbytes 7A000h-7BFFFh Boot Block 16 Kbytes 7C000h-7FFFFh Table 2. Bottom Boot Block Address Table ( Pm29F004B) Block Block Siz e Address Range Boot Block 16 Kbytes 00000h-03FFFh Parameter Block 1 8 Kbytes 04000h-05FFFh Parameter Block 2 8 Kbytes 06000h-07FFFh Main Block 1 96 Kbytes 08000h-1FFFFh Main Block 2 128 Kbytes 20000h-3FFFFh Main Block 3 128 Kbytes 40000h-5FFFFh Main Block 4 128 Kbytes 60000h-7FFFFh Programmable Microelectronics Corp. 7 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC OPERATING MODES Table 3. Bus Operation Modes Mode CE# OE# WE# Read VIL VIL VIH Write VIL VIH VIL X DIN Standby VIH X X X High Z Output Disable X VIH X X High Z Product Identification Hardware VIL VIL VIH ADDRESS X (1) I/O DOUT A2 - A18 = X, A9 = VH (2), A1 = VIL, A0 = VIL Manufacturer Code A2 - A18 = X, A9 = VH (2), A1 = VIL, A0 = VIH Device Code (3) (3) Notes: 1. X can be VIL, VIH or addresses. 2. VH = 12.0 V ± 0.5 V. 3. Manufacturer Code: 9Dh; Device Code: 1Eh (top boot), 2Eh (bottom boot) Programmable Microelectronics Corp. 8 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC COMMAND DEFINITION Table 4. Software Command Definition Command S eq u en ce B us Cycle 1st B u s Cycle Addr Data 2n d B u s Cycle Addr Data 3rd Bus Cycle Addr Data 4th Bus Cycle Addr Data 5th Bus Cylce Addr Data 6th Bus Cycle Addr Data Read 1 Addr DOUT Chip Erase 6 555h A A h 2A A h 55h 555h 80h 555h A A h 2A A h 55h 555h 10h Block Erase 6 555h A A h 2A A h 55h 555h 80h 555h A A h 2A A h 55h BA (1) 30h Byte Program 4 555h A A h 2A A h 55h 555h A 0h Addr DIN Boot Block Lockout (2,3) 6 555h A A h 2A A h 55h 555h 80h 555h A A h 2A A h 55h 555h 40h Boot Block Lockout Detection (3) 3 555h A A h 2A A h 55h 555h 90h Product Manufacturer ID 3 555h A A h 2A A h 55h 555h 90h X 00h 9D h Product Device ID (Top Boot) 3 555h A A h 2A A h 55h 555h 90h X 01h 1E h Product Device ID (Bottom Boot) 3 555h A A h 2A A h 55h 555h 90h X 01h 2E h Product ID Exit (6) 3 555h A A h 2A A h 55h 555h F 0h Product ID Exit (6) 1 X X X h F 0h BA (4) 00h (5) BA (4) 01h (5) Notes: 1. BA = Block address of the block to be erased. 2. When the boot block lockout feature is enabled, the boot block will not be erased when a chip erase command or a block erase command for boot block erasure is issued. Once the boot block is not protected, the boot block will be erased when a chip erase command or a block erase command for boot block erasure is issued. 3. After completion of the boot block lockout enable or detection command, the Product ID Exit command must be issued to return to standard read mode. 4. BA = Block address of the boot block; For top boot block location, A0 = “0”, A1 = “1”, and A14-A18 = “1” where A2-A13 = Don’t Care; For bottom boot block location, A0 = “0”, A1 = “1”, and A14-A18 = “0” where A2-A13 = Don’t Care. 5. I/O0 = “1” means boot block lockout is enabled, I/O0 = “0” means boot block lockout is disabled. 6. Either one of the Product ID Exit command can be used. Programmable Microelectronics Corp. 9 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC DEVICE OPERATIONS FLOWCHARTS AUTOMATIC PROGRAMMING Start Load Data AAh to Address 555H Load Data 55h to Address 2AAh Load Data A0h to Address 555h Address Increment Load Program Data to Program Address I/O7 = Data? or I/O6 Stop Toggle? No Yes Last Address? No Yes Programming Completed Chart 1. Automatic Programming Flowchart Programmable Microelectronics Corp. 10 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC DEVICE OPERATIONS FLOWCHARTS (CONTINUED) AUTOMATIC ERASE Start Write Chip or Block Erase Command No Data = FFh? or I/O6 Stop Toggle? Yes Erasure Completed CHIP ERASE COMMAND BLOCK ERASE COMMAND Load Data AAh to Address 555h Load Data AAh to Address 555h Load Data 55h to Address 2AAh Load Data 55h to Address 2AAh Load Data 80h to Address 555h Load Data 80h to Address 555h Load Data AAh to Address 555h Load Data AAh to Address 555h Notes: 1. Please see Software Command Definition in Table 1 and Table 2 for block addresses. Load Data 55h to Address 2AAh Load Data 55h to Address 2AAh 2. Only erase one block per each block erase cycle. Load Data 10h to Address 555h (3) Load Data 30h to Block Address (1,2,3) 3. When the boot block lockout feature has been enabled, the boot block will not be erased. Chart 2. Automatic Erase Flowchart Programmable Microelectronics Corp. 11 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC DEVICE OPERATIONS FLOWCHARTS (CONTINUED) SOFTWARE PRODUCT IDENTIFICATION ENTRY SOFTWARE PRODUCT IDENTIFICATION EXIT Load Data AAh to Address 555h Load Data AAh to Address 555h Load Data 55h to Address 2AAh Load Data 55h to Address 2AAh Load Data 90h to Address 555h Load Data F0h to Address 555h Enter Product Identification Mode (1,2) Exit Product Identification Mode (3) Load Data F0h to Address XXXh or Exit Product Identification Mode (3) Notes: 1. Manufacturer Code is read when A0-A18 = XX00h, where X = Don’t Care; Device Code is read when A0-A18 = XX01h. 2. Manufacturer Code = 9Dh; Device Code = 1Eh (top boot device); Device Code = 2Eh (bottom boot device). 3. The device returns to standard read operation. Chart 3. Software Product Identification Entry/Exit Flowchart Programmable Microelectronics Corp. 12 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC DEVICE OPERATIONS FLOWCHARTS (CONTINUED) BOOT BLOCK LOCKOUT ENABLE (1,2) Load Data AAh to Address 555h Load Data 55h to Address 2AAh Notes: 1. Please call manufacturer for the command code to disable the boot block lockout. 2. After excuting the boot block lockout command, the Product ID Exit command must be issued to return to standard read mode. Load Data 80h to Address 555h Load Data AAh to Address 555h Load Data 55h to Address 2AAh Load Data 40h to Address 555h Pause 500 ms Boot Block Lockout Enabled Chart 4. Boot Block Lockout Enable Flowchart Programmable Microelectronics Corp. 13 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC ABSOLUTE MAXIMUM RATINGS (1) Temperature Under Bias -65OC to +125OC Storage Temperature -65OC to +125OC Input Voltage with Respect to Ground on All Pins except A9 pin (2) -0.5 V to +6.25 V Input Voltage with Respect to Ground on A9 pin (3) -0.5 V to +13.0 V All Output Voltage with Respect to Ground -0.5 V to VCC + 0.6 V VCC (2) -0.5 V to +6.25 V Notes: 1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. The functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. Maximum DC voltage on input or I/O pins are +6.25 V. During voltage transitioning period, input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns. Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period, input or I/O pins may undershoot GND to -2.0 V for a period of time up to 20 ns. 3. Maximum DC voltage on A9 pin is +13.0 V. During voltage transitioning period, A9 pin may overshoot to +14.0 V for a period of time up to 20 ns. Minimum DC voltage on A9 pin is -0.5 V. During voltage transitioning period, A9 pin may undershoot GND to -2.0 V for a period of time up to 20 ns. DC AND AC OPERATING RANGE Part Number Pm29F004 Operating Temperature 0oC to 70oC Vcc Power Supply 4.5 V - 5.5 V Programmable Microelectronics Corp. 14 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC DC CHARACTERISTICS Symbol Parameter Condition Min Typ Max Units ILI Input Load Current VIN = 0 V to VCC, VCC = VCC max 1 µA ILO Output Leakage Current VI/O = 0 V to VCC, VCC = VCC max 1 µA ISB1 VCC Standby Current CMOS CE#, OE# = VCC ± 0.5 V 0.1 5 µA ISB2 VCC Standby Current TTL CE# = VIH to VCC 0.2 3 mA ICC1 VCC Active Read Current 15 30 mA ICC2 (1) VCC Program/Erase Current 40 60 mA VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V VOL Output Low Voltage IOL = 12 mA, VCC = VCC min 0.45 V VOH Output High Voltage IOH = −2.5 mA, VCC = VCC min f = 5 MHz; IOUT = 0 mA 2.4 V Note: 1. Characterized but not 100% tested. AC CHARACTERISTICS READ OPERATIONS CHARACTERISTICS Pm29F004-70 Symbol Pm29F004-90 Parameter Units Min Max 70 Min Max tRC Read Cycle Time 90 tACC Address to Output Delay 70 90 ns tCE CE# to Output Delay 70 90 ns tOE OE# to Output Delay 35 40 ns tDF CE# or OE# to Output High Z 0 30 ns tOH Output Hold from OE#, CE# or Address, whichever occured first 0 0 ns tVCS VCC Set-up Time 50 50 µs Programmable Microelectronics Corp. 15 25 0 ns Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC AC CHARACTERISTICS (CONTINUED) READ OPERATIONS AC WAVEFORMS tR C ADDRESS ADDRESS VALID tA C C tC E CE# tO E OE# tD F WE# tO H HIGH Z OUTPUT OUTPUT VALID tV C S V CC OUTPUT TEST LOAD INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL 5.0 V 1.8 K 3.0 V OUTPUT PIN Input 1.5 V AC Measurement Level 0.0 V 1.3 K 100 pF PIN CAPACITANCE ( f = 1 MHz, T = 25°C ) Typ Max Units Conditions CIN 4 6 pF VIN = 0 V C OUT 8 12 pF VOUT = 0 V Note: These parameters are characterized and are not 100% tested. Programmable Microelectronics Corp. 16 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC AC CHARACTERISTICS (CONTINUED) WRITE (PROGRAM/ERASE) OPERATIONS CHARACTERISTICS Pm29F004-70 Symbol Pm29F004-90 Parameter U nits Min Max Min Max tWC Wri te C ycle Ti me 70 90 ns tAS Address Set-up Ti me 0 0 ns tAH Address Hold Ti me 45 50 ns tCS C E# Set-up Ti me 0 0 ns tCH C E# Hold Ti me 0 0 ns tWS WE# Set-up Ti me 0 0 ns tWH WE# Hold Ti me 0 0 ns tDS D ata Set-up Ti me 30 45 ns tDH D ata Hold Ti me 0 0 ns tWP Wri te Pulse Wi dth 35 45 ns tWPH Wri te Pulse Wi dth Hi gh 20 20 ns tBP Byte Programmi ng Ti me 50 50 µs tEC C hi p or Block Erase C ycle Ti me 100 100 ms tVCS VCC Set-up Ti me 50 50 µs PROGRAM OPERATIONS AC WAVEFORMS - WE# CONTROLLED Program Cycle OE# tC H tV C S CE# tC S tB P tW P H tW P WE# tA H tA S A0 - A17 555 2AA 555 tW C tD H tD S DATA IN AA ADDRESS 55 A0 INPUT DATA VALID DATA V CC Programmable Microelectronics Corp. 17 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC AC CHARACTERISTICS (CONTINUED) PROGRAM OPERATIONS AC WAVEFORMS - CE# CONTROLLED Program Cycle OE# tW H tV C S WE# tW S tB P tW P H tW P CE# tA H tA S A0 - A17 555 2AA 555 tW C tD H tD S DATA IN ADDRESS AA 55 A0 INPUT DATA VALID DATA V CC CHIP ERASE OPERATIONS AC WAVEFORMS OE# tV C S CE# tW P tW P H WE# tA S AO - A17 tA H 555 tW C DATA IN AA tD H 2AA 555 555 2AA 555 tE C tD S 55 80 AA 55 10 V CC Programmable Microelectronics Corp. 18 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC AC CHARACTERISTICS (CONTINUED) BLOCK ERASE OPERATIONS AC WAVEFORMS OE# tV C S CE# tW P tW P H WE# tA S AO - A17 tD H tA H 555 tW C DATA IN 2AA 555 555 2AA BLOCK ADDRESS tE C tD S AA 55 80 AA 55 30 V CC PROGRAM/ERASE PERFORMANCE Parameter Unit Min Typ Max Remarks Block Erase Time ms 50 100 From writing erase command to erase completion Chip Erase Time ms 50 100 From writing erase command to erase completion Byte Programming Time µs 12 50 Excludes the time of four-cycle program command execution Program/Erase Endurance Cycles 10,000 50,000 Note: These parameters are characterized and are not 100% tested. Programmable Microelectronics Corp. 19 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC AC CHARACTERISTICS (CONTINUED) TOGGLE BIT AC WAVEFORMS WE# tO E H CE# OE# tD F tO E I/O6 Note: DATA tO H TOGGLE TOGGLE STOP TOGGLING VALID DATA Toggling either CE#, OE# or both OE# and CE# will operate Toggle Bit. DATA# POLLING AC WAVEFORMS WE# tC H tC E CE# tO E H OE# tO E tD F I/O7 I/O7# VALID DATA tO H Note: Toggling either CE#, OE# or both OE# and CE# will operate Data# Polling. Programmable Microelectronics Corp. 20 Issue Date: November, 2000 Rev: 1.0 Pm29F004 Preliminary PMC PACKAGE TYPE INFORMATION 32P 32-Pin Plastic DIP Dimensions in Inches (Millimeters) 1.640(41.7) 1.680(42.7) 32 .600(15.24) .625(15.88) 17 .008(0.20) .013(0.33) .537(13.64) .557(14.05) .625(15.88) .665(16.89) Pin 1 I.D. 16 0° 10° .005(.127) MIN .040(1.02) .065(1.65) .146(3.71) .162(4.11) SEATING PLANE .120(3.05) .160(4.07) .090(2.29) .110(2.79) .014(.36) .022(.56) .015(.38) MIN 32J 32-Pin Plastic Leaded Chip Carrier Dimensions in Inches (Millimeters) .485(12.32) .495(12.51) .447(11.35) .453(11.51) .009 .015 025(.635)X30° .585(14.86) .595(15.11) .123(3.12) .140(3.56) .076(1.93) .095(2.41) Pin 1 I.D. .547(13.89) .553(14.05) SEATING PLANE .400 REF. .510(12.95) .530(13.46) .013(.33) .021(.53) .050 REF. .026(.66) .032(.81) TOP VIEW Programmable Microelectronics Corp. SIDE VIEW 21 Issue Date: November, 2000 Rev: 1.0