QS532807 3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE QS532807 GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER FEATURES: DESCRIPTION: − − − − − − − The QS532807 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter. The QS532807 offers ten non-inverting outputs. Designed in IDT's proprietary QCMOS process, these devices provide low propagation delay buffering with onchip skew of 0.35ns for same-transition, same bank signals. The QS532807 has on-chip series termination resistors for lower noise clock signals. The QS532807 series resistor version is recommended for driving unterminated lines with capacitive loading and other noise sensitive clock distribution circuits. These clock buffer products are designed for use in high-performance workstations, embedded and personal computing systems. Several devices can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. − JEDEC compatible LVTTL level 10 low skew clock outputs Clock input is 5V tolerant Pinout and function compatible with QS5807 25Ω on-chip resistors available for low noise Input hysteresis for better noise margin Guaranteed low skew: • 0.35ns output skew (same bank) • 0.6ns output skew (different bank) • 0.75ns part-to-part skew Available in QSOP and SOIC packages FUNCTIONAL BLOCK DIAGRAM O1 O2 O3 O4 O5 IN O6 O7 O8 O9 O 10 INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2000 1 c 1999 Integrated Device Technology, Inc. DSC - 5848 QS532807 3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Symbol VTERM(2) (1) Description Supply Voltage to Ground Max. – 0.5 to +4.6 Unit V DC Output Voltage VOUT – 0.5 to VCC+0.5 V IN 1 20 VCC G ND 2 19 O 10 VTERM(3) DC Input Voltage VIN – 0.5 to +7 V O1 3 18 O9 VAC AC Input Voltage (pulse width ≤20ns) -3 V V CC 4 17 G ND IOUT DC Output Current VIN < 0 -20 mA O2 5 O8 G ND 6 SO 20-2 16 SO 20-8 15 O3 7 14 O7 V CC 8 13 G ND O4 9 12 O6 G ND 10 11 O5 DC Output Current Max. Sink Current/Pin VCC 120 mA TSTG Storage Temperature – 65 to +150 °C TJ Junction Temperature 150 °C NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc Terminals. 3. All terminals except Vcc. QSOP/ SOIC TOP VIEW CAPACITANCE (TA = +25OC, f = 1.0MHz, VIN = 0V) QSOP Pins CIN SOIC Max. (1) Typ. 3 6 Max. (1) 7 Typ. 5 NOTE: 1. This parameter is guaranteed but not production tested. PIN DESCRIPTION 2 Pin Names IN I/O I Clock Input Description Ox O Clock Outputs Unit pF QS532807 3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40°C to +85°C, VCC = 3.3V ± 0.3V Symbol VIH Parameter Input HIGH Voltage VIL VIC VOH Typ.(1) 1.7 Test Conditions Guaranteed Logic HIGH for All Inputs Min. 2 Max. 5.5 Input LOW Voltage Guaranteed Logic LOW for All Inputs –0.5 — 0.8 V Clamp Diode Voltage (3) Vcc = Min., IIN = -18mA — –0.7 –1.2 V Output HIGH Voltage Vcc = Min., IOH = -100µA Vcc - 0.2 — — V Vcc = Min., IOH = -8mA 2.4 — — Vcc = Min., IOL = 100µA — — 0.2 Vcc = Min., IOL = 6mA — — 0.4 Unit V VOL Output LOW Voltage Vcc = Min., IOL = 8mA — — 0.5 IIN Input Leakage Current Vcc = Max., VIN = VCC or GND — — ±1 µA IOFF Input Power Off Leakage Vcc = 0V, VIN = VCC or GND — — ±1 µA –60 –50 –195 –80 — mA IOS Short Circuit Current (2,3) Vcc = Max., VOUT = GND V IODH Output HIGH Current Vcc = 3.3V, –200 mA IODL Output LOW Current Vcc = 3.3V, VIN = VIH or VIL, VO = 1.5V 50 112 200 mA ∆VT Input Hysteresis VTLH - VTHL for All Inputs — 0.2 — V Vcc = Min., IOL = 12mA — 28 — Ω ROUT Output Resistance (4) VIN = VIH or VIL, VO = 1.5V NOTES: 1. Typical values are at VCC = 3.3V, TA = 25°C. 2. Not more than one output should be used to test this high power condition. Duration is less than one second. 3. Guaranteed by design but not tested. 4. Output resistance represents the total output impedance of the logic device and includes added series termination resistance. POWER SUPPLY CHARACTERISTICS Symbol ICC Parameter Quiescent Power Supply Current Test Conditions VCC = Max., VIN = GND or Vcc ∆ICC Supply Current per Input HIGH ICCD Dynamic Power Supply Current per Output (1) VCC = Max., VIN = 3V Input toggling at 50% duty cycle VCC = Max., outputs Enabled IC Total Power Supply Current Examples (1,3) VCC = Max., Input at 50% duty cycle fI = 10MHz VCC = Max., Input at 50% duty cycle fI = 2.5MHz NOTES: 1. Guaranteed by design but not tested. CL = 0pF. 2. Typical values are for reference only. Conditions are VCC = 3.3V, TA = 25°C. 3. IC = ICC + (∆ICC)(DH)(NT) + ICCD (fO)(NO) where: DH = Input Duty Cycle NT = Number of TTL HIGH inputs at DH (one) fO = Output Frequency NO = Number of outputs at fO (ten) 3 Typ. (2) 0.01 Max. 100 Unit µA 0.1 30 µA 60 90 µA/MHz VIN = GND or Vcc 6 10 mA VIN = GND or Vcc 1.5 3 QS532807 3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE TA = -40°C to +85°C, VCC = 3.3V ± 0.3V CLOAD = 50pF (no resistor) Symbol tSK(01) Parameter (1) Skew between all outputs, same transition Min. Max. Unit — ns tSK(P) Pulse Skew; skew between opposite transitions of the same output (tPHL - tPLH) — 0.5 0.5 tSK(T) tPLH tPHL tR tF Part-to-part skew (2) — 1 ns 1.5 5.2 ns — — 2 2 ns Propagation Delay (3) IN to Ox Output Rise Time, 0.8V to 2V Output Fall Time, 2V to 0.8V ns ns NOTES: 1. Skew parameters are guaranteed across temperature range, but not tested. 2. tSK(T) only applies to devices of the same transition, part type, temperature, power supply voltage, loading, and package. 3. The propagation delay range indicated by Min. and Max. specifications results from process and environmental variables. These propagation delays do not imply limit skew. 4 QS532807 3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS V CC V IN V O UT Pulse Generator DU T 50pF 50 Ω Pulse generator for all puls es: f ≤ 1.0M Hz; t F ≤ 2.5ns; tR ≤ 2.5ns PULSE SKEW — tSK(P) PROPAGATION DELAY 3V 3V 1.5V INPUT INPU T 1.5V 0V tP LH 0V t PH L tP H L t P LH VOH VOH OUTPUT 2V OUTPUT 1.5V 1.5V 0.8V VOL tR VOL tSK(p) = t PHL - t PLHL tF OUTPUT SKEW — tSK(O1) PART-TO-PART SKEW — tSK(T) 3V 3V 1.5V INPUT 1.5V INPU T 0V tP HL1 tP LH 1 0V t P HL1 tP LH 1 VOH VOH PART 1 O UTPUT 1.5V 1.5V OUTPUT 1 VOL VOL tSK (01) tSK(t) tSK(t) VOH t SK(0 1) VOH OUTPUT 2 PART 2 O UTPUT 1.5V 1.5V VOL tP LH 2 VOL tP LH 2 tP HL2 tP HL2 t SK(01) = t PLH2 - t PLH1 or t PHL 2 - t PHL1 t SK(t) = t PLH2 - t PLH1 or t PHL 2 - t PHL1 5 QS532807 3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION QS XXXX Device Type X Package SO Q Small Outline IC (300 mil) (SO20-2) Quarter-size Small Outline Package (SO20-8) 532807 Guaranteed Low Skew CMOS Clock Driver/Buffer CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. 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