SPANSION S71GS256NB0BFWAK0

S71GS256/128N based MCPs
Stacked Multi-Chip Product (MCP)
256/128 Megabit (16/8M x 16-bit) CMOS 3.0 Volt VCC and
1.8 V VIO MirrorBitTM Uniform Sector Page-mode Flash
Memory with 64/32 Megabit (4/2M x 16-bit) 1.8V pSRAM
Data Sheet
ADVANCE
INFORMATION
Distinctive Characteristics
MCP Features
■ Power supply voltage
High Performance
■ 110 ns access time
■ 30 ns page read times
■ Packages:
— Flash Memory
VCC: 2.7V to 3.1V
VIO: 1.65V to 1.95V
— 8.0x11.6x1.2 mm FBGA (TLA084)
— pSRAM
VCC: 1.7 V to 1.95 V
■ Operating Temperature
— -25°C to +85°C (Wireless)
General Description
The S71GS Series is a product line of stacked Multi-chip Product (MCP) packages
and consists of
■ One S29GL Flash memory die with 1.8 V VIO
■ one 1.8 V pSRAM (Note)
Note: Burst mode features of the pSRAM in the S71GS family of MCPs is not available. This MCP uses the page mode operation which utilizes the page mode Flash
and page mode feature-set of the pSRAM.
Publication Number S71GS256/128N_00
Revision A
Amendment 0
Issue Date December 17, 2004
This document contains information on a product under development at Spansion, LLC. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e
I n f o r m a t i o n
Product Selector Guide
Part Number
Speed/Voltage Option
Full Voltage Range
VCC = 2.7 V to 3.1 V (Flash)
VIO = 1.65 V to 1.95 V (Flash)
VCC = 1.7 V to 1.95 V (pSRAM)
S71GS256NC0
Flash
pSRAM
Max. Access Time (ns)
110
70
Max. CE# Access Time (ns)
110
70
Max. Page Access Time (tpacc)
30
25
Max. OE# Access Time (ns)
30
25
Part Number
Speed/Voltage Option
2
Full Voltage Range
VCC = 2.7 V to 3.1 V (Flash)
VIO = 1.65 V to 1.95 V (Flash)
VCC = 1.7 V to 1.95 V (pSRAM)
S71GS128NB0
Flash
pSRAM
Max. Access Time (ns)
110
70
Max. CE# Access Time (ns)
110
70
Max. Page Access Time (tpacc)
30
25
Max. OE# Access Time (ns)
30
25
S71GS256/128N based MCPs
S71GS256/128N_00_A0 December 17, 2004
A d v a n c e
I n f o r m a t i o n
S71GS256/128N based MCPs
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 2
MCP Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 9
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 11
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 13
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 15
S29GLxxxN MirrorBit
TM
Flash Family
General Description . . . . . . . . . . . . . . . . . . . . . . . 17
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 19
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
S29GL512N ....................................................................................................... 22
S29GL256N ...................................................................................................... 22
S29GL128N ...................................................................................................... 22
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 23
Table 1. Device Bus Operations ........................................... 23
VersatileIOTM (VIO) Control .............................................................................23
Requirements for Reading Array Data .........................................................23
Page Mode Read ............................................................................................. 24
Writing Commands/Command Sequences ................................................ 24
Write Buffer .................................................................................................... 24
Accelerated Program Operation .............................................................. 24
Autoselect Functions .....................................................................................25
Standby Mode .......................................................................................................25
Automatic Sleep Mode ......................................................................................25
RESET#: Hardware Reset Pin .........................................................................25
Output Disable Mode ....................................................................................... 26
Table 2. Sector Address Table–S29GL512N ........................... 26
Table 3. Sector Address Table–S29GL256N ........................... 41
Table 4. Sector Address Table–S29GL128N ........................... 48
Autoselect Mode .................................................................................................52
Low VCC Write Inhibit ................................................................................61
Write Pulse “Glitch” Protection ................................................................ 61
Logical Inhibit .................................................................................................... 61
Power-Up Write Inhibit ................................................................................61
Common Flash Memory Interface (CFI) . . . . . . . 61
Table 8. CFI Query Identification String ................................
Table 9. System Interface String..........................................
Table 10. Device Geometry Definition ...................................
Table 11. Primary Vendor-Specific Extended Query ................
62
63
64
65
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 65
Reading Array Data ...........................................................................................66
Reset Command .................................................................................................66
Autoselect Command Sequence ................................................................... 66
Enter Secured Silicon Sector/Exit Secured Silicon
Sector Command Sequence ............................................................................ 67
Word Program Command Sequence .......................................................... 67
Unlock Bypass Command Sequence ........................................................68
Write Buffer Programming .........................................................................68
Accelerated Program ....................................................................................69
Figure 1. Write Buffer Programming Operation....................... 70
Figure 2. Program Operation ............................................... 71
Program Suspend/Program Resume Command Sequence ..................... 71
Figure 3. Program Suspend/Program Resume ........................ 72
Chip Erase Command Sequence ................................................................... 72
Sector Erase Command Sequence .................................................................73
Figure 4. Erase Operation ................................................... 74
Erase Suspend/Erase Resume Commands .................................................. 74
Lock Register Command Set Definitions .................................................... 75
Password Protection Command Set Definitions ...................................... 75
Non-Volatile Sector Protection Command Set Definitions .................. 77
Global Volatile Sector Protection Freeze Command Set ...................... 77
Volatile Sector Protection Command Set .................................................. 78
Secured Silicon Sector Entry Command ..................................................... 79
Secured Silicon Sector Exit Command ........................................................ 79
Command Definitions ....................................................................................... 80
Table 12. S29GL512N, S29GL256N, S29GL128N Command
Definitions, x16 .................................................................80
Write Operation Status ................................................................................... 83
DQ7: Data# Polling ........................................................................................... 83
Table 5. Autoselect Codes, (High Voltage Method) ................ 53
Figure 5. Data# Polling Algorithm ........................................ 84
Sector Protection ................................................................................................53
Persistent Sector Protection .......................................................................53
Password Sector Protection ........................................................................53
WP# Hardware Protection .........................................................................53
Selecting a Sector Protection Mode .........................................................53
Advanced Sector Protection ...........................................................................54
Lock Register ........................................................................................................54
RY/BY#: Ready/Busy# .......................................................................................84
DQ6: Toggle Bit I ............................................................................................... 85
Table 6. Lock Register ........................................................ 55
Persistent Sector Protection ...........................................................................55
Dynamic Protection Bit (DYB) ...................................................................55
Persistent Protection Bit (PPB) ..................................................................56
Persistent Protection Bit Lock (PPB Lock Bit) ......................................56
Table 7. Sector Protection Schemes ..................................... 57
Persistent Protection Mode Lock Bit ...........................................................57
Password Sector Protection ........................................................................... 58
Password and Password Protection Mode Lock Bit ............................... 58
64-bit Password ...................................................................................................59
Persistent Protection Bit Lock (PPB Lock Bit) ...........................................59
Secured Silicon Sector Flash Memory Region ............................................59
Write Protect (WP#) ........................................................................................ 61
Hardware Data Protection .............................................................................. 61
December 17, 2004 S71GS256/128N_00_A0
Figure 6. Toggle Bit Algorithm ............................................. 86
DQ2: Toggle Bit II ..............................................................................................86
Reading Toggle Bits DQ6/DQ2 ..................................................................... 87
DQ5: Exceeded Timing Limits ........................................................................ 87
DQ3: Sector Erase Timer ................................................................................ 87
DQ1: Write-to-Buffer Abort ...........................................................................88
Table 13. Write Operation Status .........................................88
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 89
Figure 7. .......................................................................... 89
Figure 8. Maximum Positive
Overshoot Waveform.......................................................... 89
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 89
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 90
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Figure 9. Test Setup........................................................... 91
Table 14. Test Specifications ...............................................91
Key to Switching Waveforms . . . . . . . . . . . . . . . . 91
Figure 10. Input Waveforms and Measurement Levels ............ 91
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 92
3
A d v a n c e
Read-Only Operations–S29GL128N, S29GL256N, S29GL512N .......... 92
Figure 11. Read Operation Timings....................................... 93
Figure 12. Page Read Timings.............................................. 93
Hardware Reset (RESET#) .............................................................................. 94
Figure 13. Reset Timings..................................................... 94
Erase and Program Operations–S29GL128N,
S29GL256N, S29GL512N ...................................................................................95
Figure 14. Program Operation Timings .................................. 96
Figure 15. Accelerated Program Timing Diagram .................... 96
Figure 16. Chip/Sector Erase Operation Timings..................... 97
Figure 17. Data# Polling Timings
(During Embedded Algorithms) ............................................ 98
Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 99
Figure 19. DQ2 vs. DQ6 ...................................................... 99
Alternate CE# Controlled Erase and Program OperationsS29GL128N, S29GL256N, S29GL512N ........................................................100
Figure 20. Alternate CE# Controlled Write (Erase/
Program) Operation Timings.............................................. 101
Erase And Programming Performance . . . . . . 102
TSOP Pin and BGA Package Capacitance . . . . 102
CellularRAM Type 2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
General Description . . . . . . . . . . . . . . . . . . . . . . 103
Figure 21. Functional Block Diagram................................... 104
Table 15. Signal Descriptions .............................................105
Table 16. Bus Operations—Asynchronous Mode ....................106
Table 17. Bus Operations—Burst Mode ................................107
Functional Description . . . . . . . . . . . . . . . . . . . . 107
Power-Up Initialization .................................................................................... 107
Figure 22. Power-Up Initialization Timing............................. 108
Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . 108
Asynchronous Mode ........................................................................................108
Figure 23. READ Operation (ADV# LOW)............................. 108
Figure 24. WRITE Operation (ADV# LOW) ........................... 109
Page Mode READ Operation ........................................................................109
Figure 25. Page Mode READ Operation (ADV# LOW)............. 110
Burst Mode Operation .....................................................................................110
Figure 26. Burst Mode READ (4-word burst) ........................ 111
Figure 27. Burst Mode WRITE (4-word burst)....................... 111
Mixed-Mode Operation ................................................................................... 112
WAIT Operation ............................................................................................... 112
Figure 28. Wired or WAIT Configuration .............................. 112
LB#/UB# Operation .......................................................................................... 113
Figure 29. Refresh Collision During READ Operation.............. 113
Figure 30. Refresh Collision During WRITE Operation ............ 114
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . 114
Standby Mode Operation ................................................................................ 114
Temperature Compensated Refresh ........................................................... 114
Partial Array Refresh ........................................................................................ 115
Deep Power-Down Operation ...................................................................... 115
Configuration Registers . . . . . . . . . . . . . . . . . . . . 115
Access Using CRE .............................................................................................. 115
Figure 31. Configuration Register WRITE, Asynchronous Mode Followed by READ ................................................................ 116
Figure 32. Configuration Register WRITE, Synchronous Mode Followed by READ0............................................................... 117
Bus Configuration Register ............................................................................. 117
Table 18. Bus Configuration Register Definition ....................118
Table 19. Sequence and Burst Length .................................119
Burst Length (BCR[2:0]): Default = Continuous Burst ...................... 119
Burst Wrap (BCR[3]): Default = No Wrap .......................................... 119
4
I n f o r m a t i o n
Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive
Strength ............................................................................................................120
Table 20. Output Impedance ............................................. 120
WAIT Configuration (BCR[8]): Default = WAIT Transitions One
Clock Before Data Valid/Invalid ...............................................................120
WAIT Polarity (BCR[10]): Default = WAIT Active HIGH ...............120
Figure 33. WAIT Configuration (BCR[8] = 0) ....................... 120
Figure 34. WAIT Configuration (BCR[8] = 1) ....................... 121
Figure 35. WAIT Configuration During Burst Operation.......... 121
Latency Counter (BCR[13:11]): Default = Three-Clock Latency ......121
Table 21. Variable Latency Configuration Codes ................... 121
Figure 36. Latency Counter (Variable Initial Latency, No Refresh
Collision) ........................................................................ 122
Operating Mode (BCR[15]): Default = Asynchronous Operation .122
Refresh Configuration Register .....................................................................122
Table 22. Refresh Configuration Register Mapping ................ 123
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh .... 123
Table 23. 128Mb Address Patterns for PAR (RCR[4] = 1) ....... 123
Table 24. 64Mb Address Patterns for PAR (RCR[4] = 1) ........ 124
Table 25. 32Mb Address Patterns for PAR (RCR[4] = 1) ........ 124
Deep Power-Down (RCR[4]): Default = DPD Disabled ..................124
Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC Operation ..............................................................................................................124
Page Mode Operation (RCR[7]): Default = Disabled ........................124
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 125
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 126
Table 26. Electrical Characteristics and Operating Conditions . 126
Table 27. Temperature Compensated Refresh Specifications and
Conditions ....................................................................... 127
Table 28. Partial Array Refresh Specifications and Conditions . 127
Table 29. Deep Power-Down Specifications .......................... 127
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 37. AC Input/Output Reference Waveform................. 128
Figure 38. Output Load Circuit ........................................... 128
Table 30. Output Load Circuit ............................................ 128
Table 31. Asynchronous READ Cycle Timing Requirements .... 129
Table 32. Burst READ Cycle Timing Requirements ................ 130
Table 33. Asynchronous WRITE Cycle Timing Requirements ... 131
Table 34. Burst WRITE Cycle Timing Requirements ............... 131
Timing Diagrams ................................................................................................ 132
Figure 39. Initialization Period ........................................... 132
Table 35. Initialization Timing Parameters ........................... 132
Figure 40. Asynchronous READ.......................................... 133
Table 36. Asynchronous READ Timing Parameters ................ 133
Figure 41. Asynchronous READ Using ADV# ........................ 135
Table 37. Asynchronous READ Timing Parameters Using ADV# 135
Figure 42. Page Mode READ .............................................. 137
Table 38. Asynchronous READ Timing Parameters—Page Mode
Operation ....................................................................... 137
Figure 43. Single-Access Burst READ Operation—Variable
Latency .......................................................................... 139
Table 39. Burst READ Timing Parameters—Single Access, Variable
Latency .......................................................................... 139
Figure 44. Four-word Burst READ Operation—Variable Latency 141
Table 40. Burst READ Timing Parameters—4-word Burst ....... 142
Figure 45. Four-word Burst READ Operation (with LB#/UB#). 143
Table 41. Burst READ Timing Parameters—4-word Burst with LB#/
UB# ............................................................................... 144
Figure 46. READ Burst Suspend ......................................... 145
Table 42. Burst READ Timing Parameters—Burst Suspend ..... 145
Figure 47. Continuous Burst READ Showing an Output Delay with
BCR[8] = 0 for End-of-Row Condition ................................. 146
Table 43. Burst READ Timing Parameters—BCR[8] = 0 ......... 146
Figure 48. CE#-Controlled Asynchronous WRITE .................. 147
S71GS256/128N_00_A0 December 17, 2004
A d v a n c e
I n f o r m a t i o n
Table 44. Asynchronous WRITE Timing
Parameters—CE#-Controlled .............................................147
Figure 49. LB#/UB#-Controlled Asynchronous WRITE ........... 149
Table 45. Asynchronous WRITE Timing Parameters—LB#/UB#Controlled .......................................................................149
Figure 50. WE#-Controlled Asynchronous WRITE.................. 151
Table 46. Asynchronous WRITE Timing Parameters—WE#Controlled .......................................................................151
Figure 51. Asynchronous WRITE Using ADV#....................... 153
Table 47. Asynchronous WRITE Timing
Parameters Using ADV# ....................................................154
Figure 52. Burst WRITE Operation ...................................... 155
Table 48. Burst WRITE Timing Parameters ...........................156
Figure 53. Continuous Burst WRITE Showing an Output Delay with
BCR[8] = 0 for End-of-Row Condition ................................. 157
Table 49. Burst WRITE Timing Parameters—BCR[8] = 0 ........157
Figure 54. Burst WRITE Followed by Burst READ .................. 158
Table 50. WRITE Timing Parameters—Burst WRITE Followed by
Burst READ .....................................................................158
Table 51. READ Timing Parameters—Burst WRITE Followed by Burst
READ ..............................................................................158
Figure 55. Asynchronous WRITE Followed by Burst READ ...... 159
Table 52. WRITE Timing Parameters—Asynchronous WRITE
Followed by Burst READ ....................................................160
Table 53. READ Timing Parameters—Asynchronous WRITE Followed
by Burst READ .................................................................160
Figure 56. Asynchronous WRITE (ADV# LOW) Followed By Burst
READ.............................................................................. 161
Table 54. Asynchronous WRITE Timing
Parameters—ADV# LOW ...................................................161
Table 55. Burst READ Timing Parameters ............................162
Figure 57. Burst READ Followed by Asynchronous WRITE (WE#-Controlled) ........................................................................... 163
Table 56. Burst READ Timing Parameters ............................164
Table 57. Asynchronous WRITE Timing
Parameters—WE# Controlled .............................................164
Figure 58. Burst READ Followed by Asynchronous WRITE Using
ADV# ............................................................................. 165
Table 58. Burst READ Timing Parameters ............................166
Table 59. Asynchronous WRITE Timing
Parameters Using ADV# ....................................................166
Figure 59. Asynchronous WRITE Followed by Asynchronous READ—
ADV# LOW...................................................................... 167
Table 60. WRITE Timing Parameters—ADV# LOW .................167
Table 61. READ Timing Parameters—ADV# LOW ..................168
Figure 60. Asynchronous WRITE Followed by
Asynchronous READ ......................................................... 169
Table 62. WRITE Timing Parameters—Asynchronous WRITE
Followed by Asynchronous READ ........................................169
Table 63. READ Timing Parameters—Asynchronous WRITE Followed
by Asynchronous READ .....................................................170
How Extended Timings Impact CellularRAM™
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Introduction ........................................................................................................ 170
Asynchronous WRITE Operation ................................................................ 171
Figure 61. Extended Timing for tCEM.............................................. 171
Figure 62. Extended Timing for tTM................................................ 171
Table 64. Extended Cycle Impact on READ and WRITE Cycles 171
Extended WRITE Timing— Asynchronous WRITE Operation ...... 171
Figure 63. Extended WRITE Operation ................................ 172
Page Mode READ Operation ........................................................................ 172
Burst-Mode Operation .................................................................................... 172
Summary .............................................................................................................. 172
CellularRAM-2A
December 17, 2004 S71GS256/128N_00_A0
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
General Description . . . . . . . . . . . . . . . . . . . . . . 173
Figure 64. Functional Block Diagram................................... 174
Table 65. Pin Descriptions ................................................. 174
Table 66. Bus Operations—Asynchronous Mode ................... 175
Functional Description . . . . . . . . . . . . . . . . . . . . .176
Power-Up Initialization ....................................................................................176
Figure 65. Power-Up Initialization Timing ............................ 176
Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . 176
Asynchronous Mode ........................................................................................176
Figure 66. READ Operation................................................ 177
Figure 67. WRITE Operation .............................................. 177
Page Mode READ Operation ........................................................................ 177
Figure 68. Page Mode READ Operation................................ 178
LB# / UB# Operation ......................................................................................178
Low Power Operation . . . . . . . . . . . . . . . . . . . . . 178
Standby Mode Operation ...............................................................................178
Temperature Compensated Refresh ...........................................................178
Partial Array Refresh ........................................................................................179
Deep Power-Down Operation .....................................................................179
Configuration Register Operation ...............................................................179
Figure 69. Load Configuration Register Operation................. 180
Table 67. Configuration Register Bit Mapping ....................... 181
Table 68. 64Mb Address Patterns for PAR (CR[4] = 1) .......... 181
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 182
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 183
Table 69. Electrical Characteristics and Operating Conditions . 183
Table 70. Temperature Compensated Refresh Specifications and
Conditions ....................................................................... 183
Table 71. Partial Array Refresh Specifications and Conditions . 184
Table 72. Deep Power-Down Specifications .......................... 184
Table 73. Capacitance Specifications and Conditions ............. 184
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 70. AC Input/Output Reference Waveform................. 184
Figure 71. Output Load Circuit ........................................... 184
Table 74. Output Load Circuit ............................................ 184
Table 75. READ Cycle Timing Requirements ......................... 185
Table 76. WRITE Cycle Timing Requirements ....................... 186
Table 77. Load Configuration Register Timing Requirements .. 186
Table 78. Deep Power Down Timing Requirements ............... 186
Table 79. Power-up Initialization Timing Parameters ............. 187
Figure 72. Power-up Initialization Period ............................. 187
Figure 73. Load Configuration Register Timing ..................... 187
Table 80. Load Configuration Register Timing Requirements .. 187
Figure 74. Deep Power Down Entry/Exit TIming ................... 188
Table 81. Load Configuration Register Timing Requirements .. 188
Figure 75. Single READ Operation (WE# = VIH) ................... 188
Table 82. READ Timing Parameters .................................... 189
Figure 76. Page Mode Read Operation (WE# = VIH) ............. 189
Table 83. Page Mode READ Timing Parameters .................... 189
Figure 77. WRITE Cycle (WE# Control) ............................... 190
Table 84. Write Timing Parameters ..................................... 190
Figure 78. Write Timing Parameters (CE# Control) ............... 191
Table 85. Write Timing Parameters (CE# Control) ................ 191
Figure 79. WRITE Cycle (LB# / UB# Control)....................... 192
Table 86. Write Timing Parameters (LB# / UB# Control) ....... 192
How Extended Timings Impact CellularRAM™
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Introduction ........................................................................................................193
Operation When Page Mode is Disabled .................................................. 193
Figure 80. Extended Timing for tCEM..............................................
Figure 81. Extended Timing for tTM................................................
193
193
Operation When Page Mode is Enabled ....................................................193
5
A d v a n c e
Figure 82. Extended Timing for tCEM (2) .............................. 194
Impact on Extended WRITE Operations ..................................................194
I n f o r m a t i o n
Revision Summary
Figure 83. Extended WRITE Operation ................................ 194
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6
S71GS256/128N_00_A0 December 17, 2004
A d v a n c e
I n f o r m a t i o n
MCP Block Diagrams
(256 Mb Flash + 64 Mb pSRAM)
F-VIO
F-VCC
Flash-only Address
Shared Address
2
22
F-VCC
VIO
DQ15 to DQ0
16
WP#/ACC
WP#/ACC
CE#
OE#
WE#
F-RST#
F1-CE#
OE#
WE#
F-RST#
Flash
RY/BY#
RY/BY#
VSS
R- VCC
22
R-UB#
R-LB#
ZZ#
R-CE1#
December 17, 2004 S71GS256/128N_00_A0
DQ15 to DQ0
R-VCC R-VIO
I/O15 to I/O0
16
WE#
OE#
pSRAM
UB#
LB#
VSSQ
ZZ#
R-CE1#
7
A d v a n c e
I n f o r m a t i o n
(128 Mb Flash + 32 Mb pSRAM)
F-VIO
F-VCC
Flash-only Address
Shared Address
2
21
F-VCC
VIO
DQ15 to DQ0
16
WP#/ACC
WP#/ACC
CE#
OE#
WE#
F-RST#
F1-CE#
OE#
WE#
F-RST#
Flash
RY/BY#
RY/BY#
VSS
R-VCC
21
R-UB#
R-LB#
CRE
R-CE1#
8
DQ15 to DQ0
R-VCC R-VIO
I/O15 to I/O0
16
WE#
OE#
pSRAM
UB#
LB#
VSSQ
CRE
R-CE1#
S71GS256/128N_00_A0 December 17, 2004
A d v a n c e
I n f o r m a t i o n
Connection Diagrams
256 Mb Flash + 64 Mb pSRAM Pinout
84-ball Fine-Pitch Ball Grid Array
256 Mb Flash + 64 Mb pSRAM
Pinout
(Top View, Balls Facing Down)
Legend
A10
A1
DNU
B2
B3
B4
B5
B6
B7
B8
B9
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
C2
C3
C4
C5
C6
C7
C8
C9
RFU
A7
A8
A11
RFU
D2
D3
D6
D7
D8
D9
A3
A6
RFU
A19
A12
A15
E2
E3
E4
E5
E6
E7
E8
E9
A2
A5
A18
RY/BY#
A20
A9
A13
A21
F2
F3
F4
F5
F6
F7
F8
F9
A1
A4
A17
RFU
A23
A10
A14
A22
G2
G3
G4
G5
G6
G7
G8
G9
A0
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
ZZ#
J2
J3
J4
J5
J6
J7
J8
J9
R-CE1#
DQ0
DQ10
F-VCC
R-VCC
DQ12
DQ7
VSS
K2
K3
K4
K5
K6
K7
K8
K9
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
L2
L3
L4
L5
L6
L7
L8
L9
RFU
RFU
RFU
F-VCC
RFU
R-VIO
F-VIO
RFU
F1-CE#
R-LB# WP#/ACC WE#
D4
D5
DNU
Shared
Flash only
RAM only
R-UB# F-RST#
Reserved for
Future Use
M1
M10
DNU
DNU
December 17, 2004 S71GS256/128N_00_A0
9
A d v a n c e
I n f o r m a t i o n
128 Mb Flash + 32 Mb pSRAM Pinout
84-ball Fine-Pitch Ball Grid Array
128 Mb Flash + 32 Mb pSRAM
Pinout
(Top View, Balls Facing Down)
Legend
A10
A1
DNU
B2
B3
B4
B5
B6
B7
B8
B9
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
C2
C3
C4
C5
C6
C7
C8
C9
RFU
A7
A8
A11
RFU
D2
D3
D6
D7
D8
D9
A3
A6
RFU
A19
A12
A15
E2
E3
E4
E5
E6
E7
E8
E9
A2
A5
A18
RY/BY#
A20
A9
A13
A21
F2
F3
F4
F5
F6
F7
F8
F9
A1
A4
A17
RFU
RFU
A10
A14
A22
G2
G3
G4
G5
G6
G7
G8
G9
A0
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
CRE
J2
J3
J4
J5
J6
J7
J8
J9
R-CE1#
DQ0
DQ10
F-VCC
R-VCC
DQ12
DQ7
VSS
K2
K3
K4
K5
K6
K7
K8
K9
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
L2
L3
L4
L5
L6
L7
L8
L9
RFU
RFU
RFU
F-VCC
RFU
R-VIO
F-VIO
RFU
F1-CE#
10
R-LB# WP#/ACC WE#
D4
D5
DNU
Shared
Flash only
RAM only
R-UB# F-RST#
Reserved for
Future Use
M1
M10
DNU
DNU
S71GS256/128N_00_A0 December 17, 2004
A d v a n c e
I n f o r m a t i o n
Input/Output Descriptions
A23-A0
A22-A0
DQ15-DQ0
OE#
=
=
=
=
WE#
VSS
NC
F-RST#
=
=
=
=
WP#/ACC
=
R-CE1#
ZZ#
CRE
=
=
=
F1-CE#
F-VCC
R-VCC
R-UB#
R-LB#
RFU
RY/BY#
F-VIO
R-VIO
=
=
=
=
=
=
=
=
=
December 17, 2004 S71GS256/128N_00_A0
24 Address inputs (256 Mb)
23 Address inputs (128 Mb)
Data input/output
Output Enable input. Asynchronous relative to CLK
for the Burst mode.
Write Enable input.
Ground
No Connect; not connected internally
Hardware reset input. Low = device resets and
returns to reading array data
Hardware write protect input / programming
acceleration input.
Chip-enable input for pSRAM.
pSRAM Sleep mode
Configuration Register Enable. CRE is used only for
power savings, but does not enable burst
operations.
Chip-enable input for Flash 1.
Flash 3.0 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM).
Reserved for future use.
Ready/Busy output.
Flash Input/Output Buffer Power Supply
pSRAM Input/Output Buffer Power Supply
11
A d v a n c e
I n f o r m a t i o n
Logic Symbol
Max (Note 1)
AMax (Note 2) –A0
R-CE1#
16
DQ15–DQ0
OE#
WE#
WP#/ACC
WE#
F-RST#
RY/BY#
UB#
F1-CE#
CRE (Note 3)
ZZ# (Note 4)
Notes:
1. Max = 24 [256 Mb Flash], 23 [128 Mb Flash].
2. AMax = A23 [256 Mb Flash], A22 [128 Mb Flash].
3. CRE is available only in Synchronous pSRAM.
4. ZZ# is available only in Asynchronous pSRAM.
12
S71GS256/128N_00_A0 December 17, 2004
A d v a n c e
I n f o r m a t i o n
Ordering Information
The order number (Valid Combination) is formed by the following:
S71GS
256
N
C0
BA
W
AK
0
PACKING TYPE
0
= Tray
2
= 7” Tape and Reel
3
= 13” Tape and Reel
PACKAGE MODIFIER / MODEL NUMBER
See Valid Combinations table
TEMPERATURE RANGE
W
= Wireless (-25°C to +85°C)
PACKAGE TYPE
BA
= Very Thin Fine-pitch BGA Lead (Pb)-free compliant package
BF
= Very Thin Fine-pitch BGA Lead (Pb)-free package
pSRAM DENSITY
C0
= 64 Mb pSRAM
B0
= 32 Mb pSRAM
PROCESS TECHNOLOGY
N
= 110 nm, MirrorBitTM Technology
FLASH DENSITY
256 = 256 Mb
128 = 128 Mb
PRODUCT FAMILY
S71GS Multi-chip Product (MCP)
3.0 Volt-only VCC and 1.8 V VIOUniform Sector Page Mode Flash Memory
with 1.8 Volt pSRAM
S71GS256NC0 Valid Combinations
Base
Ordering
Part Number
Package &
Temperature
S71GS256NC0
BAW
Package
Modifier/
Model
Number
Packing
Type
Flash
Initial/Page
Speed (ns)
S71GS256NC0
BFW
AK
0, 2, 3
(Note 1)
110/30
AP
Notes:
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
3. For specifications, refer to the CellularRam 2A module.
December 17, 2004 S71GS256/128N_00_A0
(p)SRAM
Supplier
(p)SRAM
Type/
Access
Time (ns)
Package
Type
Package
Marking
70 / 25
8mmx11.6mm
84-ball Lead
(Pb)-free
Compliant
(Note 2)
Lowest Add
AK
AP
Address
Sector
Protection
Highest Add
Lowest Add
Highest Add
CellRam
2A
(Note 3)
8mmx11.6mm
84-ball Lead
(Pb)-free
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
13
A d v a n c e
I n f o r m a t i o n
S71GS128NB0 Valid Combinations
Base
Ordering
Part Number
Package &
Temperature
S71GS128NB0
BAW
Package
Modifier/
Model
Number
Packing
Type
Flash
Initial/Page
Speed (ns)
S71GS128NB0
BFW
AK
0, 2, 3
(Note 1)
110/30
AP
Notes:
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
3. For specifications, refer to the CellularRam 2 module.
14
(p)SRAM
Supplier
(p)SRAM
Type/
Access
Time (ns)
Package
Type
Package
Marking
70 / 25
8mmx11.6mm
84-ball Lead
(Pb)-free
Compliant
(Note 2)
Lowest Add
AK
AP
Address
Sector
Protection
Highest Add
Lowest Add
Highest Add
CellRam 2
(Note 3)
8mmx11.6mm
84-ball Lead
(Pb)-free
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
S71GS256/128N_00_A0 December 17, 2004
A d v a n c e
I n f o r m a t i o n
Physical Dimensions
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 11.6 x1.2 mm MCP
Compatible Package
D1
A
D
eD
0.15 C
(2X)
10
9
SE 7
8
7
6
E
E1
5
4
eE
3
2
1
M L K J
INDEX MARK
PIN A1
CORNER
B
10
TOP VIEW
H G F
E D C
B A
7
SD
0.15 C
PIN A1
CORNER
(2X)
BOTTOM VIEW
0.20 C
A A2
A1
C
0.08 C
SIDE VIEW
6
b
84X
0.15
0.08
M C A B
M C
NOTES:
PACKAGE
TLA 084
JEDEC
N/A
DxE
11.60 mm x 8.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.17
---
---
A2
0.81
---
0.97
NOTE
PROFILE
BODY SIZE
E
8.00 BSC.
BODY SIZE
D1
8.80 BSC.
MATRIX FOOTPRINT
E1
7.20 BSC.
MATRIX FOOTPRINT
MD
12
MATRIX SIZE D DIRECTION
ME
10
MATRIX SIZE E DIRECTION
84
0.35
0.40
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
BALL COUNT
0.45
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
eE
0.80 BSC.
BALL PITCH
eD
0.80 BSC
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
DEPOPULATED SOLDER BALLS
B1,B10,C1,C10,D1,D10,
E1,E10,F1,F10,G1,G10,
H1,H10,J1,J10,K1,K10,L1,L10,
M2,M3,M4,M5,M6,M7,M8,M9
December 17, 2004 S71GS256/128N_00_A0
2.
BODY THICKNESS
11.60 BSC.
n
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
BALL HEIGHT
D
Øb
1.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9.
N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3372-2 \ 16-038.22a
15
S29GLxxxN MirrorBitTM Flash Family
S29GL512N, S29GL256N, S29GL128N
512 Megabit, 256 Megabit, and 128 Megabit, 3.0 Volt-only
Page Mode Flash Memory featuring 110 nm MirrorBit
process technology
Data Sheet
ADVANCE
INFORMATION
Distinctive Characteristics
Architectural Advantages
„
Single power supply operation
— 3 volt read, erase, and program operations
„
Enhanced VersatileI/O™ control
— All input levels (address, control, and DQ input levels)
and outputs are determined by voltage on VIO input.
VIO range is 1.65 to VCC
„
Manufactured on 110 nm MirrorBit process
technology
„
Secured Silicon Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer
„
„
Software & Hardware Features
„
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
„
Hardware features
— Advanced Sector Protection
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
Flexible sector architecture
— S29GL512N: Five hundred twelve 64 Kword (128
Kbyte) sectors
— S29GL256N: Two hundred fifty-six 64 Kword (128
Kbyte) sectors
— S29GL128N: One hundred twenty-eight 64 Kword
(128 Kbyte) sectors
„
Compatibility with JEDEC standards
— Provides pinout and software compatibility for singlepower supply flash, and superior inadvertent write
protection
„
100,000 erase cycles per sector typical
„
20-year data retention typical
Performance Characteristics
„
— 90 ns access time (S29GL128N, S29GL256N,
S29GL512N)
— 8-word/16-byte page read buffer
— 25 ns page read times
— 16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
Low power consumption (typical values at 3.0 V, 5
MHz)
— 25 mA typical active read current;
— 50 mA typical erase/program current
— 1 µA typical standby mode current
High performance
Publication Number S29GLxxxN_MCP
Revision A
Amendment 1
Issue Date December 15, 2004
This document contains information on a product under development at Spansion LLC. The information is intended to help you evaluate this product. Spansion LLC
reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e
I n f o r m a t i o n
General Description
The S29GL512/256/128N family of devices are 3.0V single power flash memory
manufactured using 110 nm MirrorBit technology. The S29GL512N is a 512 Mbit,
organized as 33,554,432 words or 67,108,864 bytes. The S29GL256N is a 256
Mbit, organized as 16,777,216 words or 33,554,432 bytes. The S29GL128N is a
128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The device can be
programmed either in the host system or in standard EPROM programmers.
Access times as fast as 90 ns (S29GL128N, S29GL256N, S29GL512N) are available. Note that each access time has a specific operating voltage range (VCC) and
an I/O voltage range (VIO), as specified in the “Product Selector Guide” section.
The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and
write functions. In addition to a VCC input, a high-voltage accelerated program
(WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system
production, but may also be used in the field if desired.
The devices are entirely command set compatible with the JEDEC singlepower-supply Flash standard. Commands are written to the device using
standard microprocessor write timing. Write cycles also internally latch addresses
and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#
(RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead
by requiring only two write cycles to program data instead of four.
The Enhanced VersatileI/O™ (VIO) control allows the host system to set the
voltage levels that the device generates and tolerates on all input levels (address,
chip control, and DQ input levels) to the same voltage level that is asserted on
the VIO pin. This allows the device to operate in a 1.8 V or 3 V system environment as required.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. Persistent Sector
Protection provides in-system, command-enabled protection of any combination of sectors using a single power supply at VCC. Password Sector Protection
prevents unauthorized write and erase operations in any combination of sectors
through a user-defined 64-bit password.
The Erase Suspend/Erase Resume feature allows the host system to pause an
erase operation in a given sector to read or program any other sector and then
complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin may be
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
17
A d v a n c e
I n f o r m a t i o n
tied to the system reset circuitry. A system reset would thus also reset the device,
enabling the host system to read boot-up firmware from the Flash memory
device.
The device reduces power consumption in the standby mode when it detects
specific voltage levels on CE# and RESET#, or when addresses have been stable
for a specified period of time.
The Secured Silicon Sector provides a 128-word/256-byte area for code or
data that can be permanently protected. Once this sector is protected, no further
changes within the sector can occur.
The Write Protect (WP#/ACC) feature protects the first or last sector by asserting a logic low on the WP# pin.
MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via hot-hole
assisted erase. The data is programmed using hot electron injection.
18
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
Product Selector Guide
S29GL512N
Part Number
Speed Option
S29GL512N
VCC = 2.7–3.6 V
VCC = 3.0-3.6V
VIO = 2.7–3.6 V
10
11
VIO = 1.65–1.95 V
11
VIO = 3.0-3.6V
90
Max. Access Time (ns)
90
100
110
110
Max. CE# Access Time (ns)
90
100
110
110
Max. Page access time (ns)
25
25
25
30
Max. OE# Access Time (ns)
25
25
25
30
10
11
S29GL256N
Part Number
Speed Option
S29GL256N
VCC = 2.7–3.6 V
VCC = Regulated (3.0-3.6V)
VIO = 2.7–3.6 V
VIO = 1.65–1.95 V
11
VIO = Regulated (3.0-3.6V)
90
Max. Access Time (ns)
90
100
110
110
Max. CE# Access Time (ns)
90
100
110
110
Max. Page access time (ns)
25
25
25
30
Max. OE# Access Time (ns)
25
25
25
30
10
11
S29GL128N
Part Number
Speed Option
S29GL128N
VCC = 2.7–3.6 V
VCC = Regulated (3.0-3.6V)
VIO = 2.7–3.6 V
VIO = 1.65–1.95 V
VIO = Regulated (3.0-3.6V)
11
90
Max. Access Time (ns)
90
100
110
110
Max. CE# Access Time (ns)
90
100
110
110
Max. Page access time (ns)
25
25
25
30
Max. OE# Access Time (ns)
25
25
25
30
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
19
A d v a n c e
I n f o r m a t i o n
Block Diagram
DQ15–DQ0 (A-1)
RY/BY#
VCC
Sector Switches
VSS
VIO
Erase Voltage
Generator
RESET#
WE#
WP#/ACC
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Timer
AMax**–A0
Address Latch
STB
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
Notes:
1. AMax GL512N = A24, AMax GL256N = A23, AMax GL128N = A22
20
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
Pin Description
A24–A0
A23–A0
A22–A0
DQ14–DQ0
DQ15/A-1
=
=
=
=
=
CE#
OE#
WE#
WP#/ACC
=
=
=
=
RESET#
RY/BY#
VCC
=
=
=
VIO
VSS
NC
=
=
=
December 15, 2004 S29GLxxxN_MCP_A1
25 Address inputs (512 Mb)
24 Address inputs (256 Mb)
23 Address inputs (128 Mb)
15 Data inputs/outputs
DQ15 (Data input/output, word mode), A-1 (LSB
Address input
Chip Enable input
Output Enable input
Write Enable input
Hardware Write Protect input;
Acceleration input
Hardware Reset Pin input
Ready/Busy output
3.0 volt-only single power supply
(see Product Selector Guide for speed options and
voltage supply tolerances)
Output Buffer power
Device Ground
Pin Not Connected Internally
S29GLxxxN MirrorBitTM Flash Family
21
A d v a n c e
I n f o r m a t i o n
Logic Symbol
S29GL512N
25
A24–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
VIO
RY/BY#
S29GL256N
24
A23–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
VIO
RY/BY#
S29GL128N
23
A22–A0
CE#
16 or 8
DQ15–DQ0
(A-1)
OE#
WE#
WP#/ACC
RESET#
VIO
22
RY/BY#
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 1.
Device Bus Operations
CE#
OE#
WE#
RESET#
WP#/
ACC
Addresses
(Note 1)
DQ0–DQ15
Read
L
L
H
H
X
AIN
DOUT
Write (Program/Erase)
L
H
L
H
Note 2
AIN
(Note 3)
Accelerated Program
L
H
L
H
VHH
AIN
(Note 3)
X
X
VCC ±
0.3 V
H
X
High-Z
Operation
Standby
VCC
± 0.3 V
Output Disable
L
H
H
H
X
X
High-Z
Reset
X
X
X
L
X
X
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5V, X = Don’t Care, SA = Sector
Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are AMax:A0 in word mode. Sector addresses are AMax:A16 in both modes.
2. If WP# = VIL, the first or last sector group remains protected. If WP# = VIH, the first or last sector will be
protected or unprotected as determined by the method described in “Write Protect (WP#)”. All sectors are
unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending
on version ordered.)
3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2, Figure 4, and
Figure 5).
VersatileIOTM (VIO) Control
The VersatileIOTM (VIO) control allows the host system to set the voltage levels
that the device generates and tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on VIO. See Ordering Information for VIO options on this
device.
For example, a VI/O of 1.65 V to 3.6 V allows for I/O at the 1.8 or 3 volt levels,
driving and receiving signals to and from other 1.8-V or 3-V devices on the same
data bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE#
pins to VIL. CE# is the power control and selects the device. OE# is the output
control and gates array data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
23
A d v a n c e
I n f o r m a t i o n
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the command register
contents are altered.
See “Reading Array Data” on page 66 for more information. Refer to the AC ReadOnly Operations table for timing specifications and to Figure 11 for the timing diagram. Refer to the DC Characteristics table for the active current specification
on reading array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. The page size of the device is 8 words/16 bytes.
The appropriate page is selected by the higher address bits A(max)–A3. Address
bits A2–A0 determine the specific word within a page. This is an asynchronous
operation; the microprocessor supplies the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page
read accesses (as long as the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is de-asserted and reasserted
for a subsequent access, the access time is tACC or tCE. Fast page mode accesses
are obtained by keeping the “read-page addresses” constant and changing the
“intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word Program Command
Sequence” section has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 2, Table 4, and Table 5 indicate the address space that each sector occupies.
Refer to the DC Characteristics table for the active current specification for the
write mode. The AC Characteristics section contains timing specification tables
and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32
bytes in one programming operation. This results in faster effective programming
time than the standard programming algorithms. See “Write Buffer” for more
information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
is one of two functions provided by the WP#/ACC pin. This function is primarily
intended to allow faster manufacturing throughput at the factory.
24
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sector
groups, and uses the higher voltage on the pin to reduce the time required for
program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/
ACC pin returns the device to normal operation. Note that the WP#/ACC pin must
not be at VHH for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at VIH.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7–DQ0. Standard read
cycle timings apply in this mode. Refer to the “Autoselect Mode” section on page
52 and “Autoselect Command Sequence” section on page 66 sections for more
information.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device
will be in the standby mode, but the standby current will be greater. The device
requires standard access time (tCE) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
Refer to the “DC Characteristics” section on page 90 for the standby current
specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. Refer to the “DC Characteristics” section on page 90 for the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
25
A d v a n c e
I n f o r m a t i o n
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VSS±0.3 V, the device draws CMOS standby current (ICC5). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 13
for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins
are placed in the high impedance state.
Table 2.
Sector
26
Sector Address Table–S29GL512N
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA0
0
0
0
0
0
0
0
0
0
128/64
0000000–000FFFF
SA1
0
0
0
0
0
0
0
0
1
128/64
0010000–001FFFF
SA2
0
0
0
0
0
0
0
1
0
128/64
0020000–002FFFF
SA3
0
0
0
0
0
0
0
1
1
128/64
0030000–003FFFF
SA4
0
0
0
0
0
0
1
0
0
128/64
0040000–004FFFF
SA5
0
0
0
0
0
0
1
0
1
128/64
0050000–005FFFF
SA6
0
0
0
0
0
0
1
1
0
128/64
0060000–006FFFF
SA7
0
0
0
0
0
0
1
1
1
128/64
0070000–007FFFF
SA8
0
0
0
0
0
1
0
0
0
128/64
0080000–008FFFF
SA9
0
0
0
0
0
1
0
0
1
128/64
0090000–009FFFF
SA10
0
0
0
0
0
1
0
1
0
128/64
00A0000–00AFFFF
SA11
0
0
0
0
0
1
0
1
1
128/64
00B0000–00BFFFF
SA12
0
0
0
0
0
1
1
0
0
128/64
00C0000–00CFFFF
SA13
0
0
0
0
0
1
1
0
1
128/64
00D0000–00DFFFF
SA14
0
0
0
0
0
1
1
1
0
128/64
00E0000–00EFFFF
SA15
0
0
0
0
0
1
1
1
1
128/64
00F0000–00FFFFF
SA16
0
0
0
0
1
0
0
0
0
128/64
0100000–010FFFF
SA17
0
0
0
0
1
0
0
0
1
128/64
0110000–011FFFF
SA18
0
0
0
0
1
0
0
1
0
128/64
0120000–012FFFF
SA19
0
0
0
0
1
0
0
1
1
128/64
0130000–013FFFF
SA20
0
0
0
0
1
0
1
0
0
128/64
0140000–014FFFF
SA21
0
0
0
0
1
0
1
0
1
128/64
0150000–015FFFF
SA22
0
0
0
0
1
0
1
1
0
128/64
0160000–016FFFF
SA23
0
0
0
0
1
0
1
1
1
128/64
0170000–017FFFF
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 2.
I n f o r m a t i o n
Sector Address Table–S29GL512N (Continued)
Sector
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA24
0
0
0
0
1
1
0
0
0
128/64
0180000–018FFFF
SA25
0
0
0
0
1
1
0
0
1
128/64
0190000–019FFFF
SA26
0
0
0
0
1
1
0
1
0
128/64
01A0000–01AFFFF
SA27
0
0
0
0
1
1
0
1
1
128/64
01B0000–01BFFFF
SA28
0
0
0
0
1
1
1
0
0
128/64
01C0000–01CFFFF
SA29
0
0
0
0
1
1
1
0
1
128/64
01D0000–01DFFFF
SA30
0
0
0
0
1
1
1
1
0
128/64
01E0000–01EFFFF
SA31
0
0
0
0
1
1
1
1
1
128/64
01F0000–01FFFFF
SA32
0
0
0
1
0
0
0
0
0
128/64
0200000–020FFFF
SA33
0
0
0
1
0
0
0
0
1
128/64
0210000–021FFFF
SA34
0
0
0
1
0
0
0
1
0
128/64
0220000–022FFFF
SA35
0
0
0
1
0
0
0
1
1
128/64
0230000–023FFFF
SA36
0
0
0
1
0
0
1
0
0
128/64
0240000–024FFFF
SA37
0
0
0
1
0
0
1
0
1
128/64
0250000–025FFFF
SA38
0
0
0
1
0
0
1
1
0
128/64
0260000–026FFFF
SA39
0
0
0
1
0
0
1
1
1
128/64
0270000–027FFFF
SA40
0
0
0
1
0
1
0
0
0
128/64
0280000–028FFFF
SA41
0
0
0
1
0
1
0
0
1
128/64
0290000–029FFFF
SA42
0
0
0
1
0
1
0
1
0
128/64
02A0000–02AFFFF
SA43
0
0
0
1
0
1
0
1
1
128/64
02B0000–02BFFFF
SA44
0
0
0
1
0
1
1
0
0
128/64
02C0000–02CFFFF
SA45
0
0
0
1
0
1
1
0
1
128/64
02D0000–02DFFFF
SA46
0
0
0
1
0
1
1
1
0
128/64
02E0000–02EFFFF
SA47
0
0
0
1
0
1
1
1
1
128/64
02F0000–02FFFFF
SA48
0
0
0
1
1
0
0
0
0
128/64
0300000–030FFFF
SA49
0
0
0
1
1
0
0
0
1
128/64
0310000–031FFFF
SA50
0
0
0
1
1
0
0
1
0
128/64
0320000–032FFFF
SA51
0
0
0
1
1
0
0
1
1
128/64
0330000–033FFFF
SA52
0
0
0
1
1
0
1
0
0
128/64
0340000–034FFFF
SA53
0
0
0
1
1
0
1
0
1
128/64
0350000–035FFFF
SA54
0
0
0
1
1
0
1
1
0
128/64
0360000–036FFFF
SA55
0
0
0
1
1
0
1
1
1
128/64
0370000–037FFFF
SA56
0
0
0
1
1
1
0
0
0
128/64
0380000–038FFFF
SA57
0
0
0
1
1
1
0
0
1
128/64
0390000–039FFFF
SA58
0
0
0
1
1
1
0
1
0
128/64
03A0000–03AFFFF
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
27
A d v a n c e
Table 2.
Sector Address Table–S29GL512N (Continued)
Sector
28
I n f o r m a t i o n
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA59
0
0
0
1
1
1
0
1
1
128/64
03B0000–03BFFFF
SA60
0
0
0
1
1
1
1
0
0
128/64
03C0000–03CFFFF
SA61
0
0
0
1
1
1
1
0
1
128/64
03D0000–03DFFFF
SA62
0
0
0
1
1
1
1
1
0
128/64
03E0000–03EFFFF
SA63
0
0
0
1
1
1
1
1
1
128/64
03F0000–03FFFFF
SA64
0
0
1
0
0
0
0
0
0
128/64
0400000–040FFFF
SA65
0
0
1
0
0
0
0
0
1
128/64
0410000–041FFFF
SA66
0
0
1
0
0
0
0
1
0
128/64
0420000–042FFFF
SA67
0
0
1
0
0
0
0
1
1
128/64
0430000–043FFFF
SA68
0
0
1
0
0
0
1
0
0
128/64
0440000–044FFFF
SA69
0
0
1
0
0
0
1
0
1
128/64
0450000–045FFFF
SA70
0
0
1
0
0
0
1
1
0
128/64
0460000–046FFFF
SA71
0
0
1
0
0
0
1
1
1
128/64
0470000–047FFFF
SA72
0
0
1
0
0
1
0
0
0
128/64
0480000–048FFFF
SA73
0
0
1
0
0
1
0
0
1
128/64
0490000–049FFFF
SA74
0
0
1
0
0
1
0
1
0
128/64
04A0000–04AFFFF
SA75
0
0
1
0
0
1
0
1
1
128/64
04B0000–04BFFFF
SA76
0
0
1
0
0
1
1
0
0
128/64
04C0000–04CFFFF
SA77
0
0
1
0
0
1
1
0
1
128/64
04D0000–04DFFFF
SA78
0
0
1
0
0
1
1
1
0
128/64
04E0000–04EFFFF
SA79
0
0
1
0
0
1
1
1
1
128/64
04F0000–04FFFFF
SA80
0
0
1
0
1
0
0
0
0
128/64
0500000–050FFFF
SA81
0
0
1
0
1
0
0
0
1
128/64
0510000–051FFFF
SA82
0
0
1
0
1
0
0
1
0
128/64
0520000–052FFFF
SA83
0
0
1
0
1
0
0
1
1
128/64
0530000–053FFFF
SA84
0
0
1
0
1
0
1
0
0
128/64
0540000–054FFFF
SA85
0
0
1
0
1
0
1
0
1
128/64
0550000–055FFFF
SA86
0
0
1
0
1
0
1
1
0
128/64
0560000–056FFFF
SA87
0
0
1
0
1
0
1
1
1
128/64
0570000–057FFFF
SA88
0
0
1
0
1
1
0
0
0
128/64
0580000–058FFFF
SA89
0
0
1
0
1
1
0
0
1
128/64
0590000–059FFFF
SA90
0
0
1
0
1
1
0
1
0
128/64
05A0000–05AFFFF
SA91
0
0
1
0
1
1
0
1
1
128/64
05B0000–05BFFFF
SA92
0
0
1
0
1
1
1
0
0
128/64
05C0000–05CFFFF
SA93
0
0
1
0
1
1
1
0
1
128/64
05D0000–05DFFFF
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 2.
I n f o r m a t i o n
Sector Address Table–S29GL512N (Continued)
Sector
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA94
0
0
1
0
1
1
1
1
0
128/64
05E0000–05EFFFF
SA95
0
0
1
0
1
1
1
1
1
128/64
05F0000–05FFFFF
SA96
0
0
1
1
0
0
0
0
0
128/64
0600000–060FFFF
SA97
0
0
1
1
0
0
0
0
1
128/64
0610000–061FFFF
SA98
0
0
1
1
0
0
0
1
0
128/64
0620000–062FFFF
SA99
0
0
1
1
0
0
0
1
1
128/64
0630000–063FFFF
SA100
0
0
1
1
0
0
1
0
0
128/64
0640000–064FFFF
SA101
0
0
1
1
0
0
1
0
1
128/64
0650000–065FFFF
SA102
0
0
1
1
0
0
1
1
0
128/64
0660000–066FFFF
SA103
0
0
1
1
0
0
1
1
1
128/64
0670000–067FFFF
SA104
0
0
1
1
0
1
0
0
0
128/64
0680000–068FFFF
SA105
0
0
1
1
0
1
0
0
1
128/64
0690000–069FFFF
SA106
0
0
1
1
0
1
0
1
0
128/64
06A0000–06AFFFF
SA107
0
0
1
1
0
1
0
1
1
128/64
06B0000–06BFFFF
SA108
0
0
1
1
0
1
1
0
0
128/64
06C0000–06CFFFF
SA109
0
0
1
1
0
1
1
0
1
128/64
06D0000–06DFFFF
SA110
0
0
1
1
0
1
1
1
0
128/64
06E0000–06EFFFF
SA111
0
0
1
1
0
1
1
1
1
128/64
06F0000–06FFFFF
SA112
0
0
1
1
1
0
0
0
0
128/64
0700000–070FFFF
SA113
0
0
1
1
1
0
0
0
1
128/64
0710000–071FFFF
SA114
0
0
1
1
1
0
0
1
0
128/64
0720000–072FFFF
SA115
0
0
1
1
1
0
0
1
1
128/64
0730000–073FFFF
SA116
0
0
1
1
1
0
1
0
0
128/64
0740000–074FFFF
SA117
0
0
1
1
1
0
1
0
1
128/64
0750000–075FFFF
SA118
0
0
1
1
1
0
1
1
0
128/64
0760000–076FFFF
SA119
0
0
1
1
1
0
1
1
1
128/64
0770000–077FFFF
SA120
0
0
1
1
1
1
0
0
0
128/64
0780000–078FFFF
SA121
0
0
1
1
1
1
0
0
1
128/64
0790000–079FFFF
SA122
0
0
1
1
1
1
0
1
0
128/64
07A0000–07AFFFF
SA123
0
0
1
1
1
1
0
1
1
128/64
07B0000–07BFFFF
SA124
0
0
1
1
1
1
1
0
0
128/64
07C0000–07CFFFF
SA125
0
0
1
1
1
1
1
0
1
128/64
07D0000–07DFFFF
SA126
0
0
1
1
1
1
1
1
0
128/64
07E0000–07EFFFF
SA127
0
0
1
1
1
1
1
1
1
128/64
07F0000–07FFFFF
SA128
0
1
0
0
0
0
0
0
0
128/64
0800000–080FFFF
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
29
A d v a n c e
Table 2.
Sector Address Table–S29GL512N (Continued)
Sector
30
I n f o r m a t i o n
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA129
0
1
0
0
0
0
0
0
1
128/64
0810000–081FFFF
SA130
0
1
0
0
0
0
0
1
0
128/64
0820000–082FFFF
SA131
0
1
0
0
0
0
0
1
1
128/64
0830000–083FFFF
SA132
0
1
0
0
0
0
1
0
0
128/64
0840000–084FFFF
SA133
0
1
0
0
0
0
1
0
1
128/64
0850000–085FFFF
SA134
0
1
0
0
0
0
1
1
0
128/64
0860000–086FFFF
SA135
0
1
0
0
0
0
1
1
1
128/64
0870000–087FFFF
SA136
0
1
0
0
0
1
0
0
0
128/64
0880000–088FFFF
SA137
0
1
0
0
0
1
0
0
1
128/64
0890000–089FFFF
SA138
0
1
0
0
0
1
0
1
0
128/64
08A0000–08AFFFF
SA139
0
1
0
0
0
1
0
1
1
128/64
08B0000–08BFFFF
SA140
0
1
0
0
0
1
1
0
0
128/64
08C0000–08CFFFF
SA141
0
1
0
0
0
1
1
0
1
128/64
08D0000–08DFFFF
SA142
0
1
0
0
0
1
1
1
0
128/64
08E0000–08EFFFF
SA143
0
1
0
0
0
1
1
1
1
128/64
08F0000–08FFFFF
SA144
0
1
0
0
1
0
0
0
0
128/64
0900000–090FFFF
SA145
0
1
0
0
1
0
0
0
1
128/64
0910000–091FFFF
SA146
0
1
0
0
1
0
0
1
0
128/64
0920000–092FFFF
SA147
0
1
0
0
1
0
0
1
1
128/64
0930000–093FFFF
SA148
0
1
0
0
1
0
1
0
0
128/64
0940000–094FFFF
SA149
0
1
0
0
1
0
1
0
1
128/64
0950000–095FFFF
SA150
0
1
0
0
1
0
1
1
0
128/64
0960000–096FFFF
SA151
0
1
0
0
1
0
1
1
1
128/64
0970000–097FFFF
SA152
0
1
0
0
1
1
0
0
0
128/64
0980000–098FFFF
SA153
0
1
0
0
1
1
0
0
1
128/64
0990000–099FFFF
SA154
0
1
0
0
1
1
0
1
0
128/64
09A0000–09AFFFF
SA155
0
1
0
0
1
1
0
1
1
128/64
09B0000–09BFFFF
SA156
0
1
0
0
1
1
1
0
0
128/64
09C0000–09CFFFF
SA157
0
1
0
0
1
1
1
0
1
128/64
09D0000–09DFFFF
SA158
0
1
0
0
1
1
1
1
0
128/64
09E0000–09EFFFF
SA159
0
1
0
0
1
1
1
1
1
128/64
09F0000–09FFFFF
SA160
0
1
0
1
0
0
0
0
0
128/64
0A00000–0A0FFFF
SA161
0
1
0
1
0
0
0
0
1
128/64
0A10000–0A1FFFF
SA162
0
1
0
1
0
0
0
1
0
128/64
0A20000–0A2FFFF
SA163
0
1
0
1
0
0
0
1
1
128/64
0A30000–0A3FFFF
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 2.
I n f o r m a t i o n
Sector Address Table–S29GL512N (Continued)
Sector
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA164
0
1
0
1
0
0
1
0
0
128/64
0A40000–0A4FFFF
SA165
0
1
0
1
0
0
1
0
1
128/64
0A50000–0A5FFFF
SA166
0
1
0
1
0
0
1
1
0
128/64
0A60000–0A6FFFF
SA167
0
1
0
1
0
0
1
1
1
128/64
0A70000–0A7FFFF
SA168
0
1
0
1
0
1
0
0
0
128/64
0A80000–0A8FFFF
SA169
0
1
0
1
0
1
0
0
1
128/64
0A90000–0A9FFFF
SA170
0
1
0
1
0
1
0
1
0
128/64
0AA0000–0AAFFFF
SA171
0
1
0
1
0
1
0
1
1
128/64
0AB0000–0ABFFFF
SA172
0
1
0
1
0
1
1
0
0
128/64
0AC0000–0ACFFFF
SA173
0
1
0
1
0
1
1
0
1
128/64
0AD0000–0ADFFFF
SA174
0
1
0
1
0
1
1
1
0
128/64
0AE0000–0AEFFFF
SA175
0
1
0
1
0
1
1
1
1
128/64
0AF0000–0AFFFFF
SA176
0
1
0
1
1
0
0
0
0
128/64
0B00000–0B0FFFF
SA177
0
1
0
1
1
0
0
0
1
128/64
0B10000–0B1FFFF
SA178
0
1
0
1
1
0
0
1
0
128/64
0B20000–0B2FFFF
SA179
0
1
0
1
1
0
0
1
1
128/64
0B30000–0B3FFFF
SA180
0
1
0
1
1
0
1
0
0
128/64
0B40000–0B4FFFF
SA181
0
1
0
1
1
0
1
0
1
128/64
0B50000–0B5FFFF
SA182
0
1
0
1
1
0
1
1
0
128/64
0B60000–0B6FFFF
SA183
0
1
0
1
1
0
1
1
1
128/64
0B70000–0B7FFFF
SA184
0
1
0
1
1
1
0
0
0
128/64
0B80000–0B8FFFF
SA185
0
1
0
1
1
1
0
0
1
128/64
0B90000–0B9FFFF
SA186
0
1
0
1
1
1
0
1
0
128/64
0BA0000–0BAFFFF
SA187
0
1
0
1
1
1
0
1
1
128/64
0BB0000–0BBFFFF
SA188
0
1
0
1
1
1
1
0
0
128/64
0BC0000–0BCFFFF
SA189
0
1
0
1
1
1
1
0
1
128/64
0BD0000–0BDFFFF
SA190
0
1
0
1
1
1
1
1
0
128/64
0BE0000–0BEFFFF
SA191
0
1
0
1
1
1
1
1
1
128/64
0BF0000–0BFFFFF
SA192
0
1
1
0
0
0
0
0
0
128/64
0C00000–0C0FFFF
SA193
0
1
1
0
0
0
0
0
1
128/64
0C10000–0C1FFFF
SA194
0
1
1
0
0
0
0
1
0
128/64
0C20000–0C2FFFF
SA195
0
1
1
0
0
0
0
1
1
128/64
0C30000–0C3FFFF
SA196
0
1
1
0
0
0
1
0
0
128/64
0C40000–0C4FFFF
SA197
0
1
1
0
0
0
1
0
1
128/64
0C50000–0C5FFFF
SA198
0
1
1
0
0
0
1
1
0
128/64
0C60000–0C6FFFF
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
31
A d v a n c e
Table 2.
Sector Address Table–S29GL512N (Continued)
Sector
32
I n f o r m a t i o n
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA199
0
1
1
0
0
0
1
1
1
128/64
0C70000–0C7FFFF
SA200
0
1
1
0
0
1
0
0
0
128/64
0C80000–0C8FFFF
SA201
0
1
1
0
0
1
0
0
1
128/64
0C90000–0C9FFFF
SA202
0
1
1
0
0
1
0
1
0
128/64
0CA0000–0CAFFFF
SA203
0
1
1
0
0
1
0
1
1
128/64
0CB0000–0CBFFFF
SA204
0
1
1
0
0
1
1
0
0
128/64
0CC0000–0CCFFFF
SA205
0
1
1
0
0
1
1
0
1
128/64
0CD0000–0CDFFFF
SA206
0
1
1
0
0
1
1
1
0
128/64
0CE0000–0CEFFFF
SA207
0
1
1
0
0
1
1
1
1
128/64
0CF0000–0CFFFFF
SA208
0
1
1
0
1
0
0
0
0
128/64
0D00000–0D0FFFF
SA209
0
1
1
0
1
0
0
0
1
128/64
0D10000–0D1FFFF
SA210
0
1
1
0
1
0
0
1
0
128/64
0D20000–0D2FFFF
SA211
0
1
1
0
1
0
0
1
1
128/64
0D30000–0D3FFFF
SA212
0
1
1
0
1
0
1
0
0
128/64
0D40000–0D4FFFF
SA213
0
1
1
0
1
0
1
0
1
128/64
0D50000–0D5FFFF
SA214
0
1
1
0
1
0
1
1
0
128/64
0D60000–0D6FFFF
SA215
0
1
1
0
1
0
1
1
1
128/64
0D70000–0D7FFFF
SA216
0
1
1
0
1
1
0
0
0
128/64
0D80000–0D8FFFF
SA217
0
1
1
0
1
1
0
0
1
128/64
0D90000–0D9FFFF
SA218
0
1
1
0
1
1
0
1
0
128/64
0DA0000–0DAFFFF
SA219
0
1
1
0
1
1
0
1
1
128/64
0DB0000–0DBFFFF
SA220
0
1
1
0
1
1
1
0
0
128/64
0DC0000–0DCFFFF
SA221
0
1
1
0
1
1
1
0
1
128/64
0DD0000–0DDFFFF
SA222
0
1
1
0
1
1
1
1
0
128/64
0DE0000–0DEFFFF
SA223
0
1
1
0
1
1
1
1
1
128/64
0DF0000–0DFFFFF
SA224
0
1
1
1
0
0
0
0
0
128/64
0E00000–0E0FFFF
SA225
0
1
1
1
0
0
0
0
1
128/64
0E10000–0E1FFFF
SA226
0
1
1
1
0
0
0
1
0
128/64
0E20000–0E2FFFF
SA227
0
1
1
1
0
0
0
1
1
128/64
0E30000–0E3FFFF
SA228
0
1
1
1
0
0
1
0
0
128/64
0E40000–0E4FFFF
SA229
0
1
1
1
0
0
1
0
1
128/64
0E50000–0E5FFFF
SA230
0
1
1
1
0
0
1
1
0
128/64
0E60000–0E6FFFF
SA231
0
1
1
1
0
0
1
1
1
128/64
0E70000–0E7FFFF
SA232
0
1
1
1
0
1
0
0
0
128/64
0E80000–0E8FFFF
SA233
0
1
1
1
0
1
0
0
1
128/64
0E90000–0E9FFFF
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 2.
I n f o r m a t i o n
Sector Address Table–S29GL512N (Continued)
Sector
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA234
0
1
1
1
0
1
0
1
0
128/64
0EA0000–0EAFFFF
SA235
0
1
1
1
0
1
0
1
1
128/64
0EB0000–0EBFFFF
SA236
0
1
1
1
0
1
1
0
0
128/64
0EC0000–0ECFFFF
SA237
0
1
1
1
0
1
1
0
1
128/64
0ED0000–0EDFFFF
SA238
0
1
1
1
0
1
1
1
0
128/64
0EE0000–0EEFFFF
SA239
0
1
1
1
0
1
1
1
1
128/64
0EF0000–0EFFFFF
SA240
0
1
1
1
1
0
0
0
0
128/64
0F00000–0F0FFFF
SA241
0
1
1
1
1
0
0
0
1
128/64
0F10000–0F1FFFF
SA242
0
1
1
1
1
0
0
1
0
128/64
0F20000–0F2FFFF
SA243
0
1
1
1
1
0
0
1
1
128/64
0F30000–0F3FFFF
SA244
0
1
1
1
1
0
1
0
0
128/64
0F40000–0F4FFFF
SA245
0
1
1
1
1
0
1
0
1
128/64
0F50000–0F5FFFF
SA246
0
1
1
1
1
0
1
1
0
128/64
0F60000–0F6FFFF
SA247
0
1
1
1
1
0
1
1
1
128/64
0F70000–0F7FFFF
SA248
0
1
1
1
1
1
0
0
0
128/64
0F80000–0F8FFFF
SA249
0
1
1
1
1
1
0
0
1
128/64
0F90000–0F9FFFF
SA250
0
1
1
1
1
1
0
1
0
128/64
0FA0000–0FAFFFF
SA251
0
1
1
1
1
1
0
1
1
128/64
0FB0000–0FBFFFF
SA252
0
1
1
1
1
1
1
0
0
128/64
0FC0000–0FCFFFF
SA253
0
1
1
1
1
1
1
0
1
128/64
0FD0000–0FDFFFF
SA254
0
1
1
1
1
1
1
1
0
128/64
0FE0000–0FEFFFF
SA255
0
1
1
1
1
1
1
1
1
128/64
0FF0000–0FFFFFF
SA256
1
0
0
0
0
0
0
0
0
128/64
1000000–100FFFF
SA257
1
0
0
0
0
0
0
0
1
128/64
1010000–101FFFF
SA258
1
0
0
0
0
0
0
1
0
128/64
1020000–102FFFF
SA259
1
0
0
0
0
0
0
1
1
128/64
1030000–103FFFF
SA260
1
0
0
0
0
0
1
0
0
128/64
1040000–104FFFF
SA261
1
0
0
0
0
0
1
0
1
128/64
1050000–105FFFF
SA262
1
0
0
0
0
0
1
1
0
128/64
1060000–106FFFF
SA263
1
0
0
0
0
0
1
1
1
128/64
1070000–107FFFF
SA264
1
0
0
0
0
1
0
0
0
128/64
1080000–108FFFF
SA265
1
0
0
0
0
1
0
0
1
128/64
1090000–109FFFF
SA266
1
0
0
0
0
1
0
1
0
128/64
10A0000–10AFFFF
SA267
1
0
0
0
0
1
0
1
1
128/64
10B0000–10BFFFF
SA268
1
0
0
0
0
1
1
0
0
128/64
10C0000–10CFFFF
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
33
A d v a n c e
Table 2.
Sector Address Table–S29GL512N (Continued)
Sector
34
I n f o r m a t i o n
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA269
1
0
0
0
0
1
1
0
1
128/64
10D0000–10DFFFF
SA270
1
0
0
0
0
1
1
1
0
128/64
10E0000–10EFFFF
SA271
1
0
0
0
0
1
1
1
1
128/64
10F0000–10FFFFF
SA272
1
0
0
0
1
0
0
0
0
128/64
1100000–110FFFF
SA273
1
0
0
0
1
0
0
0
1
128/64
1110000–111FFFF
SA274
1
0
0
0
1
0
0
1
0
128/64
1120000–112FFFF
SA275
1
0
0
0
1
0
0
1
1
128/64
1130000–113FFFF
SA276
1
0
0
0
1
0
1
0
0
128/64
1140000–114FFFF
SA277
1
0
0
0
1
0
1
0
1
128/64
1150000–115FFFF
SA278
1
0
0
0
1
0
1
1
0
128/64
1160000–116FFFF
SA279
1
0
0
0
1
0
1
1
1
128/64
1170000–117FFFF
SA280
1
0
0
0
1
1
0
0
0
128/64
1180000–118FFFF
SA281
1
0
0
0
1
1
0
0
1
128/64
1190000–119FFFF
SA282
1
0
0
0
1
1
0
1
0
128/64
11A0000–11AFFFF
SA283
1
0
0
0
1
1
0
1
1
128/64
11B0000–11BFFFF
SA284
1
0
0
0
1
1
1
0
0
128/64
11C0000–11CFFFF
SA285
1
0
0
0
1
1
1
0
1
128/64
11D0000–11DFFFF
SA286
1
0
0
0
1
1
1
1
0
128/64
11E0000–11EFFFF
SA287
1
0
0
0
1
1
1
1
1
128/64
11F0000–11FFFFF
SA288
1
0
0
1
0
0
0
0
0
128/64
1200000–120FFFF
SA289
1
0
0
1
0
0
0
0
1
128/64
1210000–121FFFF
SA290
1
0
0
1
0
0
0
1
0
128/64
1220000–122FFFF
SA291
1
0
0
1
0
0
0
1
1
128/64
1230000–123FFFF
SA292
1
0
0
1
0
0
1
0
0
128/64
1240000–124FFFF
SA293
1
0
0
1
0
0
1
0
1
128/64
1250000–125FFFF
SA294
1
0
0
1
0
0
1
1
0
128/64
1260000–126FFFF
SA295
1
0
0
1
0
0
1
1
1
128/64
1270000–127FFFF
SA296
1
0
0
1
0
1
0
0
0
128/64
1280000–128FFFF
SA297
1
0
0
1
0
1
0
0
1
128/64
1290000–129FFFF
SA298
1
0
0
1
0
1
0
1
0
128/64
12A0000–12AFFFF
SA299
1
0
0
1
0
1
0
1
1
128/64
12B0000–12BFFFF
SA300
1
0
0
1
0
1
1
0
0
128/64
12C0000–12CFFFF
SA301
1
0
0
1
0
1
1
0
1
128/64
12D0000–12DFFFF
SA302
1
0
0
1
0
1
1
1
0
128/64
12E0000–12EFFFF
SA303
1
0
0
1
0
1
1
1
1
128/64
12F0000–12FFFFF
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 2.
I n f o r m a t i o n
Sector Address Table–S29GL512N (Continued)
Sector
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA304
1
0
0
1
1
0
0
0
0
128/64
1300000–130FFFF
SA305
1
0
0
1
1
0
0
0
1
128/64
1310000–131FFFF
SA306
1
0
0
1
1
0
0
1
0
128/64
1320000–132FFFF
SA307
1
0
0
1
1
0
0
1
1
128/64
1330000–133FFFF
SA308
1
0
0
1
1
0
1
0
0
128/64
1340000–134FFFF
SA309
1
0
0
1
1
0
1
0
1
128/64
1350000–135FFFF
SA310
1
0
0
1
1
0
1
1
0
128/64
1360000–136FFFF
SA311
1
0
0
1
1
0
1
1
1
128/64
1370000–137FFFF
SA312
1
0
0
1
1
1
0
0
0
128/64
1380000–138FFFF
SA313
1
0
0
1
1
1
0
0
1
128/64
1390000–139FFFF
SA314
1
0
0
1
1
1
0
1
0
128/64
13A0000–13AFFFF
SA315
1
0
0
1
1
1
0
1
1
128/64
13B0000–13BFFFF
SA316
1
0
0
1
1
1
1
0
0
128/64
13C0000–13CFFFF
SA317
1
0
0
1
1
1
1
0
1
128/64
13D0000–13DFFFF
SA318
1
0
0
1
1
1
1
1
0
128/64
13E0000–13EFFFF
SA319
1
0
0
1
1
1
1
1
1
128/64
13F0000–13FFFFF
SA320
1
0
1
0
0
0
0
0
0
128/64
1400000–140FFFF
SA321
1
0
1
0
0
0
0
0
1
128/64
1410000–141FFFF
SA322
1
0
1
0
0
0
0
1
0
128/64
1420000–142FFFF
SA323
1
0
1
0
0
0
0
1
1
128/64
1430000–143FFFF
SA324
1
0
1
0
0
0
1
0
0
128/64
1440000–144FFFF
SA325
1
0
1
0
0
0
1
0
1
128/64
1450000–145FFFF
SA326
1
0
1
0
0
0
1
1
0
128/64
1460000–146FFFF
SA327
1
0
1
0
0
0
1
1
1
128/64
1470000–147FFFF
SA328
1
0
1
0
0
1
0
0
0
128/64
1480000–148FFFF
SA329
1
0
1
0
0
1
0
0
1
128/64
1490000–149FFFF
SA330
1
0
1
0
0
1
0
1
0
128/64
14A0000–14AFFFF
SA331
1
0
1
0
0
1
0
1
1
128/64
14B0000–14BFFFF
SA332
1
0
1
0
0
1
1
0
0
128/64
14C0000–14CFFFF
SA333
1
0
1
0
0
1
1
0
1
128/64
14D0000–14DFFFF
SA334
1
0
1
0
0
1
1
1
0
128/64
14E0000–14EFFFF
SA335
1
0
1
0
0
1
1
1
1
128/64
14F0000–14FFFFF
SA336
1
0
1
0
1
0
0
0
0
128/64
1500000–150FFFF
SA337
1
0
1
0
1
0
0
0
1
128/64
1510000–151FFFF
SA338
1
0
1
0
1
0
0
1
0
128/64
1520000–152FFFF
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
35
A d v a n c e
Table 2.
Sector Address Table–S29GL512N (Continued)
Sector
36
I n f o r m a t i o n
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA339
1
0
1
0
1
0
0
1
1
128/64
1530000–153FFFF
SA340
1
0
1
0
1
0
1
0
0
128/64
1540000–154FFFF
SA341
1
0
1
0
1
0
1
0
1
128/64
1550000–155FFFF
SA342
1
0
1
0
1
0
1
1
0
128/64
1560000–156FFFF
SA343
1
0
1
0
1
0
1
1
1
128/64
1570000–157FFFF
SA344
1
0
1
0
1
1
0
0
0
128/64
1580000–158FFFF
SA345
1
0
1
0
1
1
0
0
1
128/64
1590000–159FFFF
SA346
1
0
1
0
1
1
0
1
0
128/64
15A0000–15AFFFF
SA347
1
0
1
0
1
1
0
1
1
128/64
15B0000–15BFFFF
SA348
1
0
1
0
1
1
1
0
0
128/64
15C0000–15CFFFF
SA349
1
0
1
0
1
1
1
0
1
128/64
15D0000–15DFFFF
SA350
1
0
1
0
1
1
1
1
0
128/64
15E0000–15EFFFF
SA351
1
0
1
0
1
1
1
1
1
128/64
15F0000–15FFFFF
SA352
1
0
1
1
0
0
0
0
0
128/64
1600000–160FFFF
SA353
1
0
1
1
0
0
0
0
1
128/64
1610000–161FFFF
SA354
1
0
1
1
0
0
0
1
0
128/64
1620000–162FFFF
SA355
1
0
1
1
0
0
0
1
1
128/64
1630000–163FFFF
SA356
1
0
1
1
0
0
1
0
0
128/64
1640000–164FFFF
SA357
1
0
1
1
0
0
1
0
1
128/64
1650000–165FFFF
SA358
1
0
1
1
0
0
1
1
0
128/64
1660000–166FFFF
SA359
1
0
1
1
0
0
1
1
1
128/64
1670000–167FFFF
SA360
1
0
1
1
0
1
0
0
0
128/64
1680000–168FFFF
SA361
1
0
1
1
0
1
0
0
1
128/64
1690000–169FFFF
SA362
1
0
1
1
0
1
0
1
0
128/64
16A0000–16AFFFF
SA363
1
0
1
1
0
1
0
1
1
128/64
16B0000–16BFFFF
SA364
1
0
1
1
0
1
1
0
0
128/64
16C0000–16CFFFF
SA365
1
0
1
1
0
1
1
0
1
128/64
16D0000–16DFFFF
SA366
1
0
1
1
0
1
1
1
0
128/64
16E0000–16EFFFF
SA367
1
0
1
1
0
1
1
1
1
128/64
16F0000–16FFFFF
SA368
1
0
1
1
1
0
0
0
0
128/64
1700000–170FFFF
SA369
1
0
1
1
1
0
0
0
1
128/64
1710000–171FFFF
SA370
1
0
1
1
1
0
0
1
0
128/64
1720000–172FFFF
SA371
1
0
1
1
1
0
0
1
1
128/64
1730000–173FFFF
SA372
1
0
1
1
1
0
1
0
0
128/64
1740000–174FFFF
SA373
1
0
1
1
1
0
1
0
1
128/64
1750000–175FFFF
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 2.
I n f o r m a t i o n
Sector Address Table–S29GL512N (Continued)
Sector
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA374
1
0
1
1
1
0
1
1
0
128/64
1760000–176FFFF
SA375
1
0
1
1
1
0
1
1
1
128/64
1770000–177FFFF
SA376
1
0
1
1
1
1
0
0
0
128/64
1780000–178FFFF
SA377
1
0
1
1
1
1
0
0
1
128/64
1790000–179FFFF
SA378
1
0
1
1
1
1
0
1
0
128/64
17A0000–17AFFFF
SA379
1
0
1
1
1
1
0
1
1
128/64
17B0000–17BFFFF
SA380
1
0
1
1
1
1
1
0
0
128/64
17C0000–17CFFFF
SA381
1
0
1
1
1
1
1
0
1
128/64
17D0000–17DFFFF
SA382
1
0
1
1
1
1
1
1
0
128/64
17E0000–17EFFFF
SA383
1
0
1
1
1
1
1
1
1
128/64
17F0000–17FFFFF
SA384
1
1
0
0
0
0
0
0
0
128/64
1800000–180FFFF
SA385
1
1
0
0
0
0
0
0
1
128/64
1810000–181FFFF
SA386
1
1
0
0
0
0
0
1
0
128/64
1820000–182FFFF
SA387
1
1
0
0
0
0
0
1
1
128/64
1830000–183FFFF
SA388
1
1
0
0
0
0
1
0
0
128/64
1840000–184FFFF
SA389
1
1
0
0
0
0
1
0
1
128/64
1850000–185FFFF
SA390
1
1
0
0
0
0
1
1
0
128/64
1860000–186FFFF
SA391
1
1
0
0
0
0
1
1
1
128/64
1870000–187FFFF
SA392
1
1
0
0
0
1
0
0
0
128/64
1880000–188FFFF
SA393
1
1
0
0
0
1
0
0
1
128/64
1890000–189FFFF
SA394
1
1
0
0
0
1
0
1
0
128/64
18A0000–18AFFFF
SA395
1
1
0
0
0
1
0
1
1
128/64
18B0000–18BFFFF
SA396
1
1
0
0
0
1
1
0
0
128/64
18C0000–18CFFFF
SA397
1
1
0
0
0
1
1
0
1
128/64
18D0000–18DFFFF
SA398
1
1
0
0
0
1
1
1
0
128/64
18E0000–18EFFFF
SA399
1
1
0
0
0
1
1
1
1
128/64
18F0000–18FFFFF
SA400
1
1
0
0
1
0
0
0
0
128/64
1900000–190FFFF
SA401
1
1
0
0
1
0
0
0
1
128/64
1910000–191FFFF
SA402
1
1
0
0
1
0
0
1
0
128/64
1920000–192FFFF
SA403
1
1
0
0
1
0
0
1
1
128/64
1930000–193FFFF
SA404
1
1
0
0
1
0
1
0
0
128/64
1940000–194FFFF
SA405
1
1
0
0
1
0
1
0
1
128/64
1950000–195FFFF
SA406
1
1
0
0
1
0
1
1
0
128/64
1960000–196FFFF
SA407
1
1
0
0
1
0
1
1
1
128/64
1970000–197FFFF
SA408
1
1
0
0
1
1
0
0
0
128/64
1980000–198FFFF
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
37
A d v a n c e
Table 2.
Sector Address Table–S29GL512N (Continued)
Sector
38
I n f o r m a t i o n
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA409
1
1
0
0
1
1
0
0
1
128/64
1990000–199FFFF
SA410
1
1
0
0
1
1
0
1
0
128/64
19A0000–19AFFFF
SA411
1
1
0
0
1
1
0
1
1
128/64
19B0000–19BFFFF
SA412
1
1
0
0
1
1
1
0
0
128/64
19C0000–19CFFFF
SA413
1
1
0
0
1
1
1
0
1
128/64
19D0000–19DFFFF
SA414
1
1
0
0
1
1
1
1
0
128/64
19E0000–19EFFFF
SA415
1
1
0
0
1
1
1
1
1
128/64
19F0000–19FFFFF
SA416
1
1
0
1
0
0
0
0
0
128/64
1A00000–1A0FFFF
SA417
1
1
0
1
0
0
0
0
1
128/64
1A10000–1A1FFFF
SA418
1
1
0
1
0
0
0
1
0
128/64
1A20000–1A2FFFF
SA419
1
1
0
1
0
0
0
1
1
128/64
1A30000–1A3FFFF
SA420
1
1
0
1
0
0
1
0
0
128/64
1A40000–1A4FFFF
SA421
1
1
0
1
0
0
1
0
1
128/64
1A50000–1A5FFFF
SA422
1
1
0
1
0
0
1
1
0
128/64
1A60000–1A6FFFF
SA423
1
1
0
1
0
0
1
1
1
128/64
1A70000–1A7FFFF
SA424
1
1
0
1
0
1
0
0
0
128/64
1A80000–1A8FFFF
SA425
1
1
0
1
0
1
0
0
1
128/64
1A90000–1A9FFFF
SA426
1
1
0
1
0
1
0
1
0
128/64
1AA0000–1AAFFFF
SA427
1
1
0
1
0
1
0
1
1
128/64
1AB0000–1ABFFFF
SA428
1
1
0
1
0
1
1
0
0
128/64
1AC0000–1ACFFFF
SA429
1
1
0
1
0
1
1
0
1
128/64
1AD0000–1ADFFFF
SA430
1
1
0
1
0
1
1
1
0
128/64
1AE0000–1AEFFFF
SA431
1
1
0
1
0
1
1
1
1
128/64
1AF0000–1AFFFFF
SA432
1
1
0
1
1
0
0
0
0
128/64
1B00000–1B0FFFF
SA433
1
1
0
1
1
0
0
0
1
128/64
1B10000–1B1FFFF
SA434
1
1
0
1
1
0
0
1
0
128/64
1B20000–1B2FFFF
SA435
1
1
0
1
1
0
0
1
1
128/64
1B30000–1B3FFFF
SA436
1
1
0
1
1
0
1
0
0
128/64
1B40000–1B4FFFF
SA437
1
1
0
1
1
0
1
0
1
128/64
1B50000–1B5FFFF
SA438
1
1
0
1
1
0
1
1
0
128/64
1B60000–1B6FFFF
SA439
1
1
0
1
1
0
1
1
1
128/64
1B70000–1B7FFFF
SA440
1
1
0
1
1
1
0
0
0
128/64
1B80000–1B8FFFF
SA441
1
1
0
1
1
1
0
0
1
128/64
1B90000–1B9FFFF
SA442
1
1
0
1
1
1
0
1
0
128/64
1BA0000–1BAFFFF
SA443
1
1
0
1
1
1
0
1
1
128/64
1BB0000–1BBFFFF
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 2.
I n f o r m a t i o n
Sector Address Table–S29GL512N (Continued)
Sector
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA444
1
1
0
1
1
1
1
0
0
128/64
1BC0000–1BCFFFF
SA445
1
1
0
1
1
1
1
0
1
128/64
1BD0000–1BDFFFF
SA446
1
1
0
1
1
1
1
1
0
128/64
1BE0000–1BEFFFF
SA447
1
1
0
1
1
1
1
1
1
128/64
1BF0000–1BFFFFF
SA448
1
1
1
0
0
0
0
0
0
128/64
1C00000–1C0FFFF
SA449
1
1
1
0
0
0
0
0
1
128/64
1C10000–1C1FFFF
SA450
1
1
1
0
0
0
0
1
0
128/64
1C20000–1C2FFFF
SA451
1
1
1
0
0
0
0
1
1
128/64
1C30000–1C3FFFF
SA452
1
1
1
0
0
0
1
0
0
128/64
1C40000–1C4FFFF
SA453
1
1
1
0
0
0
1
0
1
128/64
1C50000–1C5FFFF
SA454
1
1
1
0
0
0
1
1
0
128/64
1C60000–1C6FFFF
SA455
1
1
1
0
0
0
1
1
1
128/64
1C70000–1C7FFFF
SA456
1
1
1
0
0
1
0
0
0
128/64
1C80000–1C8FFFF
SA457
1
1
1
0
0
1
0
0
1
128/64
1C90000–1C9FFFF
SA458
1
1
1
0
0
1
0
1
0
128/64
1CA0000–1CAFFFF
SA459
1
1
1
0
0
1
0
1
1
128/64
1CB0000–1CBFFFF
SA460
1
1
1
0
0
1
1
0
0
128/64
1CC0000–1CCFFFF
SA461
1
1
1
0
0
1
1
0
1
128/64
1CD0000–1CDFFFF
SA462
1
1
1
0
0
1
1
1
0
128/64
1CE0000–1CEFFFF
SA463
1
1
1
0
0
1
1
1
1
128/64
1CF0000–1CFFFFF
SA464
1
1
1
0
1
0
0
0
0
128/64
1D00000–1D0FFFF
SA465
1
1
1
0
1
0
0
0
1
128/64
1D10000–1D1FFFF
SA466
1
1
1
0
1
0
0
1
0
128/64
1D20000–1D2FFFF
SA467
1
1
1
0
1
0
0
1
1
128/64
1D30000–1D3FFFF
SA468
1
1
1
0
1
0
1
0
0
128/64
1D40000–1D4FFFF
SA469
1
1
1
0
1
0
1
0
1
128/64
1D50000–1D5FFFF
SA470
1
1
1
0
1
0
1
1
0
128/64
1D60000–1D6FFFF
SA471
1
1
1
0
1
0
1
1
1
128/64
1D70000–1D7FFFF
SA472
1
1
1
0
1
1
0
0
0
128/64
1D80000–1D8FFFF
SA473
1
1
1
0
1
1
0
0
1
128/64
1D90000–1D9FFFF
SA474
1
1
1
0
1
1
0
1
0
128/64
1DA0000–1DAFFFF
SA475
1
1
1
0
1
1
0
1
1
128/64
1DB0000–1DBFFFF
SA476
1
1
1
0
1
1
1
0
0
128/64
1DC0000–1DCFFFF
SA477
1
1
1
0
1
1
1
0
1
128/64
1DD0000–1DDFFFF
SA478
1
1
1
0
1
1
1
1
0
128/64
1DE0000–1DEFFFF
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
39
A d v a n c e
Table 2.
Sector Address Table–S29GL512N (Continued)
Sector
40
I n f o r m a t i o n
A24–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA479
1
1
1
0
1
1
1
1
1
128/64
1DF0000–1DFFFFF
SA480
1
1
1
1
0
0
0
0
0
128/64
1E00000–1E0FFFF
SA481
1
1
1
1
0
0
0
0
1
128/64
1E10000–1E1FFFF
SA482
1
1
1
1
0
0
0
1
0
128/64
1E20000–1E2FFFF
SA483
1
1
1
1
0
0
0
1
1
128/64
1E30000–1E3FFFF
SA484
1
1
1
1
0
0
1
0
0
128/64
1E40000–1E4FFFF
SA485
1
1
1
1
0
0
1
0
1
128/64
1E50000–1E5FFFF
SA486
1
1
1
1
0
0
1
1
0
128/64
1E60000–1E6FFFF
SA487
1
1
1
1
0
0
1
1
1
128/64
1E70000–1E7FFFF
SA488
1
1
1
1
0
1
0
0
0
128/64
1E80000–1E8FFFF
SA489
1
1
1
1
0
1
0
0
1
128/64
1E90000–1E9FFFF
SA490
1
1
1
1
0
1
0
1
0
128/64
1EA0000–1EAFFFF
SA491
1
1
1
1
0
1
0
1
1
128/64
1EB0000–1EBFFFF
SA492
1
1
1
1
0
1
1
0
0
128/64
1EC0000–1ECFFFF
SA493
1
1
1
1
0
1
1
0
1
128/64
1ED0000–1EDFFFF
SA494
1
1
1
1
0
1
1
1
0
128/64
1EE0000–1EEFFFF
SA495
1
1
1
1
0
1
1
1
1
128/64
1EF0000–1EFFFFF
SA496
1
1
1
1
1
0
0
0
0
128/64
1F00000–1F0FFFF
SA497
1
1
1
1
1
0
0
0
1
128/64
1F10000–1F1FFFF
SA498
1
1
1
1
1
0
0
1
0
128/64
1F20000–1F2FFFF
SA499
1
1
1
1
1
0
0
1
1
128/64
1F30000–1F3FFFF
SA500
1
1
1
1
1
0
1
0
0
128/64
1F40000–1F4FFFF
SA501
1
1
1
1
1
0
1
0
1
128/64
1F50000–1F5FFFF
SA502
1
1
1
1
1
0
1
1
0
128/64
1F60000–1F6FFFF
SA503
1
1
1
1
1
0
1
1
1
128/64
1F70000–1F7FFFF
SA504
1
1
1
1
1
1
0
0
0
128/64
1F80000–1F8FFFF
SA505
1
1
1
1
1
1
0
0
1
128/64
1F90000–1F9FFFF
SA506
1
1
1
1
1
1
0
1
0
128/64
1FA0000–1FAFFFF
SA507
1
1
1
1
1
1
0
1
1
128/64
1FB0000–1FBFFFF
SA508
1
1
1
1
1
1
1
0
0
128/64
1FC0000–1FCFFFF
SA509
1
1
1
1
1
1
1
0
1
128/64
1FD0000–1FDFFFF
SA510
1
1
1
1
1
1
1
1
0
128/64
1FE0000–1FEFFFF
SA511
1
1
1
1
1
1
1
1
1
128/64
1FF0000–1FFFFFF
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 3.
Sector
I n f o r m a t i o n
Sector Address Table–S29GL256N
A23–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA0
0
0
0
0
0
0
0
0
128/64
0000000–000FFFF
SA1
0
0
0
0
0
0
0
1
128/64
0010000–001FFFF
SA2
0
0
0
0
0
0
1
0
128/64
0020000–002FFFF
SA3
0
0
0
0
0
0
1
1
128/64
0030000–003FFFF
SA4
0
0
0
0
0
1
0
0
128/64
0040000–004FFFF
SA5
0
0
0
0
0
1
0
1
128/64
0050000–005FFFF
SA6
0
0
0
0
0
1
1
0
128/64
0060000–006FFFF
SA7
0
0
0
0
0
1
1
1
128/64
0070000–007FFFF
SA8
0
0
0
0
1
0
0
0
128/64
0080000–008FFFF
SA9
0
0
0
0
1
0
0
1
128/64
0090000–009FFFF
SA10
0
0
0
0
1
0
1
0
128/64
00A0000–00AFFFF
SA11
0
0
0
0
1
0
1
1
128/64
00B0000–00BFFFF
SA12
0
0
0
0
1
1
0
0
128/64
00C0000–00CFFFF
SA13
0
0
0
0
1
1
0
1
128/64
00D0000–00DFFFF
SA14
0
0
0
0
1
1
1
0
128/64
00E0000–00EFFFF
SA15
0
0
0
0
1
1
1
1
128/64
00F0000–00FFFFF
SA16
0
0
0
1
0
0
0
0
128/64
0100000–010FFFF
SA17
0
0
0
1
0
0
0
1
128/64
0110000–011FFFF
SA18
0
0
0
1
0
0
1
0
128/64
0120000–012FFFF
SA19
0
0
0
1
0
0
1
1
128/64
0130000–013FFFF
SA20
0
0
0
1
0
1
0
0
128/64
0140000–014FFFF
SA21
0
0
0
1
0
1
0
1
128/64
0150000–015FFFF
SA22
0
0
0
1
0
1
1
0
128/64
0160000–016FFFF
SA23
0
0
0
1
0
1
1
1
128/64
0170000–017FFFF
SA24
0
0
0
1
1
0
0
0
128/64
0180000–018FFFF
SA25
0
0
0
1
1
0
0
1
128/64
0190000–019FFFF
SA26
0
0
0
1
1
0
1
0
128/64
01A0000–01AFFFF
SA27
0
0
0
1
1
0
1
1
128/64
01B0000–01BFFFF
SA28
0
0
0
1
1
1
0
0
128/64
01C0000–01CFFFF
SA29
0
0
0
1
1
1
0
1
128/64
01D0000–01DFFFF
SA30
0
0
0
1
1
1
1
0
128/64
01E0000–01EFFFF
SA31
0
0
0
1
1
1
1
1
128/64
01F0000–01FFFFF
SA32
0
0
1
0
0
0
0
0
128/64
0200000–020FFFF
SA33
0
0
1
0
0
0
0
1
128/64
0210000–021FFFF
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
41
A d v a n c e
Table 3.
Sector Address Table–S29GL256N (Continued)
Sector
42
I n f o r m a t i o n
A23–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA34
0
0
1
0
0
0
1
0
128/64
0220000–022FFFF
SA35
0
0
1
0
0
0
1
1
128/64
0230000–023FFFF
SA36
0
0
1
0
0
1
0
0
128/64
0240000–024FFFF
SA37
0
0
1
0
0
1
0
1
128/64
0250000–025FFFF
SA38
0
0
1
0
0
1
1
0
128/64
0260000–026FFFF
SA39
0
0
1
0
0
1
1
1
128/64
0270000–027FFFF
SA40
0
0
1
0
1
0
0
0
128/64
0280000–028FFFF
SA41
0
0
1
0
1
0
0
1
128/64
0290000–029FFFF
SA42
0
0
1
0
1
0
1
0
128/64
02A0000–02AFFFF
SA43
0
0
1
0
1
0
1
1
128/64
02B0000–02BFFFF
SA44
0
0
1
0
1
1
0
0
128/64
02C0000–02CFFFF
SA45
0
0
1
0
1
1
0
1
128/64
02D0000–02DFFFF
SA46
0
0
1
0
1
1
1
0
128/64
02E0000–02EFFFF
SA47
0
0
1
0
1
1
1
1
128/64
02F0000–02FFFFF
SA48
0
0
1
1
0
0
0
0
128/64
0300000–030FFFF
SA49
0
0
1
1
0
0
0
1
128/64
0310000–031FFFF
SA50
0
0
1
1
0
0
1
0
128/64
0320000–032FFFF
SA51
0
0
1
1
0
0
1
1
128/64
0330000–033FFFF
SA52
0
0
1
1
0
1
0
0
128/64
0340000–034FFFF
SA53
0
0
1
1
0
1
0
1
128/64
0350000–035FFFF
SA54
0
0
1
1
0
1
1
0
128/64
0360000–036FFFF
SA55
0
0
1
1
0
1
1
1
128/64
0370000–037FFFF
SA56
0
0
1
1
1
0
0
0
128/64
0380000–038FFFF
SA57
0
0
1
1
1
0
0
1
128/64
0390000–039FFFF
SA58
0
0
1
1
1
0
1
0
128/64
03A0000–03AFFFF
SA59
0
0
1
1
1
0
1
1
128/64
03B0000–03BFFFF
SA60
0
0
1
1
1
1
0
0
128/64
03C0000–03CFFFF
SA61
0
0
1
1
1
1
0
1
128/64
03D0000–03DFFFF
SA62
0
0
1
1
1
1
1
0
128/64
03E0000–03EFFFF
SA63
0
0
1
1
1
1
1
1
128/64
03F0000–03FFFFF
SA64
0
1
0
0
0
0
0
0
128/64
0400000–040FFFF
SA65
0
1
0
0
0
0
0
1
128/64
0410000–041FFFF
SA66
0
1
0
0
0
0
1
0
128/64
0420000–042FFFF
SA67
0
1
0
0
0
0
1
1
128/64
0430000–043FFFF
SA68
0
1
0
0
0
1
0
0
128/64
0440000–044FFFF
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 3.
I n f o r m a t i o n
Sector Address Table–S29GL256N (Continued)
Sector
A23–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA69
0
1
0
0
0
1
0
1
128/64
0450000–045FFFF
SA70
0
1
0
0
0
1
1
0
128/64
0460000–046FFFF
SA71
0
1
0
0
0
1
1
1
128/64
0470000–047FFFF
SA72
0
1
0
0
1
0
0
0
128/64
0480000–048FFFF
SA73
0
1
0
0
1
0
0
1
128/64
0490000–049FFFF
SA74
0
1
0
0
1
0
1
0
128/64
04A0000–04AFFFF
SA75
0
1
0
0
1
0
1
1
128/64
04B0000–04BFFFF
SA76
0
1
0
0
1
1
0
0
128/64
04C0000–04CFFFF
SA77
0
1
0
0
1
1
0
1
128/64
04D0000–04DFFFF
SA78
0
1
0
0
1
1
1
0
128/64
04E0000–04EFFFF
SA79
0
1
0
0
1
1
1
1
128/64
04F0000–04FFFFF
SA80
0
1
0
1
0
0
0
0
128/64
0500000–050FFFF
SA81
0
1
0
1
0
0
0
1
128/64
0510000–051FFFF
SA82
0
1
0
1
0
0
1
0
128/64
0520000–052FFFF
SA83
0
1
0
1
0
0
1
1
128/64
0530000–053FFFF
SA84
0
1
0
1
0
1
0
0
128/64
0540000–054FFFF
SA85
0
1
0
1
0
1
0
1
128/64
0550000–055FFFF
SA86
0
1
0
1
0
1
1
0
128/64
0560000–056FFFF
SA87
0
1
0
1
0
1
1
1
128/64
0570000–057FFFF
SA88
0
1
0
1
1
0
0
0
128/64
0580000–058FFFF
SA89
0
1
0
1
1
0
0
1
128/64
0590000–059FFFF
SA90
0
1
0
1
1
0
1
0
128/64
05A0000–05AFFFF
SA91
0
1
0
1
1
0
1
1
128/64
05B0000–05BFFFF
SA92
0
1
0
1
1
1
0
0
128/64
05C0000–05CFFFF
SA93
0
1
0
1
1
1
0
1
128/64
05D0000–05DFFFF
SA94
0
1
0
1
1
1
1
0
128/64
05E0000–05EFFFF
SA95
0
1
0
1
1
1
1
1
128/64
05F0000–05FFFFF
SA96
0
1
1
0
0
0
0
0
128/64
0600000–060FFFF
SA97
0
1
1
0
0
0
0
1
128/64
0610000–061FFFF
SA98
0
1
1
0
0
0
1
0
128/64
0620000–062FFFF
SA99
0
1
1
0
0
0
1
1
128/64
0630000–063FFFF
SA100
0
1
1
0
0
1
0
0
128/64
0640000–064FFFF
SA101
0
1
1
0
0
1
0
1
128/64
0650000–065FFFF
SA102
0
1
1
0
0
1
1
0
128/64
0660000–066FFFF
SA103
0
1
1
0
0
1
1
1
128/64
0670000–067FFFF
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
43
A d v a n c e
Table 3.
Sector Address Table–S29GL256N (Continued)
Sector
44
I n f o r m a t i o n
A23–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA104
0
1
1
0
1
0
0
0
128/64
0680000–068FFFF
SA105
0
1
1
0
1
0
0
1
128/64
0690000–069FFFF
SA106
0
1
1
0
1
0
1
0
128/64
06A0000–06AFFFF
SA107
0
1
1
0
1
0
1
1
128/64
06B0000–06BFFFF
SA108
0
1
1
0
1
1
0
0
128/64
06C0000–06CFFFF
SA109
0
1
1
0
1
1
0
1
128/64
06D0000–06DFFFF
SA110
0
1
1
0
1
1
1
0
128/64
06E0000–06EFFFF
SA111
0
1
1
0
1
1
1
1
128/64
06F0000–06FFFFF
SA112
0
1
1
1
0
0
0
0
128/64
0700000–070FFFF
SA113
0
1
1
1
0
0
0
1
128/64
0710000–071FFFF
SA114
0
1
1
1
0
0
1
0
128/64
0720000–072FFFF
SA115
0
1
1
1
0
0
1
1
128/64
0730000–073FFFF
SA116
0
1
1
1
0
1
0
0
128/64
0740000–074FFFF
SA117
0
1
1
1
0
1
0
1
128/64
0750000–075FFFF
SA118
0
1
1
1
0
1
1
0
128/64
0760000–076FFFF
SA119
0
1
1
1
0
1
1
1
128/64
0770000–077FFFF
SA120
0
1
1
1
1
0
0
0
128/64
0780000–078FFFF
SA121
0
1
1
1
1
0
0
1
128/64
0790000–079FFFF
SA122
0
1
1
1
1
0
1
0
128/64
07A0000–07AFFFF
SA123
0
1
1
1
1
0
1
1
128/64
07B0000–07BFFFF
SA124
0
1
1
1
1
1
0
0
128/64
07C0000–07CFFFF
SA125
0
1
1
1
1
1
0
1
128/64
07D0000–07DFFFF
SA126
0
1
1
1
1
1
1
0
128/64
07E0000–07EFFFF
SA127
0
1
1
1
1
1
1
1
128/64
07F0000–07FFFFF
SA128
1
0
0
0
0
0
0
0
128/64
0800000–080FFFF
SA129
1
0
0
0
0
0
0
1
128/64
0810000–081FFFF
SA130
1
0
0
0
0
0
1
0
128/64
0820000–082FFFF
SA131
1
0
0
0
0
0
1
1
128/64
0830000–083FFFF
SA132
1
0
0
0
0
1
0
0
128/64
0840000–084FFFF
SA133
1
0
0
0
0
1
0
1
128/64
0850000–085FFFF
SA134
1
0
0
0
0
1
1
0
128/64
0860000–086FFFF
SA135
1
0
0
0
0
1
1
1
128/64
0870000–087FFFF
SA136
1
0
0
0
1
0
0
0
128/64
0880000–088FFFF
SA137
1
0
0
0
1
0
0
1
128/64
0890000–089FFFF
SA138
1
0
0
0
1
0
1
0
128/64
08A0000–08AFFFF
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 3.
I n f o r m a t i o n
Sector Address Table–S29GL256N (Continued)
Sector
A23–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA139
1
0
0
0
1
0
1
1
128/64
08B0000–08BFFFF
SA140
1
0
0
0
1
1
0
0
128/64
08C0000–08CFFFF
SA141
1
0
0
0
1
1
0
1
128/64
08D0000–08DFFFF
SA142
1
0
0
0
1
1
1
0
128/64
08E0000–08EFFFF
SA143
1
0
0
0
1
1
1
1
128/64
08F0000–08FFFFF
SA144
1
0
0
1
0
0
0
0
128/64
0900000–090FFFF
SA145
1
0
0
1
0
0
0
1
128/64
0910000–091FFFF
SA146
1
0
0
1
0
0
1
0
128/64
0920000–092FFFF
SA147
1
0
0
1
0
0
1
1
128/64
0930000–093FFFF
SA148
1
0
0
1
0
1
0
0
128/64
0940000–094FFFF
SA149
1
0
0
1
0
1
0
1
128/64
0950000–095FFFF
SA150
1
0
0
1
0
1
1
0
128/64
0960000–096FFFF
SA151
1
0
0
1
0
1
1
1
128/64
0970000–097FFFF
SA152
1
0
0
1
1
0
0
0
128/64
0980000–098FFFF
SA153
1
0
0
1
1
0
0
1
128/64
0990000–099FFFF
SA154
1
0
0
1
1
0
1
0
128/64
09A0000–09AFFFF
SA155
1
0
0
1
1
0
1
1
128/64
09B0000–09BFFFF
SA156
1
0
0
1
1
1
0
0
128/64
09C0000–09CFFFF
SA157
1
0
0
1
1
1
0
1
128/64
09D0000–09DFFFF
SA158
1
0
0
1
1
1
1
0
128/64
09E0000–09EFFFF
SA159
1
0
0
1
1
1
1
1
128/64
09F0000–09FFFFF
SA160
1
0
1
0
0
0
0
0
128/64
0A00000–0A0FFFF
SA161
1
0
1
0
0
0
0
1
128/64
0A10000–0A1FFFF
SA162
1
0
1
0
0
0
1
0
128/64
0A20000–0A2FFFF
SA163
1
0
1
0
0
0
1
1
128/64
0A30000–0A3FFFF
SA164
1
0
1
0
0
1
0
0
128/64
0A40000–0A4FFFF
SA165
1
0
1
0
0
1
0
1
128/64
0A50000–0A5FFFF
SA166
1
0
1
0
0
1
1
0
128/64
0A60000–0A6FFFF
SA167
1
0
1
0
0
1
1
1
128/64
0A70000–0A7FFFF
SA168
1
0
1
0
1
0
0
0
128/64
0A80000–0A8FFFF
SA169
1
0
1
0
1
0
0
1
128/64
0A90000–0A9FFFF
SA170
1
0
1
0
1
0
1
0
128/64
0AA0000–0AAFFFF
SA171
1
0
1
0
1
0
1
1
128/64
0AB0000–0ABFFFF
SA172
1
0
1
0
1
1
0
0
128/64
0AC0000–0ACFFFF
SA173
1
0
1
0
1
1
0
1
128/64
0AD0000–0ADFFFF
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
45
A d v a n c e
Table 3.
Sector Address Table–S29GL256N (Continued)
Sector
46
I n f o r m a t i o n
A23–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA174
1
0
1
0
1
1
1
0
128/64
0AE0000–0AEFFFF
SA175
1
0
1
0
1
1
1
1
128/64
0AF0000–0AFFFFF
SA176
1
0
1
1
0
0
0
0
128/64
0B00000–0B0FFFF
SA177
1
0
1
1
0
0
0
1
128/64
0B10000–0B1FFFF
SA178
1
0
1
1
0
0
1
0
128/64
0B20000–0B2FFFF
SA179
1
0
1
1
0
0
1
1
128/64
0B30000–0B3FFFF
SA180
1
0
1
1
0
1
0
0
128/64
0B40000–0B4FFFF
SA181
1
0
1
1
0
1
0
1
128/64
0B50000–0B5FFFF
SA182
1
0
1
1
0
1
1
0
128/64
0B60000–0B6FFFF
SA183
1
0
1
1
0
1
1
1
128/64
0B70000–0B7FFFF
SA184
1
0
1
1
1
0
0
0
128/64
0B80000–0B8FFFF
SA185
1
0
1
1
1
0
0
1
128/64
0B90000–0B9FFFF
SA186
1
0
1
1
1
0
1
0
128/64
0BA0000–0BAFFFF
SA187
1
0
1
1
1
0
1
1
128/64
0BB0000–0BBFFFF
SA188
1
0
1
1
1
1
0
0
128/64
0BC0000–0BCFFFF
SA189
1
0
1
1
1
1
0
1
128/64
0BD0000–0BDFFFF
SA190
1
0
1
1
1
1
1
0
128/64
0BE0000–0BEFFFF
SA191
1
0
1
1
1
1
1
1
128/64
0BF0000–0BFFFFF
SA192
1
1
0
0
0
0
0
0
128/64
0C00000–0C0FFFF
SA193
1
1
0
0
0
0
0
1
128/64
0C10000–0C1FFFF
SA194
1
1
0
0
0
0
1
0
128/64
0C20000–0C2FFFF
SA195
1
1
0
0
0
0
1
1
128/64
0C30000–0C3FFFF
SA196
1
1
0
0
0
1
0
0
128/64
0C40000–0C4FFFF
SA197
1
1
0
0
0
1
0
1
128/64
0C50000–0C5FFFF
SA198
1
1
0
0
0
1
1
0
128/64
0C60000–0C6FFFF
SA199
1
1
0
0
0
1
1
1
128/64
0C70000–0C7FFFF
SA200
1
1
0
0
1
0
0
0
128/64
0C80000–0C8FFFF
SA201
1
1
0
0
1
0
0
1
128/64
0C90000–0C9FFFF
SA202
1
1
0
0
1
0
1
0
128/64
0CA0000–0CAFFFF
SA203
1
1
0
0
1
0
1
1
128/64
0CB0000–0CBFFFF
SA204
1
1
0
0
1
1
0
0
128/64
0CC0000–0CCFFFF
SA205
1
1
0
0
1
1
0
1
128/64
0CD0000–0CDFFFF
SA206
1
1
0
0
1
1
1
0
128/64
0CE0000–0CEFFFF
SA207
1
1
0
0
1
1
1
1
128/64
0CF0000–0CFFFFF
SA208
1
1
0
1
0
0
0
0
128/64
0D00000–0D0FFFF
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 3.
I n f o r m a t i o n
Sector Address Table–S29GL256N (Continued)
Sector
A23–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA209
1
1
0
1
0
0
0
1
128/64
0D10000–0D1FFFF
SA210
1
1
0
1
0
0
1
0
128/64
0D20000–0D2FFFF
SA211
1
1
0
1
0
0
1
1
128/64
0D30000–0D3FFFF
SA212
1
1
0
1
0
1
0
0
128/64
0D40000–0D4FFFF
SA213
1
1
0
1
0
1
0
1
128/64
0D50000–0D5FFFF
SA214
1
1
0
1
0
1
1
0
128/64
0D60000–0D6FFFF
SA215
1
1
0
1
0
1
1
1
128/64
0D70000–0D7FFFF
SA216
1
1
0
1
1
0
0
0
128/64
0D80000–0D8FFFF
SA217
1
1
0
1
1
0
0
1
128/64
0D90000–0D9FFFF
SA218
1
1
0
1
1
0
1
0
128/64
0DA0000–0DAFFFF
SA219
1
1
0
1
1
0
1
1
128/64
0DB0000–0DBFFFF
SA220
1
1
0
1
1
1
0
0
128/64
0DC0000–0DCFFFF
SA221
1
1
0
1
1
1
0
1
128/64
0DD0000–0DDFFFF
SA222
1
1
0
1
1
1
1
0
128/64
0DE0000–0DEFFFF
SA223
1
1
0
1
1
1
1
1
128/64
0DF0000–0DFFFFF
SA224
1
1
1
0
0
0
0
0
128/64
0E00000–0E0FFFF
SA225
1
1
1
0
0
0
0
1
128/64
0E10000–0E1FFFF
SA226
1
1
1
0
0
0
1
0
128/64
0E20000–0E2FFFF
SA227
1
1
1
0
0
0
1
1
128/64
0E30000–0E3FFFF
SA228
1
1
1
0
0
1
0
0
128/64
0E40000–0E4FFFF
SA229
1
1
1
0
0
1
0
1
128/64
0E50000–0E5FFFF
SA230
1
1
1
0
0
1
1
0
128/64
0E60000–0E6FFFF
SA231
1
1
1
0
0
1
1
1
128/64
0E70000–0E7FFFF
SA232
1
1
1
0
1
0
0
0
128/64
0E80000–0E8FFFF
SA233
1
1
1
0
1
0
0
1
128/64
0E90000–0E9FFFF
SA234
1
1
1
0
1
0
1
0
128/64
0EA0000–0EAFFFF
SA235
1
1
1
0
1
0
1
1
128/64
0EB0000–0EBFFFF
SA236
1
1
1
0
1
1
0
0
128/64
0EC0000–0ECFFFF
SA237
1
1
1
0
1
1
0
1
128/64
0ED0000–0EDFFFF
SA238
1
1
1
0
1
1
1
0
128/64
0EE0000–0EEFFFF
SA239
1
1
1
0
1
1
1
1
128/64
0EF0000–0EFFFFF
SA240
1
1
1
1
0
0
0
0
128/64
0F00000–0F0FFFF
SA241
1
1
1
1
0
0
0
1
128/64
0F10000–0F1FFFF
SA242
1
1
1
1
0
0
1
0
128/64
0F20000–0F2FFFF
SA243
1
1
1
1
0
0
1
1
128/64
0F30000–0F3FFFF
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
47
A d v a n c e
Table 3.
Sector Address Table–S29GL256N (Continued)
Sector
A23–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA244
1
1
1
1
0
1
0
0
128/64
0F40000–0F4FFFF
SA245
1
1
1
1
0
1
0
1
128/64
0F50000–0F5FFFF
SA246
1
1
1
1
0
1
1
0
128/64
0F60000–0F6FFFF
SA247
1
1
1
1
0
1
1
1
128/64
0F70000–0F7FFFF
SA248
1
1
1
1
1
0
0
0
128/64
0F80000–0F8FFFF
SA249
1
1
1
1
1
0
0
1
128/64
0F90000–0F9FFFF
SA250
1
1
1
1
1
0
1
0
128/64
0FA0000–0FAFFFF
SA251
1
1
1
1
1
0
1
1
128/64
0FB0000–0FBFFFF
SA252
1
1
1
1
1
1
0
0
128/64
0FC0000–0FCFFFF
SA253
1
1
1
1
1
1
0
1
128/64
0FD0000–0FDFFFF
SA254
1
1
1
1
1
1
1
0
128/64
0FE0000–0FEFFFF
SA255
1
1
1
1
1
1
1
1
128/64
0FF0000–0FFFFFF
Table 4.
Sector
48
I n f o r m a t i o n
Sector Address Table–S29GL128N
A22–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA0
0
0
0
0
0
0
128/64
0000000–000FFFF
SA1
0
0
0
0
0
1
128/64
0010000–001FFFF
SA2
0
0
0
0
1
0
128/64
0020000–002FFFF
SA3
0
0
0
0
1
1
128/64
0030000–003FFFF
SA4
0
0
0
1
0
0
128/64
0040000–004FFFF
SA5
0
0
0
1
0
1
128/64
0050000–005FFFF
SA6
0
0
0
1
1
0
128/64
0060000–006FFFF
SA7
0
0
0
1
1
1
128/64
0070000–007FFFF
SA8
0
0
1
0
0
0
128/64
0080000–008FFFF
SA9
0
0
1
0
0
1
128/64
0090000–009FFFF
SA10
0
0
1
0
1
0
128/64
00A0000–00AFFFF
SA11
0
0
1
0
1
1
128/64
00B0000–00BFFFF
SA12
0
0
1
1
0
0
128/64
00C0000–00CFFFF
SA13
0
0
1
1
0
1
128/64
00D0000–00DFFFF
SA14
0
0
1
1
1
0
128/64
00E0000–00EFFFF
SA15
0
0
1
1
1
1
128/64
00F0000–00FFFFF
SA16
0
1
0
0
0
0
128/64
0100000–010FFFF
SA17
0
1
0
0
0
1
128/64
0110000–011FFFF
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 4.
I n f o r m a t i o n
Sector Address Table–S29GL128N (Continued)
Sector
A22–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA18
0
1
0
0
1
0
128/64
0120000–012FFFF
SA19
0
1
0
0
1
1
128/64
0130000–013FFFF
SA20
0
1
0
1
0
0
128/64
0140000–014FFFF
SA21
0
1
0
1
0
1
128/64
0150000–015FFFF
SA22
0
1
0
1
1
0
128/64
0160000–016FFFF
SA23
0
1
0
1
1
1
128/64
0170000–017FFFF
SA24
0
1
1
0
0
0
128/64
0180000–018FFFF
SA25
0
1
1
0
0
1
128/64
0190000–019FFFF
SA26
0
1
1
0
1
0
128/64
01A0000–01AFFFF
SA27
0
1
1
0
1
1
128/64
01B0000–01BFFFF
SA28
0
1
1
1
0
0
128/64
01C0000–01CFFFF
SA29
0
1
1
1
0
1
128/64
01D0000–01DFFFF
SA30
0
1
1
1
1
0
128/64
01E0000–01EFFFF
SA31
0
1
1
1
1
1
128/64
01F0000–01FFFFF
SA32
1
0
0
0
0
0
128/64
0200000–020FFFF
SA33
1
0
0
0
0
1
128/64
0210000–021FFFF
SA34
1
0
0
0
1
0
128/64
0220000–022FFFF
SA35
1
0
0
0
1
1
128/64
0230000–023FFFF
SA36
1
0
0
1
0
0
128/64
0240000–024FFFF
SA37
1
0
0
1
0
1
128/64
0250000–025FFFF
SA38
1
0
0
1
1
0
128/64
0260000–026FFFF
SA39
1
0
0
1
1
1
128/64
0270000–027FFFF
SA40
1
0
1
0
0
0
128/64
0280000–028FFFF
SA41
1
0
1
0
0
1
128/64
0290000–029FFFF
SA42
1
0
1
0
1
0
128/64
02A0000–02AFFFF
SA43
1
0
1
0
1
1
128/64
02B0000–02BFFFF
SA44
1
0
1
1
0
0
128/64
02C0000–02CFFFF
SA45
1
0
1
1
0
1
128/64
02D0000–02DFFFF
SA46
1
0
1
1
1
0
128/64
02E0000–02EFFFF
SA47
1
0
1
1
1
1
128/64
02F0000–02FFFFF
SA48
1
1
0
0
0
0
128/64
0300000–030FFFF
SA49
1
1
0
0
0
1
128/64
0310000–031FFFF
SA50
1
1
0
0
1
0
128/64
0320000–032FFFF
SA51
1
1
0
0
1
1
128/64
0330000–033FFFF
SA52
1
1
0
1
0
0
128/64
0340000–034FFFF
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
49
A d v a n c e
Table 4.
Sector
50
I n f o r m a t i o n
Sector Address Table–S29GL128N (Continued)
A22–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA53
1
1
0
1
0
1
128/64
0350000–035FFFF
SA54
1
1
0
1
1
0
128/64
0360000–036FFFF
SA55
1
1
0
1
1
1
128/64
0370000–037FFFF
SA56
1
1
1
0
0
0
128/64
0380000–038FFFF
SA57
1
1
1
0
0
1
128/64
0390000–039FFFF
SA58
1
1
1
0
1
0
128/64
03A0000–03AFFFF
SA59
1
1
1
0
1
1
128/64
03B0000–03BFFFF
SA60
1
1
1
1
0
0
128/64
03C0000–03CFFFF
SA61
1
1
1
1
0
1
128/64
03D0000–03DFFFF
SA62
1
1
1
1
1
0
128/64
03E0000–03EFFFF
SA63
1
1
1
1
1
1
128/64
03F0000–03FFFFF
SA64
0
0
0
0
0
0
128/64
0400000–040FFFF
SA65
0
0
0
0
0
1
128/64
0410000–041FFFF
SA66
0
0
0
0
1
0
128/64
0420000–042FFFF
SA67
0
0
0
0
1
1
128/64
0430000–043FFFF
SA68
0
0
0
1
0
0
128/64
0440000–044FFFF
SA69
0
0
0
1
0
1
128/64
0450000–045FFFF
SA70
0
0
0
1
1
0
128/64
0460000–046FFFF
SA71
0
0
0
1
1
1
128/64
0470000–047FFFF
SA72
0
0
1
0
0
0
128/64
0480000–048FFFF
SA73
0
0
1
0
0
1
128/64
0490000–049FFFF
SA74
0
0
1
0
1
0
128/64
04A0000–04AFFFF
SA75
0
0
1
0
1
1
128/64
04B0000–04BFFFF
SA76
0
0
1
1
0
0
128/64
04C0000–04CFFFF
SA77
0
0
1
1
0
1
128/64
04D0000–04DFFFF
SA78
0
0
1
1
1
0
128/64
04E0000–04EFFFF
SA79
0
0
1
1
1
1
128/64
04F0000–04FFFFF
SA80
0
1
0
0
0
0
128/64
0500000–050FFFF
SA81
0
1
0
0
0
1
128/64
0510000–051FFFF
SA82
0
1
0
0
1
0
128/64
0520000–052FFFF
SA83
0
1
0
0
1
1
128/64
0530000–053FFFF
SA84
0
1
0
1
0
0
128/64
0540000–054FFFF
SA85
0
1
0
1
0
1
128/64
0550000–055FFFF
SA86
0
1
0
1
1
0
128/64
0560000–056FFFF
SA87
0
1
0
1
1
1
128/64
0570000–057FFFF
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 4.
I n f o r m a t i o n
Sector Address Table–S29GL128N (Continued)
Sector
A22–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA88
0
1
1
0
0
0
128/64
0580000–058FFFF
SA89
0
1
1
0
0
1
128/64
0590000–059FFFF
SA90
0
1
1
0
1
0
128/64
05A0000–05AFFFF
SA91
0
1
1
0
1
1
128/64
05B0000–05BFFFF
SA92
0
1
1
1
0
0
128/64
05C0000–05CFFFF
SA93
0
1
1
1
0
1
128/64
05D0000–05DFFFF
SA94
0
1
1
1
1
0
128/64
05E0000–05EFFFF
SA95
0
1
1
1
1
1
128/64
05F0000–05FFFFF
SA96
1
0
0
0
0
0
128/64
0600000–060FFFF
SA97
1
0
0
0
0
1
128/64
0610000–061FFFF
SA98
1
0
0
0
1
0
128/64
0620000–062FFFF
SA99
1
0
0
0
1
1
128/64
0630000–063FFFF
SA100
1
0
0
1
0
0
128/64
0640000–064FFFF
SA101
1
0
0
1
0
1
128/64
0650000–065FFFF
SA102
1
0
0
1
1
0
128/64
0660000–066FFFF
SA103
1
0
0
1
1
1
128/64
0670000–067FFFF
SA104
1
0
1
0
0
0
128/64
0680000–068FFFF
SA105
1
0
1
0
0
1
128/64
0690000–069FFFF
SA106
1
0
1
0
1
0
128/64
06A0000–06AFFFF
SA107
1
0
1
0
1
1
128/64
06B0000–06BFFFF
SA108
1
0
1
1
0
0
128/64
06C0000–06CFFFF
SA109
1
0
1
1
0
1
128/64
06D0000–06DFFFF
SA110
1
0
1
1
1
0
128/64
06E0000–06EFFFF
SA111
1
0
1
1
1
1
128/64
06F0000–06FFFFF
SA112
1
1
0
0
0
0
128/64
0700000–070FFFF
SA113
1
1
0
0
0
1
128/64
0710000–071FFFF
SA114
1
1
0
0
1
0
128/64
0720000–072FFFF
SA115
1
1
0
0
1
1
128/64
0730000–073FFFF
SA116
1
1
0
1
0
0
128/64
0740000–074FFFF
SA117
1
1
0
1
0
1
128/64
0750000–075FFFF
SA118
1
1
0
1
1
0
128/64
0760000–076FFFF
SA119
1
1
0
1
1
1
128/64
0770000–077FFFF
SA120
1
1
1
0
0
0
128/64
0780000–078FFFF
SA121
1
1
1
0
0
1
128/64
0790000–079FFFF
SA122
1
1
1
0
1
0
128/64
07A0000–07AFFFF
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
51
A d v a n c e
Table 4.
Sector
I n f o r m a t i o n
Sector Address Table–S29GL128N (Continued)
A22–A16
Sector Size
(Kbytes/
Kwords)
Address Range
(in hexadecimal)
SA123
1
1
1
0
1
1
128/64
07B0000–07BFFFF
SA124
1
1
1
1
0
0
128/64
07C0000–07CFFFF
SA125
1
1
1
1
0
1
128/64
07D0000–07DFFFF
SA126
1
1
1
1
1
0
128/64
07E0000–07EFFFF
SA127
1
1
1
1
1
1
128/64
07F0000–07FFFFF
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
group protection verification, through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment to automatically match a
device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 5.
In addition, when verifying sector protection, the sector address must appear on
the appropriate highest order address bits (see Table 2). Table 5 shows the remaining address bits that are don’t care. When all necessary bits have been set
as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12. This method does
not require VID. Refer to the Autoselect Command Sequence section for more
information.
52
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 5.
Autoselect Codes, (High Voltage Method)
A9
A8
to
A7
A6
A5
to
A4
A3
to
A2
A1
A0
DQ8 to
DQ15
DQ7 to DQ0
VID
X
L
X
L
L
L
00
01h
L
L
H
22
7Eh
H
H
L
22
23h
Cycle 3
H
H
H
22
01h
Cycle 1
L
L
H
22
7Eh
H
H
L
22
22h
Cycle 3
H
H
H
22
01h
Cycle 1
L
L
H
22
7Eh
H
H
L
22
21h
H
H
H
22
01h
Description
Manufacturer ID:
Spansion Product
Device ID
Device ID
Device ID
S29GL128N S29GL256N S29GL512N
I n f o r m a t i o n
CE#
OE#
WE
#
L
L
H
A22 A14
to
to
A15 A10
X
X
Cycle 1
Cycle 2
Cycle 2
Cycle 2
L
L
L
L
L
L
H
H
H
X
X
X
X
X
X
VID
VID
VID
X
X
X
L
L
L
X
X
X
Cycle 3
Sector Group
Protection Verification
L
L
H
SA
X
VID
X
L
X
L
H
L
X
01h (protected),
00h (unprotected)
Secured Silicon Sector
Indicator Bit (DQ7),
WP# protects highest
address sector
L
L
H
X
X
VID
X
L
X
L
H
H
X
98h (factory locked),
18h (not factory locked)
Secured Silicon Sector
Indicator Bit (DQ7),
WP# protects lowest
address sector
L
L
H
X
X
VID
X
L
X
L
H
H
X
88h (factory locked),
08h (not factory locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection
The device features several levels of sector protection, which can disable both the
program and erase operations in certain sectors or sector groups:
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled protection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before
changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in the outermost
sectors.
The WP# Hardware Protection feature is always available, independent of the
software managed protection method chosen.
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most
desirable. There are two one-time programmable non-volatile bits that define
which sector protection method will be used. If the customer decides to continue
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
53
A d v a n c e
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using the Persistent Sector Protection method, they must set the Persistent
Sector Protection Mode Locking Bit. This will permanently set the part to operate only using Persistent Sector Protection. If the customer decides to use the
password method, they must set the Password Mode Locking Bit. This will
permanently set the part to operate only using password sector protection.
It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently
selects the protection mode. It is not possible to switch between the two methods
once a locking bit has been set. It is important that one mode is explicitly
selected when the device is first programmed, rather than relying on the
default mode alone. This is so that it is not possible for a system program or
virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password
Protection Mode.
The device is shipped with all sectors unprotected. The factory offers the option
of programming and protecting sectors at the factory prior to shipping the device
through the ExpressFlash™ Service. Contact your sales representative for details.
It is possible to determine whether a sector is protected or unprotected. See “Autoselect Command Sequence” section on page 66 for details.
Advanced Sector Protection
Advanced Sector Protection features several levels of sector protection, which can
disable both the program and erase operations in certain sectors.
Persistent Sector Protection is a method that replaces the old 12V controlled
protection method.
Password Sector Protection is a highly sophisticated protection method that
requires a password before changes to certain sectors are permitted.
Lock Register
The Lock Register consists of 3 bits (DQ2, DQ1, and DQ0). These DQ2, DQ1, DQ0
bits of the Lock Register are programmable by the user. Users are not allowed to
program both DQ2 and DQ1 bits of the Lock Register to the 00 state. If the user
tries to program DQ2 and DQ1 bits of the Lock Register to the 00 state, the device
will abort the Lock Register back to the default 11 state. The programming time
of the Lock Register is same as the typical word programming time without utilizing the Write Buffer of the device. During a Lock Register programming
sequence execution, the DQ6 Toggle Bit I will toggle until the programming of the
Lock Register has completed to indicate programming status. All Lock Register
bits are readable to allow users to verify Lock Register statuses.
The Customer Secured Silicon Sector Protection Bit is DQ0, Persistent Protection
Mode Lock Bit is DQ1, and Password Protection Mode Lock Bit is DQ2 are accessible by all users. Each of these bits are non-volatile. DQ15-DQ3 are reserved and
must be 1's when the user tries to program the DQ2, DQ1, and DQ0 bits of the
Lock Register. The user is not required to program DQ2, DQ1 and DQ0 bits of the
Lock Register at the same time. This allows users to lock the Secured Silicon Sector and then set the device either permanently into Password Protection Mode or
Persistent Protection Mode and then lock the Secured Silicon Sector at separate
instances and time frames.
„ Secured Silicon Sector Protection allows the user to lock the Secured Silicon
Sector area
54
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
„ Persistent Protection Mode Lock Bit allows the user to set the device permanently to operate in the Persistent Protection Mode
„ Password Protection Mode Lock Bit allows the user to set the device permanently to operate in the Password Protection Mode
Table 6.
Lock Register
DQ15-3
DQ2
DQ1
DQ0
Don’t Care
Password Protection
Mode Lock Bit
Persistent Protection
Mode Lock Bit
Secured Silicon
Sector Protection
Bit
Persistent Sector Protection
The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three
different sector protection states:
„ Dynamically Locked-The sector is protected and can be changed by a simple command
„ Persistently Locked-A sector is protected and cannot be changed
„ Unlocked-The sector is unprotected and can be changed by a simple command
In order to achieve these states, three types of “bits” are going to be used:
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware
reset, the contents of all DYB bits are in the “unprotected state”. Each DYB is individually modifiable through the DYB Set Command and DYB Clear Command.
When the parts are first shipped, all of the Persistent Protect Bits (PPB) are
cleared into the unprotected state. The DYB bits and PPB Lock bit are defaulted
to power up in the cleared state or unprotected state - meaning the all PPB bits
are changeable.
The Protection State for each sector is determined by the logical OR of the PPB
and the DYB related to that sector. For the sectors that have the PPB bits cleared,
the DYB bits control whether or not the sector is protected or unprotected. By issuing the DYB Set and DYB Clear command sequences, the DYB bits will be
protected or unprotected, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They
are called dynamic states because it is very easy to switch back and forth between the protected and un-protected conditions. This allows software to easily
protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed.
The DYB bits maybe set or cleared as often as needed. The PPB bits allow for a
more static, and difficult to change, level of protection. The PPB bits retain their
state across power cycles because they are Non-Volatile. Individual PPB bits are
set with a program command but must all be cleared as a group through an erase
command.
The PPB Lock Bit adds an additional level of protection. Once all PPB bits are programmed to the desired settings, the PPB Lock Bit may be set to the “freeze
state”. Setting the PPB Lock Bit to the “freeze state” disables all program and
erase commands to the Non-Volatile PPB bits. In effect, the PPB Lock Bit locks the
PPB bits into their current state. The only way to clear the PPB Lock Bit to the
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
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A d v a n c e
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“unfreeze state” is to go through a power cycle, or hardware reset. The Software
Reset command will not clear the PPB Lock Bit to the “unfreeze state”. System
boot code can determine if any changes to the PPB bits are needed e.g. to allow
new system code to be downloaded. If no changes are needed then the boot code
can set the PPB Lock Bit to disable any further changes to the PPB bits during
system operation.
The WP# write protect pin adds a final level of hardware protection. When this
pin is low it is not possible to change the contents of the WP# protected sectors.
These sectors generally hold system boot code. So, the WP# pin can prevent any
changes to the boot code that could override the choices made while setting up
sector protection during system initialization.
It is possible to have sectors that have been persistently locked, and sectors that
are left in the dynamic state. The sectors in the dynamic state are all unprotected.
If there is a need to protect some of them, a simple DYB Set command sequence
is all that is necessary. The DYB Set and DYB Clear commands for the dynamic
sectors switch the DYB bits to signify protected and unprotected, respectively. If
there is a need to change the status of the persistently locked sectors, a few more
steps are required. First, the PPB Lock Bit must be disabled to the “unfreeze
state” by either putting the device through a power-cycle, or hardware reset. The
PPB bits can then be changed to reflect the desired settings. Setting the PPB Lock
Bit once again to the “freeze state” will lock the PPB bits, and the device operates
normally again.
Note: to achieve the best protection, it's recommended to execute the PPB Lock
Bit Set command early in the boot code, and protect the boot code by holding
WP# = VIL.
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to each sector. If a PPB
is programmed to the protected state through the “PPB Program” command, that
sector will be protected from program or erase operations will be read-only. If a
PPB requires erasure, all of the sector PPB bits must first be erased in parallel
through the “All PPB Erase” command. The “All PPB Erase” command will preprogrammed all PPB bits prior to PPB erasing. All PPB bits erase in parallel, unlike
programming where individual PPB bits are programmable. The PPB bits have the
same endurance as the flash memory.
Programming the PPB bit requires the typical word programming time without utilizing the Write Buffer. During a PPB bit programming and A11 PPB bit erasing
sequence execution, the DQ6 Toggle Bit I will toggle until the programming of the
PPB bit or erasing of all PPB bits has completed to indicate programming and
erasing status. Erasing all of the PPB bits at once requires typical sector erase
time. During the erasing of all PPB bits, the DQ3 Sector Erase Timer bit will output
a 1 to indicate the erasure of all PPB bits are in progress. When the erasure of all
PPB bits has completed, the DQ3 Sector Erase Timer bit will output a 0 to indicate
that all PPB bits have been erased. Reading the PPB Status bit requires the initial
access time of the device.
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. When set to the “freeze state”, the PPB bits cannot be
changed. When cleared to the “unfreeze state”, the PPB bits are changeable.
There is only one PPB Lock Bit per device. The PPB Lock Bit is cleared to the “un-
56
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
freeze state” after power-up or hardware reset. There is no command sequence
to unlock or “unfreeze” the PPB Lock Bit.
Configuring the PPB Lock Bit to the freeze state requires approximately 100ns.
Reading the PPB Lock Status bit requires the initial access time of the device.
Table 7.
Sector Protection Schemes
Protection States
Sector State
DYB Bit
PPB Bit
PPB Lock Bit
Unprotect
Unprotect
Unfreeze
Unprotected – PPB and DYB are changeable
Unprotect
Unprotect
Freeze
Unprotected – PPB not changeable, DYB is
changeable
Unprotect
Protect
Unfreeze
Protected – PPB and DYB are changeable
Unprotect
Protect
Freeze
Protected – PPB not changeable, DYB is changeable
Protect
Unprotect
Unfreeze
Protected – PPB and DYB are changeable
Protect
Unprotect
Freeze
Protected – PPB not changeable, DYB is changeable
Protect
Protect
Unfreeze
Protected – PPB and DYB are changeable
Protect
Protect
Freeze
Protected – PPB not changeable, DYB is changeable
Table 7 contains all possible combinations of the DYB bit, PPB bit, and PPB Lock
Bit relating to the status of the sector. In summary, if the PPB bit is set, and the
PPB Lock Bit is set, the sector is protected and the protection cannot be removed
until the next power cycle or hardware reset clears the PPB Lock Bit to “unfreeze
state”. If the PPB bit is cleared, the sector can be dynamically locked or unlocked.
The DYB bit then controls whether or not the sector is protected or unprotected.
If the user attempts to program or erase a protected sector, the device ignores
the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read
mode without having modified the contents of the protected sector. An erase
command to a protected sector enables status polling for approximately 50 µs
after which the device returns to read mode without having erased the protected
sector. The programming of the DYB bit, PPB bit, and PPB Lock Bit for a given sector can be verified by writing a DYB Status Read, PPB Status Read, and PPB Lock
Status Read commands to the device.
The Autoselect Sector Protection Verification outputs the OR function of the DYB
bit and PPB bit per sector basis. When the OR function of the DYB bit and PPB bit
is a 1, the sector is either protected by DYB or PPB or both. When the OR function
of the DYB bit and PPB bit is a 0, the sector is unprotected through both the DYB
and PPB.
Persistent Protection Mode Lock Bit
Like the Password Protection Mode Lock Bit, a Persistent Protection Mode Lock Bit
exists to guarantee that the device remain in software sector protection. Once
programmed, the Persistent Protection Mode Lock Bit prevents programming of
the Password Protection Mode Lock Bit. This guarantees that a hacker could not
place the device in Password Protection Mode. The Password Protection Mode
Lock Bit resides in the “Lock Register”.
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
57
A d v a n c e
I n f o r m a t i o n
Password Sector Protection
The Password Sector Protection method allows an even higher level of security
than the Persistent Sector Protection method. There are two main differences between the Persistent Sector Protection and the Password Sector Protection
methods:
„ When the device is first powered on, or comes out of a reset cycle, the PPB
Lock Bit is set to the locked state, or the freeze state, rather than cleared to
the unlocked state, or the unfreeze state.
„ The only means to clear and unfreeze the PPB Lock Bit is by writing a unique
64-bit Password to the device.
The Password Sector Protection method is otherwise identical to the Persistent
Sector Protection method.
A 64-bit password is the only additional tool utilized in this method.
The password is stored in a one-time programmable (OTP) region outside of the
flash memory. Once the Password Protection Mode Lock Bit is set, the password
is permanently set with no means to read, program, or erase it. The password is
used to clear and unfreeze the PPB Lock Bit. The Password Unlock command must
be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the
PPB Lock Bit is cleared to the “unfreezed state”, and the PPB bits can be altered.
If they do not match, the flash device does nothing. There is a built-in 2 µs delay
for each “password check” after the valid 64-bit password has been entered for
the PPB Lock Bit to be cleared to the “unfreezed state”. This delay is intended to
thwart any efforts to run a program that tries all possible combinations in order
to crack the password.
Password and Password Protection Mode Lock Bit
In order to select the Password Sector Protection method, the customer must first
program the password. The factory recommends that the password be somehow
correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should
be different for every flash device. While programming in the password region,
the customer may perform Password Read operations. Once the desired password is programmed in, the customer must then set the Password Protection
Mode Lock Bit. This operation achieves two objectives:
1. It permanently sets the device to operate using the Password Protection Mode.
It is not possible to reverse this function.
2. It also disables all further commands to the password region. All program, and
read operations are ignored.
Both of these objectives are important, and if not carefully considered, may lead
to unrecoverable errors. The user must be sure that the Password Sector Protection method is desired when programming the Password Protection Mode Lock
Bit. More importantly, the user must be sure that the password is correct when
the Password Protection Mode Lock Bit is programmed. Due to the fact that read
operations are disabled, there is no means to read what the password is afterwards. If the password is lost after programming the Password Protection Mode
Lock Bit, there will be no way to clear and unfreeze the PPB Lock Bit. The Password Protection Mode Lock Bit, once programmed, prevents reading the 64-bit
password on the DQ bus and further password programming. The Password Protection Mode Lock Bit is not erasable. Once Password Protection Mode Lock Bit is
58
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
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programmed, the Persistent Protection Mode Lock Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through
the use of the Password Program and Password Read commands. The password
function works in conjunction with the Password Protection Mode Lock Bit, which
when programmed, prevents the Password Read command from reading the contents of the password on the pins of the device.
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. The PPB Lock Bit is a volatile bit that reflects the state of the
Password Protection Mode Lock Bit after power-up reset. If the Password Protection Mode Lock Bit is also programmed after programming the Password, the
Password Unlock command must be issued to clear and unfreeze the PPB Lock Bit
after a hardware reset (RESET# asserted) or a power-up reset. Successful execution of the Password Unlock command clears and unfreezes the PPB Lock Bit,
allowing for sector PPB bits to be modified. Without issuing the Password Unlock
command, while asserting RESET#, taking the device through a power-on reset,
or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a the “freeze
state”.
If the Password Protection Mode Lock Bit is not programmed, the device defaults
to Persistent Protection Mode. In the Persistent Protection Mode, the PPB Lock Bit
is cleared to the “unfreeze state” after power-up or hardware reset. The PPB Lock
Bit is set to the “freeze state” by issuing the PPB Lock Bit Set command. Once set
to the “freeze state” the only means for clearing the PPB Lock Bit to the “unfreeze
state” is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode.
Reading the PPB Lock Bit requires a 200ns access time.
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables
permanent part identification through an Electronic Serial Number (ESN). The
Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector
Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked
when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the
security of the ESN once the product is shipped to the field.
The factory offers the device with the Secured Silicon Sector either customer
lockable (standard shipping option) or factory locked (contact an AMD sales representative for ordering information). The customer-lockable version is shipped
with the Secured Silicon Sector unprotected, allowing customers to program the
sector after receiving the device. The customer-lockable version also has the Secured Silicon Sector Indicator Bit permanently set to a “0.” The factory-locked
version is always protected when shipped from the factory, and has the Secured
Silicon Sector Indicator Bit permanently set to a “1.” Thus, the Secured Silicon
Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. Note that the ACC function and unlock
bypass modes are not available when the Secured Silicon Sector is enabled.
December 15, 2004 S29GLxxxN_MCP_A1
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The Secured Silicon sector address space in this device is allocated as follows:
Secured Silicon Sector
Address Range
Customer Lockable
000000h–000007h
ESN Factory Locked
ESN
ESN or determined by
customer
Unavailable
Determined by customer
Determined by customer
000008h–00007Fh
ExpressFlash
Factory Locked
The system accesses the Secured Silicon Sector through a command sequence
(see “Write Protect (WP#)”). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using
the addresses normally occupied by the first sector (SA0). This mode of operation
continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a
hardware reset, the device reverts to sending commands to sector SA0.
Customer Lockable: Secured Silicon Sector NOT Programmed or
Protected At the Factory
Unless otherwise specified, the device is shipped such that the customer may
program and protect the 256-byte Secured Silicon sector.
The system may program the Secured Silicon Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard
programming command sequence. See “Command Definitions” .
Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotecting the
Secured Silicon Sector area and none of the bits in the Secured Silicon Sector
memory space can be modified in any way.
The Secured Silicon Sector area can be protected using one of the following
procedures:
„ Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm, except that
RESET# may be at either VIH or VID. This allows in-system protection of the
Secured Silicon Sector without raising any device pin to a high voltage. Note
that this method is only applicable to the Secured Silicon Sector.
„ To verify the protect/unprotect status of the Secured Silicon Sector, follow the
algorithm.
Once the Secured Silicon Sector is programmed, locked and verified, the system
must write the Exit Secured Silicon Sector Region command sequence to return
to reading and writing within the remainder of the array.
Factory Locked: Secured Silicon Sector Programmed and
Protected At the Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device
is shipped from the factory. The Secured Silicon Sector cannot be modified in any
way. An ESN Factory Locked device has an 16-byte random ESN at addresses
000000h–000007h. Please contact your sales representative for details on ordering ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the
ExpressFlash service (Express Flash Factory Locked). The devices are then
shipped from the factory with the Secured Silicon Sector permanently locked.
Contact your sales representative for details on using the ExpressFlash service.
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Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or
last sector group without using VID. Write Protect is one of two functions provided
by the WP#/ACC input.
If the system asserts VIL on the WP#/ACC pin, the device disables program and
erase functions in the first or last sector group independently of whether those
sector groups were protected or unprotected using the method described in“Advanced Sector Protection” section on page 54. Note that if WP#/ACC is at VIL
when the device is in the standby mode, the maximum input load current is increased. See the table in “DC Characteristics” section on page 90.
If the system asserts VIH on the WP#/ACC pin, the device reverts to
whether the first or last sector was previously set to be protected or unprotected using the method described in “Sector Group Protection and
Unprotection”. Note that WP# has an internal pullup; when unconnected, WP# is at VIH.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Table 12 for command definitions). In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and power-down transitions,
or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# =
VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can
December 15, 2004 S29GLxxxN_MCP_A1
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then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h, any time the device is ready to read array data.
The system can read CFI information at the addresses given in Tables 8-11. To
terminate reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 8–11. The system must write the reset
command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication
100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact your sales representative for copies of these documents.
Table 8.
62
CFI Query Identification String
Addresses
(x16)
Data
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Description
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
Table 9.
System Interface String
Addresses
(x16)
Data
1Bh
0027h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0036h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
0007h
Typical timeout per single byte/word write 2N µs
20h
0007h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
000Ah
Typical timeout per individual block erase 2N ms
22h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
0001h
Max. timeout for byte/word write 2N times typical
24h
0005h
Max. timeout for buffer write 2N times typical
25h
0004h
Max. timeout per individual block erase 2N times typical
26h
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
December 15, 2004 S29GLxxxN_MCP_A1
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Table 10.
Addresses
(x16)
64
I n f o r m a t i o n
Device Geometry Definition
Data
Description
27h
001Ah
0019h
0018h
28h
29h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
0001h
Number of Erase Block Regions within device (01h = uniform device,
02h = boot device)
2Dh
2Eh
2Fh
30h
00xxh
000xh
0000h
000xh
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
00FFh, 001h, 0000h, 0002h = 512 Mb
00FFh, 0000h, 0000h, 0002h = 256 Mb
007Fh, 0000h, 0000h, 0002h = 128 Mb
31h
32h
33h
34h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information (refer to CFI publication 100)
Device Size = 2N byte
1A = 512 Mb, 19 = 256 Mb, 18 = 128 Mb
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
Table 11.
I n f o r m a t i o n
Primary Vendor-Specific Extended Query
Addresses
(x16)
Data
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
0031h
Major version number, ASCII
44h
0033h
Minor version number, ASCII
45h
0010h
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Description
Process Technology (Bits 7-2) 0100b = 110 nm MirrorBit
46h
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
0000h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
0008h
Sector Protect/Unprotect scheme
0008h = Advanced Sector Protection
4Ah
0000h
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
4Bh
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
0002h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
00B5h
4Eh
00C5h
4Fh
00xxh
50h
0001h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
WP# Protection
04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors
top WP# protect
Program Suspend
00h = Not Supported, 01h = Supported
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 12 defines the valid register command
sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is
then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing diagrams.
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Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the
erase-suspend-read mode, after which the system can read data from any nonerase-suspended sector. After completing a programming operation in the Erase
Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more
information.
The system must issue the reset command to return the device to the read (or
erase-suspend-read) mode if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode. See the next section, Reset
Command, for more information.
See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations–“AC Characteristics”
section provides the read parameters, and Figure 11 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ignores reset commands until
the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the device to the
read mode. If the program command sequence is written while the device is in
the Erase Suspend mode, writing the reset command returns the device to the
erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If the device entered the autoselect mode
while in the Erase Suspend mode, writing the reset command returns the device
to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command
returns the device to the read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the
device for the next operation.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected.
Table 12 shows the address and data requirements. This method is an alternative
to that shown in Table 5, which is intended for PROM programmers and requires
VID on address pin A9. The autoselect command sequence may be written to an
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address that is either in the read or erase-suspend-read mode. The autoselect
command may not be written while the device is actively programming or
erasing.
The autoselect command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system may read at any address any
number of times without initiating another autoselect command sequence:
„ A read cycle at address XX00h returns the manufacturer code.
„ Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code.
„ A read cycle to an address containing a sector address (SA), and the address
02h on A7–A0 in word mode returns 01h if the sector is protected, or 00h if
it is unprotected.
The system must write the reset command to return to the read mode (or erasesuspend-read mode if the device was previously in Erase Suspend).
Enter Secured Silicon Sector/Exit Secured Silicon
Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing an 8word/16-byte random Electronic Serial Number (ESN). The system can access
the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon
Sector command sequence. The device continues to access the Secured Silicon
Sector region until the system issues the four-cycle Exit Secured Silicon Sector
command sequence. The Exit Secured Silicon Sector command sequence returns
the device to normal operation. Table 12 shows the address and data requirements for both command sequences. See also “Secured Silicon Sector Flash
Memory Region” for further information. Note that the ACC function and unlock
bypass modes are not available when the Secured Silicon Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin. Table 12 shows the address and
data requirements for the word program command sequence.
When the Embedded Program algorithm is complete, the device then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that the Secured Silicon Sector, autoselect, and CFI
functions are unavailable when a program operation is in progress. Note
that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to
the read mode, to ensure data integrity.
Programming is allowed in any sequence of address locations and across sector
boundaries. Programming to the same word address multiple times without intervening erases (incremental bit programming) requires a modified
programming method. For such application requirements, please contact your
December 15, 2004 S29GLxxxN_MCP_A1
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local Spansion representative. Word programming is supported for backward
compatibility with existing Flash driver software and for occasional writing of individual words. Use of Write Buffer Programming is strongly recommended for
general programming use when more than a few words are to be programmed.
The effective word programming time using Write Buffer Programming is much
shorter than the single word programming time. Any word cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device
to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation
was successful. However, a succeeding read will show that the data is still “0.”
Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program command, A0h; the second
cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required
in the standard program command sequence, resulting in faster total programming time. Table 12 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. (See Table
12).
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32
bytes in one programming operation. This results in faster effective programming
time than the standard programming algorithms. The Write Buffer Programming
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load command written at the
Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For
example, if the system will program 6 unique address locations, then 05h should
be written to the device. This tells the device how many write buffer addresses
will be loaded with data and therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot exceed the size of the
write buffer or the operation will abort.
The fifth cycle writes the first address location and data to be programmed. The
write-buffer-page is selected by address bits AMAX–A4. All subsequent address/
data pairs must fall within the selected-write-buffer-page. The system then
writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order.
The write-buffer-page address must be the same for all address/data pairs loaded
into the write buffer. (This means Write Buffer Programming cannot be performed
across multiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load
programming data outside of the selected write-buffer page, the operation will
abort.)
68
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A d v a n c e
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Note that if a Write Buffer address location is loaded multiple times, the address/
data pair counter will be decremented for every data load operation. The host
system must therefore account for loading a write-buffer location more than
once. The counter decrements for each data load operation, not for each unique
write-buffer-address location. Note also that if an address location is loaded more
than once into the buffer, the final data loaded for that address will be
programmed.
Once the specified number of write buffer locations have been loaded, the system
must then write the Program Buffer to Flash command at the sector address. Any
other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while
monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5,
and DQ1 should be monitored to determine the device status during Write Buffer
Programming.
The write-buffer programming operation can be suspended using the standard
program suspend/resume commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to execute the next command.
The Write Buffer Programming Sequence can be aborted in the following ways:
„ Load a value that is greater than the page buffer size during the Number of
Locations to Program step.
„ Write to an address in a sector different than the one specified during the
Write-Buffer-Load command.
„ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of
the operation.
„ Write data other than the Confirm Command after the specified number of
data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address
location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. Note
that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required
when using Write-Buffer-Programming features in Unlock Bypass mode.
Write buffer programming is allowed in any sequence. Note that the Secured Silicon sector, autoselect, and CFI functions are unavailable when a program
operation is in progress. This flash device is capable of handling multiple write
buffer programming operations on the same write buffer address range without
intervening erases. For applications requiring incremental bit programming, a
modified programming method is required, please contact your local Spansion
representative. Any bit in a write buffer address range cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device
to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation
was successful. However, a succeeding read will show that the data is still “0.”
Only erase operations can convert a “0” to a “1.”
Accelerated Program
The device offers accelerated program operations through the WP#/ACC pin.
When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock
Bypass program command sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not
December 15, 2004 S29GLxxxN_MCP_A1
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be at VHH for operations other than accelerated programming, or device damage
may result. WP# has an internal pullup; when unconnected, WP# is at VIH.
Figure 2 illustrates the algorithm for the program operation. Refer to the Erase
and Program Operations–“AC Characteristics” section for parameters, and Figure
14 for timing diagrams.
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Buffer Operation?
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
to read mode.
No
(Note 1)
Write next address/data pair
WC = WC - 1
Write program buffer to
flash sector address
Notes:
1. When Sector Address is specified, any
address in the selected sector is acceptable.
However, when loading Write-Buffer
address locations with data, all addresses
must fall within the selected Write-Buffer
Page.
Read DQ15 - DQ0 at
Last Loaded Address
Yes
DQ7 = Data?
No
2. DQ7 may change simultaneously with DQ5.
Therefore, DQ7 should be verified.
3. If this flowchart location was reached
because DQ5= “1”, then the device FAILED.
If this flowchart location was reached
because DQ1= “1”, then the Write to Buffer
operation was ABORTED. In either case, the
proper reset command must be written
before the device can begin another
operation. If DQ1=1, write the WriteBuffer-Programming-Abort-Reset
command. if DQ5=1, write the Reset
command.
No
No
DQ1 = 1?
DQ5 = 1?
Yes
Yes
Read DQ15 - DQ0 with
address = Last Loaded
Address
(Note 2)
4. See Table 12 for command sequences
required for write buffer programming.
Yes
DQ7 = Data?
No
(Note 3)
FAIL or ABORT
Figure 1.
70
PASS
Write Buffer Programming Operation
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
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START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
Note: See Table 12 for program command sequence.
Figure 2.
Program Operation
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming
operation or a Write to Buffer programming operation so that data can be read
from any non-suspended sector. When the Program Suspend command is written
during a programming process, the device halts the program operation within 15
µs maximum (5µs typical) and updates the status bits. Addresses are not required when writing the Program Suspend command.
After the programming operation has been suspended, the system can read array
data from any non-suspended sector. The Program Suspend command may also
be issued during a programming operation while an erase is suspended. In this
case, data may be read from any addresses not in Erase Suspend or Program
Suspend. If a read is needed from the Secured Silicon Sector area (One-time Program area), then user must use the proper command sequences to enter and exit
this region. Note that the Secured Silicon Sector autoselect, and CFI functions are
unavailable when program operation is in progress.
The system may also write the autoselect command sequence when the device
is in the Program Suspend mode. The system can read as many autoselect codes
as required. When the device exits the autoselect mode, the device reverts to the
Program Suspend mode, and is ready for another valid operation. See Autoselect
Command Sequence for more information.
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After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information.
The system must write the Program Resume command (address bits are don’t
care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program
Suspend command can be written after the device has resume programming.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write address/data
XXXh/B0h
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Wait 15 µs
Read data as
required
No
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Done
reading?
Yes
Write address/data
XXXh/30h
Write Program Resume
Command Sequence
Device reverts to
operation prior to
Program Suspend
Figure 3.
Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 12 shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation
Status section for information on these status bits.
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Any commands written during the chip erase operation are ignored, including
erase suspend commands. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the chip erase command sequence
should be reinitiated once the device has returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation. Note that the Secured
Silicon Sector, autoselect, and CFI functions are unavailable when an
erase operation in is progress. Refer to the “Erase And Programming Performance” section on page 102 in the AC Characteristics section for parameters, and
Figure 16 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table 12 shows the address
and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs.
During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 µs, otherwise erasure
may begin. Any sector erase address and command following the exceeded timeout may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out
period resets the device to the read mode. Note that the Secured Silicon
Sector, autoselect, and CFI functions are unavailable when an erase operation in is progress. The system must rewrite the command sequence and
any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector.
Refer to the Write Operation Status section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and
Program Operations table in the AC Characteristics section for parameters, and
Figure 16 section for timing diagrams.
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START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 12 for program command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 4.
Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase
operation and then read data from, or program data to, any sector not selected
for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The
Erase Suspend command is ignored if written during the chip erase operation or
Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation,
the device requires a typical of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and
suspends the erase operation.
After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for
erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer
to the Write Operation Status section for information on these status bits.
After an erase-suspended program operation is complete, the device returns to
the erase-suspend-read mode. The system can determine the status of the pro-
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gram operation using the DQ7 or DQ6 status bits, just as in the standard word
program operation. Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the “Autoselect Mode” section and “Autoselect
Command Sequence” section on page 66 sections for details.
To resume the sector erase operation, the system must write the Erase Resume
command. The address of the erase-suspended sector is required when writing
this command. Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip has resumed erasing. It is
important to allow an interval of at least 5 ms between Erase Resume and Erase
Suspend.
Lock Register Command Set Definitions
The Lock Register Command Set permits the user to one-time program the Secured Silicon Sector Protection Bit, Persistent Protection Mode Lock Bit, and
Password Protection Mode Lock Bit. The Lock Register bits are all readable after
an initial access delay.
The Lock Register Command Set Entry command sequence must be issued
prior to any of the following commands listed, to enable proper command
execution.
Note that issuing the Lock Register Command Set Entry command disables
reads and writes for the flash memory.
„ Lock Register Program Command
„ Lock Register Read Command
The Lock Register Command Set Exit command must be issued after the execution of the commands to reset the device to read mode. Otherwise the device
will hang. If this happens, the flash device must be reset. Please refer to RESET#
for more information. It is important to note that the device will be in either Persistent Protection mode or Password Protection mode depending on the mode
selected prior to the device hang.
For either the Secured Silicon Sector to be locked, or the device to be permanently set to the Persistent Protection Mode or the Password Protection Mode, the
associated Lock Register bits must be programmed. Note that the Persistent
Protection Mode Lock Bit and Password Protection Mode Lock Bit can
never be programmed together at the same time. If so, the Lock Register
Program operation will abort.
The Lock Register Command Set Exit command must be initiated to reenable reads and writes to the main memory.
Password Protection Command Set Definitions
The Password Protection Command Set permits the user to program the 64-bit
password, verify the programming of the 64-bit password, and then later unlock
the device by issuing the valid 64-bit password.
The Password Protection Command Set Entry command sequence must be
issued prior to any of the commands listed following to enable proper command
execution.
Note that issuing the Password Protection Command Set Entry command
disabled reads and writes the main memory.
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„ Password Program Command
„ Password Read Command
„ Password Unlock Command
The Password Program command permits programming the password that is
used as part of the hardware protection scheme. The actual password is 64-bits
long. There is no special addressing order required for programming the password. The password is programmed in 8-bit or 16-bit portions. Each
portion requires a Password Program Command.
Once the Password is written and verified, the Password Protection Mode Lock Bit
in the “Lock Register” must be programmed in order to prevent verification. The
Password Program command is only capable of programming “0”s. Programming
a “1” after a cell is programmed as a “0” results in a time-out by the Embedded
Program AlgorithmTM with the cell remaining as a “0”. The password is all F’s when
shipped from the factory. All 64-bit password combinations are valid as a
password.
The Password Read command is used to verify the Password. The Password is
verifiable only when the Password Protection Mode Lock Bit in the “Lock Register”
is not programmed. If the Password Protection Mode Lock Bit in the “Lock Register” is programmed and the user attempts to read the Password, the device will
always drive all F’s onto the DQ databus.
The lower two address bits (A1–A0) for word mode and (A1–A-1) for by byte
mode are valid during the Password Read, Password Program, and Password Unlock commands. Writing a “1” to any other address bits (AMAX-A2) will
abort the Password Read and Password Program commands.
The Password Unlock command is used to clear the PPB Lock Bit to the “unfreeze
state” so that the PPB bits can be modified. The exact password must be entered
in order for the unlocking function to occur. This 64-bit Password Unlock command sequence will take at least 2 µs to process each time to prevent a
hacker from running through the all 64-bit combinations in an attempt
to correctly match the password. If another password unlock is issued
before the 64-bit password check execution window is completed, the
command will be ignored. If the wrong address or data is given during
password unlock command cycle, the device may enter the write-tobuffer abort state. In order to exit the write-to-abort state, the write-tobuffer-abort-reset command must be given. Otherwise the device will
hang.
The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit to the
“unfreeze state”. The password is 64 bits long. A1 and A0 are used for matching.
Writing the Password Unlock command does not need to be address order specific. An example sequence is starting with the lower address A1-A0=00, followed
by A1-A0=01, A1-A0=10, and A1-A0=11 if the device is configured to operate in
word mode.
Approximately 2 µs is required for unlocking the device after the valid
64-bit password is given to the device. It is the responsibility of the microprocessor to keep track of the entering the portions of the 64-bit
password with the Password Unlock command, the order, and when to
read the PPB Lock bit to confirm successful password unlock. In order to
re-lock the device into the Password Protection Mode, the PPB Lock Bit Set command can be re-issued.
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The Password Protection Command Set Exit command must be issued after
the execution of the commands listed previously to reset the device to read
mode. Otherwise the device will hang.
Note that issuing the Password Protection Command Set Exit command reenables reads and writes for the main memory.
Non-Volatile Sector Protection Command Set Definitions
The Non-Volatile Sector Protection Command Set permits the user to program the
Persistent Protection Bits (PPB bits), erase all of the Persistent Protection Bits
(PPB bits), and read the logic state of the Persistent Protection Bits (PPB bits).
The Non-Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the commands listed following to enable
proper command execution.
Note that issuing the Non-Volatile Sector Protection Command Set Entry
command disables reads and writes for the main memory.
„ PPB Program Command
The PPB Program command is used to program, or set, a given PPB bit. Each PPB
bit is individually programmed (but is bulk erased with the other PPB bits). The
specific sector address (A24-A16 for S29GL512N, A23-A16 for S29GL256N, A22A16 for S29GL128N) is written at the same time as the program command. If the
PPB Lock Bit is set to the “freeze state”, the PPB Program command will not execute and the command will time-out without programming the PPB bit.
„ All PPB Erase Command
The All PPB Erase command is used to erase all PPB bits in bulk. There is no
means for individually erasing a specific PPB bit. Unlike the PPB program, no specific sector address is required. However, when the All PPB Erase command is
issued, all Sector PPB bits are erased in parallel. If the PPB Lock Bit is set to
“freeze state”, the ALL PPB Erase command will not execute and the command
will time-out without erasing the PPB bits.
The device will preprogram all PPB bits prior to erasing when issuing the All PPB
Erase command. Also note that the total number of PPB program/erase cycles has
the same endurance as the flash memory array.
„ PPB Status Read Command
The programming state of the PPB for a given sector can be verified by writing a
PPB Status Read Command to the device. This requires an initial access time
latency.
The Non-Volatile Sector Protection Command Set Exit command must be
issued after the execution of the commands listed previously to reset the device
to read mode.
Note that issuing the Non-Volatile Sector Protection Command Set Exit
command re-enables reads and writes for the main memory.
Global Volatile Sector Protection Freeze Command Set
The Global Volatile Sector Protection Freeze Command Set permits the user to set
the PPB Lock Bit and reading the logic state of the PPB Lock Bit.
The Global Volatile Sector Protection Freeze Command Set Entry command sequence must be issued prior to any of the commands listed following to
enable proper command execution.
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Reads and writes from the main memory are not allowed.
„ PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock Bit to the “freeze state”
if it is cleared either at reset or if the Password Unlock command was successfully
executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set
to the “freeze state”, it cannot be cleared unless the device is taken through a
power-on clear (for Persistent Protection Mode) or the Password Unlock command
is executed (for Password Protection Mode). If the Password Protection Mode Lock
Bit is programmed, the PPB Lock Bit status is reflected as set to the “freeze state”,
even after a power-on reset cycle.
„ PPB Lock Bit Status Read Command
The programming state of the PPB Lock Bit can be verified by executing a PPB
Lock Bit Status Read command to the device.
The Global Volatile Sector Protection Freeze Command Set Exit command
must be issued after the execution of the commands listed previously to reset the
device to read mode.
Volatile Sector Protection Command Set
The Volatile Sector Protection Command Set permits the user to set the Dynamic
Protection Bit (DYB) to the “protected state”, clear the Dynamic Protection Bit
(DYB) to the “unprotected state”, and read the logic state of the Dynamic Protection Bit (DYB).
The Volatile Sector Protection Command Set Entry command sequence
must be issued prior to any of the commands listed following to enable proper
command execution.
Note that issuing the Volatile Sector Protection Command Set Entry command disables reads and writes from main memory.
„ DYB Set Command
„ DYB Clear Command
The DYB Set and DYB Clear commands are used to protect or unprotect a DYB for
a given sector. The high order address bits are issued at the same time as the
code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are ignored during the
data write cycle. The DYB bits are modifiable at any time, regardless of the state
of the PPB bit or PPB Lock Bit. The DYB bits are cleared to the “unprotected state”
at power-up or hardware reset.
—DYB Status Read Command
The programming state of the DYB bit for a given sector can be verified by writing
a DYB Status Read command to the device. This requires an initial access delay.
The Volatile Sector Protection Command Set Exit command must be issued
after the execution of the commands listed previously to reset the device to read
mode.
Note that issuing the Volatile Sector Protection Command Set Exit command re-enables reads and writes to the main memory.
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Secured Silicon Sector Entry Command
The Secured Silicon Sector Entry command allows the following commands to be
executed
„ Read from Secured Silicon Sector
„ Program to Secured Silicon Sector
Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon
Sector Exit command has to be issued to exit Secured Silicon Sector Mode.
Secured Silicon Sector Exit Command
The Secured Silicon Sector Exit command may be issued to exit the Secured Silicon Sector Mode.
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Command Definitions
S29GL512N, S29GL256N, S29GL128N Command Definitions, x16
Cycles
Table 12.
Command (Notes)
Bus Cycles (Notes 2–5)
First
Second
Addr
Data
Third
Fourth
Addr
Data
Addr
Data
Addr
Data
Fifth
Sixth
Addr
Data
Addr
Data
X0E
Note
17
X0F
Note
17
1
RA
RD
Reset (7)
1
XXX
F0
Manufacturer ID
4
555
AA
2AA
55
555
90
X00
01
Device ID
4
555
AA
2AA
55
555
90
X01
227E
Sector Protect Verify
4
555
AA
2AA
55
555
90
(SA)
X02
Secure Device Verify (9)
4
555
AA
2AA
55
555
90
X03
Note
10
CFI Query (11)
1
55
98
Program
4
555
AA
2AA
55
555
A0
PA
PD
Write to Buffer
3
555
AA
2AA
55
SA
25
SA
WC
PA
PD
WBL
PD
Program Buffer to Flash (confirm)
1
SA
29
Write-to-Buffer-Abort Reset (16)
3
555
AA
2AA
55
555
F0
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass Program (12)
2
XXX
A0
PA
PD
Autoselect (Note 8)
Read (6)
XX00
XX01
Unlock Bypass Sector Erase (12)
2
XXX
80
SA
30
Unlock Bypass Chip Erase (12)
2
XXX
80
XXX
10
Unlock Bypass Reset (13)
2
XXX
90
XXX
00
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend/Program Suspend (14)
1
XXX
B0
Erase Resume/Program Resume (15)
1
XXX
30
XX
00
Secured Silicon SEctor
Sector Command Definitions
Secured Silicon Sector Entry
3
555
AA
2AA
55
555
88
Secured Silicon Sector Exit (18)
4
555
AA
2AA
55
555
90
Lock Register
Lock Register Command Set Definitions
Lock Register Command Set Entry
3
555
AA
2AA
55
Lock Register Bits Program (22)
2
XXX
A0
XXX
Data
Lock Register Bits Read (22)
1
00
Data
Lock Register Command Set Exit (18, 23)
2
XXX
90
XXX
00
555
40
Password Protection Command Set Definitions
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Cycles
A d v a n c e
Password
Command (Notes)
I n f o r m a t i o n
Bus Cycles (Notes 2–5)
First
Second
Third
Addr
Data
Addr
Data
Addr
Data
555
60
Fourth
Addr
Data
Password Protection Command Set Entry
3
555
AA
2AA
55
Password Program (20)
2
XXX
A0
PWA
x
PWD
x
Password Read (19)
4
XXX
PWD
0
01
PWD
1
02
PWD
2
03
PWD
3
Password Unlock (19)
7
00
25
00
03
00
PWD
0
01
PWD
1
00
29
XXX
90
XXX
00
Password Protection Command Set Exit (18,
23)
2
Fifth
Sixth
Addr
Data
Addr
Data
02
PWD
2
03
PWD
3
PPB
Non-Volatile Sector Protection Command Set Definitions
Nonvolatile Sector Protection Command Set
Entry
3
555
AA
2AA
55
PPB Program (24, 25)
2
XXX
A0
SA
00
All PPB Erase
2
XXX
80
00
30
PPB Status Read (25)
1
SA
RD
(0)
Non-Volatile Sector Protection Command Set
Exit (18)
2
XXX
90
XXX
00
555
C0
PPB Lock Bit
Global Non-Volatile Sector Protection Freeze Command Set Definitions
Global Non-Volatile Sector Protection Freeze
Command Set Entry
3
555
AA
2AA
55
PPB Lock Bit Set (25)
2
XXX
A0
XXX
00
PPB Lock Status Read (25)
1
XXX
RD
(0)
Global Non-Volatile Sector Protection Freeze
Command Set Exit (18)
2
XXX
90
XXX
00
555
50
DYB
Volatile Sector Protection Command Set Definitions
Volatile Sector Protection Command Set Entry
3
555
AA
2AA
55
DYB Set (24, 25)
2
XXX
A0
SA
00
DYB Clear (25)
2
XXX
A0
SA
01
XXX
00
DYB Status Read (25)
1
SA
RD
(0)
Volatile Sector Protection Command Set Exit
(18)
2
XXX
90
555
E0
Legend:
X = Don’t care
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A16 uniquely select any sector.
WBL = Write Buffer Location. The address must be within the same write buffer page as PA.
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WC = Word Count is the number of write buffer locations to load minus 1.
PWD = Password
PWDx = Password word0, word1, word2, and word3.
DATA = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2)
= Password Protection Mode Lock Bit.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write
cycles.
4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles.
5. Address bits AMAX:A16 are don't cares for unlock and command cycles, unless SA or PA required. (AMAX is the Highest
Address pin.).
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status data).
8. The fourth, fifth, and sixth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more
information. This is same as PPB Status Read except that the protect and unprotect statuses are inverted here.
10. The data value for DQ7 is “1” for a serialized and protected OTP region and “0” for an unserialized and unprotected Secured
Silicon Sector region. See “Secured Silicon Sector Flash Memory Region” for more information. For S29GLxxxNH: XX18h/18h
= Not Factory Locked. XX98h/98h = Factory Locked. For S29GLxxxNL: XX08h/08h = Not Factory Locked. XX88h/88h =
Factory Locked.
11. Command is valid when device is ready to read array data or when device is in autoselect mode.
12. The Unlock-Bypass command is required prior to the Unlock-Bypass-Program command.
13. The Unlock-Bypass-Reset command is required to return to reading array data when the device is in the unlock bypass
mode.
14. The system may read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the
Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
15. The Erase Resume/Program Resume command is valid only during the Erase Suspend/Program Suspend modes.
16. Issue this command sequence to return to READ mode after detecting device is in a Write-to-Buffer-Abort state. NOTE: the
full command sequence is required if resetting out of ABORT while using Unlock Bypass Mode.
17. S29GL512NH/L = 2223h/23h, 2201h/01h; S29GL256NH/L = 2222h/22h, 2201h/01h; S29GL128NH/L = 2221h/21h, 2201h/
01h.
18. The Exit command returns the device to reading the array.
19. Note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
20. For PWDx, only one portion of the password can be programmed per each “A0” command.
21. The All PPB Erase command embeds programming of all PPB bits before erasure.
22. All Lock Register bits are one-time programmable. Note that the program state = “0” and the erase state = “1”. Also note
that of both the Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the
same time or the Lock Register Bits Program operation will abort and return the device to read mode. Lock Register bits that
are reserved for future use will default to “1's”. The Lock Register is shipped out as “FFFF's” before Lock Register Bit program
execution.
23. If any of the Entry command was initiated, an Exit command must be issued to reset the device into read mode. Otherwise
the device will hang.
24. If ACC = VHH, sector protection will match when ACC = VIH
25. Protected State = “00h”, Unprotected State = “01h”.
82
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
Write Operation Status
The device provides several bits to determine the status of a program or erase
operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 13 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress.
The device also provides a hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is in progress or has been
completed.
Note that all Write Operation Status DQ bits are valid only after 4 µs delay.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Program or Erase algorithm is in progress or completed, or whether the device is
in Erase Suspend. Data# Polling is valid after the rising edge of the final WE#
pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must
provide an address within any of the sectors selected for erasure to read valid
status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7
may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to
valid data on DQ7. Depending on when the system samples the DQ7 output, it
may read the status or valid data. Even if the device has completed the program
or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may
be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.
Table 13 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data#
Polling algorithm. Figure 17 in the AC Characteristics section shows the Data#
Polling timing diagram.
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
83
A d v a n c e
I n f o r m a t i o n
START
Read DQ15–DQ0
Addr = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1
Yes
Read DQ15–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 5.
Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an
Embedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel with
a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is in the read mode, the standby mode, or in the erase-suspend-read
mode. Table 13 shows the outputs for RY/BY#.
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S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table 13 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit
algorithm. Figure 18 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 19 shows the differences between DQ2 and DQ6 in graphical
form. See also the subsection on DQ2: Toggle Bit II.
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
85
A d v a n c e
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START
Read DQ7–DQ0
Read DQ7–DQ0
Toggle Bit
= Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note:
The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling
as DQ5 changes to “1.” See the subsections on DQ6
and DQ2 for more information.
Figure 6.
Toggle Bit Algorithm
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# to control the
86
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 13 to compare outputs for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart form, and the section “DQ2:
Toggle Bit II” explains the algorithm. See also the RY/BY#: Ready/Busy# subsection. Figure 18 shows the toggle bit timing diagram. Figure 19 shows the
differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 and Figure 19 for the following discussion. Whenever the system
initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in
a row to determine whether a toggle bit is toggling. Typically, the system would
note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If
the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5
produces a “1,” indicating that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a
location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset command to return the device
to the reading the array (or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors are selected for erasure,
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
87
A d v a n c e
I n f o r m a t i o n
the entire time-out also applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the
Sector Erase Command Sequence section.
After the sector erase command is written, the system should read the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the
system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 13 shows the status of DQ3 relative to the other status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these
conditions DQ1 produces a “1”. The system must issue the Write-to-Buffer-AbortReset command sequence to return the device to reading array data. See Write
Buffer section for more details.
Table 13.
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
DQ1
RY/
BY#
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
0
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
N/A
0
Status
Standard
Mode
Program
Suspend
Mode
Erase
Suspend
Mode
Write-toBuffer
Write Operation Status
ProgramSuspend
Read
EraseSuspend
Read
Program-Suspended
Sector
Invalid (not allowed)
1
Data
1
Non-Program
Suspended Sector
Erase-Suspended
Sector
1
No toggle
0
Non-Erase
Suspended Sector
N/A
Toggle
N/A
Data
1
1
Erase-Suspend-Program
(Embedded Program)
DQ7#
Toggle
0
N/A
N/A
N/A
0
Busy (Note 3)
DQ7#
Toggle
0
N/A
N/A
0
0
Abort (Note 4)
DQ7#
Toggle
0
N/A
N/A
1
0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum
timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.
88
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
Absolute Maximum Ratings
A9, OE#, and ACC (Note 5) . . . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V
All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to VCC + 0.5V
5. Minimum DC input voltage on pins A9, OE#, and ACC is
20 ns
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
+0.8 V
–0.5 V
–2.0 V
2.0 V
20 ns
20 ns
Figure 7.
20 ns
Figure 8. Maximum Positive
Overshoot Waveform
Operating Ranges
Notes:
1. Operating ranges define those limits between which the functionality of the device is guaranteed.
2. See “Product Selector Guide” section on page 19.
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
89
A d v a n c e
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DC Characteristics
CMOS Compatible-S29GL128N, S29GL256N, S29GL512N
Parameter
Symbol
Parameter Description
(Notes)
Test Conditions
ILI
Input Load Current (1)
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9 Input Load Current
VCC = VCC max; A9 = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
ICC1
ICC2
VCC Active Read Current (1)
VCC Intra-Page Read Current (1)
Min
Typ
Max
WP/ACC: ±2.0
Others: ±1.0
Unit
µA
35
µA
±1.0
µA
CE# = VIL, OE# = VIH, VCC = VCCmax,
f = 5 MHz
30
50
CE# = VIL, OE# = VIH, VCC = VCCmax,
f = 10 MHz
60
90
CE# = VIL, OE# = VIH, VCC = VCCmax
f = 10 MHz
1
10
CE# = VIL, OE# = VIH, VCC = VCCmax,
f=33 MHz
5
20
50
80
mA
mA
mA
ICC3
VCC Active Erase/Program Current (2, 3) CE# = VIL, OE# = VIH, VCC = VCCmax
ICC4
VCC Standby Current
CE#, RESET# = VSS ± 0.3 V, OE# =
VIH, VCC = VCCmax VIL = VSS + 0.3 V/0.1V
1
5
mA
ICC5
VCC Reset Current
VCC = VCCmax;
VIL = VSS + 0.3 V/-0.1V,
RESET# = VSS ± 0.3 V
1
5
µA
ICC6
Automatic Sleep Mode (4)
VCC = VCCmax
VIH = VCC ± 0.3 V,
VIL = VSS + 0.3 V/-0.1V,
WP#/ACC = VIH
1
5
µA
IACC
ACC Accelerated Program Current
CE# = VIL, OE# = VIH, VCC = VCCmax,
WP#/ACC = VIH
WP#/ACC
pin
10
20
VCC pin
50
80
mA
VIL
Input Low Voltage (5)
–0.1
0.3 x VIO
V
VIH
Input High Voltage (5)
0.7 x VIO
VIO + 0.3
V
VHH
Voltage for ACC Erase/Program
Acceleration
VCC = 2.7 –3.6 V
11.5
12.5
V
VID
Voltage for Autoselect and Temporary
Sector Unprotect
VCC = 2.7 –3.6 V
11.5
12.5
V
VOL
Output Low Voltage (5)
IOL = 100 µA
0.15 x VIO
V
VOH
Output High Voltage (5)
IOH = -100 µA
VLKO
Low VCC Lock-Out Voltage (3)
0.85 x VIO
V
2.3
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. ICC active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.
3. Not 100% tested.
4. Automatic sleep mode enables the lower power mode when addresses remain stable tor tACC + 30 ns.
5. VIO = 1.65–1.95 V or 2.7–3.6 V
6. VCC = 3 V and VIO = 3V or 1.8V. When VIO is at 1.8V, I/O pins cannot operate at 3V.
90
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
Test Conditions
Table 14.
3.3 V
2.7 kΩ
Device
Under
Test
CL
6.2 kΩ
Note: Diodes are IN3064 or equivalent.
Figure 9.
Test Specifications
Test Condition
All Speeds
Unit
Output Load
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
Input Pulse Levels
0.0–VIO
V
Input timing measurement
reference levels (See Note)
0.5VIO
V
Output timing measurement
reference levels
0.5 VIO
V
Test Setup
Note: If VIO < VCC, the reference level is 0.5 VIO.
Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
VIO
Input
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
0.5 VIO
Measurement Level
0.5 VIO V
Output
0.0 V
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 10.
December 15, 2004 S29GLxxxN_MCP_A1
Input Waveforms and Measurement Levels
S29GLxxxN MirrorBitTM Flash Family
91
A d v a n c e
I n f o r m a t i o n
AC Characteristics
Read-Only Operations–S29GL128N, S29GL256N, S29GL512N
Speed Options
Parameter
JEDEC
Std.
Description
Test Setup
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
Address to Output Delay
(Note 2)
tELQV
tCE
Chip Enable to Output Delay
(Note 3)
VIO = VCC = 3 V
VIO = 1.8 V, VCC = 3 V
VIO = VCC = 3 V
VIO = 1.8 V, VCC = 3 V
VIO = VCC = 3 V
VIO = 1.8 V, VCC = 3 V
tPACC Page Access Time
Min
Max
Max
90
100 110 110 Unit
90
100
110
110
90
100
110
110
90
100
110
110
ns
ns
ns
Max
25
25
25
30
ns
25
25
35
35
ns
tGLQV
tOE
Output Enable to Output Delay
Max
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
20
ns
tGHQZ
tDF
Output Enable to Output High Z
(Note 1)
Max
20
ns
tAXQX
tOH
Output Hold Time From Addresses, CE#
or OE#, Whichever Occurs First
Min
0
ns
Read
Min
0
ns
tOEH
Output Enable Hold
Time (Note 1)
Toggle and
Data# Polling
Min
10
ns
Min
35
ns
tCEH
Chip Enable Hold Time Read
Notes:
1. Not 100% tested.
2. CE#, OE# = VIL
3. OE# = VIL
4. See Figure 9 and Table 14 for test specifications.
5. Unless otherwise indicated, AC specifications for 90 ns, 100 ns, and 110 ns speed options are tested with VIO = VCC = 3 V.
AC specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V.
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S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
AC Characteristics
tRC
Addresses Stable
Addresses
tACC
CE#
tCEH
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
Outputs
HIGH Z
Output Valid
RESET#
RY/BY#
0V
Figure 11.
Read Operation Timings
Same Page
Amax-A2
A2-A0*
Aa
tACC
Data Bus
Ab
tPACC
tPACC
Qa
Ad
Ac
Qb
tPACC
Qc
Qd
CE#
OE#
Notes:
1. Figure shows word mode.
Figure 12.
December 15, 2004 S29GLxxxN_MCP_A1
Page Read Timings
S29GLxxxN MirrorBitTM Flash Family
93
A d v a n c e
I n f o r m a t i o n
AC Characteristics
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
Speed (Note 2)
Unit
tReady
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
ns
tReady
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
Reset High Time Before Read (See Note)
Min
50
ns
tRPD
RESET# Low to Standby Mode
Min
20
µs
tRB
RY/BY# Recovery Time
Min
0
ns
Notes:
1. Not 100% tested. If ramp rate is equal to or faster than 1V/100µs with a falling edge of the RESET# pin initiated, the
RESET# pin needs to be held low only for 100µs for power-up.
2. Next generation devices may have different reset speeds.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
tRH
Figure 13.
94
Reset Timings
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
AC Characteristics
Erase and Program Operations–S29GL128N, S29GL256N, S29GL512N
Parameter
Speed Options
JEDEC
Std.
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle
bit polling
Min
15
ns
tAH
Address Hold Time
Min
45
ns
tAHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
45
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tCEPH
CE# High during toggle bit polling
Min
20
tOEPH
Output Enable High during toggle bit polling
Min
20
ns
tGHWL
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
ns
tWHDL
tWPH
Write Pulse Width High
Min
30
ns
Write Buffer Program Operation (Notes 2, 3)
Typ
240
µs
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word
Typ
15
µs
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
Per Word
Typ
13.5
µs
Program Operation (Note 2)
Word
Typ
60
µs
Accelerated Programming
Operation (Note 2)
Word
Typ
54
µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
Typ
0.5
sec
tVHH
VHH Rise and Fall Time (Note 1)
Min
250
ns
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tBUSY
Erase/Program Valid to RY/BY# Delay
Min
90
ns
tWLAX
tWHWH1 tWHWH1
90
100
110
110
Unit
90
100
110
110
ns
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 90 ns, 100 ns, and 110 ns speed options are tested with VIO = VCC
= 3 V. AC specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V.
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
95
A d v a n c e
I n f o r m a t i o n
AC Characteristics
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 14.
Program Operation Timings
VHH
ACC
VIL or VIH
VIL or VIH
tVHH
tVHH
Figure 15.
Accelerated Program Timing Diagram
Notes:
1. Not 100% tested.
2. CE#, OE# = VIL
3. OE# = VIL
4. See Figure 9 and Table 14 for test specifications.
96
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
AC Characteristics
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
555h for chip erase
VA
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (.
2. These waveforms are for the word mode.
Figure 16.
December 15, 2004 S29GLxxxN_MCP_A1
Chip/Sector Erase Operation Timings
S29GLxxxN MirrorBitTM Flash Family
97
A d v a n c e
I n f o r m a t i o n
AC Characteristics
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
DQ7
DQ6–DQ0
Complement
Complement
Status Data
Status Data
Valid Data
True
Valid Data
True
High Z
High Z
tBUSY
RY/BY#
Note:
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read
cycle.
2. tOE for data polling is 45 ns when VIO = 1.65 to 2.7 V and is 35 ns when VIO = 2.7 to 3.6 V
Figure 17.
98
Data# Polling Timings (During Embedded Algorithms)
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
AC Characteristics
tAHT
tAS
Addresses
tAHT
tASO
CE#
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
DQ2 and DQ6
tOE
Valid Data
Valid
Status
Valid
Status
Valid
Status
(first read)
(second read)
(stops toggling)
Valid Data
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command
sequence, last status read cycle, and array data read cycle
Figure 18.
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Toggle Bit Timings (During Embedded Algorithms)
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Resume
Erase
Erase Suspend
Suspend
Read
Program
Erase
Erase
Complete
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE#
or CE# to toggle DQ2 and DQ6.
Figure 19.
December 15, 2004 S29GLxxxN_MCP_A1
DQ2 vs. DQ6
S29GLxxxN MirrorBitTM Flash Family
99
A d v a n c e
I n f o r m a t i o n
AC Characteristics
Alternate CE# Controlled Erase and Program OperationsS29GL128N, S29GL256N, S29GL512N
Parameter
Speed Options
JEDEC
Std.
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
Min
15
ns
Min
45
ns
Min
0
ns
TASO
tELAX
tAH
tAHT
Address Setup Time to OE# low during
toggle bit polling
Address Hold Time
Address Hold Time From CE# or OE# high
during toggle bit polling
90
100
110
110
Unit
90
100
110
110
ns
tDVEH
tDS
Data Setup Time
Min
45
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tCEPH
CE# High during toggle bit polling
Min
20
ns
tOEPH
OE# High during toggle bit polling
Min
20
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
35
ns
tEHEL
tCPH
CE# Pulse Width High
Min
30
ns
Write Buffer Program Operation (Notes 2,
3)
Typ
240
µs
Effective Write Buffer
Program Operation (Notes
2, 4)
Per Word
Typ
15
µs
tWHWH1 tWHWH1 Effective Accelerated Write
Buffer Program Operation
(Notes 2, 4)
Per Word
Typ
13.5
µs
Program Operation (Note 2)
Word
Typ
60
µs
Accelerated Programming
Operation (Note 2)
Word
Typ
54
µs
Typ
0.5
sec
tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
Notes:
1. Not 100% tested.
2. See the “AC Characteristics” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 90 ns, 100ns, and 110 ns speed options are tested with VIO = VCC
= 3 V. AC specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V.
100
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
AC Characteristics
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tCP
CE#
tWS
tWHWH1 or 2
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Figure 20.
December 15, 2004 S29GLxxxN_MCP_A1
Alternate CE# Controlled Write (Erase/Program) Operation Timings
S29GLxxxN MirrorBitTM Flash Family
101
A d v a n c e
I n f o r m a t i o n
Erase And Programming Performance
Typ
(Note 1)
Max
(Note 2)
Unit
0.5
3.5
sec
S29GL128N
64
256
S29GL256N
128
512
S29GL512N
256
1024
Parameter
Sector Erase Time
Chip Erase Time
240
µs
Total Accelerated Effective
Write Buffer Programming
Time (Note 3)
200
µs
Chip Program Time
123
S29GL256N
246
S29GL512N
492
Excludes 00h
programming prior to
erasure (Note 5)
sec
Total Write Buffer
Programming Time
(Note 3)
S29GL128N
Comments
Excludes system level
overhead (Note 6)
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 10,000 cycles, checkerboard
pattern.
2. Under worst case conditions of 90°C, VCC = 3.0 V, 100,000 cycles.
3. Effective write buffer specification is based upon a 16-word write buffer operation.
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
words program faster than the maximum program times listed.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 12 for further information on command definitions.
TSOP Pin and BGA Package Capacitance
Parameter Symbol
Parameter Description
Test Setup
CIN
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
Typ
Max
Unit
TSOP
6
7.5
pF
BGA
4.2
5.0
pF
TSOP
8.5
12
pF
BGA
5.4
6.5
pF
TSOP
7.5
9
pF
BGA
3.9
4.7
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
102
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e
I n f o r m a t i o n
CellularRAM Type 2
128/64/32 Megabit
Burst CellularRAM
Features
„ Single device supports asynchronous, page, and burst operations
„ VCC Voltages
— 1.70V–1.95V VCC
„ Random Access Time: 70ns
„ Burst Mode Write Access
— Continuous burst
„ Burst Mode Read Access
— 4, 8, or 16 words, or continuous burst
„ Page Mode Read Access
— Sixteen-word page size
— Interpage read access: 70ns
— Intrapage read access: 20ns
„ Low Power Consumption
— Asynchronous READ < 25mA
— Intrapage READ < 15mA
— Initial access, burst READ < 35mA
— Continuous burst READ < 11mA
— Standby: 180µA
— Deep power-down < 10µA
„ Low-Power Features
— Temperature Compensated Refresh (TCR) On-chip sensor control
— Partial Array Refresh (PAR)
— Deep Power-Down (DPD) Mode
General Description
CellularRAM™ products are high-speed, CMOS dynamic random access memories
developed for low-power, portable applications. These devices include an industry
standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or Pseudo SRAM offerings.
To operate smoothly on a burst Flash bus, CellularRAM products incorporate a
transparent self-refresh mechanism. The hidden refresh requires no additional
support from the system memory controller and has no significant impact on device read/write performance.
Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system
memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is
performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal
operation.
Special attention has been focused on standby current consumption during self
refresh. CellularRAM products include three mechanisms to minimize standby
current. Partial array refresh (PAR) enables the system to limit refresh to only
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
103
A d v a n c e
I n f o r m a t i o n
that part of the DRAM array that contains essential data. Temperature compensated refresh (TCR) adjusts the refresh rate to match the device temperature—
the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down (DPD) enables the system to halt the
refresh operation altogether when no vital information is stored in the device. The
system-configurable refresh mechanisms are accessed through the RCR.
128M: A[22:0]
64M: A[21:0]
32M: A[20:0]
Address Decode
Logic
DRAM
MEMORY
ARRAY
Refresh Configuration
Register (RCR)
Input/
Output
MUX
and
Buffers
DQ[7:0]
DQ[15:8]
Bus Configuration
Register (BCR)
CE#
WE#
OE#
CLK
ADV#
CRE
WAIT
LB#
UB#
Control
Logic
Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed information.
Figure 21.
104
Functional Block Diagram
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
Table 15.
Signal Descriptions
Symbol
Type
Description
128M: A[22:0]
64M: A[21:0]
32M: A[20:0]
Input
Address Inputs: Inputs for addresses during READ and WRITE operations. Addresses are
internally latched during READ and WRITE cycles. The address lines are also used to define
the value to be loaded into the BCR or the RCR.
CLK
Input
Clock: Synchronizes the memory to the system operating frequency during synchronous
operations. When configured for synchronous operation, the address is latched on the first
rising CLK edge when ADV# is active. CLK is static (HIGH or LOW) during asynchronous
access READ and WRITE operations and during PAGE READ ACCESS operations.
ADV#
Input
Address Valid: Indicates that a valid address is present on the address inputs. Addresses
can be latched on the rising edge of ADV# during asynchronous READ and WRITE
operations. ADV# can be held LOW during asynchronous READ and WRITE operations.
CRE
Input
Configuration Register Enable: When CRE is HIGH, WRITE operations load the RCR or BCR.
CE#
Input
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and
goes into standby or deep power-down mode.
OE#
Input
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output
buffers are disabled.
WE#
Input
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a
WRITE to either a configuration register or to the memory array.
LB#
Input
Lower Byte Enable. DQ[7:0]
UB#
Input
Upper Byte Enable. DQ[15:8]
DQ[15:0]
Input/
Output
Data Inputs/Outputs.
WAIT
Output
Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is
gated by CE#. WAIT is used to arbitrate collisions between refresh and READ/WRITE
operations. WAIT is asserted when a burst crosses a row boundary. WAIT is also used to
mask the delay associated with opening a new internal page. WAIT is asserted and should
be ignored during asynchronous and page mode operations. WAIT is High-Z when CE# is
HIGH.
VCC
Supply
Device Power Supply: (1.7V–1.95V) Power supply for device core operation.
VCCQ
Supply
I/O Power Supply: (1.7V–1.95V) Power supply for input/output buffers.
VSS
Supply
VSS must be connected to ground.
VSSQ
Supply
VSSQ must be connected to ground.
Note: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode.
WAIT will be asserted but should be ignored during asynchronous and page mode operations.
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
105
A d v a n c e
Table 16.
I n f o r m a t i o n
Bus Operations—Asynchronous Mode
CLK
(Note 1) ADV#
CE#
OE#
WE#
CRE
LB#/
UB#
WAIT
(Note 2)
DQ[15:0]
(Note 3)
NOTES
L
L
L
H
L
L
Low-Z
Data-Out
4
X
L
L
X
L
L
L
Low-Z
Data-In
4
Standby
X
X
H
X
X
L
X
High-Z
High-Z
5, 6
No Operation
Idle
X
X
L
X
X
L
X
Low-Z
X
4, 6
Configuration
Register
Active
X
L
L
H
L
H
X
Low-Z
High-Z
DPD
Deep
Power-down
X
X
H
X
X
X
X
High-Z
High-Z
MODE
POWER
Read
Active
X
Write
Active
Standby
7
Notes:
1. CLK may be HIGH or LOW, but must be static during synchronous read, synchronous write, burst suspend, and DPD
modes; and to achieve standby power during standby and active modes.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0]
are affected. When only UB# is in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any
external influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current.
7. DPD is maintained until RCR is reconfigured.
106
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
Table 17.
CLK
(Note 1) ADV#
Bus Operations—Burst Mode
CE#
OE#
WE#
CRE
LB#/
UB#
WAIT
(Note 2)
DQ[15:0]
(Note 3)
NOTES
L
L
L
H
L
L
Low-Z
Data-Out
4
X
L
L
X
L
L
L
Low-Z
Data-In
4
Standby
X
X
H
X
X
L
X
High-Z
High-Z
5, 6
No Operation
Idle
X
X
L
X
X
L
X
Low-Z
X
4, 6
Initial Burst Read
Active
L
L
X
H
L
L
Low-Z
Data-Out
4, 8
Initial Burst Write
Active
L
L
H
L
L
X
Low-Z
Data-In
4, 8
Burst Continue
Active
H
L
X
X
L
X
Low-Z
Data-In or
Data-Out
4, 8
Burst Suspend
Active
X
L
H
X
L
X
Low-Z
High-Z
4, 8
Configuration
Register
Active
L
L
H
L
H
X
Low-Z
High-Z
8
DPD
Deep
Power-Down
X
H
X
X
X
X
High-Z
High-Z
7
MODE
POWER
Async Read
Active
X
Async Write
Active
Standby
X
X
Notes:
1. CLK may be HIGH or LOW, but must be static during asynchronous read, synchronous write, burst suspend, and
DPD modes; and to achieve standby power during standby and active modes.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0]
are affected. When only UB# is in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any
external influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current.
7. DPD is maintained until RCR is reconfigured.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
Functional Description
The CellularRAM bus interface supports both asynchronous and burst mode
transfers. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the
power-up initialization process. Initialization will configure the BCR and the RCR
with their default settings (see Table 18 and Table 22). VCC and VCCQ must be
applied simultaneously. When they reach a stable level at or above 1.7V, the device will require 150µs to complete its self-initialization process. During the
initialization period, CE# should remain HIGH. When initialization is complete, the
device is ready for normal operation.
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
107
A d v a n c e
VCC
VCCQ
VCC = 1.7 V
I n f o r m a t i o n
tPU > 150 µs
Device Initialization
Figure 22.
Device ready for
normal operation
Power-Up Initialization Timing
Bus Operating Modes
CellularRAM products incorporate a burst mode interface found on Flash products
targeting low-power, wireless applications. This bus interface supports asynchronous, page mode, and burst mode read and write transfers. The specific interface
supported is defined by the value loaded into the BCR. Page mode is controlled
by the refresh configuration register (RCR[7]).
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode
uses the industry standard SRAM control bus (CE#, OE#, WE#, LB#/ UB#).
READ operations (Figure 23) are initiated by bringing CE#, OE#, and LB#/UB#
LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the
specified access time has elapsed. WRITE operations (Figure 24) occur when
CE#, WE#, and LB#/ UB# are driven LOW. During asynchronous WRITE operations, the OE# level is a “Don't Care,” and WE# will override OE#. The data to be
written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs
first). Asynchronous operations (page mode disabled) can either use the ADV
input to latch the address, or ADV can be driven LOW during the entire READ/
WRITE operation.
During asynchronous operation, the CLK input must be held static (HIGH or LOW,
no transitions). WAIT will be driven while the device is enabled and its state
should be ignored.
CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
tRC = READ Cycle Time
Don't Care
Note: ADV must remain LOW for page mode operation.
Figure 23.
108
READ Operation (ADV# LOW)
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
tWC = WRITE Cycle Time
Don't Care
Figure 24.
WRITE Operation (ADV# LOW)
Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous
READ operation. In page mode-capable products, an initial asynchronous read
access is performed, then adjacent addresses can be read quickly by simply
changing the low-order address. Addresses A[3:0] are used to determine the
members of the 16-address CellularRAM page. Addresses A[4] and higher must
remain fixed during the entire page mode access. Figure 25 shows the timing for
a page mode access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE
operations do not include comparable page mode functionality.
During asynchronous page mode operation, the CLK input must be held LOW.
CE# must be driven HIGH upon completion of a page mode access. WAIT will be
driven while the device is enabled and its state should be ignored. Page mode is
enabled by setting RCR[7] to HIGH. WRITE operations do not include comparable
page mode functionality. ADV must be driven LOW during all page mode read
accesses.
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
109
A d v a n c e
I n f o r m a t i o n
CE#
OE#
WE#
ADDRESS
ADD[0]
tAA
ADD[1]
tAPA
D[0]
DATA
ADD[2]
tAPA
D[1]
ADD[3]
tAPA
D[2]
D[3]
LB#/UB#
Don't Care
Figure 25.
Page Mode READ Operation (ADV# LOW)
Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock sequence that must be performed
in an ordered fashion. After CE# goes LOW, the address to access is latched on
the rising edge of the next clock that ADV# is LOW. During this first clock rising
edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH,
Figure 26) or WRITE (WE# = LOW, Figure 27).
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, or sixteen words. Continuous
bursts have the ability to start at a specified address and burst through the entire
memory.
The latency count stored in the BCR defines the number of clock cycles that
elapse before the initial data value is transferred between the processor and CellularRAM device.
The WAIT output asserts as soon as a burst is initiated, and de-asserts to indicate
when data is to be transferred into (or out of) the memory. WAIT will again be
asserted if the burst crosses a row boundary. Once the CellularRAM device has
restored the previous row's data and accessed the next row, WAIT will be deasserted and the burst can continue (see Figure 47).
To access other devices on the same bus without the timing penalty of the initial
latency for a new burst, burst mode can be suspended. Bursts are suspended by
stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the
data bus while the burst is suspended, OE# should be taken HIGH to disable the
CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT output will continue to be active, and as a result no other devices should directly
share the WAIT connection to the controller. To continue the burst sequence, OE#
is taken LOW, then CLK is restarted after valid data is available on the bus.
See “How Extended Timings Impact CellularRAM™ Operation” for restrictions on
the maximum CE# LOW time during burst operations. If a burst suspension will
110
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and
the burst restarted with a new CE# LOW/ADV# LOW cycle.
CLK
A[22:0]
Address
Valid
ADV#
Latency Code 2 (3 clocks), variable
CE#
OE#
WE#
WAIT
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
LB#/UB#
Legend:
READ Burst Identified
(WE# = HIGH)
Don't care
Undefined
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted
during delay.
Figure 26.
Burst Mode READ (4-word burst)
CLK
A[22:0]
Address
Valid
ADV#
Latency Code 2 (3 clocks), variable
CE#
OE#
WE#
WAIT
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
LB#/UB#
Legend:
WRITE Burst Identified
(WE# = LOW)
Don't care
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted
during delay.
Figure 27.
October 4, 2004 cellRAM_00_A0
Burst Mode WRITE (4-word burst)
CellularRAM Type 2
111
A d v a n c e
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Mixed-Mode Operation
The device can support a combination of synchronous READ and asynchronous
WRITE operations when the BCR is configured for synchronous operation. The
asynchronous WRITE operation requires that the clock (CLK) remain static (HIGH
or LOW) during the entire sequence. The ADV# signal can be used to latch the
target address, or it can remain LOW during the entire WRITE operation. CE# can
remain LOW when transitioning between mixed-mode operations with fixed latency enabled. Note that the tCKA period is the same as a READ or WRITE cycle.
This time is required to ensure adequate refresh. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers. See
Figure 55 for the “Asynchronous WRITE Followed by Burst READ” timing diagram.
WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, system-level WAIT signal (see Figure 28 below). The shared WAIT signal is used by
the processor to coordinate transactions with multiple memories on the synchronous bus.
CellularRAM
WAIT
External
Pull-Up/
Pull-Down
Resistor
READY
Processor
Figure 28.
WAIT
WAIT
Other
Device
Other
Device
Wired or WAIT Configuration
Once a READ or WRITE operation has been initiated, WAIT goes active to indicate
that the CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output
from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT
transitions to an inactive state, the data burst will progress on successive clock
edges.
CE# must remain asserted during WAIT cycles (WAIT asserted and WAIT configuration BCR[8] = 1). Bringing CE# HIGH during WAIT cycles may cause data
corruption. (Note that for BCR[8] = 0, the actual WAIT cycles end one cycle after
WAIT de-asserts, and for row boundary crossings, start one cycle after the WAIT
signal asserts.)
When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for READ or WRITE operations launched while an on-chip
refresh is in progress. If a collision occurs, the WAIT pin is asserted for additional
clock cycles until the refresh has completed (see Figure 29 and Figure 30). When
the refresh operation has completed, the READ or WRITE operation will continue
normally.
WAIT is also asserted when a continuous READ or WRITE burst crosses the
boundary between 128-word rows. The WAIT assertion allows time for the new
row to be accessed, and permits any pending refresh operations to be performed.
WAIT will be asserted but should be ignored during asynchronous READ and
WRITE, and page READ operations.
112
CellularRAM Type 2
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I n f o r m a t i o n
LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data transfers. During
READ operations, the enabled byte(s) are driven onto the DQs. The DQs associated with a disabled byte are put into a High-Z state during a READ operation.
During WRITE operations, any disabled bytes will not be transferred to the RAM
array and the internal value will remain unchanged. During an asynchronous
WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#,
LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device
will disable the data bus from receiving or transmitting data. Although the device
will seem to be deselected, it remains in an active mode as long as CE# remains
LOW.
CLK
VIH
VIL
A[22:0]
VIH
VIL
ADV#
Address
Valid
VIH
VIL
CE#
VIH
VIL
OE#
VIH
VIL
WE#
VIH
VIL
LB#/UB#
VIH
VIL
WAIT
VOH
VOL
DQ[15:0]
VOH
VOL
High-Z
D[0]
Additional WAIT states inserted to allow refresh completion.
D[1]
Legend:
D[2]
Don't care
D[3]
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 29.
October 4, 2004 cellRAM_00_A0
Refresh Collision During READ Operation
CellularRAM Type 2
113
A d v a n c e
CLK
VIH
VIL
A[22:0]
VIH
VIL
ADV#
VIH
VIL
CE#
VIH
VIL
OE#
I n f o r m a t i o n
Address
Valid
VIH
VIL
WE#
VIH
VIL
LB#/UB#
VIH
VIL
WAIT
VOH
VOL
DQ[15:0]
VOH
VOL
High-Z
D[0]
D[1]
Additional WAIT states inserted to allow refresh completion.
D[2]
D[3]
Legend:
Don't care
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 30.
Refresh Collision During WRITE Operation
Low-Power Operation
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary
to perform the DRAM refresh operation. Standby operation occurs when CE# is
HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE
operation, or when the address and control inputs remain static for an extended
period of time. This mode will continue until a change occurs to the address or
control inputs.
Temperature Compensated Refresh
Temperature compensated refresh (TCR) is used to adjust the refresh rate depending on the device operating temperature. DRAM technology requires
increasingly frequent refresh operation to maintain data integrity as temperatures increase. More frequent refresh is required due to increased leakage of the
DRAM capacitive storage elements as temperatures rise. A decreased refresh rate
at lower temperatures will facilitate a savings in standby current.
TCR allows for adequate refresh at four different temperature thresholds (+15°C,
+45°C, +70°C, and +85°C). The setting selected must be for a temperature
higher than the case temperature of the CellularRAM device. For example, if the
case temperature is 50°C, the system can minimize self refresh current consumption by selecting the +7°0C setting. The +15°C and +45°C settings would
result in inadequate refreshing and cause data corruption.
114
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Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total
memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The
refresh options are full array, one-half array, one-quarter array, three-quarter array, or none of the array. The mapping of these partitions can start at either the
beginning or the end of the address map (see Table 23). READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in
addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are available immediately upon
writing to the RCR.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode
is used if the system does not require the storage provided by the CellularRAM
device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled by rewriting the RCR, the CellularRAM device
will require 150µs to perform an initialization procedure before normal operations
can resume. During this 150µs period, the current consumption will be higher
than the specified standby levels, but considerably lower than the active current
specification.
DPD cannot be enabled or disabled by writing to the RCR using the software access sequence; the RCR should be accessed using CRE instead.
Configuration Registers
Two user-accessible configuration registers define the device operation. The bus
configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash
devices. The refresh configuration register (RCR) is used to control how refresh
is performed on the DRAM array. These registers are automatically loaded with
default settings during power-up, and can be updated any time the devices are
operating in a standby state.
Access Using CRE
The configuration registers can be written to using either a synchronous or an
asynchronous operation when the configuration register enable (CRE) input is
HIGH (see Figure 31 and Figure 32). When CRE is LOW, a READ or WRITE operation will access the memory array. The register values are written via address
pins A[21:0]. In an asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first;
LB# and UB# are “Don’t Care.” The BCR is accessed when A[19] is HIGH; the
RCR is accessed when A[19] is LOW. For reads, address inputs other than A[19]
are “Don’t Care,” and register bits 15:0 are output on DQ[15:0].
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
115
A d v a n c e
A[22:0]
(except A19)
I n f o r m a t i o n
ADDRESS
OPCODE
tAVH
tAVS
Select Control Register
A19
(Note)
ADDRESS
CRE
tAVS
tAVH
tVPH
ADV#
tVP
tCBPH
Initiate Control Register Access
CE#
tCW
OE#
tWP
Write Address
Bus Value to
Control Register
WE#
LB#/UB#
DQ[15:0]
DATA VALID
Legend:
Don't care
Note: A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
Figure 31.
116
Configuration Register WRITE, Asynchronous Mode Followed by READ
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
CLK
Latch Control Register Value
A[22:0]
(except A19)
ADDRESS
OPCODE
tHD
Latch Control Register Address
tSP
A19
(Note 2)
ADDRESS
tSP
CRE
tHD
tSP
ADV#
tHD
tCBPH
(Note 3)
tCSP
CE#
OE#
tSP
WE#
tHD
LB#/UB#
tCEW
WAIT
High-Z
High-Z
DATA
VALID
DQ[15:0]
Legend:
Don't care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused
by refresh collisions require a corresponding number of additional CE# LOW cycles.
Figure 32.
Configuration Register WRITE, Synchronous Mode Followed by READ0
Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory
bus. Page mode operation is enabled by a bit contained in the RCR. Table 18
below describes the control bits in the BCR. At power up, the BCR is set to 9D4Fh.
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
117
A d v a n c e
I n f o r m a t i o n
The BCR is accessed using CRE and A[19] HIGH.
Table 18.
A[22:20]
22–20
Reserved
A19
19
18–16
Register
Select
All must be set to "0"
A15
A[18:16]
Reserved
15
A14
14
Operating
Mode
Must be set to "0"
Bus Configuration Register Definition
A13 A12
13
Initial
Latency
12
A11
11
Latency
Counter
A10
10
WAIT
Polarity
Must be set to "0"
A8
A9
9
Reserved
A7
8
7
WAIT
Configuration
(WC)
Must be set to "0"
6
Reserved
A5
A6
Reserved
5
A3
A4
4
Output
Impedance
3
Burst
Wrap
(BW)
(Note)
A2
2
1
A1 A0
0
Burst
Length
(BL)
(Note)
Must be set to "0"
Setting is ignored
BCR[5] BCR[4]
Output Impedance
0
0
Full Drive (default)
0
1
1/2 Drive
1
0
1/4 Drive
1
1
Reserved
BCR[13] BCR[12] BCR[11] Latency Counter
0
0
0
Code 0–Reserved
0
0
1
Code 1–Reserved
0
1
0
Code 2
0
1
1
Code 3 (Default)
1
0
0
Code 4
1
0
1
Code 5
1
1
0
Code 6
1
1
1
Code 7–Reserved
BCR[3]
BCR[8]
Burst Wrap (Note)
0
Burst wraps within the burst length
1
Burst no wrap (default)
WAIT Configuration
0
Asserted during delay
1
Asserted one data cycle before delay (default)
BCR[10] WAIT Polarity
BCR[15]
BCR[19]
0
Active LOW
1
Active HIGH (default)
Operating Mode
0
Synchronous burst access mode
1
Asynchronous access mode (default)
BCR[2] BCR[1] BCR[0] Burst Length (Note)
Register Select
0
Select RCR
1
Select BCR
0
0
1
4 words
0
1
0
8 words
0
1
1
16 words
1
1
1
Continuous burst (default)
Others
Reserved
Note: Burst wrap and length apply to READ operations only.
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CellularRAM Type 2
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A d v a n c e
I n f o r m a t i o n
Table 19.
BURST WRAP
BCR[3]
0
1
WRAP
Sequence and Burst Length
STARTING
ADDRESS
4-WORD
BURST
LENGTH
8-WORD BURST
LENGTH
16-WORD BURST LENGTH
CONTINUOUS
BURST
(DECIMAL)
LINEAR
LINEAR
LINEAR
LINEAR
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-3-4-5-6-…
1
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
1-2-3-4-5-6-7-…
2
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
2-3-4-5-6-7-8-…
3
3-0-1-2
Yes
No
3-4-5-6-7-0-1-2
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
3-4-5-6-7-8-9-…
4
4-5-6-7-0-1-2-3
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
4-5-6-7-8-9-10-…
5
5-6-7-0-1-2-3-4
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
5-6-7-8-9-10-11-…
6
6-7-0-1-2-3-4-5
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
6-7-8-9-10-11-12-…
7
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7-8-9-10-11-12-13-…
…
…
…
14
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
14-15-16-17-18-19-20-…
15
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
15-16-17-18-19-20-21…
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-3-4-5-6-…
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16
1-2-3-4-5-6-7-…
2
2-3-4-5
2-3-4-5-6-7-8-9
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17
2-3-4-5-6-7-8-…
3
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
3-4-5-6-7-8-9-…
4
4-5-6-7-8-9-10-11
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19
4-5-6-7-8-9-10-…
5
5-6-7-8-9-10-11-12
5-6-7-8-9-10-11-12-13-…-15-16-17-18-19-20
5-6-7-8-9-10-11…
6
6-7-8-9-10-11-12-13
6-7-8-9-10-11-12-13-14-…-16-17-18-19-20-21
6-7-8-9-10-11-12…
7
7-8-9-10-11-12-13-14
7-8-9-10-11-12-13-14-…-17-18-19-20-21-22
7-8-9-10-11-12-13…
…
…
…
14
14-15-16-17-18-19-…-23-24-25-26-27-28-29
14-15-16-17-18-19-20-…
15
5-16-17-18-19-20-…-24-25-26-27-28-29-30
15-16-17-18-19-20-21-…
Burst Length (BCR[2:0]): Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst READ
operations. The device supports a burst length of 4, 8, or 16 words. The device
can also be set in continuous burst mode where data is accessed sequentially
without regard to address boundaries. Enabling burst no-wrap with BCR[3] = 1
overrides the burst-length setting.
Burst Wrap (BCR[3]): Default = No Wrap
The burst-wrap option determines if a 4-, 8-, or 16-word READ burst wraps within
the burst length or steps through sequential addresses. If the wrap option is not
enabled, the device accesses data from sequential addresses without regard to
burst boundaries. When continuous burst operation is selected, the internal address wraps to 000000h if the burst goes past the last address. Enabling burst
nowrap (BCR[3] = 1) overrides the burst-length setting.
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
119
A d v a n c e
I n f o r m a t i o n
Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive
Strength
The output driver strength can be altered to full, one-half, or one-quarter
strength to adjust for different data bus loading scenarios. The reduced-strength
options are intended for stacked chip (Flash + CellularRAM) environments when
there is a dedicated memory bus. The reduced-drive-strength option minimizes
the noise generated on the data bus during READ operations. Normal output drive
strength should be selected when using a discrete CellularRAM device in a more
heavily loaded data bus environment. Outputs are configured at full drive
strength during testing.
Table 20.
Output Impedance
BCR[5]
BCR[4]
DRIVE STRENGTH
0
0
Full
0
1
1/2
1
0
1/4
1
1
Reserved
WAIT Configuration (BCR[8]): Default = WAIT Transitions One
Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between
the asserted and the de-asserted state with respect to valid data presented on
the data bus. The memory controller will use the WAIT signal to coordinate data
transfer during synchronous READ and WRITE operations. When BCR[8] = 0,
data will be valid or invalid on the clock edge immediately after WAIT transitions
to the de-asserted or asserted state, respectively (Figure 33 and Figure 35).
When A8 = 1, the WAIT signal transitions one clock period prior to the data bus
going valid or invalid (Figure 34).
WAIT Polarity (BCR[10]): Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH
or LOW. This bit will determine whether the WAIT signal requires a pull-up or pulldown resistor to maintain the de-asserted state.
CLK
WAIT
DQ[15:0]
High-Z
Data[0]
Data[1]
Data immediately valid (or invalid)
Note: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 35.
Figure 33.
120
WAIT Configuration (BCR[8] = 0)
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
CLK
WAIT
High-Z
DQ[15:0]
Data[0]
Data valid (or invalid) after one clock delay
Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 35.
Figure 34.
WAIT Configuration (BCR[8] = 1)
CLK
WAIT
BCR[8] = 0
DATA VALID IN CURRENT CYCLE
WAIT
BCR[8] = 1
DATA VALID IN NEXT CYCLE
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
D[4]
Legend:
Don't care
Note: Non-default BCR setting: WAIT active LOW.
Figure 35.
WAIT Configuration During Burst Operation
Latency Counter (BCR[13:11]): Default = Three-Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. Latency
codes from two (three clocks) to six (seven clocks) are allowed (see Table 21 and
Figure 36 below).
Table 21.
Variable Latency Configuration Codes
LATENCY (Note)
MAX INPUT CLK FREQUENCY (MHz)
BCR[13:11]
LATENCY
CONFIGURATION CODE
NORMAL
REFRESH
COLLISION
70ns/80 MHz
85ns/66 MHz
010
2 (3 clocks)
2
4
75 (13.0ns)
44 (22.7ns)
011
3 (4 clocks)—default
3
6
100
4 (5 clocks)
4
8
80 (12.5ns)
66 (15.2ns)
Note: Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle.
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
121
A d v a n c e
CLK
A[21:0]
ADV#
I n f o r m a t i o n
VIH
VIL
VIH
VIL
Valid Address
VIH
VIL
Code 2
A/DQ[15:0]
VOH
Valid
Output
VOL
Code 3
A/DQ[15:0]
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
(Default)
VOH
VOL
Code 4
A/DQ[15:0]
VOH
VOL
Legend:
Figure 36.
Don't care
Undefined
Latency Counter (Variable Initial Latency, No Refresh Collision)
Operating Mode (BCR[15]): Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default
asynchronous mode of operation.
Refresh Configuration Register
The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can
dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Table 22 below describes the control bits used
in the RCR. At power-up, the RCR is set to 0070h. The RCR is accessed using CRE
and A[19] LOW.
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A d v a n c e
Table 22.
A[22:20]
A19
22–20
Reserved
Refresh Configuration Register Mapping
A[18:8]
19
Register
Select
I n f o r m a t i o n
18–8
7
Reserved
Page
A5
A6
A7
6
A4
5
4
TCR
3
DPD
Select RCR
1
Select BCR
2
Reserved
RCR[19] Register Select
0
A2
A1
Address Bus
A0
1
Read Configuration
Register
0
PAR
Must be set to "0"
All must be set to "0"
All must be set to "0"
A3
RCR[2] RCR[1] RCR[0]
Refresh Coverage
0
0
0
Full array (default)
0
0
1
Bottom 1/2 array
0
1
0
Bottom 1/4 array
Page Mode Enable/Disable
0
1
1
Bottom 1/8 array
0
Page Mode Disabled (default)
1
0
0
None of array
1
Page Mode Enable
1
0
1
Top 1/2 array
1
1
0
Top 1/4 array
1
1
1
Top 3/4 array
RCR[7]
Maximum Case Temp
RCR[6]
RCR[5]
1
1
+85ºC (default)
0
0
+70ºC
0
1
+45ºC
1
0
+15ºC
RCR[4]
Deep Power-Down
0
DPD Enable
1
DPD Disable (default)
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the device to reduce standby current by refreshing only that part
of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, three-quarters array, or none of the array.
The mapping of these partitions can start at either the beginning or the end of
the address map (see Table 23 through Table 25).
Table 23.
128Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
ADDRESS SPACE
SIZE
DENSITY
0
0
0
Full die
000000h–7FFFFFh
8 Meg x 16
128Mb
0
0
1
One-half of die
000000h–3FFFFFh
4 Meg x 16
64Mb
0
1
0
One-quarter of die
000000h–1FFFFFh
2 Meg x 16
32Mb
0
1
1
One-eighth of die
000000h–0FFFFFh
1 Meg x 16
16Mb
1
0
0
None of die
0
0 Meg x 16
0Mb
1
0
1
One-half of die
400000h–7FFFFFh
4 Meg x 16
64Mb
1
1
0
One-quarter of die
600000h–7FFFFFh
2 Meg x 16
32Mb
1
1
1
One-eighth of die
700000h–7FFFFFh
1 Meg x 16
16Mb
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
123
A d v a n c e
Table 24.
I n f o r m a t i o n
64Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
ADDRESS SPACE
SIZE
DENSITY
0
0
0
Full die
000000h–3FFFFFh
4 Meg x 16
64Mb
0
0
1
One-half of die
000000h–2FFFFFh
3 Meg x 16
48Mb
0
1
0
One-quarter of die
000000h–1FFFFFh
2 Meg x 16
32Mb
0
1
1
One-eighth of die
000000h–0FFFFFh
1 Meg x 16
16Mb
1
0
0
None of die
0
0 Meg x 16
0Mb
1
0
1
One-half of die
100000h–3FFFFFh
3 Meg x 16
48Mb
1
1
0
One-quarter of die
200000h–3FFFFFh
2 Meg x 16
32Mb
1
1
1
One-eighth of die
300000h–3FFFFFh
1 Meg x 16
16Mb
Table 25.
32Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
ADDRESS SPACE
SIZE
DENSITY
0
0
0
Full die
000000h–1FFFFFh
2 Meg x 16
32Mb
0
0
1
One-half of die
000000h–17FFFFh
1.5 Meg x 16
24Mb
0
1
0
One-quarter of die
000000h–0FFFFFh
1 Meg x 16
16Mb
0
1
1
One-eighth of die
000000h–07FFFFh
512K x 16
8Mb
1
0
0
None of die
0
0 Meg x 16
0Mb
1
0
1
One-half of die
080000h–1FFFFFh
1.5 Meg x 16
24Mb
1
1
0
One-quarter of die
100000h–1FFFFFh
1 Meg x 16
16Mb
1
1
1
One-eighth of die
180000h–1FFFFFh
512K x 16
8Mb
Deep Power-Down (RCR[4]): Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This
mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When
refresh activity has been re-enabled, the CellularRAM device will require 150µs
to perform an initialization procedure before normal operations can resume.
Deep power-down is enabled when RCR[4] = 0, and remains enabled until
RCR[4] is set to “1.”
Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC
Operation
The TCR bits allow for adequate refresh at four different temperature thresholds
(+15ºC, +45ºC, +70ºC, and +85ºC). The setting selected must be for a temperature higher than the case temperature of the CellurlarRAM device. If the case
temperature is +50ºC, the system can minimize self refresh current consumption
by selecting the +70ºC setting. The +15ºC and +45ºC settings would result in
inadequate refreshing and cause data corruption.
Page Mode Operation (RCR[7]): Default = Disabled
The page mode operation bit determines whether page mode is enabled for asynchronous READ operations. In the power-up default state, page mode is disabled.
124
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
Absolute Maximum Ratings
Voltage to Any Ball Except VCC, VCCQ
Relative to VSS . . . . . -0.50V to (4.0V or VCCQ + 0.3V, whichever is less)
Voltage on VCC Supply Relative to VSS . . . . . . . . . . . . . . . .
-0.2V to +2.45V
Voltage on VCCQ Supply Relative to VSS . . . . . . . . . . . . . . . . -0.2V to +2.45V
Storage Temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . -55ºC to +150ºC
Operating Temperature (case)
Wireless. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25ºC to +85ºC
*Stresses greater than those listed may cause permanent damage to the device. This
is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
125
A d v a n c e
I n f o r m a t i o n
DC Characteristics
Table 26.
Description
Electrical Characteristics and Operating Conditions
Conditions
Symbol
Min
Max
Units
1.70
1.95
V
W: 1.8V
1.70
1.95
V
J: 1.5V
1.35
1.65
V
Notes
Supply Voltage
VCC
I/O Supply Voltage
VCCQ
Input High Voltage
VIH
VCCQ - 0.4
VCCQ + 0.2
V
2
Input Low Voltage
VIL
-0.20
0.4
V
3
0.80 VCCQ
V
4
4
Output High Voltage
IOH = -0.2mA
VOH
Output Low Voltage
IOL = +0.2mA
VOL
0.20 VCCQ
V
Input Leakage Current
VIN = 0 to VCCQ
ILI
1
µA
Output Leakage Current
OE# = VIH or
Chip Disabled
ILO
1
µA
Operating Current
Asynchronous Random READ
Asynchronous Page READ
Initial Access, Burst READ
Continuous Burst READ
VIN = VCCQ or 0V
Chip Enabled,
IOUT = 0
VIN = VCCQ or 0V
Chip Enabled,
IOUT = 0
WRITE Operating Current
VIN = VCCQ or 0V
Chip Enabled
Standby Current
VIN = VCCQ or 0V
CE# = VCCQ
ICC1
ICC1
ICC2
ISB
-70
25
-85
20
-70
15
-85
12
80 MHz
35
66 MHz
30
80 MHz
18
66 MHz
15
-70
25
-85
20
128 M
180
64 M
120
32 M
110
mA
5
mA
5
mA
µA
6
Notes:
1. Wireless Temperature (-25ºC < TC < +85ºC); Industrial Temperature (-40ºC < TC < +85ºC).
2. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions.
3. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions.
4. BCR[5:4] = 00b.
5. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the
current required to drive output capacitance expected in the actual system.
6. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85°C. To achieve low standby current,
all inputs must be driven to either VCCQ or VSS.
126
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
Table 27.
I n f o r m a t i o n
Temperature Compensated Refresh Specifications and Conditions
Description
Conditions
Symbol
Density
Max Case
Temperature
Standard
Power
(No Desig.)
+85°C
120
+70°C
105
+45°C
85
+15°C
70
+85°C
110
+70°C
95
+45°C
80
+15°C
70
64 Mb
Temperature Compensated
Refresh Standby Current
VIN = VCCQ or 0V,
CE# = VCCQ
ITCR
32 Mb
Units
µA
Note: IPAR (MAX) values measured with TCR set to 85°C.
Table 28.
Description
Partial Array Refresh Specifications and Conditions
Conditions
Symbol
Density
64 Mb
Partially Array Refresh Standby
Current
VIN = VCCQ or 0V,
CE# = VCCQ
IPAR
32 Mb
128 Mb
Array
Partition
Standard
Power
(No Desig.)
Full
120
1/2
115
1/4
110
1/8
105
0
70
Full
110
1/2
105
1/4
100
1/8
95
0
70
Full
180
0
50
Units
µA
Note:IPAR (MAX) values measured with TCR set to 85°C.
Table 29.
Deep Power-Down Specifications
Description
Conditions
Symbol
Typ
Units
Deep Power-down
VIN = VCCQ or 0V; +25°C; VCC = 1.8V
IZZ
10
µA
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
127
A d v a n c e
I n f o r m a t i o n
AC Characteristics
VCC Q
Input
(Note 1)
VSS
VCCQ /2
(Note 2)
VCCQ/2
(Note 3)
Test Points
Output
Notes:
1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns.
2. Input timing begins at VCCQ/2.
3. Output timing ends at VCCQ/2.
Figure 37.
AC Input/Output Reference Waveform
VCCQ
R1
Test Point
DUT
30pF
R2
Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
128
Figure 38.
Output Load Circuit
Table 30.
Output Load Circuit
VCCQ
R1/R2
1.8V
2.7K Ω
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
Table 31.
I n f o r m a t i o n
Asynchronous READ Cycle Timing Requirements
85ns/66 MHz
70ns/80 MHz
Min
Min
Max
Units
Notes
Parameter
Symbol
Address Access Time
tAA
85
70
ns
ADV# Access Time
tAADV
85
70
ns
Page Access Time
tAPA
25
20
ns
Address Hold from ADV# HIGH
tAVH
5
5
ns
Address Setup to ADV# HIGH
tAVS
10
10
ns
LB#/UB# Access Time
tBA
85
70
ns
LB#/UB# Disable to DQ High-Z Output
tBHZ
8
8
ns
4
LB#/UB# Enable to Low-Z Output
tBLZ
10
10
ns
3
CE# HIGH between Subsequent Mixed-Mode Operations
tCBPH
5
5
ns
Maximum CE# Pulse Width
tCEM
CE# LOW to WAIT Valid
tCEW
Chip Select Access Time
tCO
CE# LOW to ADV# HIGH
tCVS
Chip Disable to DQ and WAIT High-Z Output
tHZ
Chip Enable to Low-Z Output
tLZ
Output Enable to Valid Output
tOE
Output Hold from Address Change
tOH
Output Disable to DQ High-Z Output
tOHZ
Output Enable to Low-Z Output
tOLZ
5
Page Cycle Time
tPC
READ Cycle Time
4
1
7.5
1
85
10
Max
4
µs
7.5
ns
70
ns
10
8
10
ns
8
10
20
5
20
5
8
2
ns
4
ns
3
ns
ns
8
ns
4
5
ns
3
25
20
ns
tRC
85
70
ns
ADV# Pulse Width LOW
tVP
10
10
ns
ADV# Pulse Width HIGH
tVPH
10
10
ns
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. See “How Extended Timings Impact CellularRAM™ Operation” below.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 38. The Low-Z timings measure a
4. 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
5. Low-Z to High-Z timings are tested with the circuit shown in Figure 38. The High-Z timings measure a 100mV
transition from either VOH or VOL toward VCCQ/2.
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
129
A d v a n c e
Table 32.
I n f o r m a t i o n
Burst READ Cycle Timing Requirements
70ns/80 MHz
85ns/66 MHz
Min
Min
Parameter
Symbol
Max
Max
Units
Burst to READ Access Time (Variable Latency)
tABA
35
55
ns
CLK to Output Delay
tACLK
9
11
ns
Address Setup to ADV# HIGH
tAVS
Burst OE# LOW to Output Delay
tBOE
CE# HIGH between Subsequent Mixed-Mode Operations
tCBPH
5
CE# LOW to WAIT Valid
tCEW
1
CLK Period
tCLK
12.5
15
ns
CE# Setup Time to Active CLK Edge
tCSP
4
5
ns
Hold Time from Active CLK Edge
tHD
2
2
ns
Chip Disable to DQ and WAIT High-Z Output
tHZ
8
8
ns
CLK Rise or Fall Time
tKHKL
1.6
1.6
ns
CLK to WAIT Valid
tKHTL
9
11
ns
CLK to DQ High-Z Output
tKHZ
3
8
3
8
ns
CLK to Low-Z Output
tKLZ
2
5
2
5
ns
Output HOLD from CLK
tKOH
2
2
ns
CLK HIGH or LOW Time
tKP
3
3
ns
Output Disable to DQ High-Z Output
tOHZ
Output Enable to Low-Z Output
tOLZ
5
Setup Time to Active CLK Edge
tSP
3
10
10
20
ns
20
5
7.5
1
8
Notes
ns
ns
7.5
8
ns
2
ns
2
5
ns
3
3
ns
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 38. The High-Z timings measure a 100mV
transition from either VOH or VOL toward VCCQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 38. The Low-Z timings measure a 100mV
transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
130
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
Table 33.
I n f o r m a t i o n
Asynchronous WRITE Cycle Timing Requirements
70ns/80 MHz
85ns/66 MHz
Min
Parameter
Symbol
Min
Max
Address and ADV# LOW Setup Time
tAS
0
0
ns
Address Hold from ADV# Going HIGH
tAVH
5
5
ns
Address Setup to ADV# Going HIGH
tAVS
10
10
Address Valid to End of Write
tAW
70
85
ns
LB#/UB# Select to End of Write
tBW
70
85
ns
Maximum CE# Pulse Width
tCEM
CE# LOW to WAIT Valid
tCEW
1
Async Address-to-Burst Transition Time
tCKA
70
85
ns
CE# Low to ADV# HIGH
tCVS
10
10
ns
Chip Enable to End of Write
tCW
70
85
ns
Data Hold from Write Time
tDH
0
0
ns
Data WRITE Setup Time
tDW
23
23
ns
Chip Disable to WAIT High-Z Output
tHZ
Chip Enable to Low-Z Output
tLZ
10
10
ns
3
End WRITE to Low-Z Output
tOW
5
5
ns
3
ADV# Pulse Width
tVP
10
10
ns
ADV# Pulse Width HIGH
tVPH
10
10
ns
ADV# Setup to End of WRITE
tVS
70
85
ns
WRITE Cycle Time
tWC
70
85
ns
WRITE to DQ High-Z Output
tWHZ
WRITE Pulse Width
tWP
46
WRITE Pulse Width HIGH
tWPH
WRITE Recovery Time
tWR
4
7.5
1
8
Max
Notes
ns
4
µs
7.5
ns
8
8
Units
8
1
1
ns
ns
2
55
ns
1
10
10
ns
0
0
ns
Notes:
1. See “How Extended Timings Impact CellularRAM™ Operation” below.
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 38. The High-Z timings measure a 100mV
transition from either VOH or VOL toward VCCQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 38. The Low-Z timings measure a 100mV
transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
Table 34.
Burst WRITE Cycle Timing Requirements
70ns/80 MHz
85ns/66 MHz
Min
Parameter
Symbol
Min
CE# HIGH between Subsequent Mixed-Mode Operations
tCBPH
5
CE# LOW to WAIT Valid
tCEW
1
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
Max
Max
5
7.5
1
Units
Notes
ns
7.5
ns
131
A d v a n c e
Table 34.
I n f o r m a t i o n
Burst WRITE Cycle Timing Requirements (Continued)
70ns/80 MHz
85ns/66 MHz
Min
Parameter
Symbol
Min
Max
Max
Units
Clock Period
tCLK
12.5
15
ns
CE# Setup to CLK Active Edge
tCSP
4
5
ns
Hold Time from Active CLK Edge
tHD
2
2
ns
Chip Disable to WAIT High-Z Output
tHZ
8
8
ns
CLK Rise or Fall Time
tKHKL
1.6
1.6
ns
Clock to WAIT Valid
tKHTL
9
11
ns
CLK HIGH or LOW Time
tKP
3
3
ns
Setup Time to Activate CLK Edge
tSP
3
3
ns
Notes
Timing Diagrams
VCC (MIN)
VCC, VCCQ = 1.7V
tPU
Figure 39.
Table 35.
Initialization Period
Initialization Timing Parameters
Parameter
Symbol
Initialization Period (required before normal operations)
tPU
132
Device ready for
normal operation
CellularRAM Type 2
70ns/80 MHz
85ns/66 MHz
Min
Min
Max
150
Max
Units
150
µs
Notes
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
t RC
A[22:0]
V IH
VALID ADDRESS
V IL
t AA
ADV#
V IH
V IL
t CBPH
CE#
t HZ
V IH
V IL
t CO
t BHZ
t BA
LB#/UB#
V IH
V IL
t OE
OE#
WE#
t OHZ
V IH
V IL
V IH
V IL
t OLZ
t BLZ
t LZ
DQ[15:0]
V OH
High-Z
VALID OUTPUT
V OL
t HZ
t CEW
WAIT
V IH
High-Z
High-Z
V IL
Legend:
Figure 40.
Table 36.
Min
Undefined
Asynchronous READ
Asynchronous READ Timing Parameters
70ns/80 MHz
Symbol
Don't Care
85ns/66 MHz
Max
Min
Max
Units
tAA
70
85
ns
tBA
70
85
ns
tBHZ
8
8
ns
tBLZ
10
10
ns
tCBPH
5
5
ns
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
133
A d v a n c e
Table 36.
I n f o r m a t i o n
Asynchronous READ Timing Parameters (Continued)
70ns/80 MHz
Symbol
Min
Max
Min
Max
Units
tCEW
1
7.5
1
7.5
ns
tCO
70
tHZ
8
tLZ
134
85ns/66 MHz
10
ns
8
10
ns
ns
tOE
20
20
ns
tOHZ
8
8
ns
tOLZ
5
5
ns
tRC
70
85
ns
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
A[22:0]
V IH
I n f o r m a t i o n
VALID ADDRESS
V IL
t AA
t AVS
t VPH
ADV#
t AVH
V IH
V IL
t AADV
t VP
t CBPH
CE#
t CVS
t HZ
V IH
V IL
t CO
t BHZ
t BA
LB#/UB#
V IH
V IL
t OE
OE#
WE#
t OHZ
V IH
V IL
V IH
V IL
t OLZ
t BLZ
t LZ
DQ[15:0]
V OH
High-Z
VALID OUTPUT
V OL
t HZ
t CEW
WAIT
V IH
High-Z
High-Z
V IL
Legend:
Figure 41.
Table 37.
Min
Undefined
Asynchronous READ Using ADV#
Asynchronous READ Timing Parameters Using ADV#
70ns/80 MHz
Symbol
Don't Care
85ns/66 MHz
Max
Min
Max
Units
tAA
70
85
ns
tAADV
70
85
ns
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
135
A d v a n c e
Table 37.
I n f o r m a t i o n
Asynchronous READ Timing Parameters Using ADV# (Continued)
70ns/80 MHz
Symbol
Min
tCVS
10
10
ns
tAVH
5
5
ns
tAVS
10
10
ns
Max
Min
Max
Units
tBA
70
85
ns
tBHZ
8
8
ns
tBLZ
10
10
ns
tCBPH
5
5
ns
tCEW
1
tCO
tCVS
tLZ
7.5
1
70
10
7.5
ns
85
ns
10
8
tHZ
136
85ns/66 MHz
10
ns
8
10
ns
ns
tOE
20
20
ns
tOHZ
8
8
ns
tOLZ
5
5
ns
tVP
10
10
ns
tVPH
10
10
ns
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
t RC
A[22:0]
A[3:0]
V IH
VALID ADDRESS
V IL
V IH
VALID ADDRESS
V IL
t AA
ADV#
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
t PC
V IH
V IL
t CEM
t CBPH
CE#
t CBPH
t CO
t HZ
V IH
V IL
t BHZ
t BA
LB#/UB#
V IH
V IL
t OE
OE#
WE#
V IH
V IL
V IH
t OLZ
V IL
t BLZ
t APA
t OH
t LZ
DQ[15:0]
t OHZ
V OH
High-Z
VALID
OUTPUT
V OL
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
t HZ
t CEW
WAIT
V IH
High-Z
High-Z
V IL
Legend:
Figure 42.
Table 38.
Undefined
Page Mode READ
Asynchronous READ Timing Parameters—Page Mode Operation
70ns/80 MHz
Symbol
Don't Care
Min
85ns/66 MHz
Max
Min
Max
Units
tAA
70
85
ns
tAPA
20
25
ns
tBA
70
85
ns
tBHZ
8
8
ns
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
137
A d v a n c e
Table 38.
I n f o r m a t i o n
Asynchronous READ Timing Parameters—Page Mode Operation (Continued)
70ns/80 MHz
Symbol
Min
tBLZ
10
10
ns
tCBPH
5
5
ns
tCEW
Max
Min
4
tCEM
1
7.5
1
Max
Units
4
µs
7.5
ns
tCO
70
85
ns
tHZ
8
8
ns
tLZ
10
tOH
10
20
tOE
ns
20
5
5
8
tOHZ
138
85ns/66 MHz
ns
ns
8
ns
tOLZ
5
5
ns
tPC
20
25
ns
tRC
70
85
ns
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
t KP
t CLK
t KP
V IH
CLK
V IL
t KHKL
t SP
V IH
A[22:0]
t HD
VALID ADDRESS
V IL
t SP
t HD
V IH
ADV#
V IL
t HD
t HZ
t ABA
t CSP
V IH
CE#
V IL
OE#
V IL
t SP
t OLZ
t HD
V IH
WE#
V IL
t SP
t HD
V IH
LB#/UB#
V IL
t CEW
WAIT
t OHZ
t BOE
V IH
V OH
t KHTL
High-Z
High-Z
V OL
t KOH
t ACLK
DQ[15:0]
V OH
High-Z
VALID OUTPUT
V OL
Legend:
READ Burst Identified
(WE# = HIGH)
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 43.
Table 39.
Single-Access Burst READ Operation—Variable Latency
Burst READ Timing Parameters—Single Access, Variable Latency
70ns/80 MHz
Symbol
Min
85ns/66 MHz
Max
Min
Max
Units
tABA
35
55
ns
tACLK
9
11
ns
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
139
A d v a n c e
Table 39.
I n f o r m a t i o n
Burst READ Timing Parameters—Single Access, Variable Latency (Continued)
70ns/80 MHz
Symbol
Min
tBOE
Max
Min
20
7.5
1
Max
Units
20
ns
7.5
ns
tCEW
1
tCLK
12.5
15
ns
tCSP
4
5
ns
tHD
2
2
ns
tHZ
8
8
ns
tKHKL
1.6
1.6
ns
tKHTL
9
11
ns
tKOH
2
2
ns
tKP
3
3
ns
8
tOHZ
140
85ns/66 MHz
8
ns
tOLZ
5
5
ns
tSP
3
3
ns
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
t CLK
t KHKL
CLK
V IL
V IH
V IL
t HD
Valid
Address
t SP
ADV#
t HD
V IH
V IL
t CSP
CE#
t KP
V IH
t SP
A[22:0]
t KP
t HD
t ABA
t CBPH
V IH
V IL
t HZ
OE#
WE#
LB#/UB#
V IL
t SP
t HD
t SP
t HD
t OLZ
V IH
V IL
V IH
V IL
t CEW
WAIT
t OHZ
t BOE
V IH
V OH
t KHTL
High-Z
High-Z
V OL
t KOH
t ACLK
DQ[15:0]
V OH
High-Z
VALID
OUTPUT
V OL
VALID
OUTPUT
VALID
OUTPUT
Legend:
READ Burst Identified
(WE# = HIGH)
VALID
OUTPUT
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 44.
October 4, 2004 cellRAM_00_A0
Four-word Burst READ Operation—Variable Latency
CellularRAM Type 2
141
A d v a n c e
Table 40.
I n f o r m a t i o n
Burst READ Timing Parameters—4-word Burst
70ns/80 MHz
Symbol
Min
Max
Min
Max
Units
tABA
35
55
ns
tACLK
9
11
ns
tBOE
20
20
ns
tCBPH
5
tCEW
1
tCLK
12.5
15
ns
tCSP
4
5
ns
tHD
2
2
ns
5
7.5
1
ns
7.5
ns
tHZ
8
8
ns
tKHKL
1.6
1.6
ns
tKHTL
9
11
ns
tKOH
2
2
ns
tKP
3
3
ns
8
tOHZ
142
85ns/66 MHz
8
ns
tOLZ
5
5
ns
tSP
3
3
ns
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
t CLK
CLK
V IH
V IL
t SP
A[22:0]
V IH
V IL
t HD
Valid
Address
t SP
ADV#
t HD
V IH
V IL
t HD
t CSP
CE#
t CBPH
V IH
V IL
t HZ
OE#
WE#
LB#/UB#
V IL
t SP
t HD
t SP
t HD
t OLZ
V IH
V IL
V IH
V IL
t CEW
WAIT
t OHZ
t BOE
V IH
V OH
t KHTL
High-Z
High-Z
V OL
t KOH
t ACLK
DQ[15:0]
V OH
High-Z
t KHTL
VALID
OUTPUT
V OL
VALID
OUTPUT
Legend:
READ Burst Identified
(WE# = HIGH)
t KHTL
t KHTL
VALID
OUTPUT
High-Z
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 45.
October 4, 2004 cellRAM_00_A0
Four-word Burst READ Operation (with LB#/UB#)
CellularRAM Type 2
143
A d v a n c e
Table 41.
I n f o r m a t i o n
Burst READ Timing Parameters—4-word Burst with LB#/UB#
70ns/80 MHz
Symbol
Min
Max
Min
Max
Units
tACLK
9
11
ns
tBOE
20
20
ns
tCBPH
5
tCEW
1
tCLK
12.5
15
ns
tCSP
4
5
ns
tHD
2
2
ns
5
7.5
1
ns
7.5
ns
tHZ
8
8
ns
tKHTL
9
11
ns
tKHZ
3
8
3
8
ns
tKLZ
2
5
2
5
ns
tKOH
2
2
8
tOHZ
144
85ns/66 MHz
ns
8
ns
tOLZ
5
5
ns
tSP
3
3
ns
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
t CLK
CLK
V IH
V IL
t SP
A[22:0]
V IH
t HD
Valid
Address
Valid
Address
V IL
t HD
t SP
ADV#
V IH
V IL
t CBPH
t HZ
t CSP
CE#
OE#
V IH
V IL
t OHZ
V IH
t SP
WE#
t HD
V IH
V IL
t SP
LB#/UB#
t HD
V IH
V IL
t CEW
WAIT
t OHZ
(Note 2)
V IL
V IH
t OLZ
t BOE
High-Z
High-Z
V IL
t KOH
t BOE
t ACLK
t OLZ
DQ[15:0]
V OH
High-Z
VALID
OUTPUT
V OL
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Legend:
VALID
OUTPUT
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. OE# can stay LOW during burst suspend. If OE# is LOW, DQ[15:0] will continue to output valid data.
Figure 46.
Table 42.
READ Burst Suspend
Burst READ Timing Parameters—Burst Suspend
70ns/80 MHz
Symbol
Min
85ns/66 MHz
Max
Min
Max
Units
tACLK
9
11
ns
tBOE
20
20
ns
tCBPH
5
5
ns
tCLK
12.5
15
ns
tCSP
4
5
ns
tHD
2
2
ns
8
tHZ
tKOH
2
October 4, 2004 cellRAM_00_A0
2
8
tOHZ
tOLZ
8
5
CellularRAM Type 2
ns
8
5
ns
ns
ns
145
A d v a n c e
Table 42.
I n f o r m a t i o n
Burst READ Timing Parameters—Burst Suspend (Continued)
70ns/80 MHz
Symbol
Min
tSP
3
CLK
85ns/66 MHz
Max
Min
Max
Units
3
ns
V IH
V IL
t CLK
A[22:0]
ADV#
LB#/UB#
CE#
OE#
WE#
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
t OHZ
V IL
t KHTL
t KHTL
WAIT
V OH
(Note 2)
V OL
t KOH
t ACLK
DQ[15:0]
V OH
V OL
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Legend:
Don't Care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 47.
Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition
Table 43.
Burst READ Timing Parameters—BCR[8] = 0
70ns/80 MHz
Symbol
Min
tACLK
tCLK
146
Max
Min
9
12.5
Max
Units
11
ns
15
9
tKHTL
tKOH
85ns/66 MHz
2
11
2
CellularRAM Type 2
ns
ns
ns
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
t AA
A[22:0]
V IH
VALID ADDRESS
V IL
t AW
t AS
ADV#
t WR
V IH
V IL
t CEM
t CW
CE#
V IH
V IL
t BW
LB#/UB#
OE#
V IH
V IL
V IH
V IL
t WPH
WE#
t WP
V IH
V IL
t DW
DQ[15:0] V IH
IN V
IL
High-Z
t LZ
VALID
INPUT
t WHZ
DQ[15:0] V OH
OUT V
OL
t HZ
t CEW
WAIT
V IH
t DH
High-Z
High-Z
V IL
Legend:
Figure 48.
Table 44.
Don't Care
CE#-Controlled Asynchronous WRITE
Asynchronous WRITE Timing Parameters—CE#-Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
Min
tAS
0
0
ns
tAW
70
85
ns
tBW
70
85
ns
tCEM
October 4, 2004 cellRAM_00_A0
Max
Min
4
CellularRAM Type 2
Max
4
Units
µs
147
A d v a n c e
Table 44.
I n f o r m a t i o n
Asynchronous WRITE Timing Parameters—CE#-Controlled (Continued)
70ns/80 MHz
Symbol
Min
Max
Min
Max
Units
tCEW
1
7.5
1
7.5
ns
tCW
70
85
ns
tDH
0
0
ns
tDW
23
23
ns
8
tHZ
8
ns
tLZ
10
10
ns
tWC
70
85
ns
8
tWHZ
148
85ns/66 MHz
8
ns
tWP
46
55
ns
tWPH
10
10
ns
tWR
0
0
ns
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
t WC
A[22:0]
V IH
VALID ADDRESS
V IL
t AW
t AS
ADV#
t WR
V IH
V IL
t CEM
t CW
CE#
V IH
V IL
t BW
LB#/UB#
OE#
V IH
V IL
V IH
V IL
t WPH
WE#
t WP
V IH
V IL
t DW
High-Z
DQ[15:0] V IH
IN V
IL
t LZ
VALID
INPUT
t WHZ
DQ[15:0] V OH
OUT V
OL
t HZ
t CEW
WAIT
t DH
V IH
High-Z
High-Z
V IL
Legend:
Figure 49.
Table 45.
Don't Care
LB#/UB#-Controlled Asynchronous WRITE
Asynchronous WRITE Timing Parameters—LB#/UB#-Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
Min
tAS
0
0
ns
tAW
70
85
ns
tBW
70
85
ns
October 4, 2004 cellRAM_00_A0
Max
Min
CellularRAM Type 2
Max
Units
149
A d v a n c e
Table 45.
I n f o r m a t i o n
Asynchronous WRITE Timing Parameters—LB#/UB#-Controlled (Continued)
70ns/80 MHz
Symbol
Min
tCEM
Max
Min
4
7.5
1
Max
Units
4
µs
7.5
ns
tCEW
1
tCW
70
85
ns
tDH
0
0
ns
tDW
23
23
ns
8
tHZ
8
ns
tLZ
10
10
ns
tWC
70
85
ns
tWHZ
150
85ns/66 MHz
8
8
ns
tWP
46
55
ns
tWPH
10
10
ns
tWR
0
0
ns
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
t WC
A[22:0]
V IH
VALID ADDRESS
V IL
t AW
t WR
ADV#
V IH
V IL
t CEM
t CW
CE#
V IH
V IL
t BW
LB#/UB#
OE#
V IH
V IL
V IH
V IL
t AS
t WPH
WE#
t WP
V IH
V IL
t DW
High-Z
DQ[15:0] V IH
IN V
IL
t LZ
t DH
VALID
INPUT
t WHZ
t OW
DQ[15:0] V OH
OUT V
OL
t CEW
WAIT
V IH
t HZ
High-Z
High-Z
V IL
Legend:
Figure 50.
Table 46.
WE#-Controlled Asynchronous WRITE
Asynchronous WRITE Timing Parameters—WE#-Controlled
70ns/80 MHz
Symbol
Min
tAS
0
October 4, 2004 cellRAM_00_A0
Don't Care
85ns/66 MHz
Max
Min
0
CellularRAM Type 2
Max
Units
ns
151
A d v a n c e
Table 46.
I n f o r m a t i o n
Asynchronous WRITE Timing Parameters—WE#-Controlled (Continued)
70ns/80 MHz
Symbol
Min
tAW
70
85
ns
tBW
70
85
ns
Max
Min
4
tCEM
7.5
1
Max
Units
4
µs
7.5
ns
tCEW
1
tCW
70
85
ns
tDH
0
0
ns
tDW
23
23
ns
8
tHZ
8
ns
tLZ
10
10
ns
tOW
5
5
ns
tWC
70
85
ns
8
tWHZ
152
85ns/66 MHz
8
ns
tWP
46
55
ns
tWPH
10
10
ns
tWR
0
0
ns
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
A[22:0]
I n f o r m a t i o n
V IH
VALID ADDRESS
V IL
t AVS
t AVH
t VS
t VPH
t VP
t AS
ADV#
V IH
V IL
t AS
t AW
t CEM
t CW
CE#
V IH
V IL
t BW
LB#/UB#
OE#
V IH
V IL
V IH
V IL
t WP
WE#
t WPH
V IH
V IL
t DW
High-Z
DQ[15:0] V IH
IN V
IL
t LZ
t DH
VALID
INPUT
t WHZ
t OW
DQ[15:0] V OH
OUT V
OL
t CEW
WAIT
V IH
t HZ
High-Z
High-Z
V IL
Legend:
Figure 51.
October 4, 2004 cellRAM_00_A0
Don't Care
Asynchronous WRITE Using ADV#
CellularRAM Type 2
153
A d v a n c e
Table 47.
I n f o r m a t i o n
Asynchronous WRITE Timing Parameters Using ADV#
70ns/80 MHz
Symbol
Min
tAS
0
0
ns
tAVH
5
5
ns
tAVS
10
10
ns
tAW
70
85
ns
tBW
70
85
ns
Max
Min
4
tCEM
7.5
1
Max
Units
4
µs
7.5
ns
tCEW
1
tCW
70
85
ns
tDH
0
0
ns
tDW
23
23
ns
8
tHZ
8
ns
tLZ
10
10
ns
tOW
5
5
ns
tAS
0
0
ns
tVP
10
10
ns
tVPH
10
10
ns
tVS
70
85
ns
8
tWHZ
154
85ns/66 MHz
8
ns
tWP
46
55
ns
tWPH
10
10
ns
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
t KHKL
t KP
t CLK
CLK
V IH
V IL
t SP
A[22:0]
V IH
V IL
t HD
Valid
Address
t SP
ADV#
t KP
t HD
V IH
V IL
t SP
t HD
LB#/UB#
V IH
V IL
t CSP
CE#
OE#
WE#
t HD
V IL
V IH
V IL
t SP
t HD
V IH
t OHZ
V IL
t CEW
WAIT
V IH
t HZ
t KHTL
High-Z
(Note 2)
High-Z
V IL
t SP
DQ[15:0]
t CBPH
V IH
V OH
t HD
D[1]
V OL
D[2]
D[3]
D[0]
Legend:
READ Burst Identified
(WE# = LOW)
Don't Care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay; burst
length four; burst wrap enabled.
Figure 52.
October 4, 2004 cellRAM_00_A0
Burst WRITE Operation
CellularRAM Type 2
155
A d v a n c e
Table 48.
I n f o r m a t i o n
Burst WRITE Timing Parameters
70ns/80 MHz
156
85ns/66 MHz
Symbol
Min
Max
Min
Max
tCBPH
5
tCEW
1
tCLK
12.5
15
ns
tCSP
4
5
ns
tHD
2
2
ns
5
7.5
1
Units
ns
7.5
ns
tHZ
8
8
ns
tKHKL
1.6
1.6
ns
tKHTL
9
11
ns
tKP
3
3
ns
tSP
3
3
ns
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
CLK
I n f o r m a t i o n
V IH
V IL
t CLK
A[22:0]
ADV#
LB#/UB#
CE#
WE#
OE#
WAIT
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
t OHZ
V IL
V IH
V IL
t KHTL
V OH
V OL
t SP
DQ[15:0]
t KHTL
(Note 2)
V OH
V OL
t HD
Valid Input Valid Input
D[n+3]
D[n+2]
Valid Input Valid Input
D[n]
D[n+1]
Legend:
END OF ROW
Don't Care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 53.
Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition
Table 49.
Burst WRITE Timing Parameters—BCR[8] = 0
70ns/80 MHz
85ns/66 MHz
Symbol
Min
Max
Min
Max
Units
tCLK
12.5
15
ns
tHD
2
2
ns
tKHTL
8
11
ns
tSP
3
3
ns
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
157
A d v a n c e
I n f o r m a t i o n
t CLK
CLK
V IH
V IL
t SP
A[22:0]
V IH
t SP
t HD
Valid
Address
V IL
t HD
Valid
Address
t SP
t SP
ADV#
t HD
t HD
V IH
V IL
t SP
LB#/UB#
t HD
V IH
V IL
t HD
t CSP
CE#
t CBPH
V IH
V IL
(Note 2)
OE#
WAIT
t SP
t HD
t HD
V IH
V IL
V OH
t BOE
High-Z
High-Z
V OL
t SP
DQ[15:0]
t OHZ
V IL
t SP
WE#
t CSP
V IH
V IH
High-Z
V IL
t ACLK
t HD
D[0]
D[1]
D[2]
V OH
D[3]
High-Z
t KOH
Valid
Output
V OL
Valid
Output
Valid
Output
Legend:
Valid
Output
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. To allow self-refresh operations to occur between transactions, CE# must remain HIGH for at least 5ns (tCBPH) to
schedule the appropriate internal refresh operation. CE# can stay LOW between burst READ and burst WRITE
operations. See “How Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE#
LOW time (tCEM).
Figure 54.
Table 50.
Burst WRITE Followed by Burst READ
WRITE Timing Parameters—Burst WRITE Followed by Burst READ
70ns/80 MHz
85ns/66 MHz
Symbol
Min
tCBPH
5
tCLK
12.5
20
15
20
ns
tCSP
4
20
5
20
ns
tHD
2
2
ns
tSP
3
3
ns
Table 51.
Max
Min
5
Symbol
Min
tACLK
9
ns
85ns/66 MHz
Max
Min
Max
11
ns
20
tBOE
158
Units
READ Timing Parameters—Burst WRITE Followed by Burst READ
70ns/80 MHz
tCLK
Max
12.5
20
15
CellularRAM Type 2
Units
ns
ns
cellRAM_00_A0 October 4, 2004
A d v a n c e
Table 51.
I n f o r m a t i o n
READ Timing Parameters—Burst WRITE Followed by Burst READ (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
Min
Max
Min
Max
tCSP
4
5
ns
tHD
2
2
ns
tKOH
2
2
ns
8
tOHZ
8
3
tSP
Units
ns
3
ns
t CLK
CLK
V IH
V IL
t WC
A[22:0]
V IH
t WC
Valid
Address
V IL
t AVS
t CKA
Valid
Address
t AVH
t AW
LB#/UB#
t WR
t SP
t HD
V IH
V IL
t VP
t VS
t CVS
t BW
t SP
t HD
V IH
V IL
t CW
CE#
t HD
Valid
Address
t VPH
ADV#
t SP
t CBPH
t CSP
V IH
V IL
(Note 2)
OE#
t OHZ
V IH
V IL
t WC
t AS
WE#
t WP t WPH
t SP
t HD
V IH
V IL
t CEW
WAIT
t BOE
V OH
High-Z
V OL
t WHZ
DQ[15:0]
V IH
V IL
t ACLK
High-Z
DATA
t DH
DATA
V OH
High-Z
V OL
t DW
Valid
Output
Valid
Output
Valid
Output
Valid
Output
t KOH
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How
Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 55.
October 4, 2004 cellRAM_00_A0
Asynchronous WRITE Followed by Burst READ
CellularRAM Type 2
159
A d v a n c e
Table 52.
I n f o r m a t i o n
WRITE Timing Parameters—Asynchronous WRITE Followed by Burst READ
70ns/80 MHz
85ns/66 MHz
Symbol
Min
Max
Min
tAVH
5
5
ns
tAS
0
0
ns
tAVS
10
10
ns
tAW
70
85
ns
tBW
70
85
ns
tCKA
70
85
ns
tCVS
10
10
ns
tCW
70
85
ns
tDH
0
0
ns
tDW
20
23
ns
tVP
10
10
ns
tVPH
10
10
ns
tVS
70
85
ns
tWC
70
85
ns
8
tWHZ
Units
8
ns
tWP
46
55
ns
tWPH
10
10
ns
tWR
0
0
ns
Table 53.
READ Timing Parameters—Asynchronous WRITE Followed by Burst READ
70ns/80 MHz
Symbol
Min
85ns/66 MHz
Max
Min
Max
Units
tACLK
9
11
ns
tBOE
20
20
ns
tCBPH
5
tCEW
1
tCLK
12.5
15
ns
tCSP
4
5
ns
tHD
2
2
ns
tKOH
2
2
ns
tSP
5
7.5
1
8
tOHZ
160
Max
3
7.5
8
3
CellularRAM Type 2
ns
ns
ns
ns
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
t CLK
CLK
V IH
V IL
t WC
A[22:0]
V IH
V IL
t WC
Valid
Address
t CKA
t SP
Valid
Address
t AW
Valid
Address
t WR
t SP
ADV#
V IL
t SP
t HD
V IH
V IL
t CW
CE#
t HD
V IH
t BW
LB#/UB#
t HD
t CSP
t CSP
V IH
V IL
(Note 2)
OE#
t OHZ
V IH
V IL
t WC
t WP t WPH
WE#
t SP
t HD
V IH
V IL
t BOE
t CEW
WAIT
V OH
High-Z
V OL
t WHZ
DQ[15:0]
V IH
t DW
t ACLK
High-Z
DATA
V IL
V OH
DATA
High-Z
t KOH
Valid
Output
V OL
Valid
Output
Valid
Output
Valid
Output
t DH
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How
Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 56.
Asynchronous WRITE (ADV# LOW) Followed By Burst READ
Table 54.
Asynchronous WRITE Timing Parameters—ADV# LOW
70ns/80 MHz
85ns/66 MHz
Symbol
Min
tAW
70
85
ns
tBW
70
85
ns
tCKA
70
85
ns
tCW
70
85
ns
tDH
0
0
ns
tDW
23
23
ns
tWC
70
85
ns
tWHZ
October 4, 2004 cellRAM_00_A0
Max
Min
8
CellularRAM Type 2
Max
8
Units
ns
161
A d v a n c e
Table 54.
I n f o r m a t i o n
Asynchronous WRITE Timing Parameters—ADV# LOW (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
Min
Max
tWP
46
55
ns
tWPH
10
10
ns
tWR
0
0
ns
Table 55.
Min
Min
85ns/66 MHz
Max
Min
Max
Units
tACLK
9
11
ns
tBOE
20
20
ns
tCBPH
5
tCEW
1
tCLK
12.5
15
ns
tCSP
4
5
ns
tHD
2
2
ns
tKOH
2
2
ns
tSP
5
7.5
1
8
tOHZ
162
Units
Burst READ Timing Parameters
70ns/80 MHz
Symbol
Max
3
7.5
8
3
CellularRAM Type 2
ns
ns
ns
ns
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
t CLK
CLK
V IH
V IL
t SP t HD
A[22:0]
V IH
t WC
Valid
Address
V IL
Valid
Address
t AW
t SP
t WR
t HD
ADV#
V IH
V IL
t CBPH
t CEM
t HD
t CSP
CE#
V IH
(Note 2)
V IL
t OHZ
t BOE
OE#
V IH
V IL
t AS
t SP
WE#
t HD
t OLZ
t WPH
V IL
t BW
t HD
V IH
V IL
t CEW
WAIT
t WP
V IH
t SP
LB#/UB#
t CW
t HZ
V OH
t CEW
t KHTL
t HZ
High-Z
High-Z
V OL
t DW
t ACLK
DQ[15:0]
High-Z
V IH
V IL
t DH
t KOH
Valid
Output
Valid
Input
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How
Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 57.
October 4, 2004 cellRAM_00_A0
Burst READ Followed by Asynchronous WRITE (WE#-Controlled)
CellularRAM Type 2
163
A d v a n c e
Table 56.
I n f o r m a t i o n
Burst READ Timing Parameters
70ns/80 MHz
Symbol
Min
85ns/66 MHz
Max
Min
Units
tACLK
9
11
ns
tBOE
20
20
ns
tCBPH
5
5
tCEW
1
tCLK
12.5
15
ns
tCSP
4
5
ns
tHD
2
2
ns
7.5
ns
1
7.5
ns
tHZ
8
8
ns
tKHKL
1.6
1.6
ns
tKHTL
9
11
ns
tKOH
2
2
ns
tKP
3
3
ns
8
tOHZ
Table 57.
8
ns
Asynchronous WRITE Timing Parameters—WE# Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
Min
tAS
0
tAW
70
85
ns
tBW
70
85
ns
Max
Min
4
tCEM
Max
Units
0
ns
4
µs
tCW
70
85
ns
tDH
0
0
ns
tDW
23
23
ns
8
tHZ
164
Max
8
ns
tWC
70
85
ns
tWP
46
55
ns
tWPH
10
10
ns
tWR
0
0
ns
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
t CLK
CLK
V IH
V IL
t SP
A[22:0]
V IH
t HD
Valid
Address
V IL
Valid
Address
t AVS
t VPH
t SP
t VS
t HD
ADV#
t AVH
t VP
V IH
V IL
t AW
t CBPH
t AS
t CEM
t HD
t CSP
CE#
V IH
(Note 2)
V IL
t OHZ
t BOE
OE#
V IH
V IL
t AS
t SP
WE#
t OLZ
t HD
t WPH
V IL
t BW
t HD
V IH
V IL
t CEW
WAIT
t WP
V IH
t SP
LB#/UB#
t CW
t HZ
V OH
t CEW
t KHTL
t HZ
High-Z
High-Z
V OL
t DW
t ACLK
DQ[15:0]
High-Z
V OH
V OL
t DH
t KOH
Valid
Output
Valid
Input
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How
Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 58.
October 4, 2004 cellRAM_00_A0
Burst READ Followed by Asynchronous WRITE Using ADV#
CellularRAM Type 2
165
A d v a n c e
Table 58.
I n f o r m a t i o n
Burst READ Timing Parameters
70ns/80 MHz
Symbol
Min
85ns/66 MHz
Max
Min
Units
tACLK
9
11
ns
tBOE
20
20
ns
tCBPH
5
5
tCEW
1
tCLK
12.5
15
ns
tCSP
4
5
ns
tHD
2
2
ns
7.5
ns
1
7.5
ns
tHZ
8
8
ns
tKHKL
1.6
1.6
ns
tKHTL
9
11
ns
tKOH
2
2
ns
tKP
3
3
ns
8
tOHZ
Table 59.
8
ns
Asynchronous WRITE Timing Parameters Using ADV#
70ns/80 MHz
85ns/66 MHz
Symbol
Min
tAS
0
0
ns
tAVH
5
5
ns
tAVS
10
10
ns
tAW
70
85
ns
tBW
70
85
ns
Max
Min
4
tCEM
7.5
1
Max
Units
4
µs
7.5
ns
tCEW
1
tCW
70
85
ns
tDH
0
0
ns
tDW
23
23
ns
8
tHZ
166
Max
8
ns
tVP
10
10
ns
tVPH
10
10
ns
tVS
70
85
ns
tWP
46
55
ns
tWPH
10
10
ns
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
Table 59.
I n f o r m a t i o n
Asynchronous WRITE Timing Parameters Using ADV# (Continued)
70ns/80 MHz
Symbol
Min
tWR
0
A[22:0]
V IH
Max
Max
Valid
Address
t WR
t AA
V IH
V IL
t BW
LB#/UB#
t BHZ
t BLZ
V IH
V IL
t CBPH
t CW
CE#
Units
ns
Valid
Address
t AW
ADV#
Min
0
Valid
Address
V IL
85ns/66 MHz
t CEM
t HZ
V IH
V IL
(Note)
t LZ
t OHZ
t OE
OE#
V IH
V IL
t WC
t AS
WE#
t WP t WPH
V IH
V IL
t HZ
WAIT
t HZ
V OH
V OL
t WHZ
DQ[15:0]
V IH
t OLZ
High-Z
V IL
High-Z
DATA
t DH
V OH
DATA
Valid
Output
V OL
t DW
Legend:
Don't Care
Undefined
Note: CE# can stay LOW when transitioning between asynchronous operations. If CE# goes HIGH, it must remain HIGH
for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 59.
Asynchronous WRITE Followed by Asynchronous READ—ADV# LOW
Table 60.
WRITE Timing Parameters—ADV# LOW
70ns/80 MHz
85ns/66 MHz
Symbol
Min
tAS
0
0
ns
tAW
70
85
ns
tBW
70
85
ns
tCW
70
85
ns
October 4, 2004 cellRAM_00_A0
Max
Min
CellularRAM Type 2
Max
Units
167
A d v a n c e
Table 60.
I n f o r m a t i o n
WRITE Timing Parameters—ADV# LOW (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
Min
Max
tDH
0
0
ns
tDW
23
23
ns
70
8
85
Units
ns
ns
8
tWHZ
8
ns
tWP
46
55
ns
tWPH
10
10
ns
tWR
0
0
ns
Table 61.
READ Timing Parameters—ADV# LOW
70ns/80 MHz
Symbol
Min
85ns/66 MHz
Max
Min
Max
Units
tAA
70
85
ns
tBHZ
8
8
ns
tBLZ
10
10
ns
tCBPH
5
5
ns
tCEM
4
4
µs
tHZ
8
8
ns
tLZ
10
10
ns
tOE
20
20
ns
tOHZ
8
8
ns
tOLZ
168
Max
8
tHZ
tWC
Min
5
5
CellularRAM Type 2
ns
cellRAM_00_A0 October 4, 2004
A d v a n c e
A[22:0]
V IH
Valid
Address
V IL
t AVS
Valid
Address
t AVH
t AW
t VPH t VP
ADV#
Valid
Address
t AA
t WR
t VS
V IH
V IL
t BW
t CVS
LB#/UB#
I n f o r m a t i o n
V IL
t CBPH
t CW
CE#
t CEM
t HZ
V IH
V IL
(Note)
t AS
OE#
t BHZ
t BLZ
V IH
t LZ
t OHZ
V IH
V IL
t WC
t AS
WE#
WAIT
t WP t WPH
t OLZ
V IH
V IL
V OH
V OL
t WHZ
DQ[15:0]
V IH
t OE
High-Z
DATA
V IL
t DH
High-Z
V OH
DATA
Valid
Output
V OL
t DW
Legend:
Don't Care
Undefined
Note: CE# can stay LOW when transitioning between asynchronous operations. If CE# goes HIGH, it must remain HIGH
for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 60.
Table 62.
Asynchronous WRITE Followed by Asynchronous READ
WRITE Timing Parameters—Asynchronous WRITE Followed by Asynchronous READ
70ns/80 MHz
85ns/66 MHz
Symbol
Min
tAS
0
0
ns
tAVH
5
5
ns
tAVS
10
10
ns
tAW
70
85
ns
tBW
70
85
ns
tCVS
10
10
ns
tCW
70
85
ns
tDH
0
0
ns
tDW
23
23
ns
October 4, 2004 cellRAM_00_A0
Max
Min
CellularRAM Type 2
Max
Units
169
A d v a n c e
Table 62.
I n f o r m a t i o n
WRITE Timing Parameters—Asynchronous WRITE Followed by Asynchronous READ
70ns/80 MHz
85ns/66 MHz
Symbol
Min
Max
Min
Max
tVP
10
10
ns
tVPH
10
10
ns
tVS
70
85
ns
tWC
70
85
ns
8
tWHZ
Units
8
ns
tWP
46
55
ns
tWPH
10
10
ns
tWR
0
0
ns
Table 63.
READ Timing Parameters—Asynchronous WRITE Followed by Asynchronous READ
70ns/80 MHz
Symbol
Min
85ns/66 MHz
Max
Min
Max
Units
tAA
70
85
ns
tBHZ
8
8
ns
tBLZ
10
10
ns
tCBPH
5
5
ns
tCEM
4
4
µs
tHZ
8
8
ns
10
tLZ
10
ns
tOE
20
20
ns
tOHZ
8
8
ns
5
tOLZ
5
ns
How Extended Timings Impact CellularRAM™ Operation
Introduction
This section describes CellularRAM™ timing requirements in systems that perform extended operations.
CellularRAM products use a DRAM technology that periodically requires refresh to
ensure against data corruption. CellularRAM devices include on-chip circuitry that
performs the required refresh in a manner that is completely transparent in systems with normal bus timings. The refresh circuitry imposes constraints on
timings in systems that take longer than 4µs to complete an operation. WRITE
operations are affected if the device is configured for asynchronous operation.
Both READ and WRITE operations are affected if the device is configured for page
or burst-mode operation.
170
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
Asynchronous WRITE Operation
The timing parameters provided in Figure 33 require that all WRITE operations
must be completed within 4µs. After completing a WRITE operation, the device
must either enter standby (by transitioning CE# HIGH), or else perform a second
operation (READ or WRITE) using a new address. Figure 61 and Figure 62 demonstrate these constraints as they apply during an asynchronous (page-modedisabled) operation. Either the CE# active period (tCEM in Figure 61) or the address valid period (tTM in Figure 62) must be less than 4µs during any WRITE
operation, otherwise, the extended WRITE timings must be used.
tCEM < 4 µs
CE#
ADDRESS
Figure 61.
Extended Timing for tCEM
CE#
tTM < 4µs
ADDRESS
Figure 62.
Table 64.
Extended Timing for tTM
Extended Cycle Impact on READ and WRITE Cycles
Page Mode
Timing Constraint
Read Cycle
Write Cycle
Asynchronous
Page Mode Disabled
tCEM and tTM > 4µs
(See Figure 61 and Figure 62.)
No impact.
Must use extended WRITE
timing.
(See Figure 62)
Asynchronous
Page Mode Enabled
tCEM > 4µs
(See Figure 61.)
All following intrapage READ
access times are tAA (not tAPA).
Must use extended WRITE
timing.
(See Figure 63)
Burst
tCEM > 4µs (See Figure 61.)
Burst must cross a row boundary within 4µs.
Extended WRITE Timing— Asynchronous WRITE Operation
Modified timings are required during extended WRITE operations (see Figure 63).
An extended WRITE operation requires that both the write pulse width (tWP) and
the data valid period (tDW) be lengthened to at least the minimum WRITE cycle
time (tWC [MIN]). These increased timings ensure that time is available for both
a refresh operation and a successful completion of the WRITE operation.
October 4, 2004 cellRAM_00_A0
CellularRAM Type 2
171
A d v a n c e
I n f o r m a t i o n
t CEM or t TM > 4µs
ADDRESS
CE#
LB#/UB#
t WP > t WC (MIN)
WE#
t DW > t WC (MIN)
DATA-IN
Figure 63.
Extended WRITE Operation
Page Mode READ Operation
When a CellularRAM device is configured for page mode operation, the address
inputs are used to accelerate read accesses and cannot be used by the on-chip
circuitry to schedule refresh. If CE# is LOW longer than the tCEM maximum time
of 4µs during a READ operation, the system must allow tAA (not tAPA, as would
otherwise be expected) for all subsequent intrapage accesses until CE# goes
HIGH.
Burst-Mode Operation
When configured for burst-mode operation, it is necessary to allow the device to
perform a refresh within any 4µs window. One of two conditions will enable the
device to schedule a refresh within 4µs. The first condition is when all burst operations complete within 4µs. A burst completes when the CE# signal is
registered HIGH on a rising clock edge. The second condition that allows a refresh
is when a burst access crosses a row boundary. The row-boundary crossing
causes WAIT to be asserted while the next row is accessed and enables the
scheduling of refresh.
Summary
CellularRAM products are designed to ensure that any possible asynchronous timings do not cause data corruption due to lack of refresh. Slow bus timings on
asynchronous WRITE operations require that tWP and tDW be lengthened. Slow
bus timings during asynchronous page READ operations cause the next intrapage
READ data to be delayed to tAA.
Burst mode timings must allow the device to perform a refresh within any 4µs
period. A burst operation must either complete (CE# registered HIGH) or cross a
row boundary within 4µs to ensure successful refresh scheduling. These timing
requirements are likely to have little or no impact when interfacing a CellularRAM
device with a low-speed memory bus.
172
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
A d v a n c e
I n f o r m a t i o n
CellularRAM-2A
64 Megabit
Asynchronous CellularRAM
Features
„ Asynchronous and Page Mode interface
„ Random Access Time: 70 ns
„ Page Mode Read Access
— Sixteen-word page size
— Interpage read access: 70 ns
— Intrapage read access: 20 ns
„ VCC, VCCQ Voltages
— 1.70 V to 1.95 V VCC
— 1.70 V to 2.25 V VCCQ
„ Low Power Consumption
— Asynchronous READ < 25 mA
— Intrapage READ < 15 mA
— Standby: 100 µA
— Deep power-down < 10 µA
„ Low-Power Features
— Temperature Compensated Refresh (TCR)
— Partial Array Refresh (PAR)
— Deep Power-Down (DPD) Mode
General Description
CellularRAM™ products are high-speed, CMOS dynamic random access memories
that have been developed for low-power portable applications. The 64Mb device
is organized as 4 Meg x 16 bits. These devices include the industry-standard,
asynchronous memory interface found on other low-power SRAM or Pseudo
SRAM offerings.
A user-accessible configuration register (CR) has been included to define device
operation. The CR defines how the CellularRAM device performs on-chip refresh
and whether page mode read accesses are permitted. This register is automatically loaded with a default setting during power-up and can be updated at any
time during normal operation.
To operate smoothly on an asynchronous memory bus, CellularRAM products
have incorporated a transparent self refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no
significant impact on device read/write performance.
Special attention has been focused on current consumption during self refresh.
CellularRAM products include three system-accessible mechanisms used to minimize refresh current. Temperature compensated refresh (TCR) is used to adjust
the refresh rate according to the case temperature. The refresh rate can be decreased at lower temperatures to minimize current consumption during standby.
Setting the sleep enable pin ZZ# to LOW enables one of two low-power modes:
partial array refresh (PAR); or deep power-down (DPD). PAR limits refresh to only
that part of the DRAM array that contains essential data. DPD halts refresh oper-
December 15, 2004 cellRAM_02_A0
CellularRAM-2A
173
A d v a n c e
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ation altogether and is used when no vital information is stored in the device.
These three refresh mechanisms are accessed through the CR.
A[21:0]
Address Decode
Logic
4,096K x 16
DRAM
Memory
Array
Input/
Output
MUX
and
Buffers
Configuration
Register (CR)
DQ[7:0]
DQ[15:8]
CE#
WE#
OE#
LB#
UB#
ZZ#
Control
Logic
Note: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing diagrams for detailed information.
Figure 64.
Functional Block Diagram
Table 65.
174
Pin Descriptions
Symbol
Type
Description
A[21:0]
Input
Address Inputs: Inputs for the address accessed during READ or WRITE operations. The
address lines are also used to define the value to be loaded into the configuration register.
ZZ#
Input
Sleep Enable: When ZZ# is LOW, the configuration register can be loaded or the device can
enter one of two low-power modes (DPD or PAR).
CE#
Input
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and
goes into standby power mode.
OE#
Input
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output
buffers are disabled.
WE#
Input
Write Enable: Enables WRITE operations when LOW.
LB#
Input
Lower Byte Enable. DQ[7:0]
UB#
Input
Upper Byte Enable. DQ[15:8]
DQ[15:0]
Input/
Output
Data Inputs/Outputs.
VCC
Supply
Device Power Supply: (1.7 V–1.95 V) Power supply for device core operation.
VCCQ
Supply
I/O Power Supply: (1.8 V) Power supply for input/output buffers.
VSS
Supply
VSS must be connected to ground.
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Table 65.
Symbol
Type
VSSQ
Supply
Pin Descriptions (Continued)
Description
VSSQ must be connected to ground.
Table 66.
Bus Operations—Asynchronous Mode
Power
CE#
WE#
OE#
LB#/UB#
ZZ#
DQ[15:0]
(Note 1)
Notes
Standby
H
X
X
X
H
High-Z
2, 5
Read
Active > Standby
L
H
L
L
H
Data-Out
1, 4
Write
Active > Standby
L
L
X
L
H
Data-In
1, 3, 4
Active
Standby
L
H
H
L
H
High-Z
4, 5
PAR
Partial Array Refresh
H
X
X
X
L
High-Z
6
DPD
Deep Power-down
H
X
X
X
L
High-Z
6
Active
L
L
X
X
L
High-Z
Mode
Standby
Load Configuration
Register
Notes:
1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# only is in select mode, only
DQ[7:0] are affected. When UB# only is in the select mode, DQ[15:8] are affected.
2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data inputs/outputs are
internally isolated from any external influence.
3. When WE# is invoked, the OE# input is internally disabled and has no effect on the I/Os.
4. The device consumes active power in this mode whenever addresses are changed.
5. VIN = VCC or 0V; all device balls must be static (unswitched) in order to achieve minimum standby current.
6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
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Functional Description
The 64Mb async/page CellularRAM device is a high-density alternative to SRAM
and Pseudo SRAM products, popular in low-power, portable applications. The device contains 67,108,864 bits organized as 4,194,304 addresses by 16 bits. It
includes the industry-standard, asynchronous memory interface found on other
low-power SRAM or Pseudo SRAM offerings. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor that is used to launch the
power-up initialization process. Initialization will load the CR with its default settings. VCC and VCCQ must be applied simultaneously, and when they reach a
stable level above 1.70 V, the device requires 150 µs to complete its self initialization process (see Figure 2). During the initialization period, CE# should remain
HIGH. When initialization is complete, the device is ready for normal operation.
At power-up, the CR is set to 0070h.
VCC
VCCQ
VCC = 1.7 V
tPU > 150 µs
Device Initialization
Figure 65.
Device ready for
normal operation
Power-Up Initialization Timing
Bus Operating Modes
CellularRAM products incorporate the industry-standard, asynchronous interface
found on other low-power SRAM or Pseudo SRAM offerings. This bus interface
supports asynchronous READ and WRITE operations as well as the bandwidthenhancing page mode READ operation. The specific interface that is supported is
defined by the value loaded into the CR.
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode
uses the industry standard SRAM control interface (CE#, OE#, WE#, LB#/ UB#).
READ operations (Figure 66) are initiated by bringing CE#, OE#, and LB#/UB#
LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the
specified access time has elapsed. WRITE operations (Figure 67) occur when
CE#, WE#, and LB#/ UB# are driven LOW. During WRITE operations, the level
of OE# is a “Don't Care”; WE# will override OE#. The data to be written will be
latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first).
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CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
tRC = READ Cycle Time
Don't Care
Figure 66.
READ Operation
CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
tWC = WRITE Cycle Time
Don't Care
Figure 67.
WRITE Operation
Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous
READ operation. In page mode-capable products, an initial asynchronous read
access is performed, then adjacent addresses can be quickly read by simply
changing the low-order address. Addresses A[3:0] are used to determine the
members of the 16-address CellularRAM page. Addresses A[4] and higher must
remain fixed during the entire page mode access. Figure 68 shows the timing diagram for a page mode access.
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Page mode takes advantage of the fact that adjacent addresses can be read in a
shorter period of time than random addresses. WRITE operations do not include
comparable page mode functionality.
CE#
OE#
WE#
ADDRESS
ADD[0]
tAA
ADD[1]
tAPA
D[0]
DATA
ADD[2]
tAPA
D[1]
ADD[3]
tAPA
D[2]
D[3]
LB#/UB#
Don't Care
Figure 68.
Page Mode READ Operation
LB# / UB# Operation
The lower byte (LB#) enable and upper byte (UB#) enable signals allow for bytewide data transfers. During READ operations, enabled bytes are driven onto the
DQs. The DQs associated with a disabled byte are put into a High-Z state during
a READ operation. During WRITE operations, any disabled bytes will not be transferred to the memory array and the internal value will remain unchanged. During
a WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#,
LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device
will disable the data bus from receiving or transmitting data. Although the device
will seem to be deselected, the device remains in an active mode as long as CE#
remains LOW.
Low Power Operation
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary
to perform the DRAM refresh operation on the full array. Standby operation occurs when CE# and ZZ# are HIGH and there are no transactions in progress.
The device will enter standby operation during READ and WRITE operations
where the address and control inputs remain static for an extended period of
time. This “active” standby mode will continue until a change occurs to the address or control inputs.
Temperature Compensated Refresh
Temperature compensated refresh (TCR) is used to adjust the refresh rate depending on the device operating temperature. DRAM technology requires more
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frequent refresh operations to maintain data integrity as temperatures increase.
More frequent refresh is required due to the increased leakage of the DRAM's capacitive storage elements as temperatures rise. A decreased refresh rate at lower
temperatures will facilitate a savings in standby current.
TCR allows for adequate refresh at four different temperature thresholds: +15°C,
+45°C, +70°C, and +85°C. The setting selected must be for a temperature
higher than the case temperature of the CellularRAM device. If the case temperature is +50°C, the system can minimize self refresh current consumption by
selecting the +70°C setting. The +15°C and +45°C settings would result in inadequate refreshing and cause data corruption.
Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total
memory array. This feature enables the system to reduce refresh current by only
refreshing that part of the memory array that is absolutely necessary. The refresh
options are full array, three-quarters array, one-half array, one-quarter array, or
none of the array. Data stored in addresses not receiving refresh will become corrupted. The mapping of these partitions can start at either the beginning or the
end of the address map (Tables 5 and 6). READ and WRITE operations are ignored
during PAR operation.
The device can only enter PAR mode if the SLEEP bit in the configuration register
has been set HIGH (CR[4] = 1). PAR is initiated by bring the ZZ# pin to the LOW
state for longer than 10µs. Returning ZZ# to HIGH will cause an exit from PAR
and the entire array will be immediately available for READ and WRITE
operations.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode
is used when the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is entered. When
refresh activity has been re-enabled, the CellularRAM device will require 150µs
to perform an initialization procedure before normal operations can resume.
READ and WRITE operations are ignored during DPD operation.
The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4]
= 0). DPD is initiated by bringing the ZZ# pin to the LOW state for longer than
10µs. Returning ZZ# to HIGH will cause the device to exit DPD and begin a 150µs
initialization process. During this 150µs period, the current consumption will be
higher than the specified standby levels but considerably lower than the active
current specification.
Driving the ZZ# pin LOW will place the device in the PAR mode if the SLEEP bit
in the CR has been set HIGH (CR[4] = 1).
Configuration Register Operation
The configuration register (CR) defines how the CellularRAM device performs its
transparent self refresh. This register is automatically loaded with default settings
during power-up and can be updated anytime while the device is operating in a
standby state.
The CR is loaded using a WRITE operation immediately after ZZ# makes a HIGHto-LOW transition (Figure 69). The values placed on addresses A[21:0] are
latched into the CR on the rising edge of CE# or WE#, whichever occurs first. Al-
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tering the refresh parameters can dramatically reduce current consumption
during standby mode. Page mode control is also embedded into the configuration
register. Table 67 describes the control bits used in the CR. At power up, the CR
is set to 0070h.
ADDRESS
ADDRESS VALID
CE#
WE#
t < 500ns
ZZ#
Figure 69.
Load Configuration Register Operation
Partial Array Refresh (CR[2:0]) Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the system to reduce current by only refreshing that part of the
memory array required by the host system. The refresh options are full array,
three-quarters array, one-half array, one-quarter array, or none of the array. The
mapping of these partitions can start at either the beginning or the end of the
address map (see Table 68 on page 181).
Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled
The sleep mode bit determines which low-power mode is to be entered when ZZ#
is driven LOW. If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is enabled.
DPD operation disables all refresh-related activity. This mode will be used when
the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity
has been re-enabled, the CellularRAM device will require 150µs to perform an initialization procedure before normal operation can resume.
Temperature Compensated Refresh (CR[6:5]) Default = +85°C Operation
The TCR bits allow for adequate refresh at four different temperature thresholds:
+15°C, +45°C, +70°C, and +85°C. The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. If the case
temperature is +50°C, the system can minimize self refresh current consumption
by selecting the +70°C setting. The +15°C and +45°C settings would result in
inadequate refreshing and cause data corruption.
Page Mode READ Operation (CR[7]) Default = Disabled
The page mode operation bit determines whether page mode READ operations
are enabled. In the power-up default state, page mode is disabled.
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Table 67.
A7
A[21:8]
7
21–8
A6
6
PAGE
RESERVED
Configuration Register Bit Mapping
A4
A5
5
TCR
A2
3
RESERVED
1
Page Mode Enabled
CR[6] CR[5]
Configuration
Register
0
CR[2] CR[1] CR[0]
Page Mode Enable/Disable
Page Mode Disabled (default)
1
Address Bus
A0
PAR
Must be set to "0"
0
A1
2
4
SLEEP
All must be set to "0"
CR[7]
A3
0
0
0
0
0
1
Bottom 3/4 array
1
0
Bottom 1/2 array
0
Maximum Case Temp.
PAR Refresh Coverage
Full array (default)
0
1
1
Bottom 1/4 array
1
0
0
None of array
Top 3/4 array
1
0
1
1
1
+85
C (default)
1
1
0
Top 1/2 array
0
0
+70
C
1
1
1
Top 1/4 array
0
1
+45
C
1
0
+15
C
CR[4]
Table 68.
Sleep Mode
0
DPD Enabled
1
PAR Enabled (default)
64Mb Address Patterns for PAR (CR[4] = 1)
CR[2]
CR[1]
CR[0]
Active Section
Address Space
Size
Density
0
0
0
Full die
000000h–3FFFFFh
4 Meg x 16
64Mb
0
0
1
Three-quarters of die
000000h–2FFFFFh
3 Meg x 16
48Mb
0
1
0
One-half of die
000000h–1FFFFFh
2 Meg x 16
32Mb
0
1
1
One-quarter of die
000000h–0FFFFFh
1 Meg x 16
16Mb
1
0
0
None of die
0
0 Meg x 16
0Mb
1
0
1
Three-quarters of die
100000h–3FFFFFh
3 Meg x 16
48Mb
1
1
0
One-half of die
200000h–3FFFFFh
2 Meg x 16
32Mb
1
1
1
One-quarter of die
300000h–3FFFFFh
1 Meg x 16
16Mb
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Absolute Maximum Ratings
Voltage to Any Ball Except VCC, VCCQ
Relative to VSS . . . -0.50 V to (4.0 V or VCCQ + 0.3 V, whichever is less)
Voltage on VCC Supply Relative to VSS . . . . . . . . . . . . . . . -0.20 V to +2.45 V
Voltage on VCCQ Supply Relative to VSS . . . . . . . . . . . . . . . -0.20 V to +4.0 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55ºC to +150ºC
Operating Temperature (case)
Wireless. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25ºC to +85ºC
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40ºC to +85ºC
Soldering Temperature and Time
10s (lead only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260ºC
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
182
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DC Characteristics
Wireless Temperature (-25°C ≤ TC ≤ +85°C)
Industrial Temperature (-40°C < TC < +85°C)
Table 69.
Description
Electrical Characteristics and Operating Conditions
Conditions
Symbol
Min
Max
Units
VCC
1.70
1.95
V
VCCQ
1.70
2.25
V
Input High Voltage
VIH
1.4
VCCQ + 0.2
V
Input Low Voltage
VIL
-0.20
0.4
V
0.80 VCCQ
Supply Voltage
I/O Supply Voltage
1.8 V
Notes
Output High Voltage
IOH = -0.2mA
VOH
Output Low Voltage
IOL = +0.2mA
VOL
0.20 VCCQ
V
Input Leakage Current
VIN = 0 to VCCQ
ILI
1
µA
Output Leakage Current
OE# = VIH or
Chip Disabled
ILO
1
µA
2
ICC1
25
mA
1, 2
ICC2
25
mA
1, 2
ISB
100
µA
2, 3
Read Operating Current
Write Operating Current
MAX Standby Current
VIN = VCCQ or 0V
Chip Enabled, IOUT = 0
VIN = VCCQ or 0V
Chip Enabled
VIN = VCCQ or 0V
Chip Disabled
V
Notes:
1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current
required to drive output capacitance expected in the actual system.
2. This device assumes a standby mode if the chip is disabled (CE# HIGH). It will also automatically go into a standby
mode whenever all input signals are quiescent (not toggling), regardless of the state of CE#, LB#, and UB#. In
order to achieve low standby current, all inputs must be either VCCQ or VSS.
3. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85°C.
Table 70.
Description
Temperature Compensated
Refresh Standby Current
Temperature Compensated Refresh Specifications and Conditions
Conditions
VIN = VCCQ or 0V,
Chip Disabled
Symbol
ITCR
Density
64 Mb
Max Case
Temperature
Typ
Max
+85°C
100
+70°C
TBD
+45°C
TBD
+15°C
50
Units
µA
Notes:
1. ITCR (MAX) values measured with FULL ARRAY refresh.
2. This device assumes a standby mode if the chip is disabled (CE# HIGH). It will also automatically go into a standby mode
whenever all input signals are quiescent (not toggling), regardless of the state of CE#, LB#, and UB#. In order to achieve
low standby current, all inputs must be either VCCQ or VSS.
December 15, 2004 cellRAM_02_A0
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Table 71.
Description
Partial Array Refresh Specifications and Conditions
Conditions
Partially Array Refresh Current
I n f o r m a t i o n
Symbol
VIN = VCCQ or 0V,
ZZ# = Low
CR[4] = 1
IPAR
Density
Array
Partition
64 Mb
Typ
Max
Full
100
3/4
TBD
1/2
TBD
1/4
TBD
0
50
Units
µA
Note:IPAR (MAX) values measured with TCR set to 85°C.
Table 72.
Deep Power-Down Specifications
Description
Conditions
Symbol
Deep Power-down
VIN = VCCQ or 0V; +25°C; ZZ# = LOW CR[4] = 0
IZZ
Table 73.
Conditions
Input/Output Capacitance (DQ)
Max
Units
10
µA
Capacitance Specifications and Conditions
Description
Input Capacitance
Typ
TC = +25ºC; f = 1 MHz; VIN = 0V
Symbol
Min
Max
Units
Notes
CIN
-
6
pF
1
CIO
-
6
pF
1
Notes:
1. These parameters are verified in device characterization and are not 100% tested.
AC Characteristics
VCC Q
Input
VCCQ /2
VCCQ/2
Test Points
Output
VSS
Notes:
1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input timing begins at VCCQ/2, and output
timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 1.6ns.
Figure 70.
AC Input/Output Reference Waveform
VCCQ
R1
Test Point
DUT
30pF
R2
Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
184
Figure 71.
Output Load Circuit
Table 74.
Output Load Circuit
VCCQ
R1/R2
1.8 V
2.7 KΩ
CellularRAM-2A
cellRAM_02_A0 December 15, 2004
A d v a n c e
Table 75.
I n f o r m a t i o n
READ Cycle Timing Requirements
Parameter
Symbol
Min
Max
Units
Notes
Address Access Time
tAA
70
ns
Page Access Time
tAPA
20
ns
LB#/UB# Access Time
tBA
70
ns
LB#/UB# Disable to High-Z Output
tBHZ
0
8
ns
2
LB#/UB# Enable to Low-Z Output
tBLZ
10
ns
1
Chip Select Access Time
tCO
Chip Disable to High-Z Output
tHZ
0
Chip Enable to Low-Z Output
tLZ
10
Output Enable to Valid Output
tOE
Output Hold from Address Change
tOH
5
Output Disable to High-Z Output
tOHZ
0
Output Enable to Low-Z Output
tOLZ
Page Cycle Time
READ Cycle Time
70
ns
8
ns
2
ns
1
20
ns
ns
8
ns
2
5
ns
1
tPC
20
ns
tRC
70
ns
Notes:
1. High-Z to Low-Z timings are tested with the circuit shown in Figure 71 on page 184. The Low-Z timings measure a
100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 71 on page 184. The High-Z timings measure
a 100mV transition from either VOH or VOL toward VCCQ/2.
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Table 76.
Parameter
I n f o r m a t i o n
WRITE Cycle Timing Requirements
Symbol
Min
Max
Units
Address Setup Time
tAS
0
ns
Address Valid to End of Write
tAW
70
ns
Byte Select to End of Write
tBW
70
ns
CE# HIGH Time During Write
tCEH
5
ns
Maximum CE# Pulse Width
tCEM
Chip Enable to End of Write
tCW
70
ns
Data Hold from Write Time
tDH
0
ns
Data WRITE Setup Time
tDW
23
ns
Chip Enable to Low-Z Output
tLZ
10
ns
End WRITE to Low-Z Output
tOW
5
ns
Write Cycle Time
tWC
70
ns
Write to High-Z Output
tWHZ
0
Write Pulse Width
tWP
46
Write Recovery Time
tWR
0
10
Notes
µs
8
1
ns
2
ns
Notes:
1. High-Z to Low-Z timings are tested with the circuit shown in Figure 71 on page 184. The Low-Z timings measure a
100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 71 on page 184. The High-Z timings measure
a 100mV transition from either VOH or VOL toward VCCQ/2.
Table 77.
Load Configuration Register Timing Requirements
Parameter
Symbol
Min
Address Setup Time
tAS
0
ns
Address Valid to End of Write
tAW
70
ns
Chip Deselect to ZZ# LOW
tCDZZ
5
ns
Chip Enable to End of Write
tCW
70
ns
Write Cycle Time
tWC
70
ns
Write Pulse Width
tWP
40
ns
Write Recovery Time
tWR
0
ns
tZZWE
10
ns
ZZ# LOW to WE# LOW
Table 78.
Parameter
Units
Notes
Deep Power Down Timing Requirements
Symbol
Min
tCDZZ
5
ns
tR
150
µs
tZZMIN
10
µs
Chip Deselect to ZZ# LOW
Deep Power-Down Recovery
Minimum ZZ# Pulse Width
186
Max
CellularRAM-2A
Max
Units
Notes
cellRAM_02_A0 December 15, 2004
A d v a n c e
Table 79.
I n f o r m a t i o n
Power-up Initialization Timing Parameters
Parameter
Symbol
Min
Max
Initialization Period (required before normal operations)
tPU
150
Units
Notes
µs
VCC (MIN)
VCC, VCCQ = 1.7V
tPU
Figure 72.
Device ready for
normal operation
Power-up Initialization Period
tWC
OPCODE
ADDRESS
tAW
CE#
tWR
tCW
LB#/UB#
tWP
tAS
WE#
OE#
tCDZZ
tZZWE
ZZ#
DON’T CARE
Figure 73.
Table 80.
Load Configuration Register Timing Requirements
Symbol
Min
tAS
0
tAW
70
tCDZZ
5
tCW
70
December 15, 2004 cellRAM_02_A0
Load Configuration Register Timing
Max
Units
Symbol
Min
tWC
70
tWP
40
tWR
0
tZZWE
10
ns
CellularRAM-2A
Max
Units
ns
500
187
A d v a n c e
t CDZZ
I n f o r m a t i o n
t ZZ (MIN)
ZZ#
tR
CE#
Device ready for
normal operation
DON’T CARE
Figure 74.
Table 81.
Deep Power Down Entry/Exit TIming
Load Configuration Register Timing Requirements
Symbol
Min
Max
Units
tCDZZ
5
ns
tR
150
µs
tZZ(MIN)
10
µs
tRC
ADDRESS VALID
ADDRESS
tAA
tHZ
CE#
tCO
tBHZ
tBA
LB#/UB#
tLZ
tBLZ
tOHZ
tOE
OE#
tOLZ
DATA-OUT
High-Z
Data Valid
DON’T CARE
Figure 75.
188
High-Z
UNDEFINED
Single READ Operation (WE# = VIH)
CellularRAM-2A
cellRAM_02_A0 December 15, 2004
A d v a n c e
I n f o r m a t i o n
Table 82.
Symbol
Min
Max
READ Timing Parameters
Units
Symbol
Min
10
tAA
70
tLZ
tBA
70
tOE
tBHZ
0
tBLZ
10
8
ns
70
tCO
0
tHZ
Max
Units
20
tOHZ
0
tOLZ
5
tRC
70
8
ns
Max
Units
8
tRC
ADDRESS
A[21:4]
ADDRESS VALID
ADDRESS
A[3:0]
tPC
tAA
tHZ
CE#
tCO
tBHZ
tBA
LB#/UB#
tBLZ
tLZ
tOHZ
tOE
OE#
tAPA
tOLZ
DATA-OUT
tOH
Data
Valid
High-Z
Data
Valid
Data
Valid
Data
Valid
DON’T CARE
Figure 76.
Table 83.
Symbol
Min
High-Z
UNDEFINED
Page Mode Read Operation (WE# = VIH)
Page Mode READ Timing Parameters
Max
Units
Symbol
Min
10
tAA
70
tLZ
tAPA
20
tOE
tBA
70
tOH
5
tOHZ
0
tOLZ
5
70
tPC
20
8
tRC
70
tBHZ
0
tBLZ
10
tCO
tHZ
December 15, 2004 cellRAM_02_A0
0
8
ns
CellularRAM-2A
20
8
ns
189
A d v a n c e
I n f o r m a t i o n
tWC
ADDRESS
ADDRESS VALID
tAW
tWR
tCEM
tCW
CE#
tBW
LB#/UB#
tWP
tAS
WE#
OE#
tDW
DATA-IN
tDH
Data Valid
tWHZ
tOW
DATA-OUT
High-Z
DON’T CARE
Figure 77.
Table 84.
Symbol
Min
tAS
0
tAW
70
tBW
70
tCW
70
tDH
0
Write Timing Parameters
Units
Symbol
Min
tDW
23
tOW
5
tWC
70
tWHZ
0
tWP
46
tWR
0
ns
10
tCEM
190
Max
WRITE Cycle (WE# Control)
µs
ns
CellularRAM-2A
Max
8
Units
ns
cellRAM_02_A0 December 15, 2004
A d v a n c e
I n f o r m a t i o n
tWC
ADDRESS
tAW
tWR
tCW
tCEH
CE#
tAS
tCEM
tBW
LB#/UB#
tWP
WE#
OE#
tDW
DATA-IN
tDH
Data Valid
tLZ
tWHZ
DATA-OUT
High-Z
DON'T CARE
Figure 78.
Write Timing Parameters (CE# Control)
Table 85.
Write Timing Parameters (CE# Control)
Symbol
Min
tAS
0
tAW
70
tBW
70
tCEH
5
tCW
70
tDH
0
Units
Symbol
Min
tDW
23
tLZ
10
tWC
70
tWHZ
0
tWP
46
tWR
0
ns
10
tCEM
December 15, 2004 cellRAM_02_A0
Max
µs
ns
CellularRAM-2A
Max
8
Units
ns
191
A d v a n c e
I n f o r m a t i o n
tWC
ADDRESS
tAW
tWR
tCEM
CE#
tAS
tBW
LB#/UB#
WE#
OE#
tDW
DATA-IN
tDH
Data Valid
tLZ
tWHZ
DATA-OUT
High-Z
DON’T CARE
Figure 79.
Table 86.
Symbol
Min
tAS
0
tAW
70
tBW
70
tDH
192
Write Timing Parameters (LB# / UB# Control)
Max
0
Units
Symbol
Min
tDW
23
tLZ
10
tWC
70
µs
tWHZ
0
ns
tWR
0
ns
10
tCEM
WRITE Cycle (LB# / UB# Control)
CellularRAM-2A
Max
Units
ns
8
cellRAM_02_A0 December 15, 2004
A d v a n c e
I n f o r m a t i o n
How Extended Timings Impact CellularRAM™ Operation
Introduction
CellularRAM products use a DRAM technology that periodically requires refresh to
ensure against data corruption. CellularRAM devices include on-chip circuitry that
performs the required refresh in a manner that is completely transparent in systems with normal bus timings. The refresh circuitry does impose constraints on
timings in systems that take longer than 10µs to complete WRITE operations.
This section describes CellularRAM timing requirements in systems that perform
extended operations.
Operation When Page Mode is Disabled
CellularRAM products require that all WRITE operations must be completed within
10µs. After completing an operation, the device must either enter standby (by
transitioning CE# HIGH), or else perform a second operation using a new address. Figures 80 and 81 demonstrate these constraints as they apply during an
asynchronous (page-mode-disabled) operation. Either the CE# active period
(tCEM in Figure 80) or the address valid period (tTM in Figure 81) must be less than
10 µs during any operation to accommodate orderly scheduling of refresh.
tCEM < 10 µs
CE#
ADDRESS
Note:Timing constraints when page mode is enabled.
Figure 80.
Extended Timing for tCEM
CE#
tTM < 10µs
ADDRESS
Note:Timing constraints when page mode is enabled.
Figure 81.
Extended Timing for tTM
Operation When Page Mode is Enabled
When a CellularRAM device is configured for page mode operation, the address
inputs are used to accelerate read accesses and cannot be used by the on-chip
circuitry to schedule refresh. CE# must return HIGH upon completion of all
WRITE operations when page mode is enabled (Figure 82). The total time taken
for a WRITE operation should not exceed 10 µs to accommodate orderly scheduling of refresh.
December 15, 2004 cellRAM_02_A0
CellularRAM-2A
193
A d v a n c e
I n f o r m a t i o n
tCEM <10µs
CE#
Note:Timing constraints when page mode is enabled.
Figure 82.
Extended Timing for tCEM (2)
Impact on Extended WRITE Operations
Modified timings are only required during extended WRITE operations (see Figure
83 below). An extended WRITE operation requires that both the write pulse width
(tWP) and the data valid period (tDW) will need to be lengthened to at least the
minimum WRITE cycle time (tWC[MIN]). These increased timings ensure that time
is available for both a refresh operation and successful completion of the WRITE
operation.
t CEM or t TM > 4µs
ADDRESS
CE#
LB#/UB#
t WP > t WC (MIN)
WE#
t DW > t WC (MIN)
DATA-IN
Figure 83.
Extended WRITE Operation
Summary
CellularRAM products are designed to ensure that any possible bus timings do not
cause corruption of array data due to lack of refresh. The on-chip refresh circuitry
will only affect the required timings for WRITE operations (READs are unaffected)
performed in a system with a slow memory interface. The impact for WRITE operations is that some of the timing parameters (tWP, tDW) are lengthened. The
modified timings are likely to have little or no impact when interfacing a CellularRAM device with a low-speed memory bus.
194
CellularRAM-2A
cellRAM_02_A0 December 15, 2004
A d v a n c e
I n f o r m a t i o n
Revision Summary
Revision A0 (December 17, 2004)
Initial release.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
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The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of thirdparty rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the
information in this document.
Copyright © 2004 Spansion. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion.
Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
December 17, 2004 S71GS256/128N_00_A0
Revision Summary
195